JP2009231823A - Thin-film transistor and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem with ON-state current and OFF-state current of a thin-film transistor, and to provide a thin-film transistor capable of high-speed operation. <P>SOLUTION: The thin-film transistor has: a semiconductor layer doped with an impurity element serving as an accepter and overlapped over a gate electrode via a gate insulation film; a buffer layer provided so as to overlap over the semiconductor layer doped with the impurity element serving as an accepter; an amorphous semiconductor layer for covering the upper surface of the buffer layer and the side surfaces of the buffer layer and the semiconductor layer doped with the impurity element serving as an acceptor; and a pair of impurity semiconductor layers having one end overlapped over the buffer layer, provided on the amorphous semiconductor layer and doped with an impurity element imparting one conductivity type forming a source region and a drain region. In the thin-film transistor, the buffer layer has film thickness thicker than the film thickness of the amorphous semiconductor layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a thin film transistor or a display device using the thin film transistor.

As a kind of field effect transistor, a thin film transistor in which a channel region is formed in a semiconductor layer formed over a substrate having an insulating surface is known. A technique using amorphous silicon, microcrystalline silicon, or polycrystalline silicon as a semiconductor layer used in a thin film transistor is disclosed (see Patent Documents 1 to 5). A typical application example of a thin film transistor is a liquid crystal television device, which is put into practical use as a switching transistor of each pixel constituting a display panel.

JP 2001-053283 A JP-A-5-129608 JP 2005-049832 A Japanese Patent Laid-Open No. 7-131030 JP 2005-191546 A

A thin film transistor in which a channel is formed in an amorphous silicon layer has a problem that field effect mobility and on-state current are low. A thin film transistor in which a channel is formed in a microcrystalline silicon layer has a problem in that the field-effect mobility is improved but the off-current is increased and sufficient switching characteristics cannot be obtained as compared with a thin film transistor using amorphous silicon. There is.

A thin film transistor in which a polycrystalline silicon layer serves as a channel formation region has characteristics that field effect mobility is significantly higher than that of the two types of thin film transistors, and a high on-state current can be obtained. Due to the above-described characteristics, this thin film transistor can constitute not only a switching transistor provided in a pixel but also a driver circuit that requires high-speed operation.

However, a thin film transistor in which a polycrystalline silicon layer serves as a channel formation region requires a semiconductor layer crystallization step as compared with the case where a thin film transistor is formed using an amorphous silicon layer, which increases the manufacturing cost. . For example, a laser annealing technique necessary for manufacturing a polycrystalline silicon layer has a problem that a large area liquid crystal panel cannot be efficiently produced with a small laser beam irradiation area.

Thus, an object is to solve the above problems related to the on-state current and off-state current of a thin film transistor. Another object is to provide a thin film transistor capable of high-speed operation.

A thin film transistor which is one embodiment of the present invention includes a semiconductor layer to which an impurity element which serves as an acceptor overlaps with a gate electrode through a gate insulating layer. A buffer layer is provided over the semiconductor layer to which an impurity element serving as an acceptor is added. This buffer layer is provided so as to substantially overlap with a semiconductor layer to which an impurity element serving as an acceptor is added. An amorphous semiconductor layer covers the upper surface of the buffer layer and the side surface of the semiconductor layer to which the impurity element serving as the buffer layer and the acceptor is added. A pair of impurity semiconductor layers to which an impurity element imparting one conductivity type that forms a source region and a drain region in the thin film transistor is added are provided over the amorphous semiconductor layer. The pair of impurity semiconductor layers to which the impurity element imparting one conductivity type is added are provided so as to correspond to each region so as to form a source region and a drain region. The pair of impurity semiconductor layers to which the impurity element imparting one conductivity type is added are provided so that one end thereof overlaps the buffer layer.

In the thin film transistor, carriers (electrons or holes) flowing between the source region and the drain region are controlled by a voltage applied to the gate electrode. However, in the thin film transistor according to the present invention, the carriers flowing between the source region and the drain region are controlled. Flows through a semiconductor layer to which an impurity element which serves as an acceptor is provided so as to overlap with the gate electrode, and an amorphous semiconductor layer which is provided in contact with the semiconductor layer to which the impurity element which serves as an acceptor is added.

The concentration of the impurity element serving as an acceptor added to the semiconductor layer to which the impurity element serving as an acceptor is added is 5 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ^3. The conductivity is lower than that of a semiconductor layer to which an impurity element serving as an acceptor is added. A semiconductor layer to which an impurity element which serves as an acceptor is added extends at least in the channel length direction of the thin film transistor, and can have a high on-state current by having the above-described electrical conductivity. Here, the thickness of the amorphous semiconductor layer is smaller than the thickness of the buffer layer provided on the semiconductor layer to which the impurity element serving as an acceptor is added, and the off current is reduced while maintaining the on current of the thin film transistor. Has a sufficient thickness.

A pair of impurity semiconductor layers to which an impurity element imparting one conductivity type which forms a source region and a drain region is added so that one end portion overlaps with the buffer layer, thereby maintaining an on-current of the thin film transistor, and an off-current Acts to lower the The thickness of the buffer layer is larger than that of each of the semiconductor layer to which the impurity element serving as an acceptor is added and the amorphous semiconductor layer. The buffer layer has a film thickness of 500 nm to 3000 nm, whereas the film thickness of the amorphous semiconductor layer is 50 nm to less than 500 nm. By setting the thickness of the buffer layer in this way, the parasitic capacitance between the source or drain and the gate is reduced.

In the present invention, the length in the channel length direction of the amorphous semiconductor layer inserted between the source region and the drain region in order to reduce off current is set by the film thickness of the amorphous semiconductor layer. That is, the distance between a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type that forms a source region or a drain region is added and a semiconductor layer to which an impurity element to be an acceptor is added is the film of an amorphous semiconductor layer Thick. The channel length of the thin film transistor according to one embodiment of the present invention includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type that forms a source region or a drain region is added and a semiconductor layer to which an impurity element serving as an acceptor is added. Corresponds to distance. For this reason, it is possible to form a nanometer-sized fine structure in a thin film transistor in a self-aligning manner without using photolithographic techniques to align the photomask with submicron level accuracy.

That is, the channel length of a thin film transistor in which at least one amorphous semiconductor layer substantially becomes a channel formation region is determined by the film thickness of the amorphous semiconductor layer, and is a nanometer-level length as described above. One embodiment of the present invention solves the problem by simultaneously manufacturing deep sub-micron thin film transistors while performing a thin film transistor manufacturing process based on a design rule of several microns.

An impurity semiconductor refers to a semiconductor supplied from an impurity element to which most of carriers involved in electric conduction are added. An impurity element is an element that can serve as a donor that supplies electrons as carriers or an acceptor that supplies holes. Typically, a donor corresponds to a Group 15 element of the periodic table, and an acceptor corresponds to a Group 13 element of the periodic table.

A microcrystalline semiconductor exemplarily has a crystal grain size of 2 nm to 200 nm, or 10 nm to 80 nm, or 20 nm to 50 nm, and an electric conductivity of approximately 10 ⁻⁷ S / cm to 10 ⁻⁴ S / cm. What is cm indicates a semiconductor that can be increased to about 10 ¹ S / cm by valence electron control. However, the concept of the microcrystalline semiconductor is not limited only to the values of the crystal grain size and electric conductivity described above, and can be replaced with other semiconductor materials as long as they have equivalent physical property values. An amorphous semiconductor refers to a semiconductor having no crystal structure (no long-range order in the arrangement of atoms). Note that amorphous silicon includes those containing hydrogen.

The “on-current” is a current that flows through the channel formation region when an appropriate gate voltage is applied to the gate electrode in order to pass a current through the channel formation region (that is, when the thin film transistor is in an on state). The “off-state current” is a current that flows between the source and the drain when the gate voltage is lower than the threshold voltage of the thin film transistor (that is, when the thin film transistor is in the off state).

Carriers flowing between the source region and the drain region are provided in contact with a semiconductor layer to which an impurity element serving as an acceptor is provided so as to overlap with the gate electrode and a semiconductor layer to which the impurity element serving as an acceptor is added. By adopting a structure in which the crystalline semiconductor layer flows, a sufficient on-current can be passed while reducing the off-current.

In addition, a buffer layer is provided over the semiconductor layer to which the impurity element that serves as an acceptor is added, and an amorphous semiconductor layer that is in contact with the upper surface of the buffer layer and the side surface of the semiconductor layer to which the impurity element that serves as an acceptor is added. Therefore, a thin film transistor with a nanometer-sized channel length can be formed in a self-aligned manner, a sufficient on-current can be passed while reducing an off-current, and a high-speed operation of the thin-film transistor can be enabled. it can.

FIG. 10 is a cross-sectional view illustrating a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. 5A and 5B are a cross-sectional view and a top view illustrating a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. It is a figure explaining the multi-tone mask applicable to this Embodiment. FIG. 10 is a top view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a top view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. It is a top view explaining the element substrate concerning this embodiment. It is sectional drawing explaining the terminal part and pixel part of the element substrate which concern on this Embodiment. It is a perspective view explaining the display panel which concerns on this Embodiment. FIG. 11 is a perspective view illustrating an electronic device using the display device according to this embodiment. It is a figure explaining the electronic device using the display apparatus which concerns on this Embodiment. FIG. 11 is a perspective view illustrating an electronic device using the display device according to this embodiment.

Embodiments of the following invention will be described below with reference to the drawings. However, the disclosed invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the disclosed invention. The Therefore, the disclosed invention is not construed as being limited to the description of the embodiments below. In the structures of the invention described below, the same reference numerals are used in common in different drawings.

In the following embodiments, the gate electrode 05 is a part of the gate wiring. For this reason, the gate electrode 05 is sometimes referred to as a gate wiring 05. Similarly, the wiring 63 may be referred to as a source wiring 63 or a source electrode 63 in some cases.

(Embodiment 1)
Here, off-state current is lower than that of a thin film transistor having a microcrystalline semiconductor layer in a channel formation region, high-speed operation is possible, and on-state current is lower than that of a thin film transistor having an amorphous semiconductor layer in a channel formation region. A high structure of a thin film transistor will be described with reference to FIGS.

In the thin film transistor illustrated in FIG. 1A, a gate electrode 05 is formed over a substrate 01, gate insulating layers 09a and 09b are formed over the gate electrode 05, and an impurity element serving as an acceptor is formed over the gate insulating layers 09a and 09b. Is formed, and a buffer layer 53 is formed over the semiconductor layer 51 to which an impurity element serving as an acceptor is added. The buffer layer 53 is provided so as to substantially overlap with the semiconductor layer 51 to which an impurity element serving as an acceptor is added. In addition, a pair of amorphous semiconductor layers 55 and 57 are formed to cover the side surfaces of the semiconductor layer 51 and the buffer layer 53 to which an impurity element serving as an acceptor is added. A source region is formed over the pair of amorphous semiconductor layers 55 and 57. And a pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added to form a drain region are formed on the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added. Wirings 63 and 65 are formed. One end portion of the pair of impurity semiconductor layers to which the impurity element imparting one conductivity type is added overlaps with the buffer layer 53.

In the semiconductor layer 51 to which the impurity element that serves as an acceptor is added, an acceptor that is an element that supplies holes as carriers is added. An impurity element that serves as an acceptor is typically boron, which is a Group 12 element of the periodic table. The semiconductor layer 51 to which an impurity element serving as an acceptor is added includes an amorphous silicon layer, an amorphous silicon germanium layer, an amorphous germanium layer, a microcrystalline silicon layer, a microcrystalline silicon germanium layer, a microcrystalline germanium layer, a polycrystalline silicon layer, and a polycrystalline layer. A silicon germanium layer, a polycrystalline germanium layer, or the like is formed.

When the concentration of the impurity element serving as an acceptor added to the semiconductor layer 51 to which the impurity element serving as an acceptor is added is measured by secondary ion mass spectrometry (SIMS), 5 × 10 ¹⁶ atoms / cm 3. By setting it to ³ or more and 5 × 10 ¹⁹ atoms / cm ³ , it is possible to reduce the resistivity at the interface between the gate insulating layer 09b and the semiconductor layer 51 to which the impurity element serving as an acceptor is added, and high-speed operation. A thin film transistor with high on-state current can be manufactured.

The microcrystalline semiconductor here is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). This semiconductor is a semiconductor having a third state that is stable in terms of free energy, and is crystalline with a short-range order and lattice distortion, and a particle size of 2 nm to 200 nm, or 10 nm to 80 nm. Alternatively, columnar or needle-like crystals having a diameter of 20 nm or more and 50 nm or less are grown in the normal direction with respect to the substrate surface. In addition, a semiconductor whose electrical conductivity is approximately 10 ⁻⁷ S / cm to 10 ⁻⁴ S / cm indicates a semiconductor that can be increased to about 10 ¹ S / cm by valence electron control. In addition, a non-single-crystal semiconductor exists between the plurality of microcrystalline semiconductors. Microcrystalline silicon, which is a typical example of a microcrystalline semiconductor, has its Raman spectrum peak shifted to a lower wave number side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. Further, in order to terminate dangling bonds (dangling bonds), hydrogen or halogen may be contained at least 1 atomic% or more. Further, a rare gas element such as helium, argon, krypton, or neon may be included. By further promoting lattice distortion, the stability of the microcrystalline structure is increased and a good microcrystalline semiconductor can be obtained. Such a description of the microcrystalline semiconductor layer is disclosed in, for example, US Pat. No. 4,409,134. However, the concept of the microcrystalline semiconductor is not limited only to the values of the crystal grain size and electric conductivity described above, and can be replaced with other semiconductor materials as long as they have equivalent physical property values.

The thickness of the semiconductor layer 51 to which the impurity element which serves as an acceptor is added is 5 nm to 50 nm, preferably 5 nm to 30 nm.

The oxygen concentration and nitrogen concentration of the semiconductor layer 51 to which the impurity element serving as an acceptor is added are typically less than 3 × 10 ¹⁹ atoms / cm ³ , more preferably less than 3 × 10 ¹⁸ atoms / cm ³ , carbon The concentration of is preferably 3 × 10 ¹⁸ atoms / cm ³ or less. In the case where the semiconductor layer 51 to which the impurity element to be an acceptor is added is a microcrystalline semiconductor layer by reducing the concentration of oxygen, nitrogen, and carbon in the semiconductor layer 51 to which the impurity element to be an acceptor is added, Generation of defects in the semiconductor layer can be suppressed. Furthermore, when oxygen and nitrogen are contained in the microcrystalline semiconductor layer, crystallization is difficult. Therefore, in the case where the semiconductor layer 51 to which the impurity element which serves as an acceptor is added is a microcrystalline semiconductor layer, the crystallinity of the microcrystalline semiconductor layer can be increased by relatively low oxygen concentration and nitrogen concentration in the microcrystalline semiconductor layer. it can.

In addition, since the impurity element that serves as an acceptor is added to the semiconductor layer 51 to which the impurity element that serves as an acceptor of this embodiment is added, the impurity element that serves as a donor is added to the semiconductor layer 51 to which the impurity element that serves as an acceptor is added. The threshold voltage can be controlled by adding at the same time as the film formation or after the film formation. The impurity element that serves as a donor is typically phosphorus, and an impurity gas such as PH ₃ may be mixed into silicon hydride at a rate of 1 ppm to 1000 ppm, preferably 1 to 100 ppm. The phosphorus concentration is preferably about one-tenth of the impurity element that serves as an acceptor.

The buffer layer 53 is formed using an amorphous semiconductor layer. Alternatively, an amorphous semiconductor layer to which a halogen such as fluorine or chlorine is added is used. The thickness of the buffer layer 53 is set to 500 nm to 3000 nm. As the amorphous semiconductor layer, an amorphous silicon layer, an amorphous silicon layer containing germanium, or the like can be given.

When the semiconductor layer 51 to which the impurity element serving as an acceptor is added is a microcrystalline semiconductor layer by tilting the side surface of the buffer layer 53 to 30 to 60 °, the microcrystalline semiconductor layer is used as a crystal growth nucleus. Since the crystallinity of the interface between the amorphous semiconductor layers 55 and 56 in contact with the thin film transistor can be increased, the thin film transistor can operate at high speed and the on-state current can be increased.

As the amorphous semiconductor layers 55 and 57, amorphous semiconductor layers are used. There are an amorphous silicon layer, an amorphous silicon layer containing germanium, and the like. Further, the amorphous semiconductor layers 55 and 57 may contain fluorine, chlorine, or the like. Further, the thickness of the amorphous semiconductor layers 55 and 57 is set to 50 nm or more and less than 500 nm.

The amorphous semiconductor layers 55 and 57 cover the side surfaces of the semiconductor layer 51 and the buffer layer 53 to which an impurity element serving as an acceptor is added. In addition, the gate insulating layer 52b and the amorphous semiconductor layers 55 and 57 are in contact with each other in the periphery of the semiconductor layer 51 to which the impurity element serving as an acceptor is added. With these structures, the semiconductor layer 51 to which the impurity element to be an acceptor is added and the pair of impurity semiconductor layers 59 and 61 to which the impurity element imparting one conductivity type is isolated are isolated, and the semiconductor to which the impurity element to be an acceptor is added Leakage current generated between the layer 51 and the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added can be reduced. In addition, the end portions of the amorphous semiconductor layers 55 and 57 preferably overlap with the buffer layer 53. Since the end portions of the amorphous semiconductor layers 55 and 57 overlap with the buffer layer 53, the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added and the buffer layer 53 are not in direct contact with each other. Furthermore, since the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added and the semiconductor layer 51 to which the impurity element to be an acceptor is not directly in contact with each other, leakage current can be reduced. .

In the case where the semiconductor layer 51 to which the impurity element which serves as an acceptor is added is a microcrystalline semiconductor layer, an amorphous semiconductor layer and further an amorphous semiconductor layer containing hydrogen, nitrogen, or halogen are formed as the buffer layer 53. Further, it is possible to prevent natural oxidation of the surface of the crystal grain to which the semiconductor layer 51 to which the impurity element serving as an acceptor is added is added. In particular, in a microcrystalline semiconductor layer, a region where an amorphous semiconductor and microcrystalline grains are in contact with each other is likely to crack due to local stress. When this crack comes into contact with oxygen, the crystal grains are oxidized, and silicon oxide is formed on the surface of the crystal grains. However, the formation of the buffer layer 53 on the surface of the semiconductor layer 51 to which the impurity element serving as an acceptor is added can prevent the microcrystalline grains from being oxidized. Therefore, defects in which carriers are trapped or a region that hinders the progress of carriers can be reduced, the thin film transistor can operate at high speed, and the on-state current can be increased.

The substrate 01 has heat resistance that can withstand the processing temperature of the present manufacturing process in addition to an alkali-free glass substrate, a ceramic substrate, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, or a ceramic substrate. A plastic substrate or the like having the above can be used. Alternatively, a substrate in which an insulating layer is provided on the surface of a metal substrate such as a stainless alloy may be used. When the substrate 01 is mother glass, the size of the substrate is the first generation (320 mm × 400 mm), the second generation (400 mm × 500 mm), the third generation (550 mm × 650 mm), the fourth generation (680 mm × 880 mm, or 730mm x 920mm), 5th generation (1000mm x 1200mm or 1100mm x 1250mm), 6th generation 1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160mm x 2460mm), 9th generation (2400mm x 2800 mm, 2450 mm × 3050 mm), 10th generation (2950 mm × 3400 mm), or the like can be used.

The gate electrode 05 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, or the like is applied. A preferred example of the gate electrode 05 is formed of aluminum or a laminated structure of aluminum and a barrier metal. As the barrier metal, a refractory metal such as titanium, molybdenum, or chromium is used. The barrier metal is preferably provided to prevent hillocks and oxidation of aluminum.

The gate electrode 05 is formed with a thickness of 50 nm to 300 nm. By setting the thickness of the gate electrode 05 to 50 nm or more and 100 nm or less, it is possible to prevent disconnection of a semiconductor layer or a wiring to be formed later. In addition, by setting the thickness of the gate electrode 05 to 150 nm or more and 300 nm or less, the resistance of the gate electrode 05 can be reduced and the area of the substrate can be increased.

Note that since a semiconductor layer and a wiring are formed over the gate electrode 05, it is desirable that the end portion be tapered so as to prevent disconnection. Although not shown, a wiring connected to the gate electrode and a capacitor wiring can be formed at the same time in this step.

Each of the gate insulating layers 09a and 09b can be formed using a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer with a thickness of 50 to 150 nm. Here, a silicon nitride layer or a silicon nitride oxide layer is formed as the gate insulating layer 09a, and a silicon oxide layer or a silicon oxynitride layer is formed and stacked as the gate insulating layer 09b. Note that the gate insulating layer can be formed as a single layer of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer without using two gate insulating layers.

When the gate insulating layer 09a is formed using a silicon nitride layer or a silicon nitride oxide layer, adhesion between the substrate 01 and the gate insulating layer 09a is increased. When a glass substrate is used as the substrate 01, impurities from the substrate 01 However, it is possible to prevent diffusion into the semiconductor layer 51, the buffer layer 53, and the amorphous semiconductor layers 55 and 57 to which the impurity element serving as an acceptor is added, and further, the gate electrode 05 can be prevented from being oxidized. is there. That is, film peeling can be prevented and electrical characteristics of a thin film transistor to be formed later can be improved. In addition, it is preferable that the gate insulating layers 09a and 09b each have a thickness of 50 nm or more because reduction in coverage due to unevenness of the gate electrode 05 can be reduced.

Note that since the channel length of the thin film transistor can be shortened in accordance with this embodiment mode, it is preferable to reduce the thickness of the gate insulating layer so that a short channel effect is not generated in the thin film transistor.

Here, the silicon oxynitride layer has a higher oxygen content than nitrogen, and has Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS). ) In the range of 50 to 70 atomic% for oxygen, 0.5 to 15 atomic% for nitrogen, 25 to 35 atomic% for Si, and 0.1 to 10 atomic% for hydrogen. It means what is included. In addition, the silicon nitride oxide layer has a nitrogen content higher than that of oxygen as a composition. When measured using RBS and HFS, the composition range is 5 to 30 atomic% oxygen, nitrogen. In the range of 20 to 55 atomic%, Si in the range of 25 to 35 atomic%, and hydrogen in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, Si, and hydrogen is included in the above range.

The pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added may be formed by adding phosphorus as a typical impurity element when an n-channel thin film transistor is formed. An impurity gas such as PH ₃ may be added. In the case of forming a p-channel thin film transistor, boron may be added as a typical impurity element, and an impurity gas such as B ₂ H ₆ may be added to silicon hydride. By setting the concentration of phosphorus or boron to 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ , ohmic contact with the wirings 63 and 65 is possible and functions as a source region and a drain region. The pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added can be formed using a microcrystalline semiconductor layer or an amorphous semiconductor layer. The pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added are formed to a thickness of 10 nm to 100 nm, preferably 30 nm to 50 nm. By reducing the thickness of the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added, throughput can be improved.

The wirings 63 and 65 are formed of a single layer or a laminated layer of aluminum, copper, or an aluminum alloy to which a migration prevention element, a heat resistance improvement element, or a hillock prevention element is added, such as copper, silicon, titanium, neodymium, scandium, or molybdenum It is preferable to do. In addition, a layer in contact with the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added is formed using titanium, tantalum, molybdenum, tungsten, or a nitride of these elements. A laminated structure in which aluminum or an aluminum alloy is formed may be used. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed. Here, as the wirings 63 and 65, a stacked conductive layer of a titanium layer, an aluminum layer, and a titanium layer can be used.

In addition, in the thin film transistor illustrated in FIG. 1A, the pair of impurity semiconductor layers 59 and 61 to which the amorphous semiconductor layers 55 and 57 are not in contact with the wirings 63 and 65 and an impurity element imparting one conductivity type is added. In the structure shown in FIG. 1B, the side surfaces of the amorphous semiconductor layers 55 and 57 are in contact with the wirings 63 and 65. It can be.

In the thin film transistor of this embodiment, in order to increase on-state current, the length of the amorphous semiconductor layer inserted between the source region and the drain region in the channel length direction is set by the thickness of the amorphous semiconductor layer. . This makes it possible to create a nanometer-sized fine structure in a thin film transistor in a self-aligning manner without using photolithographic techniques to align the photomask with submicron level accuracy.

That is, the channel length of a thin film transistor in which at least one amorphous semiconductor layer substantially becomes a channel formation region is determined by the film thickness of the amorphous semiconductor layer, and is a nanometer-level length as described above. In the thin film transistor of this embodiment, a manufacturing process is performed based on a design rule of several micron level, and a deep submicron thin film transistor is formed at the same time, so that a sufficient on current flows while reducing an off current. In addition, the thin film transistor can be operated at high speed.

Further, since the buffer layer 53 is thick, in the case of a channel-etched thin film transistor, even if the amorphous semiconductor layer is over-etched when the source region, the drain region, and the wiring are etched, the film thickness is large. Since the buffer layer 53 is formed, the channel formation region is not divided and the yield can be improved. In addition, since the buffer layer 53 is thick, leakage current flowing from the source region and the drain region to the semiconductor layer 51 to which the impurity element serving as an acceptor is added can be reduced. For this reason, off-current can be reduced.

Further, in addition to the gate insulating layer, an amorphous semiconductor is interposed between the gate electrode 05 and the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type that functions as a source region and a drain region is added. Layers 55 and 57 are formed, and a gap between the gate electrode 05 and the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added is widened. Thus, parasitic capacitance generated between the gate electrode 05 and the pair of impurity semiconductor layers 59 and 61 to which the impurity element imparting one conductivity type is added can be reduced. In particular, the thin film transistor can reduce a voltage drop on the drain side. For this reason, the display device using the structure can improve the response speed of the pixel. In particular, in the case of a thin film transistor formed in a pixel of a liquid crystal display device, the voltage drop of the drain voltage can be reduced, so that the response speed of the liquid crystal material can be increased.

(Embodiment 2)
In this embodiment mode, other shapes of the semiconductor layer 51 and the buffer layer 53 to which an impurity element serving as an acceptor is added are described with reference to FIGS.

The thin film transistor illustrated in FIG. 2A has a cross-sectional structure in which the sidewalls of the semiconductor layer 51a and the buffer layer 53a to which an impurity element serving as an acceptor is added are substantially vertical, or the side surface has an inclination angle of 80 to 100 °, preferably 85 to It is a thin film transistor which is 95 °. By making the sidewalls of the semiconductor layer 51a to which the impurity element to be an acceptor is added and the buffer layer 53a substantially vertical, the area occupied by the thin film transistor can be reduced. Therefore, the aperture ratio of a transmissive display device using the thin film transistor for a pixel can be increased.

FIG. 2B illustrates a thin film transistor in which a buffer layer 53b is formed inside a semiconductor layer 51b to which an impurity element serving as an acceptor is added. That is, in the thin film transistor in which the buffer layer 53b having a smaller area of the semiconductor layer 51b to which the impurity element to be an acceptor is added is formed and a part of the semiconductor layer 51b to which the impurity element to be an acceptor is added is exposed from the buffer layer 53b. is there. With such a structure, when the semiconductor layer 51b to which the impurity element serving as an acceptor is added is a microcrystalline semiconductor layer, the amorphous semiconductor layer in contact with the microcrystalline semiconductor layer using the microcrystalline semiconductor layer as a crystal growth nucleus Since the crystallinity of 55 and 56 can be increased, the thin film transistor can be operated at high speed, and the on-state current can be increased.

This embodiment can be combined with any of the other embodiments.

(Embodiment 3)
In this embodiment mode, another mode of the buffer layer is shown with reference to FIGS. In this embodiment mode, the buffer layer 52 is formed using an insulating layer.

In the thin film transistor illustrated in FIG. 3A, a gate electrode 05 is formed over a substrate 01, gate insulating layers 09a and 09b are formed over the gate electrode 05, and an impurity element serving as an acceptor is formed over the gate insulating layers 09a and 09b. Is added, and a buffer layer 52 is formed over the semiconductor layer 51 to which an impurity element serving as an acceptor is added. The buffer layer 52 is provided so as to substantially overlap the semiconductor layer 51 to which an impurity element serving as an acceptor is added. In addition, a pair of amorphous semiconductor layers 55 and 57 are formed to cover the side surfaces of the semiconductor layer 51 and the buffer layer 52 to which an impurity element serving as an acceptor is added. One conductivity type is formed on the pair of amorphous semiconductor layers 55 and 57. A pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting is added is formed, and wirings 63 and 65 are formed over the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added. One end portion of the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added overlaps with the buffer layer 53.

In this embodiment mode, the buffer layer 52 is formed using an insulating layer. Typically, the buffer layer 52 is formed using a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, a silicon oxynitride layer, or another inorganic insulating layer. Alternatively, polyimide, acrylic resin, epoxy resin, or another organic insulating layer is used. Further, the thickness of the buffer layer 52 is set to 500 to 3000 nm. By forming the buffer layer 52 with a thick thickness and an insulating layer, leakage current flows from the pair of impurity semiconductor layers 59 and 61 to which the impurity element imparting one conductivity type is added to the amorphous semiconductor layers 55 and 57. Can be blocked by the buffer layer 52, so that leakage current can be reduced. In addition, off-state current can be reduced.

As shown in FIG. 3B, a buffer layer 53 formed of a semiconductor layer is formed over the semiconductor layer 51 to which an impurity element serving as an acceptor is added, and a buffer formed of an insulating layer over the buffer layer 53. Layer 54 is formed. The buffer layer 54 is formed using a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, a silicon oxynitride layer, or another inorganic insulating layer. Alternatively, polyimide, acrylic resin, epoxy resin, or another organic insulating layer is used.

In FIG. 3B, the buffer layer 53 formed of a semiconductor layer is thicker than the buffer layer 54 formed of an insulating layer, but the buffer layer 54 may be thicker than the buffer layer 53. . Note that the total film thickness of the buffer layer 53 and the buffer layer 54 is set to 500 nm to 3000 nm. By forming the buffer layer 53 formed of a semiconductor layer over the semiconductor layer 51 to which the impurity element that serves as an acceptor is added, oxidation of the semiconductor layer 51 to which the impurity element that serves as an acceptor is added can be reduced. It is possible to suppress a decrease in resistivity of the semiconductor layer 51 to which the impurity element to be added is added. Further, by providing the buffer layer 54 formed of an insulating layer over the buffer layer 53 formed of a semiconductor layer, an amorphous structure is formed from a pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added. Since the leak current flowing through the semiconductor layers 55 and 57 can be blocked by the buffer layer 54, the leak current can be reduced. In addition, off-state current can be reduced.

This embodiment can be combined with any of the other embodiments.

(Embodiment 4)
In this embodiment mode, another mode of the semiconductor layer 51 to which an impurity element which serves as an acceptor is added is shown.

The thin film transistor illustrated in FIG. 4 includes a semiconductor crystal in which a gate electrode 05 is formed over a substrate 01, gate insulating layers 09a and 09b are formed over the gate electrode 05, and an impurity element serving as an acceptor is added over the gate insulating layer 09b. Grains 56 are formed, and a buffer layer 53 is formed over the semiconductor crystal grains 56 to which an impurity element serving as an acceptor is added and the gate insulating layers 09a and 09b. The buffer layer 53 is provided so as to substantially overlap with the semiconductor crystal grains 56 to which an impurity element serving as an acceptor is added. In addition, a pair of amorphous semiconductor layers 55 and 57 covering the side surfaces of the buffer layer 53 are formed, and a pair of impurity semiconductors in which an impurity element imparting one conductivity type is added to the pair of amorphous semiconductor layers 55 and 57. Layers 59 and 61 are formed, and wirings 63 and 65 are formed over the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added. One end portion of the pair of impurity semiconductor layers to which the impurity element imparting one conductivity type is added overlaps with the buffer layer 53.

The semiconductor crystal grain 56 to which the impurity element serving as an acceptor is added can be formed using silicon or silicon germanium (Si _x Ge _1-x , 0.5 <x <1) containing more silicon than germanium. When the size of the semiconductor crystal grains 56 to which the impurity element serving as an acceptor is added is 1 to 30 nm and the density is less than 1 × 10 ¹³ / cm ² , preferably less than 1 × 10 ¹⁰ / cm ² , separated crystals Grains can be formed and adhesion between the buffer layer 53 and the gate insulating layer 09b to be formed later can be improved. Therefore, the yield of thin film transistors can be increased.

As a method for forming the semiconductor crystal grains 56 to which the impurity element that serves as an acceptor is added, a microcrystalline semiconductor layer that is doped with the impurity element that serves as an acceptor is formed by a sputtering method or a plasma CVD method, and then the impurity element that serves as an acceptor is added. By exposing the microcrystalline semiconductor layer to hydrogen plasma and etching the amorphous semiconductor component of the semiconductor crystal layer to which the acceptor impurity element is added, semiconductor crystal grains 56 to which the acceptor impurity element is added are formed. be able to. Alternatively, an acceptor can be obtained by forming a microcrystalline semiconductor layer or a crystalline semiconductor layer to which an impurity element serving as an acceptor is added with a thickness in which crystal grains are dispersed without being continuous, by a sputtering method or a plasma CVD method. Semiconductor crystal grains 56 to which an impurity element is added can be formed.

Further, instead of the semiconductor crystal grain 56 to which the impurity element to be an acceptor is added, a semiconductor layer to which the impurity element to be an acceptor is added is formed over the gate insulating layer 09b, and then a resist mask formed by a photolithography process is used. The semiconductor layer to which the impurity element serving as an acceptor is added may be etched to form a semiconductor layer to which the separated impurity element serving as an acceptor is added.

This embodiment can be combined with any of the other embodiments.

(Embodiment 5)
In this embodiment mode, another mode of a thin film transistor structure is shown.

In the thin film transistor shown in FIG. 5, a gate electrode 05 is formed over a substrate 01, gate insulating layers 09a and 09b are formed over the gate electrode 05, and an impurity element serving as an acceptor is added over the gate insulating layers 09a and 09b. Semiconductor layers 51, 51f, and 51g are formed, and buffer layers 53, 53f, and 53g are formed over the semiconductor layers 51, 51f, and 51g to which an impurity element serving as an acceptor is added. The buffer layers 53, 53f, and 53g are provided so as to substantially overlap with the semiconductor layer 51 to which an impurity element serving as an acceptor is added. In addition, a pair of amorphous semiconductor layers 55 and 57 covering the side surfaces of the semiconductor layers 51, 51f, and 51g to which the impurity element to be an acceptor is added and the buffer layers 53, 53f, and 53g are formed, and the pair of amorphous semiconductor layers is formed. A pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added are formed on 55 and 57, and wiring is formed on the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added. 63 and 65 are formed. One end portion of the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added overlaps with the buffer layer 53. In addition, a stack of the semiconductor layer 51 and the buffer layers 53, 53f, and 53g to which the impurity element to be an acceptor is added, a stack of the semiconductor layer 51f and the buffer layer 53f to which the impurity element to be an acceptor is added, and an impurity element to be the acceptor. The stacked layers of the added semiconductor layer 51g and buffer layer 53g are separated from each other.

In the thin film transistor illustrated in FIG. 6, a gate electrode 05 is formed over a substrate 01, gate insulating layers 09a and 09b are formed over the gate electrode 05, and an impurity element serving as an acceptor is added over the gate insulating layers 09a and 09b. The semiconductor layer 51e is formed in a ring shape, and the buffer layer 53e is formed in a ring shape over the semiconductor layer 51e to which an impurity element serving as an acceptor is added. The buffer layer 53 is provided so as to substantially overlap with the semiconductor layer 51e to which an impurity element serving as an acceptor is added. In addition, a pair of amorphous semiconductor layers 55 and 57 are formed to cover the side surfaces of the semiconductor layer 51e to which the impurity element serving as an acceptor is added and the buffer layer 53e. A pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added are formed over the pair of amorphous semiconductor layers 55 and 57, and a pair of impurities to which an impurity element imparting one conductivity type is added. Wirings 63 and 65 are formed on the semiconductor layers 59 and 61. One end portion of the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added overlaps with the buffer layer 53e. The thin film transistor illustrated in FIG. 6 is characterized in that a channel formation region where a source region and a drain region face each other is circular.

Note that one of the pair of amorphous semiconductor layers 55 and 57 and one of the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added are annular, and the pair of amorphous semiconductor layers 55 and 57 and the other 61 of the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added are circular. That is, one of the source region and the drain region surrounds the other of the source region and the drain region with a certain interval. Therefore, in the case where the wiring 63 is a source wiring and the wiring 65 is a drain wiring, if the channel formation region is curved, fluctuation in threshold voltage can be reduced, and reliability of characteristics of the thin film transistor can be reduced. Can be increased. In addition, compared with a typical thin film transistor in which the source wiring and the drain wiring are linear, when the source region and the drain region are curved, their opposing areas are increased. Therefore, a thin film transistor having the same channel width is designed. The area of the thin film transistor can be reduced.

This embodiment can be combined with any of the other embodiments.

(Embodiment 6)
In this embodiment, a manufacturing process of a thin film transistor which can operate at high speed, has high on-state current, and low off-state current as illustrated in FIG.

A thin film transistor including an amorphous semiconductor layer or a microcrystalline semiconductor layer is more suitable for use in a driver circuit because an n-type thin film transistor has higher field-effect mobility than a p-type. In order to reduce the number of steps, it is desirable to arrange all thin film transistors formed on the same substrate to have the same conductivity type. Here, description is made using an n-channel thin film transistor.

A manufacturing process of the thin film transistor illustrated in FIG. 1A will be described with reference to FIGS. 7 and 8, the left side is a cross-sectional view taken along line AB in FIG. 10, showing a cross section of a region where a thin film transistor is formed, and the right side is a cross-sectional view taken along line CD in FIG. The cross section of the area | region where wiring and source wiring cross | intersect is shown.

As shown in FIG. 7A, a conductive layer 03 is formed over the substrate 01. The conductive layer 03 can be formed using any of the materials listed for the gate electrode 05 described in Embodiment 1. The conductive layer 03 is formed by a sputtering method, a CVD method, a plating method, a printing method, a droplet discharge method, or the like.

Next, the conductive layer 03 is etched into a desired shape using a resist mask formed by a photolithography process using a first photomask, so that the gate wiring 05 is formed as shown in FIG. Form. Thereafter, the resist mask is removed.

Next, a gate insulating layer 09 is formed over the gate wiring 05 and the substrate 01. The gate insulating layer 09 can be formed using the materials listed in the gate insulating layers 09a and 09b described in Embodiment 1. The gate insulating layer 09 is formed using a CVD method, a sputtering method, or the like.

Next, the semiconductor layer 11 to which an impurity element serving as an acceptor is added and the buffer layer 13 are stacked over the gate insulating layer 09. A method for forming the semiconductor layer 11 to which an impurity element serving as an acceptor is added is described below.

A deposition gas containing silicon or germanium and hydrogen are mixed in a reaction chamber of a plasma CVD apparatus, and a microcrystalline semiconductor layer is formed by glow discharge plasma. The microcrystalline semiconductor layer is formed by diluting the flow rate of hydrogen 10 to 2000 times, preferably 50 to 200 times the flow rate of the deposition gas containing silicon or germanium. The heating temperature of the substrate is 100 ° C to 300 ° C, preferably 120 ° C to 220 ° C. In addition, by mixing a gas containing boron together with the source gas, the semiconductor layer 11 to which an impurity element serving as an acceptor is added can be formed. Here, diborane is mixed with silane and hydrogen and / or a rare gas, and a microcrystalline silicon layer containing boron can be formed as the semiconductor layer 11 to which an impurity element serving as an acceptor is added by glow discharge plasma.

In the process of forming the semiconductor layer 11 to which the impurity element serving as an acceptor is added, generation of glow discharge plasma is performed in a HF (high frequency) band from about 3 MHz to about 30 MHz, typically high frequency power of 13.56 MHz and 27.12 MHz, Alternatively, it is performed by applying high-frequency power in the VHF band from 30 MHz to about 300 MHz, typically 60 MHz.

Typical examples of the deposition gas containing silicon or germanium include SiH ₄ , Si ₂ H ₆ , GeH ₄ , and Ge ₂ H ₆ .

Note that, instead of forming the semiconductor layer 11 to which the impurity element to be an acceptor is added, an insulating layer to which the impurity element to be an acceptor is added is formed as the gate insulating layer 09, and the semiconductor that does not contain the impurity element to be an acceptor is formed thereover A layer may be formed. For example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or the like containing an impurity element (boron) serving as an acceptor can be formed as the gate insulating layer. In the case where the gate insulating layer 09 has a stacked structure, an impurity element serving as an acceptor may be added to the layer in contact with the microcrystalline semiconductor layer or the layer in contact with the substrate 01.

As a method for forming an insulating layer to which an impurity element serving as an acceptor is added as the gate insulating layer 09, an insulating layer may be formed using a gas containing an impurity element serving as an acceptor together with a source gas for the insulating layer. For example, boron nitride-containing silicon nitride can be formed by a plasma CVD method using silane, ammonia, and diborane. Further, a silicon oxynitride layer containing boron can be formed by a plasma CVD method using silane, dinitrogen monoxide, ammonia, and diborane.

Alternatively, before the gate insulating layer 09 is formed, a gas containing an impurity element serving as an acceptor may be flowed into the reaction chamber of the deposition apparatus so that the impurity element serving as the acceptor is adsorbed on the surface of the substrate 01 and the reaction chamber wall. After that, by forming the gate insulating layer 09, the insulating layer is deposited while the impurity element serving as the acceptor is taken in, and thus the insulating layer to which the impurity element serving as the acceptor is added can be formed.

In addition, before forming the semiconductor layer 11 to which the impurity element serving as an acceptor is added, a gas containing the impurity element serving as an acceptor is flowed into the reaction chamber of the deposition apparatus, and the impurity serving as the acceptor is supplied to the gate insulating layer 09 and the reaction chamber wall. Elements may be adsorbed. After that, by depositing the semiconductor layer, the microcrystalline semiconductor layer is deposited while the impurity element serving as the acceptor is taken in, so that the semiconductor layer 11 to which the impurity element serving as the acceptor is added can be formed.

Note that in the case where the gate insulating layer 09 is a silicon oxide layer or a silicon oxynitride layer, the surface of the gate insulating layer 09 may be subjected to plasma treatment before the semiconductor layer 11 to which the impurity element serving as an acceptor is added is formed. . Typically, plasma such as hydrogen plasma, ammonia plasma, H ₂ O plasma, helium plasma, argon plasma, or neon plasma is exposed to the surface of the gate insulating layer 09. As a result, defects on the surface of the gate insulating layer can be reduced. Typically, dangling bonds on the surface of the gate insulating layer 09 can be terminated. After that, when a semiconductor layer to which an impurity element to be an acceptor is added is formed, defects at the interface of the semiconductor layer to which the impurity element to be an acceptor is added can be reduced. As a result, carrier capture due to defects can be reduced, and on-state current can be increased.

Next, the buffer layer 13 is formed. In the case of forming a semiconductor layer as the buffer layer 13, an amorphous semiconductor layer can be formed by a plasma CVD method using a deposition gas containing silicon or germanium. Alternatively, an amorphous semiconductor layer can be formed by diluting a deposition gas containing silicon or germanium with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon. Alternatively, an amorphous semiconductor layer containing hydrogen can be formed using hydrogen at a flow rate of 0 to 10 times, more preferably 1 to 5 times the flow rate of the silane gas. Further, a halogen such as fluorine or chlorine may be added to the hydrogenated semiconductor layer.

The amorphous semiconductor layer can be formed by sputtering with hydrogen or a rare gas using a semiconductor target such as silicon or germanium as a target.

In the case where an insulating layer is formed as the buffer layer 13, it can be formed in the same manner as the gate insulating layer 09. Alternatively, an insulating layer can be formed by applying polyimide, an acrylic resin, an epoxy resin, or other raw materials for an organic insulating layer, and then baking.

In addition, it is preferable to form the buffer layer 13 at a temperature of 300 ° C. to 400 ° C. by a plasma CVD method after forming the semiconductor layer 11 to which an impurity element serving as an acceptor is added. By this film formation process, hydrogen is supplied to the semiconductor layer 11 to which the impurity element that serves as an acceptor is added, and an effect equivalent to that obtained by hydrogenating the semiconductor layer 11 to which the impurity element that serves as an acceptor is hydrogenated is obtained. That is, by depositing the buffer layer 13 on the semiconductor layer 11 to which the impurity element serving as an acceptor is added, hydrogen is diffused into the semiconductor layer 11 to which the impurity element serving as an acceptor is added, thereby terminating the dangling bond. Can do.

In the case where the semiconductor layer 11 to which the impurity element to be an acceptor is added is formed using a microcrystalline semiconductor layer, an amorphous semiconductor layer as a buffer layer 13 and further a hydrogen gas are formed on the surface of the semiconductor layer 11 to which the impurity element to be an acceptor is added. By forming an amorphous semiconductor layer containing nitrogen, or halogen, natural oxidation of the surface of crystal grains contained in the semiconductor layer 11 to which an impurity element serving as an acceptor is added can be prevented. In particular, in a region where an amorphous semiconductor is in contact with microcrystalline grains, cracks are likely to occur due to local stress. When this crack comes into contact with oxygen, the crystal grains are oxidized and silicon oxide is formed. However, by forming an amorphous semiconductor layer on the surface of the semiconductor layer 11 to which an impurity element serving as an acceptor is added, oxidation of microcrystalline grains can be prevented. Further, in a display device with a high applied voltage to the thin film transistor (for example, about 15 V), typically a liquid crystal display device, when the buffer layer is formed thick, the drain withstand voltage increases and a high voltage is applied to the thin film transistor. However, it is possible to avoid the deterioration of the thin film transistor.

Next, after applying a resist on the buffer layer 13, the buffer layer 13 and a semiconductor layer to which an impurity element serving as an acceptor is added using a resist mask formed by a photolithography process using a second photomask. 11 is etched into a desired shape, and as shown in FIG. 7C, a semiconductor layer 15 to which an impurity element serving as an acceptor is added and a buffer layer 19 are formed in a region where a thin film transistor is formed. In addition, in the region where the gate wiring and the source wiring intersect, the semiconductor layer 17 to which an impurity element serving as an acceptor is added and the buffer layer 21 are formed. Thereafter, the resist mask is removed.

Next, as illustrated in FIG. 7D, an amorphous semiconductor layer 23 and an impurity semiconductor layer 25 to which an impurity element imparting one conductivity type is added are formed.

The amorphous semiconductor layer 23 can be formed in the same manner as when the buffer layer 13 is formed using a semiconductor layer.

Note that when the amorphous semiconductor layer 23 is formed, a silicon nitride oxide layer, a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer is precoated on the deposition chamber wall of the plasma CVD apparatus, and then deposition including silicon or germanium is performed. When the semiconductor layer is formed by diluting the hydrogen flow rate 10 to 2000 times, preferably 50 to 200 times the flow rate of the reactive gas, the film is taken in while oxygen, nitrogen, etc. in the film formation chamber wall are taken into the film. Therefore, a dense amorphous semiconductor layer can be formed without being crystallized. Note that the semiconductor layer may include microcrystal. In the case where the gate insulating layer 09 is a silicon nitride layer, the amorphous semiconductor layer is formed by the deposition method, so that the film is not peeled off and the yield can be increased.

Here, a plasma CVD method using a deposition gas containing silicon or germanium and phosphine is used as the impurity semiconductor layer 25 to which an impurity element imparting one conductivity type is added in order to form an n-channel thin film transistor. To form. In the case of forming a p-channel thin film transistor, the p-channel thin film transistor is formed by a plasma CVD method using a deposition gas containing silicon or germanium and diborane.

In the step of forming the semiconductor layer 11 to which the impurity element serving as an acceptor is added, the buffer layer 13, the amorphous semiconductor layer 23, and the impurity semiconductor layer 25 to which the impurity element imparting one conductivity type is added, generation of glow discharge plasma is performed. HF band from 3 MHz to about 30 MHz, typically high frequency power of 13.56 MHz, 27.12 MHz, or high frequency power of VHF band from 30 MHz to about 300 MHz, typically 60 MHz is applied. .

The conductive layer 27 can be formed using the materials listed in the wirings 63 and 65 described in Embodiment 1. The conductive layer 27 is formed using a CVD method, a sputtering method, a printing method, a droplet discharge method, or the like.

Next, a resist is applied on the conductive layer 27. As the resist, a positive resist or a negative resist can be used. Here, a positive resist is used.

Next, using a multi-tone mask as a third photomask, the resist is irradiated with light and then developed to form a resist mask 29.

Here, exposure using a multi-tone mask will be described with reference to FIG.

A multi-tone mask is a mask capable of performing three exposure levels on an exposed portion, an intermediate exposed portion, and an unexposed portion, and a plurality of (typically two types) can be obtained by one exposure and development process. It is possible to form a resist mask having a region with a thickness of. Therefore, the number of photomasks can be reduced by using a multi-tone mask.

Typical examples of the multi-tone mask include a gray-tone mask 159a as shown in FIG. 9A and a half-tone mask 159b as shown in FIG. 9C.

As shown in FIG. 9A, the gray tone mask 159a includes a light-transmitting substrate 163, a light shielding portion 164 and a diffraction grating 165 formed thereon. In the light shielding portion 164, the light transmittance is 0%. On the other hand, the diffraction grating 165 can control the light transmittance by setting the interval between the light transmitting portions such as slits, dots, and meshes to be equal to or less than the resolution limit of light used for exposure. Note that the diffraction grating 165 can use either a periodic slit, a dot, or a mesh, or an aperiodic slit, dot, or mesh.

As the substrate 163 having a light-transmitting property, a substrate having a light-transmitting property such as quartz can be used. The light shielding portion 164 and the diffraction grating 165 can be formed using a light shielding material that absorbs light such as chromium or chromium oxide.

When the gray-tone mask 159a is irradiated with exposure light, as shown in FIG. 9B, the light transmittance 166 is 0% in the light shielding portion 164, and the light shielding portion 164 and the diffraction grating 165 are not provided. In the region, the light transmittance 166 is 100%. The diffraction grating 165 can be adjusted in the range of 10 to 70%. The light transmittance of the diffraction grating 165 can be adjusted by adjusting the interval and pitch of slits, dots, or meshes of the diffraction grating.

As shown in FIG. 9C, the halftone mask 159b includes a light-transmitting substrate 163, a semi-transmissive portion 167 and a light-shielding portion 168 formed thereon. For the semi-transmissive portion 167, MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like can be used. The light shielding portion 168 can be formed using a light shielding material that absorbs light, such as chromium or chromium oxide.

When the halftone mask 159b is irradiated with exposure light, as shown in FIG. 9D, the light transmittance 169 is 0% in the light shielding portion 168, and the light shielding portion 168 and the semi-transmissive portion 167 are provided. In the absence region, the light transmittance 169 is 100%. Moreover, in the semi-transmissive part 167, it can adjust in 10 to 70% of range. The light transmittance in the semi-transmissive portion 167 can be adjusted by adjusting the material of the semi-transmissive portion 167.

By performing development after exposure using a multi-tone mask, a resist mask 29 having regions with different thicknesses can be formed as shown in FIG. 7D.

Next, the amorphous semiconductor layer 23, the impurity semiconductor layer 25 to which an impurity imparting one conductivity type is added, and the conductive layer 27 are etched and separated by the resist mask 29. As a result, amorphous semiconductor layers 33 and 35, semiconductor layers 37 and 39 to which an impurity imparting one conductivity type is added, and a conductive layer 41 as illustrated in FIG. 7E can be formed.

  Next, the resist mask 29 is ashed. As a result, the resist area is reduced and the thickness is reduced. At this time, the resist in a thin region (a region overlapping with part of the gate wiring 05) is removed, and a separated resist mask 45 can be formed as illustrated in FIG.

Next, the conductive layer 41 is etched and separated using the resist mask 45. As a result, the source wiring 63 and the drain electrode 65 as shown in FIG. 8E can be formed. When the conductive layer 41 is wet-etched using the resist mask 45, the end portion of the conductive layer 41 is selectively etched. As a result, the source wiring 63 and the drain electrode 65 having a smaller area than the resist mask 45 can be formed.

At the intersection of the gate wiring 05 and the impurity semiconductor layer 39 to which the impurity element imparting one conductivity type is added, in addition to the gate insulating layer 09, the semiconductor layer 17 to which the impurity element to be an acceptor is added, the buffer layer 21, and An amorphous semiconductor layer 35 is formed, and a gap between the gate wiring 05 and the impurity semiconductor layer 39 to which an impurity element imparting one conductivity type is added is widened. Therefore, parasitic capacitance in a region where the gate wiring 05 and the impurity semiconductor layer 39 to which an impurity element imparting one conductivity type is added can be reduced.

Next, the semiconductor layer 37 to which an impurity imparting one conductivity type is added is etched using the resist mask 45 to form a pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added. To do. Note that in the etching step, part of the amorphous semiconductor layer 33 is also etched to form a pair of amorphous semiconductor layers 55 and 57. In addition, a part of the buffer layer is etched. A partially etched buffer layer is referred to as a buffer layer 53. A concave portion is formed in the buffer layer 53. The step of forming the source region and the drain region and the concave portion of the buffer layer 53 can be formed in the same step.

Here, the end portions of the source wiring 63 and the drain electrode 65 and the end portions of the pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added are not aligned with each other. Outside the end portion of the drain electrode 65, end portions of a pair of impurity semiconductor layers 59 and 61 to which an impurity element imparting one conductivity type is added are formed. Thereafter, the resist mask 45 is removed.

Next, the exposed buffer layer 53 may be irradiated with H ₂ O plasma. Typically, radicals generated by discharging vaporized water using plasma are a buffer layer 53, a pair of amorphous semiconductor layers 55 and 57, and a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added. By irradiating the exposed portions of 59 and 61, the source wiring 63, and the drain electrode 65, the thin film transistor can be operated at high speed, and the on-current can be further increased. In addition, off-state current can be reduced.

Through the above process, a thin film transistor can be formed.

Next, as illustrated in FIG. 8B, the protective insulating layer 67 is formed over the source wiring 63, the drain electrode 65, and the gate insulating layer 09. The protective insulating layer 67 can be formed using a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, or a silicon oxynitride layer. Note that the protective insulating layer 67 is for preventing entry of contaminant impurities such as organic substances, metal substances, and water vapor floating in the atmosphere, and is preferably a dense film.

Next, a planarization layer 69 may be formed over the protective insulating layer 67. The planarizing layer 69 can be formed using an organic insulating layer such as acrylic resin, polyimide, epoxy resin, or siloxane polymer. Here, the planarization layer 69 is formed using a photosensitive organic resin. Next, the planarizing layer 69 is exposed using a fourth photomask and then developed to expose the protective insulating layer 67 as shown in FIG. 8C. Next, the protective insulating layer 67 is etched using the planarizing layer 69 to form a contact hole exposing a part of the drain electrode 65.

Next, the pixel electrode 71 is formed in the contact hole. Here, after a conductive layer is formed over the planarization layer 69, a resist is applied over the conductive layer. Next, the conductive layer is etched using a resist mask formed by a photolithography process using a fifth photomask, so that the pixel electrode 71 is formed.

The pixel electrode 71 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, oxidation A light-transmitting conductive material such as indium tin oxide to which silicon is added can be used.

The pixel electrode 71 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

Here, as the pixel electrode 71, an ITO film is formed by a sputtering method, and then a resist is applied on the ITO. Next, the resist is exposed and developed using a sixth photomask to form a resist mask. Next, the ITO is etched using a resist mask to form the pixel electrode 71. Thereafter, the resist mask is removed. 8C corresponds to a cross-sectional view taken along AB and CD in FIG. The thin film transistor shown in FIG. 10 has a C-shaped (U-shaped) upper surface shape of a channel formation region where a source region and a drain region are opposed to each other. Also good.

Through the above steps, a thin film transistor with low off-state current, high on-state current, and high-speed operation can be manufactured. In addition, an element substrate having the thin film transistor as a switching element of a pixel electrode can be manufactured. Note that in this embodiment, as compared with a manufacturing process of a normal inverted staggered thin film transistor, there is one photomask for etching a semiconductor layer to which an impurity element serving as an acceptor and a buffer layer are etched into a predetermined shape. A multi-tone mask is used as a pair of amorphous semiconductor layers, a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, and a photomask for etching a wiring into a predetermined shape. Therefore, since the number of photomasks can be reduced by one in the process, the number of masks does not increase in the entire manufacturing process.

This embodiment can be combined with any of the other embodiments.

(Embodiment 7)
In this embodiment mode, high-speed operation is possible as compared with a thin film transistor including an amorphous semiconductor layer in a channel formation region as illustrated in FIG. 1B, high on-state current, and a microcrystalline semiconductor layer is formed. A manufacturing process of a thin film transistor whose off-state current is lower than that of a thin film transistor included in a channel formation region is described.

Note that the left side of FIG. 11 is a cross-sectional view taken along the line AB in FIG. 12, showing a cross-section of a region where a thin film transistor is formed, and the right side is a cross-sectional view taken along the line CD in FIG. The cross section of the area | region where wiring intersects is shown.

Through the process of FIG. 7A shown in Embodiment Mode 6, a gate wiring 05 is formed. Next, a gate insulating layer 09 is formed over the gate wiring 05 and the substrate 01.

Next, the semiconductor layer 11 to which an impurity element serving as an acceptor is added and the buffer layer 13 are sequentially stacked over the gate insulating layer 09 through the process of FIG. Next, a resist is applied on the buffer layer 13. Next, the semiconductor layer 11 to which the impurity element which serves as an acceptor is added and the buffer layer 13 are etched using a resist mask formed by a photolithography process, so that an impurity serving as an acceptor is formed as illustrated in FIG. Semiconductor layers 15 and 17 to which elements are added and buffer layers 19 and 21 are formed.

Next, an amorphous semiconductor layer 23 and an impurity semiconductor layer 25 to which an impurity element imparting one conductivity type is added are formed.

Next, using the resist mask formed by a photolithography process, the impurity semiconductor layer 25 to which the impurity element imparting one conductivity type is added and the amorphous semiconductor layer 23 are etched into a desired shape. As shown in FIG. 11B, an amorphous semiconductor layer 81 and an impurity semiconductor layer 83 to which an impurity element imparting one conductivity type is added are formed in a region where a thin film transistor is formed. In addition, in a region where the gate wiring and the source wiring intersect, an amorphous semiconductor layer 82 and an impurity semiconductor layer 84 to which an impurity element imparting one conductivity type is added are formed. Thereafter, the resist mask is removed. Note that side surfaces of the semiconductor layers 15 and 17 to which an impurity element serving as an acceptor is added are covered with the amorphous semiconductor layers 81 and 82.

Next, a conductive layer 27 is formed as shown in FIG.

Next, the conductive layer 27 is etched into a desired shape using a resist mask formed by a photolithography process, so that a source wiring 85 and a drain electrode 87 are formed as shown in FIG.

At the intersection of the gate wiring 05 and the source wiring 85, in addition to the gate insulating layer 09, the semiconductor layer 17, the buffer layer 21, and the amorphous semiconductor layer 82 to which an impurity element serving as an acceptor is added are formed. The distance between 05 and the source wiring 85 is increased. For this reason, the parasitic capacitance in the region where the gate wiring 05 and the source wiring 85 intersect can be reduced.

Next, the impurity semiconductor layer 83 to which the impurity element imparting one conductivity type is added is etched using a resist mask to form a pair of impurity semiconductor layers 91 and 93 to which the impurity element imparting one conductivity type is added. . In the etching step, the amorphous semiconductor layer 81 is also etched to form a pair of amorphous semiconductor layers 95 and 97. Further, a part of the buffer layer 19 is also etched. A buffer layer that is partially etched and has a recess is referred to as a buffer layer 99. The step of forming the source region and the drain region and the concave portion of the buffer layer 99 can be formed in the same step. Thereafter, the resist mask is removed.

Next, the exposed buffer layer 53 may be irradiated with H ₂ O plasma. Typically, radicals generated by discharging vaporized water using plasma are a buffer layer 99, a pair of amorphous semiconductor layers 95 and 97, and a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added. By irradiating the exposed portions of 91 and 93, the source wiring 85, and the drain electrode 87, the thin film transistor can be operated at high speed, and the on-current can be further increased. In addition, off-state current can be reduced.

Through the above steps, a thin film transistor that can operate at high speed, has high on-state current, and low off-state current is formed.

Next, through the steps shown in FIGS. 8B and 8C, as shown in FIG. 11E, the protective insulating layer 67, the planarization layer 69, and the pixel electrode 71 connected to the drain electrode are formed. Form. Note that FIG. 11E corresponds to a cross-sectional view taken along a line AB and a line CD in FIG. The thin film transistor shown in FIG. 12 has a C-shaped (U-shaped) upper surface shape of a channel formation region where a source region and a drain region are opposed to each other. May be.

Through the above steps, a thin film transistor with low off-state current, high on-state current, and high-speed operation can be manufactured. In addition, an element substrate having the thin film transistor as a switching element of a pixel electrode can be manufactured.

This embodiment can be combined with any of the other embodiments.

(Embodiment 8)
In this embodiment mode, structures of a scanning line input terminal portion and a signal line input terminal portion provided in the periphery of the element substrate 300 illustrated in FIG. 13 are described below with reference to FIGS. FIG. 14 is a cross-sectional view of a thin film transistor in a scan line input terminal portion, a signal line input terminal portion, and a pixel portion provided in the peripheral portion of the substrate 01.

Note that in the case of an active matrix display device in which a thin film transistor that controls the potential of a pixel electrode is provided in a pixel provided in a pixel portion, a scanning line is connected to a gate electrode. Alternatively, part of the scan line functions as a gate electrode. Therefore, hereinafter, the scanning line is also referred to as a gate wiring 05. Since the signal line is connected to the source of the thin film transistor, the signal line is also referred to as a source wiring 63 hereinafter. However, when the signal line is connected to the drain of the thin film transistor, the signal line can be a drain wiring.

A pixel portion 301 is provided in the element substrate 300 illustrated in FIG. 13, and protection circuits 302 and 322, a signal line 323, and a scanning line 303 are provided between the pixel portion 301 and the peripheral portion of the substrate 01. Although not shown, signal lines and scanning lines are formed from the protection circuits 302 and 322 to the pixel portion 301. A signal line input terminal portion 326 and a scanning line input terminal portion 306 are provided at end portions of the signal line 323 and the scanning line 303. FPCs 324 and 304 are connected to terminals of the signal line input terminal portion 326 and the scanning line input terminal portion 306, respectively, and a signal line driving circuit 325 and a scanning line driving circuit 305 are provided in the FPCs 324 and 304, respectively. Although details are not shown in the pixel portion 301, the pixels 331 are arranged in a matrix.

In FIG. 14A, the scan line input terminal 306 a is connected to the gate wiring 05 of the thin film transistor 330. The signal line input terminal 326a is connected to the source wiring 63.

The scan line input terminal 306a and the signal line input terminal 326a are each formed using the same layer as the pixel electrode 71 of the thin film transistor 330 in the pixel portion. The scanning line input terminals 306 a and 326 a are formed on the planarization layer 69 formed on the source wiring 63. On the planarization layer 69, the scanning line input terminal 306 a and the signal line input terminal 326 a are connected to the wirings 309 and 329 of the FPCs 304 and 324 through the conductive particles 308 and 328 of the anisotropic conductive adhesives 307 and 327. Connected.

Note that although the gate wiring 05 and the scanning line input terminal 306a are connected here, a conductive layer formed using the same layer as the source wiring 63 may be provided between the gate wiring 05 and the scanning line input terminal 306a. .

In FIG. 14B, the scan line input terminal 306 b is connected to the gate wiring 05 of the thin film transistor 330. The signal line input terminal 326 b is connected to the source wiring 63 of the thin film transistor 330.

The scan line input terminal 306b and the signal line input terminal 326b are each formed using the same layer as the pixel electrode 71 of the thin film transistor 330 in the pixel portion. Further, the scan line input terminal 306 b and the signal line input terminal 326 b are formed over the planarization layer 69 and the protective insulating layer 67. Further, in the openings of the planarization layer 69 and the protective insulating layer 67, the scanning line input terminal 306b and the signal line input terminal 326b are connected to the FPC 304, the conductive particles 308 and 328 of the anisotropic conductive adhesives 307 and 327, respectively. 324 is connected to wirings 309 and 329.

The signal line input terminal 326b connected to the source wiring 63 is an impurity in which an amorphous semiconductor layer 35 and an impurity element imparting one conductivity type are added in addition to the gate insulating layer 09 between the substrate 01 and the source wiring 63. A semiconductor layer 39 is formed and the thickness is increased. For this reason, the connection between the signal line input terminal 326b and the wiring 329 of the FPC 324 becomes easy.

This embodiment can be combined with any of the other embodiments.

(Embodiment 9)
Next, a structure of a display panel which is one embodiment of the present invention is described below.

FIG. 15A shows a mode of a display panel in which only the signal line driver circuit 6013 is separately formed and connected to the pixel portion 6012 formed over the substrate 6011. The element substrate over which the pixel portion 6012, the protection circuit 6016, and the scan line driver circuit 6014 are formed is formed using the element substrate described in the above embodiment mode. A signal line that requires a higher driving frequency than a scanning line driver circuit by forming a signal line driver circuit with a thin film transistor that can obtain higher field-effect mobility than a thin film transistor that uses an amorphous semiconductor layer for a channel formation region The operation of the drive circuit can be stabilized. Note that the signal line driver circuit 6013 may be a transistor using a single crystal semiconductor for a channel formation region, a thin film transistor using a polycrystalline semiconductor for a channel formation region, or a transistor using SOI for a channel formation region. The transistor using SOI includes a transistor in which a single crystal semiconductor layer provided over a glass substrate is used for a channel formation region. The pixel portion 6012, the signal line driver circuit 6013, and the scan line driver circuit 6014 are supplied with a potential of a power source, various signals, and the like through the FPC 6015. A protective circuit 6016 formed using the thin film transistor described in the above embodiment may be provided between the signal line driver circuit 6013 and the FPC 6015 or between the signal line driver circuit 6013 and the pixel portion 6012. The protective circuit 6016 is provided with a protective circuit including one or a plurality of elements selected from a thin film transistor, a diode, a resistor, a capacitor, and the like instead of the protective circuit formed using the thin film transistor described in the above embodiment. May be.

Note that both the signal line driver circuit and the scan line driver circuit may be formed over the same substrate as the pixel portion.

In the case where a driver circuit is separately formed, the substrate on which the driver circuit is formed is not necessarily bonded to the substrate on which the pixel portion is formed, and may be bonded to, for example, an FPC. In FIG. 15B, only the signal line driver circuit 6023 is separately formed, and the element substrate on which the pixel portion 6022, the protection circuit 6026, and the scan line driver circuit 6024 formed over the substrate 6021 are connected to the FPC. The form of the display device panel is shown. The pixel portion 6022, the protection circuit 6026, and the scan line driver circuit 6024 are formed using the thin film transistor described in the above embodiment. The signal line driver circuit 6023 is connected to the pixel portion 6022 through the FPC 6025 and the protection circuit 6026. The pixel portion 6022, the signal line driver circuit 6023, and the scan line driver circuit 6024 are supplied with power supply potential, various signals, and the like through the FPC 6025. A protective circuit 6026 formed using the thin film transistor described in the above embodiment may be provided between the FPC 6025 and the pixel portion 6022. The protective circuit 6026 is provided with a protective circuit including one or more elements selected from a thin film transistor, a diode, a resistor, a capacitor, and the like instead of the protective circuit formed using the thin film transistor described in the above embodiment. May be.

Further, only part of the signal line driver circuit or part of the scan line driver circuit is formed over the same substrate as the pixel portion by using the thin film transistor described in the above embodiment mode, and the rest is separately formed to be electrically connected to the pixel portion. You may make it connect. In FIG. 15C, an analog switch 6033a included in the signal line driver circuit is formed over the same substrate 6031 as the pixel portion 6032 and the scan line driver circuit 6034, and a shift register 6033b included in the signal line driver circuit is provided over a different substrate. The form of the display device panel formed and bonded is shown. The pixel portion 6032, the protection circuit 6036, and the scan line driver circuit 6034 are formed using the thin film transistor described in the above embodiment. A shift register 6033 b included in the signal line driver circuit is connected to the pixel portion 6032 through an FPC 6035 and a protection circuit 6036. A potential of a power source, various signals, and the like are supplied to the pixel portion 6032, the signal line driver circuit, and the scan line driver circuit 6034 through the FPC 6035, respectively. A protective circuit 6036 formed using the thin film transistor described in the above embodiment may be provided between the shift register 6033b and the analog switch 6033a. The protective circuit 6036 is provided with a protective circuit including one or more elements selected from a thin film transistor, a diode, a resistor, a capacitor, and the like instead of the protective circuit formed using the thin film transistor described in the above embodiment. May be.

As shown in FIG. 15, in the display device of this embodiment, part or all of the driver circuit can be formed over the same substrate as the pixel portion using the thin film transistor described in the above embodiment.

Note that a method for connecting a separately formed substrate is not particularly limited, and a known COG method, wire bonding method, TAB method, or the like can be used. Further, the connection position is not limited to the position illustrated in FIG. 15 as long as electrical connection is possible. In addition, a controller, a CPU, a memory, and the like may be separately formed and connected.

Note that the signal line driver circuit used here includes a shift register and an analog switch. Alternatively, in addition to the shift register and the analog switch, other circuits such as a buffer, a level shifter, and a source follower may be included. The shift register and the analog switch are not necessarily provided. For example, another circuit that can select a signal line such as a decoder circuit may be used instead of the shift register, or a latch or the like may be used instead of the analog switch. May be.

This embodiment can be combined with any of the other embodiments.

(Embodiment 10)
The element substrate obtained by the present invention, a display device using the element substrate, and the like can be used for an active matrix display device panel. That is, the above-described embodiment can be implemented in all electronic devices in which they are incorporated in the display unit.

Such electronic devices include cameras such as video cameras and digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) ) And the like. An example of them is shown in FIG.

FIG. 16A illustrates a television device. As shown in FIG. 16A, a television device can be completed by incorporating a display panel into a housing. A main screen 2003 is formed by the display panel, and a speaker portion 2009, operation switches, and the like are provided as other accessory equipment. In this manner, a television device can be completed.

As shown in FIG. 16A, a display panel 2002 using a display element is incorporated in a housing 2001, and reception of general television broadcasts by a receiver 2005, as well as wired or wireless via a modem 2004. By connecting to a communication network, information communication can be performed in one direction (from a sender to a receiver) or in both directions (between a sender and a receiver, or between receivers). The television device can be operated by a switch incorporated in the housing or a separate remote controller 2006. The remote controller 2006 is also provided with a display unit 2007 for displaying information to be output. May be.

In addition, the television device may have a configuration in which a sub screen 2008 is formed using the second display panel in addition to the main screen 2003 to display a channel, a volume, and the like. In this configuration, the main screen 2003 may be formed using a liquid crystal display panel, and the sub screen may be formed using a light-emitting display panel. In order to give priority to lower power consumption, the main screen 2003 may be formed using a light-emitting display panel, the sub screen may be formed using a light-emitting display panel, and the sub screen may be blinkable.

FIG. 17 is a block diagram illustrating a main configuration of the television device. In the display panel 900, a pixel portion 921 is formed. The signal line driver circuit 922 and the scan line driver circuit 923 may be mounted on the display panel 900 by a COG method.

As other external circuit configurations, on the input side of the video signal, among the signals received by the tuner 924, the video signal amplification circuit 925 that amplifies the video signal, and the signal output therefrom is each of red, green, and blue And a control circuit 927 for converting the video signal into an input specification of the driver IC. The control circuit 927 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 928 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

Of the signals received by the tuner 924, the audio signal is sent to the audio signal amplification circuit 929, and the output is supplied to the speaker 933 through the audio signal processing circuit 930. The control circuit 931 receives control information on the receiving station (reception frequency) and volume from the input unit 932 and sends a signal to the tuner 924 and the audio signal processing circuit 930.

Of course, the present invention is not limited to a television device, and can be applied to various uses such as a personal computer monitor, an information display board at a railway station or airport, an advertisement display board in a street, etc. it can.

By using the element substrate described in the above embodiment and the display device including the element substrate in the main screen 2003 and the sub screen 2008, mass productivity of the television device with improved image quality such as contrast can be increased. .

FIG. 16B illustrates an example of a mobile phone 2301. The cellular phone 2301 includes a display portion 2302, an operation portion 2303, and the like. In the display portion 2302, by using the element substrate described in the above embodiment and a display device including the element substrate, mass productivity of mobile phones with improved image quality such as contrast can be improved.

A portable computer illustrated in FIG. 16C includes a main body 2401, a display portion 2402, and the like. By applying the element substrate described in any of the above embodiments and a display device including the element substrate to the display portion 2402, the mass productivity of a computer with improved image quality such as contrast can be increased.

FIG. 16D illustrates a table lamp, which includes a lighting unit 2501, an umbrella 2502, a variable arm 2503, a column 2504, a stand 2505, and a power source 2506. It is manufactured by using a light emitting device for the lighting portion 2501. The lighting fixture includes a ceiling-fixed lighting fixture or a wall-mounted lighting fixture. By applying the element substrate described in any of the above embodiments and a display device including the element substrate, mass productivity can be increased and an inexpensive desk lamp can be provided.

18A and 18B illustrate an example of a structure of a smartphone mobile phone to which the above embodiment is applied. FIG. 18A is a front view, FIG. 18B is a rear view, and FIG. The smart phone mobile phone includes two housings 1111 and 1112. A smart phone mobile phone has functions of both a mobile phone and a portable information terminal, has a built-in portable computer, and can perform various data processing in addition to voice calls.

The housing 1111 includes a display portion 1101, a speaker 1102, a microphone 1103, an operation key 1104, a pointing device 1105, a front camera lens 1106, an external connection terminal jack 1107, an earphone terminal 1108, and the like. 1201, an external memory slot 1202, a rear camera 1203, a light 1204, and the like. An antenna is incorporated in the housing 1111.

In addition to the above structure, a non-contact IC chip, a small recording device, or the like may be incorporated.

The housing 1111 and the housing 1112 that overlap with each other (FIG. 18A) slide and expand as illustrated in FIG 18C. The display device described in any of the above embodiments can be incorporated in the display portion 1101. The display direction can be changed as appropriate depending on the usage mode, and the video camera can be used because the display unit 1101 and the front camera lens 1106 are provided on the same surface. The rear camera 1203 and the light 1204 can shoot still images and moving images.

The speaker 1102 and the microphone 1103 can be used not only for voice calls but also for videophone calls, recording, and playback. With the operation keys 1104, making and receiving calls, inputting simple information such as e-mails, scrolling the screen, moving the cursor, and the like are possible.

Further, when there is a lot of information to be handled, such as creation of a document or use as a portable information terminal, it is convenient to use the keyboard 1201. Further, the housing 1111 and the housing 1112 (FIG. 18A) which are overlapped with each other are slid and developed as illustrated in FIG. 18C, and when the portable information terminal can be used, the keyboard 1201 and the pointing device 1105 are used. Smooth operation is possible. The external connection terminal jack 1107 can be connected to an AC adapter and various cables such as a USB cable, and charging and data communication with a personal computer or the like are possible. Further, a recording medium can be inserted into the external memory slot 1202 to cope with storing and moving a larger amount of data.

The rear surface of the housing 1112 (FIG. 18B) is provided with a rear camera 1203 and a light 1204, and a still image and a moving image can be taken using the display portion 1101 as a viewfinder.

Further, in addition to the above functional configuration, an infrared communication function, a USB port, a TV one-segment reception function, a non-contact IC chip, an earphone jack, and the like may be provided.

By applying the display device described in the above embodiment, mass productivity can be improved.

Claims (8)

A semiconductor layer to which an impurity element which serves as an acceptor overlaps with the gate electrode through the gate insulating layer;
A buffer layer provided over the semiconductor layer to which the impurity element serving as an acceptor is added; and
An amorphous semiconductor layer covering the upper surface of the buffer layer and the side surface of the semiconductor layer to which the buffer layer and the acceptor impurity element are added; and
A pair of impurity semiconductor layers to which an impurity element imparting one conductivity type that forms a source region and a drain region is added, the one end portion overlapping with the buffer layer, and provided on the amorphous semiconductor layer; A thin film transistor, wherein a thickness of the buffer layer is larger than a thickness of the amorphous semiconductor layer. 2. The concentration of the impurity element serving as an acceptor added to the semiconductor layer to which the impurity element serving as an acceptor is added is 5 × 10 ¹⁶ cm ⁻³ or more and 5 × 10 ¹⁹ cm ^−3. Thin film transistor.   3. The thin film transistor according to claim 1, wherein the semiconductor layer to which the impurity element serving as an acceptor is added is a microcrystalline semiconductor.   4. The thin film transistor according to claim 3, wherein the microcrystalline semiconductor is microcrystalline silicon.   5. The thin film transistor according to claim 1, wherein the amorphous semiconductor layer is amorphous silicon.   2. The thin film transistor according to claim 1, wherein the thickness of the buffer layer is larger than the thickness of each of the semiconductor layer to which the impurity element serving as an acceptor is added and the amorphous semiconductor layer.   2. The thin film transistor according to claim 1, wherein the buffer layer has a thickness of 500 nm to 3000 nm, and the amorphous semiconductor layer has a thickness of 50 nm to less than 500 nm.   A display device comprising the thin film transistor according to claim 1 provided in each pixel of a pixel portion.

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