JP2009224636A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2009224636A
JP2009224636A JP2008068778A JP2008068778A JP2009224636A JP 2009224636 A JP2009224636 A JP 2009224636A JP 2008068778 A JP2008068778 A JP 2008068778A JP 2008068778 A JP2008068778 A JP 2008068778A JP 2009224636 A JP2009224636 A JP 2009224636A
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wiring board
semiconductor device
package
layer
manufacturing
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Yoichi Matae
洋一 俣江
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method with a high yield suppressing a defect at a multi-layered connection position in manufacturing a multi-layer POP structure semiconductor device by multi-layering the semiconductor device in the state of a multiple patterning wiring substrate package, and thereafter cutting it by collective cutting. <P>SOLUTION: In multi-layering the multiple patterning wiring substrate package, a space filling layer 13 such as a thermally-curable resin is filled at least in inter-substrate spaces between division regions 9A of respective substrates, and thereafter the package is cut as multi-layer POP structure semiconductor devices with a dicing blade at the division regions 9A, whereby concentration of stress in cutting on connection parts between the substrates such as spherical electrodes can be eliminated, and the occurrence of a crack in a connection location can be suppressed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体など電子部品を三次元的に積層形成する半導体装置の製造方法に関し、特に封止電子部品搭載の多数取り配線基板を用いて効率良く、三次元積層型の半導体装置を製造する方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device in which electronic components such as semiconductors are three-dimensionally stacked, and more particularly, to efficiently manufacture a three-dimensional stacked semiconductor device using a multi-layer wiring board mounted with sealed electronic components. It is about the method.

電子機器の機能向上・小型化に伴い、それに使用される半導体素子等電子部品点数の増加とともに電子部品の小型化が進む一方、それら部品の高密度実装の実現が重要なポイントとなっている。半導体素子等電子部品の二次元的な実装技術は、適用装置に応じて各種方法によって高密度化が進んできたが、その高密度化は、ほぼ限界状況に近づいて来ているとも言える。そこで、昨今、三次元的な実装技術の開発が活発に行われるようになってきた。   With the improvement and miniaturization of functions of electronic devices, the electronic components are becoming smaller with the increase in the number of electronic components such as semiconductor elements used therein. On the other hand, it is important to realize high-density mounting of these components. The two-dimensional mounting technology for electronic components such as semiconductor elements has been increased in density by various methods depending on the application apparatus, but it can be said that the density increase is almost approaching the limit. Therefore, recently, development of three-dimensional mounting technology has been actively performed.

配線基板上に半導体素子等電子部品を搭載して樹脂封止し、基板裏面に球形（ボール）電極を形成した単体の半導体実装パッケージに、同様に形成された他の機能をもつ単体の半導体実装パッケージを搭載して、二層に、更にその上に複数の他のパッケージを順次搭載して多層に実装して形成する、いわゆるパッケージ・オン・パッケージ（ＰＯＰ）と称される、三次元の半導体装置が提案されている（例えば、特許文献１、２、３）。   A single semiconductor mounting package with other functions formed in the same way on a single semiconductor mounting package in which electronic components such as semiconductor elements are mounted on the wiring board and sealed with resin, and a spherical (ball) electrode is formed on the back of the board A three-dimensional semiconductor called a so-called package-on-package (POP), in which a package is mounted, and a plurality of other packages are sequentially mounted on the two layers and then mounted in multiple layers. Devices have been proposed (for example, Patent Documents 1, 2, and 3).

図７は、このような半導体装置の製造方法における工程を示す断面模式図である。図７（１）は、二種類の、多数個取りの配線基板上に形成された、多数個取り配線基板実装パッケージ１０１Ａ、１０１Ｂを示す。多数個取り配線基板実装パッケージ１０１Ａは、基板１０２Ａの主面（上面）に、半導体素子など電子部品が樹脂封止された封止体１０３Ａが搭載され、裏面（下面）には、封止体１０３Ａと電気接続された電極パッド１０４Ａとその面上に形成された球状（ボール）電極１０５Ａが形成される。   FIG. 7 is a schematic cross-sectional view showing steps in the method for manufacturing such a semiconductor device. FIG. 7A shows the multi-chip wiring board mounting packages 101A and 101B formed on two types of multi-chip wiring boards. In the multi-cavity wiring board mounting package 101A, a sealing body 103A in which an electronic component such as a semiconductor element is resin-sealed is mounted on the main surface (upper surface) of the substrate 102A, and a sealing body 103A is mounted on the back surface (lower surface). The electrode pad 104A and the spherical electrode 105A formed on the surface are formed.

他方、多数個取り配線基板実装パッケージ１０１Ｂは、基板１０２Ｂの主面（上面）に、例えば他の種類の半導体素子など電子部品が樹脂封止された封止体１０３Ｂが搭載され、裏面（下面）には、封止体１０３Ｂと電気接続された電極パッド１０４Ｂとその面上に形成された球状（ボール）電極１０５Ｂが形成される。   On the other hand, in the multi-cavity wiring board mounting package 101B, a sealing body 103B in which electronic components such as other types of semiconductor elements are sealed with resin is mounted on the main surface (upper surface) of the substrate 102B, and the back surface (lower surface). The electrode pad 104B electrically connected to the sealing body 103B and the spherical (ball) electrode 105B formed on the surface are formed.

多数個取り配線基板実装パッケージ１０１Ａの一つの個片実装パッケージ上に、多数個取り配線基板実装パッケージ１０１Ｂの一つの個片実装パッケージが搭載かつ接続されて、一つのＰＯＰの半導体装置が形成される。そのために、多数個取り配線基板実装パッケージ１０１Ａの主面には、多数個取り配線基板実装パッケージ１０１Ｂの球状（ボール）電極１０５Ｂが相応する位置に接続電極１０６が形成される。   A single POP semiconductor device is formed by mounting and connecting one individual mounting package of the multi-cavity wiring board mounting package 101B on one individual mounting package of the multi-cavity wiring board mounting package 101A. . Therefore, on the main surface of the multi-cavity wiring board mounting package 101A, connection electrodes 106 are formed at positions corresponding to the spherical (ball) electrodes 105B of the multi-cavity wiring board mounting package 101B.

各多数個取り配線基板実装パッケージを個片実装パッケージに分離するために、図中、各多数個取り配線基板実装パッケージ基板の分割領域内の、それぞれ図中のＺ−Ｚ’のラインの位置で、例えばダイシングソウを用いて切断する。   In order to separate each multi-cavity wiring board mounting package into individual mounting packages, in the figure, at the position of the line ZZ ′ in the divided area of each multi-cavity wiring board mounting package board, respectively. For example, cut using a dicing saw.

図７（２）に個片実装パッケージ１０７Ａ、１０７Ｂを示し、これを図７（３）の示すように両者を球状（ボール）電極１０５Ｂと接続電極１０６とで接続して、二層ＰＯＰ構造半導体装置１０８が完成する。   FIG. 7 (2) shows individual mounting packages 107A and 107B, which are connected by a spherical (ball) electrode 105B and a connection electrode 106 as shown in FIG. The device 108 is completed.

なお、封止体１０３については、図７内では、便宜上、封止樹脂などでモールドパッケージした一個の封止素子のように図示しているが、これに限らないのは勿論である。例えば、複数の半導体チップを配線基板上にワイヤ接続して搭載し、更に他種の電子部品等を搭載し、それらを封止樹脂で封止した構成でも構わないし、例えばモールドパッケージしたＬＳＩ素子を複数搭載したもの、更にこれを一体で樹脂封止したものでも良い。その他多様な半導体電子部品封止体が適用可能である。
特開平１０−１３５２６７号公報 特開２００３−１８８３４２号公報 特開２００７−５９５５７号公報 The sealing body 103 is illustrated in FIG. 7 as a single sealing element molded and packaged with a sealing resin or the like for the sake of convenience, but is not limited to this. For example, a plurality of semiconductor chips may be mounted on a wiring board by wire connection, and another type of electronic component may be mounted and sealed with a sealing resin. For example, a molded packaged LSI element may be used. A plurality of such devices may be mounted, and those may be integrally sealed with resin. Various other semiconductor electronic component sealing bodies can be applied.
Japanese Patent Laid-Open No. 10-135267 JP 2003-188342 A JP 2007-59557 A

先に述べたように、従来の多層ＰＯＰ構造半導体装置の製造方法は、異なる各多数個取り配線基板実装パッケージを個片実装パッケージに分離し、個片実装パッケージ同士を積層接続する方法をとる。しかし、この方法では効率よくＰＯＰ構造半導体装置を製造することができなかった。   As described above, the conventional method for manufacturing a multi-layer POP structure semiconductor device employs a method in which each multi-piece wiring board mounting package is separated into individual mounting packages, and the individual mounting packages are stacked and connected. However, this method cannot efficiently manufacture a POP structure semiconductor device.

そこで、本発明の課題は、効率よくＰＯＰ構造半導体装置を製造することが可能な半導体装置の製造方法を提供することにある。   Accordingly, an object of the present invention is to provide a semiconductor device manufacturing method capable of efficiently manufacturing a POP structure semiconductor device.

本発明の半導体装置の製造方法は、
複数の第１の半導体素子が搭載された第１の配線基板上に、複数の第２の半導体素子が搭載された第２の配線基板を配置するとともに、前記第１の配線基板と前記第２の配線基板とを導電部材により電気的に接続する工程と、
前記第１の配線基板と前記第２の配線基板とを電気的に接続した後、前記第１の配線基板及び前記第２の配線基板を切断する工程と、を含み、
前記第１の配線基板及び前記第２の配線基板を切断する前に、前記第１の配線基板と前記第２の配線基板との間に補強部材が配置されていることを特徴とする。 A method for manufacturing a semiconductor device of the present invention includes:
A second wiring board on which a plurality of second semiconductor elements are mounted is disposed on a first wiring board on which a plurality of first semiconductor elements are mounted, and the first wiring board and the second wiring board are arranged. Electrically connecting the wiring board with a conductive member;
Cutting the first wiring board and the second wiring board after electrically connecting the first wiring board and the second wiring board;
A reinforcing member is disposed between the first wiring board and the second wiring board before cutting the first wiring board and the second wiring board.

そして、
前記第１の配線基板と前記第２の配線基板とを電気的に接続する前に、前記第１の配線基板及び前記第２の配線基板の少なくとも一方に前記補強部材を配設しておくことを特徴とする。 And
The reinforcing member is disposed on at least one of the first wiring board and the second wiring board before electrically connecting the first wiring board and the second wiring board. It is characterized by.

そして、
前記補強部材は、前記第１の配線基板上に供給される樹脂であることを特徴とする。 And
The reinforcing member is a resin supplied onto the first wiring board.

そして、
前記補強部材は、前記第１の配線基板上に配置されるテープ材であることを特徴とする。 And
The reinforcing member is a tape material disposed on the first wiring board.

そして、
前記第１の配線基板は、前記第１の半導体素子が搭載される複数の第１の領域と、前記複数の第１の領域を画定する第２の領域とを含み、
前記補強部材は、前記第２の領域上に配設されることを特徴とする。 And
The first wiring board includes a plurality of first regions on which the first semiconductor elements are mounted, and a second region that defines the plurality of first regions,
The reinforcing member is disposed on the second region.

開示した半導体装置の製造方法は、多数個取り配線基板実装パッケージの状態で多層化し、その後、ブレードダイシング装置などによる一括切断による個片化をおこなって多層ＰＯＰ構造半導体装置を製造する場合において、多層ＰＯＰ構造を構成する球状電極やそれを含む電極近傍にクラックが発生するのを抑制することができる。   The disclosed method for manufacturing a semiconductor device is a multi-layered POP structure semiconductor device in which a multi-layered PWB structure semiconductor device is manufactured by performing multi-layering in the state of a multi-piece wiring board mounting package and then performing individual batch cutting with a blade dicing apparatus or the like. It is possible to suppress the generation of cracks in the vicinity of the spherical electrode constituting the POP structure and the electrode including the spherical electrode.

これまでの製造方法は、前述のように、個片実装パッケージ化して、不良個片実装パッケージを除外するという意味がある。しかし、例えば、不良の個片実装パッケージの発生が非常に稀である場合は、異なる、多数個取り配線基板実装パッケージを基板同士で一度に積層・接続し、その後、個片の多層ＰＯＰ構造半導体装置にするために、積層・接続した基板を切断するといった、より効率的な方法が考えられる。   As described above, the manufacturing method so far has the meaning of forming individual package and excluding defective individual package. However, for example, when the occurrence of a defective individual mounting package is very rare, different, multi-piece wiring board mounting packages are stacked and connected together at the same time, and then the individual multi-layer POP structure semiconductor In order to form an apparatus, a more efficient method such as cutting the stacked and connected substrates can be considered.

図１に、一括した多層ＰＯＰ構造化による多層構造の三次元半導体装置を形成する工程の断面模式図を示す。   FIG. 1 shows a schematic cross-sectional view of a process for forming a multi-layered three-dimensional semiconductor device by batch multi-layer POP structuring.

図１（１）は、同数同列で、互いに機能が異なるあるいは同じの、多数個取り配線基板実装パッケージ１Ａと１Ｂとで、多数個取り配線基板実装パッケージ１Ｂ上に多数個取り配線基板実装パッケージ１Ａを用意する。これらを積層し、後者の球状電極と前者の接続電極で電気的接続をなし、二層多数個取り配線基板ＰＯＰ構造パッケージ化していく。   FIG. 1A is a multi-cavity wiring board mounting package 1A and 1B of the same number in the same row and having different functions or the same function, and a multi-cavity wiring board mounting package 1A on the multi-cavity wiring board mounting package 1B. Prepare. These are stacked, and the latter spherical electrode and the former connection electrode are electrically connected to form a multi-layer wiring board POP structure package.

ここにおいて、例えば基材が樹脂で、多層の配線層を用いて形成された、同数同列で同配置の個片領域（図中の個片領域８Ａ、８Ｂに関して、主面平面においていずれも同じものとする。その際、分離領域９Ａ、９Ｂも、主面平面においていずれも同じものとする）の多数個取りの配線基板２Ａ、２Ｂを用い、その主面（上面）に封止体３Ａ、３Ｂが形成される。   Here, for example, the base material is a resin and is formed by using a multilayer wiring layer, and the same number of identically arranged individual regions (the same one in the main surface plane with respect to the individual regions 8A and 8B in the figure) In that case, the separation regions 9A and 9B are both the same on the main surface plane, and the multi-cavity wiring boards 2A and 2B are used, and the sealing bodies 3A and 3B are used on the main surfaces (upper surfaces). Is formed.

封止体３Ａ、３Ｂは、主面の各個片領域毎に配置されており、各個片上の封止体３Ａ、３Ｂは、図示されていない配線パッド上に、１Ａ、１Ｂ互いに異なる、あるいは同じ機能を有する、半導体チップ・モールド半導体素子・その他の電子部品などをワイヤボンディング・はんだリフローなどの方法で搭載し、それら素子全体、あるいは一部を例えばシリコーン樹脂などの封止樹脂で封止した機能素子モジュールである。   The sealing bodies 3A and 3B are arranged for each individual region of the main surface, and the sealing bodies 3A and 3B on each individual piece are different from each other or have the same function on the wiring pads (not shown). A functional element in which a semiconductor chip, a molded semiconductor element, and other electronic components are mounted by a method such as wire bonding or solder reflow, and all or part of the element is sealed with a sealing resin such as silicone resin It is a module.

配線基板２Ａ、２Ｂの裏面（下面）に、例えばＡｕの電極パッド４Ａ、４Ｂと、その上に、例えばはんだ製の球状（ボール）電極５Ａ、５Ｂが形成される。電極パッド４Ａ、４Ｂ及び球状（ボール）電極５Ａ、５Ｂは、裏面の各個片領域毎にそれぞれ必要数からなる一群のものが配置形成されている。本例のように、多数個取りの配線基板２Ｂが多数個取りの配線基板２Ａ上に積層・接続される場合は、個片領域の球状（ボール）電極５Ｂの一群の配置は、多数個取りの配線基板２Ａの主面の個片の領域毎に形成される、一群の接続電極６の配置に相応している。   For example, Au electrode pads 4A and 4B and, for example, solder spherical (ball) electrodes 5A and 5B are formed on the back surfaces (lower surfaces) of the wiring boards 2A and 2B. The electrode pads 4A and 4B and the spherical (ball) electrodes 5A and 5B are arranged and formed in a necessary number for each individual region on the back surface. When the multi-piece wiring board 2B is stacked and connected on the multi-piece wiring board 2A as in this example, the arrangement of a group of spherical (ball) electrodes 5B in the single-piece region is large. This corresponds to the arrangement of the group of connection electrodes 6 formed for each region of the main surface of the wiring board 2A.

図１（２）は、多数個取り配線基板実装パッケージ１Ａ、１Ｂを、はんだリフロー法を用いて、球状（ボール）電極５Ｂと接続電極６とを接続して積層したときの状態（二層多数個取り配線基板ＰＯＰ構造パッケージ７）を示す。分割領域９Ａ、９Ｂ（９Ａ＝９Ｂ）の内の位置Ｚ−Ｚ’で、多数個取り配線基板実装パッケージ１Ｂの上面側から、下の多数個取り配線基板実装パッケージ１Ａの裏面に向かって、ダイシングブレードを用いて切断した。   FIG. 1 (2) shows a state in which the multi-piece wiring board mounting packages 1A and 1B are laminated by connecting the spherical (ball) electrode 5B and the connection electrode 6 by using the solder reflow method (two-layer many). The single-piece wiring board POP structure package 7) is shown. Dicing from the upper surface side of the multi-cavity wiring board mounting package 1B toward the back surface of the lower multi-cavity wiring board mounting package 1A at the position ZZ ′ in the divided areas 9A and 9B (9A = 9B) Cut with a blade.

そして、図１（２）中に示すような、多数個取り分の、二層ＰＯＰ構造半導体装置１０を得ることができる。この手法は、個片実装パッケージ化し、それぞれを接続・積層して二層ＰＯＰ構造半導体装置を得るのに比べ、工数削減が可能である。例えば、多数個取りのパッケージ個数が５００個であれば、従来法では５００回の個別の多層化のための位置あわせとはんだリフローが必要であるが、この多数個取り配線基板実装パッケージを重ねる方法では一回の位置あわせと一回のリフロー、そして、ダイシング装置での一括切断で形成できる。   As a result, a two-layer POP structure semiconductor device 10 can be obtained as shown in FIG. This method can reduce the number of man-hours as compared with the case where a two-layer POP structure semiconductor device is obtained by packaging individual packages and connecting and stacking them. For example, if the number of multi-packages is 500, the conventional method requires 500 individual alignments and solder reflow, but this multi-layer wiring board mounting package is stacked. Then, it can be formed by one alignment, one reflow, and batch cutting with a dicing machine.

こうして製造したときの、図１（２）の円形点線領域で示す切断個所要部の拡大模式図を図１（３）に示す。この図にあるように、このようにして製造した二層ＰＯＰ構造半導体装置１０において、特に、多数個取り配線基板実装パッケージ１Ｂの球状電極５Ｂが電極パッド４Ｂや接続電極６と接続する個所およびそれに繋がる球形電極５Ｂに、切断個所の隣接場所や近接場所でのそれらはもとより、比較的離れた場所においても、クラック１１状の欠陥が入る現象がかなりの確率で見られた。このような欠陥発生が抑止することは、多層ＰＯＰ構造半導体装置を効率よく製造する上で非常に重要となる。   FIG. 1 (3) shows an enlarged schematic view of the cut required portion indicated by the circular dotted line region in FIG. 1 (2) when manufactured in this way. As shown in this figure, in the two-layer POP structure semiconductor device 10 manufactured in this way, in particular, the locations where the spherical electrodes 5B of the multi-piece wiring board mounting package 1B are connected to the electrode pads 4B and the connection electrodes 6, and The phenomenon that crack 11-like defects enter the connected spherical electrode 5B not only in the adjacent place of the cut part and in the close place but also in a relatively distant place was seen with a considerable probability. Suppressing the occurrence of such defects is very important in efficiently manufacturing a multilayer POP structure semiconductor device.

図１（３）に模式的に示した、電極パッド４Ｂ，接続電極６と球状電極５Ｂとの接続点とそれに繋がる球状電極５Ｂ内に発生するクラックは、多数個取り配線基板実装パッケージの、樹脂からなる配線基板１Ｂ主面の分割領域９Ｂにブレードを押し当てながら回路基板２Ｂを切断し、そして更に配線基板２Ａを切断している中で発生する。これは、ブレードが配線基板を切断中に、各配線基板を下に押し曲げるような強い変形ストレスがかかり、そのストレスが、はんだリフローで接続した球状電極５Ｂとパッド電極３４Ｂや接続電極６との狭い接続点に集中するともの考えられる。より強いストレスや、電極間接続強度が弱い場合は、その狭い接続領域個所での切断に至るが、多くは切断まで至らずに、その途中を示すクラックが、接続境界ないし球状電極５Ｂ内に進入するように発生するものと考えられる。従って、ブレードを押し当てても配線基板が変形しないようにすることが重要で、そのためには、配線基板を強い強度で平坦状態で固定する対策を講じる必要がある。   Cracks generated in the electrode pad 4B, the connection point of the connection electrode 6 and the spherical electrode 5B and the spherical electrode 5B connected to the electrode pad 4B, schematically shown in FIG. This occurs when the circuit board 2B is cut while pressing the blade against the divided area 9B of the main surface of the wiring board 1B, and the wiring board 2A is further cut. This is because a strong deformation stress that pushes and bends each wiring board while the blade is cutting the wiring board is applied, and the stress is applied between the spherical electrode 5B, the pad electrode 34B, and the connection electrode 6 connected by solder reflow. It is thought that it concentrates on a narrow connection point. If the stress is stronger or the connection strength between the electrodes is weaker, cutting will occur at the narrow connection area, but many will not reach cutting, and cracks indicating the way will enter the connection boundary or spherical electrode 5B. It is thought to occur. Therefore, it is important to prevent the wiring board from being deformed even when the blade is pressed, and for that purpose, it is necessary to take measures to fix the wiring board in a flat state with high strength.

その方法として、両配線基板の切断個所同士の基板間の間隙、つまり切断個所は各配線基板の分割領域を用いることから、この分割領域同士での基板間の間隙に、例えば熱硬化樹脂等の間隙充填層を埋め込み、固着化した状態とすることで、各配線基板に対するブレード押し当てによる変形（ストレス発生）を抑止することが、最も有効かつ容易に行える方法であると考えられる。   As the method, since the gap between the cut portions of both wiring boards, that is, the cut portion uses a divided area of each wiring board, the gap between the boards in the divided areas, for example, a thermosetting resin or the like It is considered that the most effective and easy method is to suppress deformation (stress generation) due to blade pressing against each wiring board by embedding the gap filling layer and fixing it.

この固着化する場所は、上述のようにブレードで切断する場所でもあり、固定化樹脂領域の、例えば中心部分を通過するように両配線基板は切断され、基板切断中であっても、ブレードの押し下げストレスが他の配線基板領域に伝わらないことともなり、離れた領域での基板変形による接続点などでのクラック発生を抑止できるといった効果が期待できるといえよう。   This fixing place is also a place where the blade is cut as described above, and both the wiring boards are cut so as to pass through, for example, the central portion of the fixed resin region. It can be said that the pressing stress is not transmitted to other wiring board regions, so that an effect of suppressing the generation of cracks at connection points due to board deformation in a remote area can be expected.

以下に、本発明の実施の形態を、添付図を参照しつつ説明する。   Embodiments of the present invention will be described below with reference to the accompanying drawings.

（実施例）
図２は、本発明の半導体装置の製造方法によって形成される工程を示すものである。図２（１）に示した、二層多数個取り配線基板ＰＯＰ構造パッケージ１２は、基本的に、図１（１）に示した、多数個取り配線基板実装パッケージ１Ａ、１Ｂと同等のものを用意し、それを同じく図１（２）に示した、二層多数個取り配線基板ＰＯＰ構造パッケージ７を形成した状態と類似であるが、但し、各分割領域９Ａ、９Ｂ（９Ａ＝９Ｂ）において各多数個取りの配線基板の間隙に間隙充填層１３を形成している点で異なる。 (Example)
FIG. 2 shows steps formed by the method for manufacturing a semiconductor device of the present invention. The two-layer multi-cavity wiring board POP structure package 12 shown in FIG. 2 (1) is basically the same as the multi-cavity wiring board mounting packages 1A and 1B shown in FIG. 1 (1). This is similar to the state in which the two-layer multi-cavity wiring board POP structure package 7 shown in FIG. 1 (2) is formed, but in each of the divided regions 9A and 9B (9A = 9B). The difference is that a gap filling layer 13 is formed in the gap between each of the multiple wiring boards.

この間隙充填層１３によって、この個所での上下二つの基板間の間隙を固定化し、この基板個所で上下からの加圧に対して基板の変形を阻止するように作用する。この分割領域９Ａ、９Ｂ（９Ａ＝９Ｂ）において、二層多数個取り配線基板ＰＯＰ構造パッケージ１２は、間隙充填層１３とともにダイシングブレードで切断され、個片の二層ＰＯＰ構造半導体装置となる。   The gap filling layer 13 fixes the gap between the upper and lower substrates at this location, and acts to prevent the substrate from being deformed against pressure from above and below at this location. In the divided regions 9A and 9B (9A = 9B), the two-layer multi-piece wiring board POP structure package 12 is cut by a dicing blade together with the gap filling layer 13 to form a single-layer two-layer POP structure semiconductor device.

図２（２）に、図２（１）に対応する間隙充填層１３形成例の平面図を示す。この図は多数個取り配線基板実装パッケージ１Ｂの裏面の平面から、多数個取り配線基板実装パッケージ１Ａの主面方向を見たときの平面図である。この場合の多数個取り配線基板実装パッケージ１Ａは、一方向（横方向）にのみ多数個配列がなされた（即ち縦方向は一個）の多数個取りの配線基板２Ａを用いた例である。   FIG. 2 (2) shows a plan view of an example of forming the gap filling layer 13 corresponding to FIG. 2 (1). This figure is a plan view when the main surface direction of the multi-cavity wiring board mounting package 1A is viewed from the back surface of the multi-cavity wiring board mounting package 1B. The multi-cavity wiring board mounting package 1A in this case is an example using a multi-cavity wiring board 2A that is arranged in only one direction (horizontal direction) (that is, one in the vertical direction).

このとき、封止体３Ａと接続電極６からなる個片の形成領域１０の外側である分割領域９Ａ以外の領域である、外周領域１５Ａにも間隙充填層１３を形成している。勿論、（本図面上の）横方向と共に縦方向にも多数個配列をした、マトリックス状に個片の形成領域８Ａが配列された配線基板である場合は、外周領域１５Ａは、分割領域機９Ａに相当し、ダイシングブレードによる切断個所となることは言うまでもない。   At this time, the gap filling layer 13 is also formed in the outer peripheral region 15 </ b> A, which is a region other than the divided region 9 </ b> A that is outside of the individual region 10 formed of the sealing body 3 </ b> A and the connection electrode 6. Of course, in the case of a wiring board in which a large number of array areas 8A are arranged in the matrix in the horizontal direction (on the drawing), the outer peripheral area 15A is divided into the divided area machine 9A. Needless to say, this is a cutting point by a dicing blade.

図２（３）は、図１（３）に相当し、図２（１）のＺ−Ｚ’個所にダイシングブレードが、上側の配線基板２Ｂの主面側から入って、全基板を切断するときの状況を説明するためのもので、図２（１）の円形点線領域で示す切断個所要部の拡大模式図である。切断個所である分割領域９Ａに、間隙充填層１３が挿入されているために、球状（バール）電極５Ｂ内、および電極パッド４Ｂ、接続電極６との接続個所近傍などでクラック発生が観察されることは無かった。またこれと離れた領域でのクラック発生は見出されなかった。これにより、本方法の有効性が確認できた。   FIG. 2 (3) corresponds to FIG. 1 (3). A dicing blade enters the ZZ ′ portion of FIG. 2 (1) from the main surface side of the upper wiring board 2B and cuts the entire board. FIG. 3 is an enlarged schematic diagram of a cut piece required portion indicated by a circular dotted line region in FIG. Since the gap filling layer 13 is inserted into the divided area 9A, which is a cutting point, cracks are observed in the spherical (bar) electrode 5B and in the vicinity of the connection point with the electrode pad 4B and the connection electrode 6. There was nothing. In addition, no cracks were found in the area apart from this. This confirmed the effectiveness of the method.

上記の、間隙充填層６の形成方法は、以下に述べるような方法を実施した。   The above-described method for forming the gap filling layer 6 was performed as described below.

（１）印刷方式
図３に、印刷方式による間隙充填層１３の形成工程断面図を示す。本方式は、マスクを用い、流動性材料をスクリーン印刷と同様な孔版印刷と類似の方法を用いる。図３（１）において、二層多数個取り配線基板ＰＯＰ構造パッケージ７（図１（２）参照）の下側の多数個取り配線基板実装パッケージ１Ａの主面に、封止体３Ａと接続電極６、裏面に球状（ボール）電極５Ａが形成された状態で、この主面上に、所要の位置と厚さを有する間隙充填層１３を形成するに必要な開口部１５と厚さを持つマスク１４をセットする。マスク１４は、例えば金属・ガラスなどの材料で製作可能である。開口部１５の位置は、勿論、後にダイシングブレードで切断する所定幅の分割領域９Ａを、少なくとも含んでいる。 (1) Printing Method FIG. 3 shows a cross-sectional view of the formation process of the gap filling layer 13 by the printing method. This method uses a mask and uses a fluid material similar to stencil printing similar to screen printing. In FIG. 3A, a sealing body 3A and connection electrodes are formed on the main surface of a multi-layer wiring board mounting package 1A on the lower side of the two-layer multi-chip wiring board POP structure package 7 (see FIG. 1B). 6. A mask having an opening 15 and a thickness necessary for forming a gap filling layer 13 having a required position and thickness on the main surface in a state where a spherical (ball) electrode 5A is formed on the back surface. 14 is set. The mask 14 can be made of a material such as metal or glass. Of course, the position of the opening 15 includes at least a divided region 9A having a predetermined width to be cut later by a dicing blade.

この際、図に示すように、マスク１４を、封止体３Ａ上をブリッジするなどの構成にし、所定の個所の基板主面上のみに流動性材料が印刷されるようにすることも必要である。   At this time, as shown in the drawing, it is also necessary to make the mask 14 have a configuration such as bridging the sealing body 3A so that the fluid material is printed only on the substrate main surface at a predetermined location. is there.

このマスク７上に、例えば流動性材料として、エポキシ樹脂・ポリイミドなどを原料とした、室温で流動性をもつ熱硬化性樹脂１６を滴下し、スキージ１７を用いて、図３（２）に示すように摺動（図中のＨ方向）させ、開口部１５に熱硬化性樹脂１６を充填する。   On the mask 7, for example, as a fluid material, a thermosetting resin 16 having a fluidity at room temperature using epoxy resin / polyimide as a raw material is dropped, and a squeegee 17 is used as shown in FIG. The opening 15 is filled with the thermosetting resin 16 as shown in FIG.

そして、図３（３）に示すように、所定の樹脂乾燥工程を経て、マスク１４を上方（図中のＶ方向）に取り外し、多数個取り配線基板実装パッケージ１Ａの主面上に乾燥した熱硬化性樹脂１６パターンを得る。こうして、例えば図２（２）の平面図に示したような。間隙充填層１３のパターンと同等の熱硬化性樹脂１６のパターンを形成できる。   Then, as shown in FIG. 3 (3), through a predetermined resin drying process, the mask 14 is removed upward (in the V direction in the figure) and dried on the main surface of the multi-cavity wiring board mounting package 1A. A curable resin 16 pattern is obtained. Thus, for example, as shown in the plan view of FIG. A pattern of the thermosetting resin 16 equivalent to the pattern of the gap filling layer 13 can be formed.

次いで、例えば、この上に多数個取り配線基板実装パッケージ（Ｂ）を搭載・接続（図２（１）参照）し、所定の熱処理を行って熱硬化性樹脂１６パターンを熱硬化させ、所期の間隙充填層１３を得ることができる。   Next, for example, a multi-piece wiring board mounting package (B) is mounted and connected (see FIG. 2 (1)) on this, and a predetermined heat treatment is performed to thermally cure the thermosetting resin 16 pattern. The gap filling layer 13 can be obtained.

この場合、はじめに、多数個取り配線基板実装パッケージ１Ｂの裏面側に、同様にマスクを用いて熱硬化性樹脂１６パターンを形成し、その後、これを多数個取り配線基板実装パッケージ１Ａの主面側と接続するようにしても構わないことは言うまでもない。   In this case, first, a thermosetting resin 16 pattern is similarly formed on the back surface side of the multi-cavity wiring board mounting package 1B using a mask, and this is then used as the main surface side of the multi-cavity wiring board mounting package 1A. Needless to say, it is also possible to connect to.

（２）ディスペンス方式
図４に、ディスペンス方式による間隙充填層１３の形成工程斜視図を示す。本方式は、図１（１）に示したように、上側となる多数個取り配線基板実装パッケージ１Ｂと、下側となる多数個取り配線基板実装パッケージ１Ａを用意し、図４の斜視図に示すように、前者の多数個取り配線基板実装パッケージの配線基板２Ｂ側に、図示するようなスリット１８を開口して、両多数個取り配線基板実装パッケージ１Ｂ、１Ａを積層・接続し、二層多数個取り配線基板ＰＯＰ構造パッケージ１２とする。勿論、各種実装が行われる前の、多数個取りの配線基板２Ｂの状態でスリットを開口してもよい。 (2) Dispensing Method FIG. 4 shows a perspective view of the formation process of the gap filling layer 13 by the dispensing method. In this method, as shown in FIG. 1A, the upper multi-cavity wiring board mounting package 1B and the lower multi-cavity wiring board mounting package 1A are prepared, and the perspective view of FIG. As shown in the figure, a slit 18 as shown is opened on the wiring board 2B side of the former multi-cavity wiring board mounting package, and both of the multi-cavity wiring board mounting packages 1B and 1A are stacked and connected to form two layers. The multi-cavity wiring board POP structure package 12 is used. Of course, the slit may be opened in the state of the multi-piece wiring board 2B before various mountings are performed.

このスリット１８の、位置と形状は、個片領域を分ける分割領域相当とする。但しスリット１８の形成上、配線基板の全体形状維持の点から、適宜、スリットの非開口個所１９を設ける必要がある。   The positions and shapes of the slits 18 are equivalent to the divided regions that divide the individual regions. However, in forming the slit 18, it is necessary to appropriately provide a non-opening portion 19 of the slit from the viewpoint of maintaining the overall shape of the wiring board.

そして、例えばエポキシ樹脂・ポリイミドなどを原料とした、室温で流動性をもつ熱硬化性樹脂１６を、ディスペンサのノズル２０を用いて、スリット１８中に充填する。   Then, for example, a thermosetting resin 16 having a fluidity at room temperature using epoxy resin / polyimide as a raw material is filled into the slit 18 using the nozzle 20 of the dispenser.

次いで、この充填済みの二層多数個取り配線基板ＰＯＰ構造パッケージ１２を恒温槽などに入れて熱処理を行い、熱硬化性樹脂１６を硬化させて、基本的に分離領域を含む個所の配線基板間の間隙に間隙充填層１３（図２（１）参照）を得ることができる。   Next, the filled two-layer multi-piece wiring board POP structure package 12 is put in a thermostatic chamber or the like, and heat treatment is performed to cure the thermosetting resin 16, so that basically between the wiring boards at locations including the separation region. A gap filling layer 13 (see FIG. 2A) can be obtained in the gap.

（３）テープ方式
図５の、テープ方式による間隙充填層１３の形成工程の断面斜視図を示す。本方式は、図１（１）に示したように、上側となる多数個取り配線基板実装パッケージ１Ｂと、下側となる多数個取り配線基板実装パッケージ１Ａを準備し、そして絶縁性・耐熱性を有する、例えば、テフロン（登録商標）などの樹脂材料からなる、所定の厚さ（例えば、封止体３Ａの高さより厚い）のテープ（使用面積により、より広いシートを使用）を個片領域８Ａの形状に開口、あるいは分割領域９Ａの幅形状で切り出し、この形状化テープ２１を、多数個取り配線基板実装パッケージ１Ａ、１Ｂで挟み、両配線基板２Ａ、２Ｂの面に接着剤を介して強固に接着させ、両多数個取り配線基板実装パッケージ１Ｂ、１Ａを積層・接続して二層多数個取り配線基板ＰＯＰ構造パッケージ１２を形成する。実際的には、形状化テープ２１は多数個取り配線基板実装パッケージ１Ａの主面所上、あるいは多数個取り配線基板実装パッケージ１Ｂの裏面上に先ず接着し、その後に、両方の多数個取り配線基板実装パッケージを接続することとなろう。 (3) Tape Method FIG. 5 is a cross-sectional perspective view of the step of forming the gap filling layer 13 using the tape method. As shown in FIG. 1 (1), this system prepares a multi-cavity wiring board mounting package 1B on the upper side and a multi-cavity wiring board mounting package 1A on the lower side, and has insulation and heat resistance. For example, a tape having a predetermined thickness (for example, thicker than the height of the sealing body 3A) made of a resin material such as Teflon (registered trademark) is used. 8A shape is cut out in the shape of the opening or divided area 9A, and the shaped tape 21 is sandwiched between the multi-layer wiring board mounting packages 1A and 1B, and an adhesive is provided between the surfaces of both wiring boards 2A and 2B. The two-layer multi-cavity wiring board POP structure package 12 is formed by laminating and connecting the multiple multi-cavity wiring board mounting packages 1B and 1A. In practice, the shaped tape 21 is first adhered to the main surface of the multi-cavity wiring board mounting package 1A or the back surface of the multi-cavity wiring board mounting package 1B, and then both of the multi-cavity wiring boards 1B. A board mounted package will be connected.

上記間隙充填層１３の形成工程に関しては、間隙充填層用材料の形成順序に関して、
タイプ１：多数個取り配線基板実装パッケージ１Ａ、１Ｂのどちらか一方に先ず間隙充填層用材料を形成し、その後、両方の多数個取り配線基板実装パッケージを接続する方法（印刷方式、テープ方式）
タイプ２：、両多数個取り配線基板実装パッケージ１Ｂ、１Ａを積層・接続した後、間隙充填層用材料を間隙に（注入して）形成する方法（ディスペンス方式）
の２タイプがあることを示した。 Regarding the formation process of the gap filling layer 13, regarding the formation order of the gap filling layer material,
Type 1: A method of first forming a gap filling layer material on one of the multi-cavity wiring board mounting packages 1A and 1B, and then connecting both of the multi-wiring wiring board mounting packages (printing method, tape method)
Type 2: A method of forming (filling) a gap filling layer material in the gap after stacking and connecting both multi-cavity wiring board mounting packages 1B and 1A (dispensing method)
It was shown that there are two types.

こうして、二層多数個取り配線基板ＰＯＰ構造パッケージ１２には、少なくとも分割領域に、配線基板に固着した絶縁・耐熱樹脂材料が挿入され、固着されており、これにより上記の間隙充填層１３（図２（１）参照）として機能せしめることができる。   In this way, in the two-layer multi-piece wiring board POP structure package 12, the insulating / heat-resistant resin material fixed to the wiring board is inserted and fixed at least in the divided region, whereby the gap filling layer 13 (see FIG. 2 (1)).

以上述べたような方法で、間隙充填層１３が挿入された二層多数個取り配線基板ＰＯＰ構造パッケージを形成した後、分割領域を用いて、例えばダイシングブレードで切断して個片化することで、図６（１）に示すような、球状（ボール）電極やその近傍にクラックなどの欠陥が生じることのない、二層ＰＯＰ構造半導体装置２２を製造することができる。   After forming the two-layer multi-piece wiring board POP structure package in which the gap filling layer 13 is inserted by the method described above, it is cut into pieces using, for example, a dicing blade using the divided regions. As shown in FIG. 6A, a two-layer POP structure semiconductor device 22 in which defects such as cracks do not occur in the spherical (ball) electrode or in the vicinity thereof can be manufactured.

これまでは、二枚の多数個取り配線基板実装パッケージを積層・接続し、かつ間隙充填層を挿入して、二層多数個取り配線基板ＰＯＰ構造パッケージを形成し、これを個片化して二層ＰＯＰ構造半導体装置を製造する方法を述べた。同様な方法を繰り返えすことにより、二枚以上の多数枚の多数個取り配線基板実装パッケージを用いて、二層以上の多層ＰＯＰ構造半導体装置を製造することは容易であることは言うまでもない。   Up to now, two multi-cavity wiring board mounting packages are stacked and connected, and a gap filling layer is inserted to form a double-layer multi-cavity wiring board POP structure package. A method of manufacturing a layer POP structure semiconductor device has been described. It goes without saying that it is easy to manufacture a multi-layer POP structure semiconductor device having two or more layers by using two or more multi-piece wiring board mounting packages by repeating the same method.

図６（２）に、こうして間隙充填層１３が挿入されて製造された、四層のＰＯＰ構造半導体装置２３の例を示す。こうした多層のＰＯＰ構造半導体装置でも、各層の間での間隙充填層１３の存在により、多数個取り基板から個片化へのダイシング工程を経ても、球状端子の接続個所へストレスが集中することなく、歩留まり良く製造することが可能となる。   FIG. 6B shows an example of a four-layer POP structure semiconductor device 23 manufactured by inserting the gap filling layer 13 in this way. Even in such a multi-layer POP structure semiconductor device, due to the presence of the gap filling layer 13 between each layer, stress is not concentrated at the connection point of the spherical terminal even after the dicing process from the multi-piece substrate to the singulation. Thus, it is possible to manufacture with a high yield.

上記実施例で述べた半導体装置の製造方法においては、配線基板上に搭載される半導体素子（半導体素子など電子部品が樹脂封止された封止体）の電極は、配線基板上に形成された薄膜電極上に形成される断面模式図を用いているが、勿論、この接続においても、球状（ボール）電極を用いたフリップチップ接続によって実施しても構わない。また半導体素子（半導体素子など電子部品が樹脂封止された封止体）が配線基板の表面（上面）に配された構成の断面模式図を示してきたが、勿論、配線基板の裏面（下面）や、両面に配された構成でも構わない。   In the method of manufacturing a semiconductor device described in the above embodiment, the electrode of the semiconductor element (sealing body in which an electronic component such as a semiconductor element is resin-sealed) mounted on the wiring board is formed on the wiring board. Although a schematic cross-sectional view formed on a thin film electrode is used, of course, this connection may also be performed by flip chip connection using a spherical (ball) electrode. Moreover, although the cross-sectional schematic diagram of the structure which has arrange | positioned the semiconductor element (sealed body which electronic components, such as a semiconductor element were resin-sealed) was distribute | arranged to the surface (upper surface) of the wiring board was shown, of course, the back surface (lower surface) of a wiring board ) Or a configuration arranged on both sides.

本発明の課題を説明する図The figure explaining the subject of this invention 本発明の方法を説明する図The figure explaining the method of this invention 本発明の方法を実施する具体的方法を説明する図（その１）The figure explaining the concrete method which enforces the method of this invention (the 1) 本発明の方法を実施する具体的方法を説明する図（その２）The figure explaining the concrete method which enforces the method of this invention (the 2) 本発明の方法を実施する具体的方法を説明する図（その３）The figure explaining the specific method which enforces the method of this invention (the 3) 本発明による半導体装置を説明する図FIG. 6 illustrates a semiconductor device according to the present invention. 従来の方法を説明する図Diagram explaining the conventional method

符号の説明Explanation of symbols

１Ａ、１Ｂ、１０１Ａ、１０１Ｂ 多数個取り配線基板実装パッケージ
２Ａ、２Ｂ、１０２Ａ、１０２Ｂ 配線基板
３Ａ、３Ｂ、１０３Ａ、１０３Ｂ 封止体
４Ａ、４Ｂ、１０４Ａ、１０４Ｂ 電極パッド
５Ａ、５Ｂ、１０５Ａ、１０５Ｂ 球状（ボール）電極
６、１０６ 接続電極
７ 二層多数個取り配線基板ＰＯＰ構造パッケージ
８Ａ、８Ｂ 個片領域
９Ａ、９Ｂ 分割領域
１０、１０８ 二層ＰＯＰ構造半導体装置
１１ クラック
１２ 間隙充填層入り二層多数個取り配線基板ＰＯＰ構造パッケージ
１３ 間隙充填層
１４ マスク
１５ 開口部
１６ 熱硬化性樹脂
１７ スキージ
１８ スリット
１９ 非開口個所
２０ ノズル
２１ 形状化テープ
２２ 二層ＰＯＰ構造半導体装置
２３ 多層（四層）ＰＯＰ構造半導体装置
１０７Ａ、１０７Ｂ 個片実装パッケージ
1A, 1B, 101A, 101B Multi-cavity wiring board mounting package 2A, 2B, 102A, 102B Wiring board
3A, 3B, 103A, 103B Sealed body
4A, 4B, 104A, 104B Electrode pad
5A, 5B, 105A, 105B Spherical (ball) electrode 6, 106 Connection electrode 7 Two-layer multi-piece wiring board POP structure package 8A, 8B Single area 9A, 9B Divided area 10, 108 Double-layer POP structure semiconductor device 11 Crack DESCRIPTION OF SYMBOLS 12 Two-layer multi-piece wiring board POP structure package containing gap filling layer 13 Gap filling layer 14 Mask 15 Opening part 16 Thermosetting resin 17 Squeegee 18 Slit 19 Non-opening part 20 Nozzle 21 Shaped tape 22 Two-layer POP structure semiconductor device 23 Multi-layer (four-layer) POP structure semiconductor device 107A, 107B Single package

Claims (5)

複数の第１の半導体素子が搭載された第１の配線基板上に、複数の第２の半導体素子が搭載された第２の配線基板を配置するとともに、前記第１の配線基板と前記第２の配線基板とを導電部材により電気的に接続する工程と、
前記第１の配線基板と前記第２の配線基板とを電気的に接続した後、前記第１の配線基板及び前記第２の配線基板を切断する工程と、を含み、
前記第１の配線基板及び前記第２の配線基板を切断する前に、前記第１の配線基板と前記第２の配線基板との間に補強部材が配置されていることを特徴とする半導体装置の製造方法。 A second wiring board on which a plurality of second semiconductor elements are mounted is disposed on a first wiring board on which a plurality of first semiconductor elements are mounted, and the first wiring board and the second wiring board are arranged. Electrically connecting the wiring board with a conductive member;
Cutting the first wiring board and the second wiring board after electrically connecting the first wiring board and the second wiring board;
A semiconductor device, wherein a reinforcing member is disposed between the first wiring board and the second wiring board before cutting the first wiring board and the second wiring board. Manufacturing method. 前記第１の配線基板と前記第２の配線基板とを電気的に接続する前に、前記第１の配線基板及び前記第２の配線基板の少なくとも一方に前記補強部材を配設しておくことを特徴とする請求項１記載の半導体装置の製造方法。   The reinforcing member is disposed on at least one of the first wiring board and the second wiring board before electrically connecting the first wiring board and the second wiring board. The method of manufacturing a semiconductor device according to claim 1. 前記補強部材は、前記第１の配線基板上に供給される樹脂であることを特徴とする請求項２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 2, wherein the reinforcing member is a resin supplied onto the first wiring board. 前記補強部材は、前記第１の配線基板上に配置されるテープ材であることを特徴とする請求項２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 2, wherein the reinforcing member is a tape material disposed on the first wiring board. 前記第１の配線基板は、前記第１の半導体素子が搭載される複数の第１の領域と、前記複数の第１の領域を画定する第２の領域とを含み、
前記補強部材は、前記第２の領域上に配設されることを特徴とする請求項１ないし４のいずれかに記載の半導体装置の製造方法。



The first wiring board includes a plurality of first regions on which the first semiconductor elements are mounted, and a second region that defines the plurality of first regions,
5. The method of manufacturing a semiconductor device according to claim 1, wherein the reinforcing member is disposed on the second region.



JP2008068778A 2008-03-18 2008-03-18 Manufacturing method of semiconductor device Pending JP2009224636A (en)

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