JP2009224489A - Wiring substrate equipment - Google Patents

Wiring substrate equipment Download PDF

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JP2009224489A
JP2009224489A JP2008066242A JP2008066242A JP2009224489A JP 2009224489 A JP2009224489 A JP 2009224489A JP 2008066242 A JP2008066242 A JP 2008066242A JP 2008066242 A JP2008066242 A JP 2008066242A JP 2009224489 A JP2009224489 A JP 2009224489A
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differential signal
signal line
wiring
delay
wiring board
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Masahiro Otani
昌弘 大谷
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Toshiba Corp
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Toshiba Corp
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<P>PROBLEM TO BE SOLVED: To provide wiring substrate equipment composed of two differential signal lines wired so as to be parallel to each other, wherein a difference of wiring path lengths is absorbed for a pair of differential signal lines about which regions with different mutual wiring path lengths are prepared to resolve a delay time difference in signals propagation, thereby improving the quality of signal transmission. <P>SOLUTION: Two or more electronic components Sa and Sb are mounted on a wiring substrate 1, to which two differential signal lines G composed of a first differential signal line Ga and a second differential signal line Gb are wired parallel to each other, a dividing region Z is formed in a halfway portion of the pair of differential signal lines, a delay wire object 10 is mounted in this dividing region, on which a first delay wire path 11 and a second delay wire path 12 are prepared that have the same wiring path length, and respective ends of these delay wiring paths and the divided pair of differential signal lines are connected. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、たとえば携帯電話等に搭載され、差動信号伝送方式により2つの電子部品間に信号を伝送する配線基板装置に関する。   The present invention relates to a wiring board device that is mounted on, for example, a mobile phone and transmits a signal between two electronic components by a differential signal transmission method.

一般的には、2つの電子部品間に信号を伝送するのに、いわゆる「シングルエンド伝送方式」が採用されている。これは、1本の信号線を2つの電子部品相互に接続していて、ドライバ側の電子部品からハイレベルの電位信号(以下、「H信号」と呼ぶ)と、ローレベルの電位信号(以下、「L信号」と呼ぶ)を、交互に前記1本の信号線に送る。   In general, a so-called “single-end transmission method” is employed to transmit a signal between two electronic components. This is because one signal line is connected to two electronic components, a high-level potential signal (hereinafter referred to as “H signal”) and a low-level potential signal (hereinafter referred to as “H” signal) from the electronic component on the driver side. , Referred to as “L signal”) alternately to the one signal line.

前記信号線は、レシーバ側の電子部品に、H信号とL信号を交互に伝送する。レシーバ側の電子部品においては、これらH信号とL信号を受けて、たとえばLSIロジック回路を作動する。   The signal line alternately transmits the H signal and the L signal to the electronic component on the receiver side. The electronic component on the receiver side receives these H and L signals and operates, for example, an LSI logic circuit.

このシングルエンド伝送方式は、信号伝送の手段として何らの支障もないが、H信号とL信号との電位差が大であり、信号振幅が大きく、信号切換え時の波形が鮮明でない。そのため、ノイズが発生し易いとともに、単位時間に多くの信号数をとることができない。すなわち、大量の情報を、速く伝送できないという不具合がある。   This single-ended transmission method has no problem as a signal transmission means, but the potential difference between the H signal and the L signal is large, the signal amplitude is large, and the waveform at the time of signal switching is not clear. Therefore, noise is likely to occur and a large number of signals cannot be taken per unit time. That is, there is a problem that a large amount of information cannot be transmitted quickly.

そこで、近年は、「差動信号伝送方式」と呼ばれる信号伝送手段が採用されるようになった。これは、2つの電子部品間を、Pチャンネル配線とNチャンネル配線との2本の差動信号線で結線する。
はじめに、ドライバ側の電子部品からPチャンネル配線にH信号を送るとともに、Nチャンネル配線にL信号を送る。そのあと、ドライバ側の電子部品からPチャンネル配線にL信号を送るとともに、Nチャンネル配線にH信号を送る。
Therefore, in recent years, signal transmission means called “differential signal transmission system” has come to be adopted. In this case, two electronic components are connected by two differential signal lines of P channel wiring and N channel wiring.
First, an H signal is sent from the electronic component on the driver side to the P channel wiring, and an L signal is sent to the N channel wiring. Thereafter, an L signal is sent from the electronic component on the driver side to the P channel wiring, and an H signal is sent to the N channel wiring.

それぞれ信号はPチャンネル配線とNチャンネル配線を介して、レシーバ側の電子部品に送られる。レシーバ側の電子部品においては、これらH信号とL信号を受けて、たとえばLSIロジック回路を作動する。
具体的には、図8(A)に示すように、ドライバ側の電子部品から互いに論理値を逆転した逆位相(「逆相」とも呼ぶ)となる信号を、図8(B)に示すように、対となる2本の差動信号線Ga,Gbに入力する。レシーバ側の電子部品においては、図8(C)に示すように、差動信号線Ga,GBから伝送された信号の電位差でデータを識別する。
Each signal is sent to an electronic component on the receiver side via a P-channel wiring and an N-channel wiring. The electronic component on the receiver side receives these H and L signals and operates, for example, an LSI logic circuit.
Specifically, as shown in FIG. 8 (A), signals having opposite phases (also referred to as “reverse phases”) obtained by reversing the logical values from the electronic components on the driver side are shown in FIG. 8 (B). The two differential signal lines Ga and Gb are input to the pair. In the electronic component on the receiver side, as shown in FIG. 8C, data is identified by the potential difference between the signals transmitted from the differential signal lines Ga and GB.

このような差動信号伝送方式においては、シングルエンド伝送方式と比較して、それぞれの差動信号線が伝送する信号の振幅幅が小さくてすむ。外部からノイズがあっても、その差分に対しては保証されるので、ノイズに強い特徴がある。単位時間に多くの信号を送ることができ、より大量の情報を、より速く伝送できる利点がある。   In such a differential signal transmission method, the amplitude width of the signal transmitted by each differential signal line can be smaller than that in the single-end transmission method. Even if there is noise from the outside, the difference is guaranteed, so it has a strong characteristic against noise. Many signals can be transmitted per unit time, and there is an advantage that a larger amount of information can be transmitted faster.

しかしながら、この差動信号伝送方式には、以下に述べるような制約がある。
すなわち、2本の差動信号線Ga,Gbを用いて信号を送るので、互いの差動信号線Ga,Gbとの間で、何らかの事情により信号の伝送時間に差が生じ、もしくはタイミングずれなどの、いわゆるスキューと呼ばれる現象が生じることがある。
However, this differential signal transmission system has the following limitations.
That is, since signals are sent using the two differential signal lines Ga and Gb, there is a difference in signal transmission time between the differential signal lines Ga and Gb, or a timing shift, etc. A phenomenon called so-called skew may occur.

図9に示すように、本来は、H信号に対してL信号はスキューがない状態(実線で示す)で伝送されるのが理想のタイミングである。しかしながら、後述する理由により、b線(一点鎖線)で示すようなa時間のスキューが生じ、あるいはc線(二点鎖線)で示すような2a時間のスキューが生じることがある。   As shown in FIG. 9, the ideal timing is that the L signal is originally transmitted with no skew (indicated by a solid line) with respect to the H signal. However, due to reasons described later, there may be a skew of a time as shown by b line (one-dot chain line) or a skew of 2a time as shown by c line (two-dot chain line).

図10は、図9に示した2本の差動信号線に流れる信号の電位差の波形であり、太線で示す波形線Aはスキューが無い状態、一点鎖線で示す波形線Bは前記b線で示すスキューがあるとき、二点鎖線で示す波形線Cは前記c線で示すスキューがあるときである。H信号とL信号を識別するのに閾値E,Fを定めていて、H信号は閾値E以上、L信号は閾値F以下とする。   FIG. 10 is a waveform of the potential difference between the signals flowing in the two differential signal lines shown in FIG. 9. The waveform line A indicated by the thick line is in a state without skew, and the waveform line B indicated by the alternate long and short dash line is the b line. When there is a skew indicated, a waveform line C indicated by a two-dot chain line is when there is a skew indicated by the c line. Threshold values E and F are defined for identifying the H signal and the L signal. The H signal is equal to or higher than the threshold value E, and the L signal is equal to or lower than the threshold value F.

いずれの波形線A〜Cであっても、閾値F以下では充分な時間があるので判別するのに支障がない。また、閾値F以上のH信号を識別するのに、波形線Aで示すスキューの無い状態では、閾値Fを越える時間Daが長い。したがって、データを判別するためのトリガ信号をかけるのに充分な時間があり、データ伝送品質を高く保持できる。   Any of the waveform lines A to C has a sufficient time below the threshold F, so that there is no problem in the determination. Further, in order to identify the H signal equal to or higher than the threshold F, the time Da exceeding the threshold F is long when there is no skew indicated by the waveform line A. Therefore, there is sufficient time to apply a trigger signal for discriminating data, and the data transmission quality can be kept high.

しかしながら、波形線Bでは閾値Fを越える時間Dbが短くなり、さらに波形線Cでは閾値Fを越える時間Dcが極めて短い。このようにスキューが大きくなるにしたがって、データを判別するためのトリガ信号をかける時間が不足し、データを判別できる時間が短縮して、信号伝送の品質が低下してしまう。   However, the waveform line B has a short time Db exceeding the threshold F, and the waveform line C has a very short time Dc exceeding the threshold F. Thus, as the skew increases, the time for applying a trigger signal for discriminating data becomes insufficient, the time during which data can be discriminated is shortened, and the signal transmission quality deteriorates.

差動信号伝送方式において、スキューが発生する原因として、2つの電子部品相互間を接続する2本の差動信号線の長さが互いに相違している場合と、2本の差動信号線の長さは互いに完全同一ではあるけれども、電子部品と差動信号線対とを接続するコネクタの構造自体に問題がある場合が考えられる。   In the differential signal transmission method, the cause of the skew is that the lengths of the two differential signal lines connecting the two electronic components are different from each other, Although the lengths are completely the same, there may be a problem in the structure of the connector that connects the electronic component and the differential signal line pair.

後者のコネクタの構造に問題がない場合、[特許文献1]は、前者の2つの電子部品間を接続する2本の信号線の長さが互いに相違しているのに近い状態で対応している。すなわち、この発明は、プリント配線基板に形成される複数組の差動信号線対をジグザグ状に蛇行形成して、遅延配線路長を実質的に同一としている。
特開2004−325820号公報
When there is no problem in the structure of the latter connector, [Patent Document 1] responds in a state where the lengths of the two signal lines connecting the two electronic components are different from each other. Yes. That is, according to the present invention, a plurality of sets of differential signal line pairs formed on a printed wiring board meander in a zigzag manner so that the delay wiring path lengths are substantially the same.
JP 2004-325820 A

しかしながら、[特許文献1]の技術は、2つの電子部品間に何らの障害物(電気部品等)も存在せず、整然と、複数組の差動信号線対をジグザグ状に蛇行形成できる場合に限る。実際には、2つの電子部品間に他の電子部品や電気部品が介在することは、ごく普通の構成である。   However, the technique of [Patent Document 1] is in the case where there are no obstacles (electrical parts, etc.) between two electronic components, and a plurality of differential signal line pairs can be formed in a zigzag manner in an orderly manner. Limited. Actually, it is an ordinary configuration that another electronic component or electrical component is interposed between two electronic components.

このときは、プリント配線のレイアウト上、差動信号線対の中途部を屈曲して迂回する。あるいは、一方の差動信号線は直状で、他方の差動信号線のみ屈曲しなければならない。いずれにしても、一方の差動信号線の長さと、他方の差動信号線の長さが相違することが多く、前記したスキューの発生要因となってしまう。   At this time, the middle part of the differential signal line pair is bent to bypass the printed wiring layout. Alternatively, one differential signal line is straight and only the other differential signal line must be bent. In any case, the length of one differential signal line is often different from the length of the other differential signal line, which causes the aforementioned skew.

たとえば、図11に示す配線基板装置がある。すなわち、第1の電子部品Saと、第2の電子部品Sbが配線基板上の互いに離間した位置に実装される。これら第1、第2の電子部品Sa,Sb相互を電気的に接続する第1の差動信号線Gaと、第2の差動信号線Gbとからなる、差動信号線対Gがプリント配線されている。   For example, there is a wiring board device shown in FIG. That is, the first electronic component Sa and the second electronic component Sb are mounted at positions separated from each other on the wiring board. A differential signal line pair G composed of a first differential signal line Ga and a second differential signal line Gb that electrically connect the first and second electronic components Sa and Sb to each other is printed wiring. Has been.

第1の差動信号線Gaと第2の差動信号線Gbのほとんど大部分は互いに直状で、かつ互いに並行に形成されている。したがって、この並行部分を[特許文献1]のように蛇行形成することで、2本の差動信号線Ga,Gb間における配線路長を実質的に同一とすることはできる。   Almost most of the first differential signal line Ga and the second differential signal line Gb are formed in a straight line with each other and in parallel with each other. Therefore, the parallel path length between the two differential signal lines Ga and Gb can be made substantially the same by forming the parallel portion meandering as in [Patent Document 1].

しかしながら、ここでは第1の差動信号線Gaのみ、この両端部に屈曲部Kが設けられる。第1の差動信号線Gaの配線路長をL1(mm)、第2の差動信号線Gbの配線路長をL2(mm)とすると、第1の差動信号線Gaは2つの屈曲部Kが形成されるので、この配線路長L1は、第2の差動信号線Gbの配線路長L2より長い。   However, here, only the first differential signal line Ga is provided with bent portions K at both ends thereof. When the wiring path length of the first differential signal line Ga is L1 (mm) and the wiring path length of the second differential signal line Gb is L2 (mm), the first differential signal line Ga has two bends. Since the portion K is formed, the wiring path length L1 is longer than the wiring path length L2 of the second differential signal line Gb.

以上の条件において、第1の差動信号線Gaにおいて第1の電子部品Saから第2の電子部品Sb間に伝送(伝播)される信号の伝送時間(t1:s)と、第2の差動信号線Gbにおいて第1の電子部品Saから第2の電子部品Sb間に伝送(伝播)される信号の伝送時間(t2:s)を求める。
第1の差動信号線Ga: t1(s) = L1(mm)/Vg(m/s)
第2の差動信号線Gb: t2(s) = L2(mm)/Vg(m/s)
前記Vg(m/s)は位相速度である。すなわち、信号が単位時間あたりに進む(変化する)位相量であって、配線基板の物性値と差動信号線の線路幅で決まる値である。このように、対となる差動信号線の長さL1,L2が異なると、伝送時間t1,t2も異なることとなり、先に説明したスキューの発生要因となる。
Under the above conditions, the transmission time (t1: s) of the signal transmitted (propagated) between the first electronic component Sa and the second electronic component Sb on the first differential signal line Ga, and the second difference A transmission time (t2: s) of a signal transmitted (propagated) between the first electronic component Sa and the second electronic component Sb on the dynamic signal line Gb is obtained.
First differential signal line Ga: t1 (s) = L1 (mm) / Vg (m / s)
Second differential signal line Gb: t2 (s) = L2 (mm) / Vg (m / s)
The Vg (m / s) is a phase velocity. That is, it is a phase amount that a signal advances (changes) per unit time, and is a value determined by the physical property value of the wiring board and the line width of the differential signal line. As described above, if the lengths L1 and L2 of the differential signal lines to be paired are different, the transmission times t1 and t2 are also different, which causes the skew described above.

[特許文献1]の技術を用いて、差動信号線Ga,Gb相互のほとんど大部分の配線路長を同一にできたとしても、互いの差動信号線Ga,Gbの一部に配線路長が少しでも相違する箇所(屈曲部Kなど)があれば、結果として配線路長全体が相違してしまう。そのため、各差動信号線における位相速度が相違して、差動信号伝送の品質劣化を防止するには至らない。   Even if the wiring path lengths of most of the differential signal lines Ga and Gb can be made the same by using the technique of [Patent Document 1], the wiring path is connected to a part of the mutual differential signal lines Ga and Gb. If there is a place where the length is slightly different (such as the bent portion K), the entire wiring path length will be different as a result. For this reason, the phase velocities of the differential signal lines are different, and it is impossible to prevent the quality deterioration of the differential signal transmission.

本発明は上記事情にもとづきなされたものであり、その目的とするところは、互いに並行して配線される2本の差動信号線からなり、互いの差動信号線の配線路長が異なる部位が形成される差動信号線対に対して配線路長の相違を吸収し、信号伝播の遅延時間差を解消して、信号伝送品質の向上化を得る配線基板装置を提供しようとするものである。   The present invention has been made on the basis of the above circumstances, and an object of the present invention is to be composed of two differential signal lines that are wired in parallel to each other, where the differential signal lines have different wiring path lengths. It is intended to provide a wiring board device that absorbs a difference in wiring path length with respect to a differential signal line pair formed, eliminates a delay time difference in signal propagation, and improves signal transmission quality. .

上記目的を満足するため本発明は、配線基板に複数の電子部品を実装し、この配線基板に一対の差動信号線からなる差動信号線対を互いに並行して配線し、この差動信号線対の中途部に分断された領域を形成し、この分断された領域の配線基板に遅延配線体を実装し、この遅延配線体に互いの配線路長を同一に設定した第1の遅延配線路および第2の遅延配線路を設け、これら遅延配線路のそれぞれ端部と、分断された一対の差動信号線とを接続した。   In order to satisfy the above-described object, the present invention mounts a plurality of electronic components on a wiring board, and wires a differential signal line pair composed of a pair of differential signal lines on the wiring board in parallel with each other. A first delay wiring in which a divided region is formed in the middle of the line pair, a delay wiring body is mounted on the wiring board in the divided region, and the length of each wiring path is set to be the same in this delay wiring body A path and a second delay wiring path are provided, and each end of the delay wiring path is connected to a pair of divided differential signal lines.

本発明によれば、互いの差動信号線の配線路長が相違する部位における信号伝播の遅延を解消して、差動信号配線のバランス乱れを最小限に止め、信号伝送品質の向上化を得るという効果を奏する。   According to the present invention, the delay of signal propagation in the part where the wiring path lengths of the differential signal lines are different is eliminated, the balance disturbance of the differential signal wiring is minimized, and the signal transmission quality is improved. There is an effect of obtaining.

以下、本発明の実施の形態を、図面にもとづいて説明する。
図1(A)は、配線基板装置の基本構成を説明する図である。
いわゆる、「差動信号伝送方式」と呼ばれる信号伝送手段を採用するため、第1の電子部品Saと、第2の電子部品Sbとの間を、一対(2本)の差動信号線からなる差動信号線対Gで結線する。いずれか一方の差動信号線を、「第1の差動信号線Ga」と呼び、他方の差動信号線を、「第2の差動信号線Gb」と呼ぶ。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a diagram illustrating a basic configuration of a wiring board device.
In order to employ a so-called “differential signal transmission method”, a pair of (two) differential signal lines are formed between the first electronic component Sa and the second electronic component Sb. The differential signal line pair G is used for connection. One of the differential signal lines is referred to as “first differential signal line Ga”, and the other differential signal line is referred to as “second differential signal line Gb”.

第1の電子部品Saと第2の電子部品Sb間を最短距離で結線するため、差動信号線対Gを直状に配線できれば、第1の差動信号線Gaの配線路長と、第2の差動信号線Gbの配線路長とが互いに同一となり、信号伝播時間が同一でスキューの発生はない。
しかしながら、配線基板1には多くの電子部品が実装されていることから、図に示すように中途部に屈曲部Kが形成されてしまう。前記屈曲部Kにおいて、外側配線を第1の差動信号線Gaとし、内側配線を第2の差動信号線Gbとすると、屈曲部Kでの第1の差動信号線Gaの配線路長Laは、第2の差動信号線Gbの配線路長Lbよりも長い。
In order to connect the first electronic component Sa and the second electronic component Sb with the shortest distance, if the differential signal line pair G can be wired in a straight line, the wiring path length of the first differential signal line Ga, The two differential signal lines Gb have the same wiring path length, the same signal propagation time, and no skew.
However, since many electronic components are mounted on the wiring board 1, a bent portion K is formed in the middle as shown in the figure. In the bent portion K, when the outer wiring is the first differential signal line Ga and the inner wiring is the second differential signal line Gb, the wiring path length of the first differential signal line Ga at the bent portion K La is longer than the wiring path length Lb of the second differential signal line Gb.

ただし、第1の電子部品Saから屈曲部Kの一端部に至る間の距離Lcにおける、第1、第2の差動信号線Ga,Gbの配線路長は互いに同一である。さらに、屈曲部Kの他端部から第2の電子部品Sbに至る間の距離Ldにおける、第1、第2の差動信号線Ga,Gbの配線路長は互いに同一である。   However, the wiring path lengths of the first and second differential signal lines Ga and Gb at the distance Lc from the first electronic component Sa to one end of the bent portion K are the same. Furthermore, the wiring path lengths of the first and second differential signal lines Ga and Gb at the distance Ld between the other end of the bent portion K and the second electronic component Sb are the same.

このように、屈曲部Kを除く両側部位において差動信号線対Gを構成する第1の差動信号線Gaと、第2の差動信号線Gbの合計配線路長Lc+Ldは互いに同一であるので、屈曲部Kにおいても互いの差動信号線Ga,Gbの配線路長La,Lbを実質的に同一に形成しなければならない。   As described above, the total wiring path length Lc + Ld of the first differential signal line Ga and the second differential signal line Gb constituting the differential signal line pair G is the same in both side portions excluding the bent portion K. Therefore, the wiring path lengths La and Lb of the differential signal lines Ga and Gb must be formed substantially the same in the bent portion K.

図1(B)は、本発明における第1の実施の形態に係る、配線基板装置一部の模式的な説明図である。
配線基板1の板面に、第1の電子部品Saと、第2の電子部品Sbが互いに離間した位置に実装される。第1の電子部品Saから第2の電子部品Sbに、互いに並行して第1の差動信号線Gaと第2の差動信号線Gbからなる差動信号線対Gが接続される。
FIG. 1B is a schematic explanatory view of a part of the wiring board device according to the first embodiment of the present invention.
The first electronic component Sa and the second electronic component Sb are mounted on the plate surface of the wiring board 1 at positions separated from each other. A differential signal line pair G including a first differential signal line Ga and a second differential signal line Gb is connected in parallel with each other from the first electronic component Sa to the second electronic component Sb.

前記差動信号線対Gの中途部に形成される屈曲部Kに相当する部位が分断されて、分断領域Zが設けられる。したがって、第1の電子部品Saから分断領域Zに至るまでの差動信号線対Gの線方向と、分断領域Zから第2の電子部品Sbに至るまでの差動信号線対Gの線方向とが相違し、ここでは互いに直角状(90°)に交差する。   A portion corresponding to the bent portion K formed in the middle portion of the differential signal line pair G is divided, and a divided region Z is provided. Therefore, the line direction of the differential signal line pair G from the first electronic component Sa to the divided region Z and the line direction of the differential signal line pair G from the divided region Z to the second electronic component Sb. Here, they intersect each other at right angles (90 °).

前記分断領域Zに、遅延配線体10が当て嵌められ、かつ配線基板1に実装される。前記遅延配線体10は、後述するように複数の構成が考えられるが、いずれも2つの配線パターンである第1の遅延配線路11と、第2の遅延配線路12を備えている。これら第1の遅延配線路11の配線路長と、第2の遅延配線路12の配線路長は互いに同一に設定されていることが特徴である。   The delay wiring body 10 is fitted in the dividing region Z and mounted on the wiring board 1. The delay wiring body 10 may have a plurality of configurations as will be described later, and includes a first delay wiring path 11 and a second delay wiring path 12 each having two wiring patterns. The wiring path length of the first delay wiring path 11 and the wiring path length of the second delay wiring path 12 are the same as each other.

第1の遅延配線路11の両端には接続部g1,g2が設けられていて、一端側の接続部g1は、第1の電子部品Saから配線される第1の差動信号線Gaの分断領域端部に接続される。他端側の接続部g2は、第2の電子部品Sbに至る第1の差動信号線Gaの分断領域端部に接続される。   Connection portions g1 and g2 are provided at both ends of the first delay wiring path 11, and the connection portion g1 on one end side is a division of the first differential signal line Ga wired from the first electronic component Sa. Connected to the edge of the region. The connection part g2 on the other end side is connected to the end part of the divided region of the first differential signal line Ga reaching the second electronic component Sb.

第2の遅延配線路12の両端にも接続部h1,h2が設けられていて、一端側の接続部h1は、第1の電子部品Saから配線される第2の差動信号線Gbの分断領域端部に接続される。他端側の接続部h2は、第2の電子部品Sbに至る第2の差動信号線Gbの分断領域端部に接続される。   Connection portions h1 and h2 are also provided at both ends of the second delay wiring path 12, and the connection portion h1 on one end side is divided by the second differential signal line Gb wired from the first electronic component Sa. Connected to the edge of the region. The connection portion h2 on the other end side is connected to the end portion of the divided region of the second differential signal line Gb that reaches the second electronic component Sb.

第1の電子部品Saから分断領域Zに至るまでの差動信号線対Gの線方向と、分断領域Zから第2の電子部品Sbに至るまでの差動信号線対Gの線方向とが互いに直交している。そのままの配線であれば、屈曲部Kにおいて、外側配線である第1の差動信号線Gaの配線路長と、内側配線である第2の差動信号線Gbの配線路長が相違する。   The line direction of the differential signal line pair G from the first electronic component Sa to the dividing region Z and the line direction of the differential signal line pair G from the dividing region Z to the second electronic component Sb are: They are orthogonal to each other. If the wiring is as it is, the wiring path length of the first differential signal line Ga that is the outer wiring differs from the wiring path length of the second differential signal line Gb that is the inner wiring at the bent portion K.

しかしながら、前記屈曲部Kに相当する部位を分断し、この分断領域Zに前記遅延配線体10を実装している。前記遅延配線体10は、互いに同じ長さの配線路長に形成される第1の遅延配線路11と、第2の遅延配線路12を備えている。
前述したように、第1の電子部品Saから分断領域Z(すなわち、遅延配線体10)に至るまでの第1の差動信号線Gaの配線路長および第2の差動信号線12の配線路長が互いに等く、分断領域Z(遅延配線体10)から第2の電子部品Sbに至る第1の差動信号線Gaの配線路長および第2の差動信号線12の配線路長が互いに等しい。
However, the portion corresponding to the bent portion K is divided, and the delay wiring body 10 is mounted in the divided region Z. The delay wiring body 10 includes a first delay wiring path 11 and a second delay wiring path 12 which are formed to have the same wiring path length.
As described above, the wiring path length of the first differential signal line Ga and the wiring of the second differential signal line 12 from the first electronic component Sa to the divided region Z (that is, the delay wiring body 10). The path lengths of the first differential signal lines Ga and the path lengths of the second differential signal lines 12 from the divided region Z (delay wiring body 10) to the second electronic component Sb are equal to each other. Are equal to each other.

したがって、第1の電子部品Saから第1の差動信号線Gaと、遅延配線体10の第1の遅延配線路11および第1の差動信号線Gaを介して第2の電子部品Sbに至るまでの全配線路長と、第1の電子部品Saから第2の差動信号線Gbと、遅延配線体10の第2の遅延配線路12および第2の差動信号線Gbを介して第2の電子部品Sbに至るまでの全配線路長とが、互いに等しい。   Therefore, from the first electronic component Sa to the first differential signal line Ga and the second electronic component Sb via the first delay wiring path 11 of the delay wiring body 10 and the first differential signal line Ga. Through the first electronic component Sa to the second differential signal line Gb, the second delay wiring path 12 of the delay wiring body 10 and the second differential signal line Gb. The total wiring path length up to the second electronic component Sb is equal to each other.

このような構成を採用して、たとえば第1の差動信号線GaをPチャンネル配線とし、第2の差動信号線GbをNチャンネル配線として、ドライバ側の電子部品である第1の電子部品Saから第1の差動信号線GaにH信号を送るとともに、第2の差動信号線GbにL信号を送る。   By adopting such a configuration, for example, the first differential signal line Ga is a P-channel wiring, and the second differential signal line Gb is an N-channel wiring. An H signal is sent from Sa to the first differential signal line Ga, and an L signal is sent to the second differential signal line Gb.

そのあと、第1の電子部品Saから第1の差動信号線GaにL信号を送るとともに、第2の差動信号線GbにH信号を送る。さらに、第1の電子部品Saから第1の差動信号線GaにH信号を送るとともに、第2の差動信号線GbにL信号を送る。
交互に送られるL信号とH信号は、第1の差動信号線Gaと第1の遅延配線路11および、第2の差動信号線Gbと第2の遅延配線路12を、それぞれ介して、レシーバ側の電子部品である第2の電子部品Sbへ送られる。
Thereafter, an L signal is sent from the first electronic component Sa to the first differential signal line Ga, and an H signal is sent to the second differential signal line Gb. Further, an H signal is sent from the first electronic component Sa to the first differential signal line Ga, and an L signal is sent to the second differential signal line Gb.
The L signal and the H signal sent alternately are respectively transmitted through the first differential signal line Ga and the first delay wiring path 11 and the second differential signal line Gb and the second delay wiring path 12. The second electronic component Sb which is the electronic component on the receiver side is sent.

第2の電子部品Sbにおいては、これら2本の差動信号線Ga,Gbおよび第1、第2の遅延配線路11,12からH信号とL信号を交互に受け、伝送された信号の電位差でデータを識別して、たとえばLSIロジック回路を作動し信号処理をなす。
このように、第1の電子部品Saから第2の電子部品Sbに至るまでの差動信号線対Gの中途部に、互いの差動信号線Ga,Gbの配線路長が異なる部位があっても、そこに遅延配線体10を備えることで、第1、第2の差動信号線Ga,Gb相互の配線路長の相違を吸収するので、互いの配線路長が等しくなる。
In the second electronic component Sb, the H signal and the L signal are alternately received from the two differential signal lines Ga and Gb and the first and second delay wiring lines 11 and 12, and the potential difference between the transmitted signals is determined. Then, the data is identified and, for example, an LSI logic circuit is operated to perform signal processing.
As described above, there is a portion where the wiring lengths of the differential signal lines Ga and Gb are different in the middle portion of the differential signal line pair G from the first electronic component Sa to the second electronic component Sb. However, by providing the delay wiring body 10 there, the difference in wiring path length between the first and second differential signal lines Ga and Gb is absorbed, so that the wiring path lengths are equal to each other.

したがって、配線基板1の物性値と線路幅で決まる、信号の単位時間当たりに進む位相量である位相速度(Vg[m/s])が、互いに同一となる。第1の電子部品Saから差動信号線対Gおよび遅延配線体10を介して第2の電子部品Sbへ、L信号とH信号がスキューの無い状態で交互に導かれ、鮮明な波形が得られて、データ伝送品質の向上化を図れる。   Therefore, the phase velocities (Vg [m / s]), which are phase amounts advanced per unit time of the signal, determined by the physical property value of the wiring board 1 and the line width are the same. The L signal and the H signal are alternately led from the first electronic component Sa through the differential signal line pair G and the delay wiring body 10 to the second electronic component Sb without any skew to obtain a clear waveform. Thus, the data transmission quality can be improved.

以下、より具体的な構成を説明する。
図2(A)(B)は、第1の実施の形態に係る第1実施例の、基板配線装置一部の斜視図と、基板配線装置の分解した斜視図である。
ここでは、第1の電子部品Saおよび第2の電子部品Sbを省略しているが、これらは先に図1(A)(B)で説明したように実装されているものとする。第1の電子部品Saから第2の電子部品Sbに、第1の差動信号線Gaおよび第2の差動信号線Gbからなる差動信号線対Gが接続される。
Hereinafter, a more specific configuration will be described.
FIGS. 2A and 2B are a perspective view of a part of the substrate wiring device and an exploded perspective view of the substrate wiring device in the first example according to the first embodiment.
Here, the first electronic component Sa and the second electronic component Sb are omitted, but they are assumed to be mounted as described above with reference to FIGS. A differential signal line pair G composed of a first differential signal line Ga and a second differential signal line Gb is connected from the first electronic component Sa to the second electronic component Sb.

前記差動信号線対Gの中途部に分断領域Zが形成されていて、第1の電子部品Saから分断領域Zに至るまでの差動信号線対Gの線方向と、分断領域Zから第2の電子部品Sbに至るまでの差動信号線対Gの線方向とが相違し、互いに直角状に交差する。前記分断領域Zに遅延配線体10Aが当て嵌められ、かつ配線基板1に実装される。   A dividing region Z is formed in the middle portion of the differential signal line pair G, the line direction of the differential signal line pair G from the first electronic component Sa to the dividing region Z, and the dividing region Z The line direction of the differential signal line pair G up to the second electronic component Sb is different and intersects at right angles. The delay wiring body 10 </ b> A is fitted into the dividing region Z and mounted on the wiring board 1.

前記遅延配線体10Aは、所定の板厚を有し、平面視で矩形状をなすブロック体からなる。この遅延配線体10Aに、後述する第1の遅延配線路11aおよび第2の遅延配線路12aが設けられる。
すなわち、前記第1の電子部品Saと対向する遅延配線体10Aの側面m1に、第1の遅延配線路11aおよび第2の遅延配線路12aの一方の接続部g1,h1が設けられる。また、第2の電子部品Sbと対向する遅延配線体10Aの他側面m2に、第1の遅延配線路11aおよび第2の遅延配線路12aの他方の接続部g2,h2が設けられる。
The delay wiring body 10A is a block body having a predetermined plate thickness and having a rectangular shape in plan view. The delay wiring body 10A is provided with a first delay wiring path 11a and a second delay wiring path 12a described later.
That is, one connection part g1, h1 of the first delay wiring path 11a and the second delay wiring path 12a is provided on the side surface m1 of the delay wiring body 10A facing the first electronic component Sa. Further, the other connection portions g2 and h2 of the first delay wiring path 11a and the second delay wiring path 12a are provided on the other side surface m2 of the delay wiring body 10A facing the second electronic component Sb.

前記それぞれの接続部g1,g2,h1,h2の具体的構造は特に図示していないが、遅延配線体10Aの側面から外方へ突出する舌片でよい。したがって、第1の遅延配線路11aの両接続部g1,g2は、第1の差動信号線Gaの分断された端部に確実に接続される。第2の遅延配線路12aの両接続部h1,h2は、第2の差動信号線Gbの分断された端部に確実に接続される。   Although the specific structure of each of the connection portions g1, g2, h1, and h2 is not particularly illustrated, a tongue piece protruding outward from the side surface of the delay wiring body 10A may be used. Therefore, both connection parts g1 and g2 of the first delay wiring path 11a are reliably connected to the divided end of the first differential signal line Ga. Both connection portions h1 and h2 of the second delay wiring path 12a are securely connected to the divided end portion of the second differential signal line Gb.

前記遅延配線体10Aにおいて、第1の遅延配線路11aの両接続部g1,g2相互間は、配線基板1への実装面である主面m3に設けられていて、ここでは分断される以前の屈曲部Kにおける外側差動信号線と全く同一の直角状に形成される。
なお説明すると、前記第1の遅延配線路11aは、一方の接続部g1から主面m3において第1の電子部品Saに接続する第1の差動信号線Gaの線方向に沿って延長される。中途部で、第2の電子部品Sbに接続する第1の差動信号線Gaの線方向に沿うよう屈曲され、他方の接続部g2に至る。
In the delay wiring body 10A, the connection portions g1 and g2 of the first delay wiring path 11a are provided on the main surface m3 which is a mounting surface on the wiring board 1, and here, before the separation. The bent portion K is formed in the same right-angle shape as the outer differential signal line.
In other words, the first delay wiring path 11a extends from the one connection portion g1 along the line direction of the first differential signal line Ga connected to the first electronic component Sa on the main surface m3. . In the middle part, it is bent along the line direction of the first differential signal line Ga connected to the second electronic component Sb and reaches the other connection part g2.

一方、前記第2の遅延配線路12aは、接続部h1から側面m1を直上して横断し、さらに前記主面m3と対向する主面m4に延長される。この主面m4において、分断される以前の屈曲部Kを形成する内側差動信号線と全く同一の直角状に屈曲形成される。さらに、側面m2を直下して横断し、前記接続部h2に至る。   On the other hand, the second delay wiring path 12a extends from the connection portion h1 directly above the side surface m1 to the main surface m4 facing the main surface m3. The main surface m4 is bent at the same right angle as the inner differential signal line forming the bent portion K before being divided. Furthermore, it traverses right below the side surface m2 and reaches the connecting portion h2.

このように、前記遅延配線体10Aに設けられる第1の遅延配線路11aは、一方の主面m3のみに屈曲形成されるだけの配線路長となる。これに対して前記第2の遅延配線路12aは、90°存した2つの側面m1,m2に設けられる部分と、他方の主面m4に屈曲形成される部分との、合計の配線路長である。   In this way, the first delay wiring path 11a provided in the delay wiring body 10A has a wiring path length that is only bent and formed only on one main surface m3. On the other hand, the second delay wiring path 12a has a total wiring path length of a portion provided on two side surfaces m1 and m2 which are 90 ° and a portion formed to bend on the other main surface m4. is there.

そのため、第2の遅延配線路12aが第1の遅延配線路11aの内側配線になっているにもかかわらず、第2の遅延配線路12aの配線路長は第1の遅延配線路11aの配線路長と互いに同一となる。
以上の構成の配線基板装置において、たとえば、第1の差動信号線GaをPチャンネル配線とし、第2の差動信号線GbをNチャンネル配線として、ドライバ側の電子部品である第1の電子部品Saからレシーバ側の電子部品である第2の電子部品Sbに、H信号とL信号を同時に送り、そのあと、交互に、かつ同時に送る。
Therefore, even though the second delay wiring path 12a is the inner wiring of the first delay wiring path 11a, the wiring length of the second delay wiring path 12a is the wiring of the first delay wiring path 11a. It is the same as the road length.
In the wiring board device having the above configuration, for example, the first differential signal line Ga is a P-channel wiring, and the second differential signal line Gb is an N-channel wiring. The H signal and the L signal are sent simultaneously from the component Sa to the second electronic component Sb which is the electronic component on the receiver side, and then alternately and simultaneously.

第2の電子部品Sbにおいては、これら2本の差動信号線Ga,Gbと2つの遅延配線路11a,12aからH信号とL信号を交互に受ける。そして、伝送された信号の電位差でデータを識別し、たとえばLSIロジック回路を作動して信号処理をなす。
第1の電子部品Saから第2の電子部品Sbに至るまでの間に、本来、差動信号線対Gの配線路長が異なる部位があっても、遅延配線体10Aを備えることで配線路長の相違を吸収でき、信号伝播の遅延時間差であるスキューを解消して、差動信号線対Gのバランスを最小限に止め、信号伝送品質の向上を得られる。
In the second electronic component Sb, the H signal and the L signal are alternately received from the two differential signal lines Ga and Gb and the two delay wiring paths 11a and 12a. Then, data is identified by the potential difference of the transmitted signal, and signal processing is performed by operating, for example, an LSI logic circuit.
Even if there is a portion where the wiring path length of the differential signal line pair G is originally different from the first electronic component Sa to the second electronic component Sb, the wiring path can be provided by providing the delay wiring body 10A. Differences in length can be absorbed, skew that is a difference in signal propagation delay time is eliminated, the balance of the differential signal line pair G is minimized, and signal transmission quality can be improved.

図3は、第1の実施の形態に係る第2実施例の、基板配線装置一部の斜視図である。
ここでは、第1の電子部品Saと第2の電子部品Sbおよび配線基板1を省略しているが、配線基板1に対し第1の電子部品Saと第2の電子部品Sbは先に図1で説明した位置に実装されている。
FIG. 3 is a perspective view of a part of the substrate wiring apparatus of the second example according to the first embodiment.
Here, the first electronic component Sa, the second electronic component Sb, and the wiring board 1 are omitted, but the first electronic component Sa and the second electronic component Sb are first shown in FIG. It is mounted at the position explained in.

第1の電子部品Saから第2の電子部品Sbに、第1の差動信号線Gaと第2の差動信号線Gbとからなる差動信号線対Gが接続される。この差動信号線対Gの中途部に分断領域Zが形成され、第1の電子部品Saから分断領域Zに至るまでの差動信号線対Gの線方向と、分断領域Zから第2の電子部品Sbに至るまでの差動信号線対Gの線方向とが、互いに直角状に交差する。   A differential signal line pair G including a first differential signal line Ga and a second differential signal line Gb is connected from the first electronic component Sa to the second electronic component Sb. A dividing region Z is formed in the middle portion of the differential signal line pair G, the line direction of the differential signal line pair G from the first electronic component Sa to the dividing region Z, and the second region from the dividing region Z. The line direction of the differential signal line pair G up to the electronic component Sb intersects at right angles.

前記分断領域Zに遅延配線体10Bが当て嵌められ、かつ配線基板1に実装される。この遅延配線体10Bは、所定の板厚を有し平面視で矩形状をなす遅延配線層を、複数枚(ここでは3枚)積層して、互いを一体化したブロック体をなしている。
配線基板1に直接実装される最下部の遅延配線層を「第1の遅延配線層10b1」と呼び、中間部の遅延配線層を「第2の遅延配線層10b2」と呼び、最上部の遅延配線層を「第3の遅延配線層10b3」と呼ぶ。
The delay wiring body 10 </ b> B is fitted to the dividing region Z and mounted on the wiring board 1. The delay wiring body 10B is a block body in which a plurality (three in this case) of delay wiring layers having a predetermined plate thickness and having a rectangular shape in plan view are stacked and integrated with each other.
The lowermost delay wiring layer directly mounted on the wiring board 1 is called “first delay wiring layer 10b1”, the middle delay wiring layer is called “second delay wiring layer 10b2”, and the uppermost delay wiring layer is called delay. The wiring layer is referred to as “third delay wiring layer 10b3”.

このように、第1の遅延配線層10b1と第2の遅延配線層10b2および第3の遅延配線層10b3を積層し一体化してなる遅延配線体10Bに、第1の遅延配線路11bと第2の遅延配線路12bが設けられる。
すなわち、第1の電子部品Saと対向する第1の遅延配線層10b1の側面m1に、第1の遅延配線路11bと第2の遅延配線路12bの一方の接続部g1、h1が設けられる。また、第2の電子部品Sbと対向する第1の遅延配線層10b1の他側面m2に、第1の遅延配線路11bと第2の遅延配線路12bの他方の接続部g2、h2が設けられる。
As described above, the first delay wiring path 10b1, the second delay wiring layer 10b2, and the third delay wiring layer 10b3 are laminated and integrated into the delay wiring body 10B. Delay wiring path 12b is provided.
That is, one connection part g1, h1 of the first delay wiring path 11b and the second delay wiring path 12b is provided on the side surface m1 of the first delay wiring layer 10b1 facing the first electronic component Sa. Further, the other connection portions g2 and h2 of the first delay wiring path 11b and the second delay wiring path 12b are provided on the other side surface m2 of the first delay wiring layer 10b1 facing the second electronic component Sb. .

前記第1の遅延配線路11bは、一方の接続部g1から第1の遅延配線層10b1の側面を直上して横断し、配線基板1に実装される主面と対向する主面(上面)m5において屈曲形成される。屈曲形状は、分断される以前の屈曲部Kの外側配線と全く同一の直角状である。この主面m5から側面m2を直下して横断し、他方の接続部g2に至る。   The first delay wiring path 11b traverses the first delay wiring layer 10b1 right above the side surface of the first delay wiring layer 10b1 from one connecting portion g1 and faces the main surface (upper surface) m5 that is mounted on the wiring board 1. Is bent. The bent shape is exactly the same right angle as the outer wiring of the bent portion K before being divided. The main surface m5 is crossed directly below the side surface m2 and reaches the other connection portion g2.

前記第2の遅延配線路12bは、一方の接続部h1から第1の遅延配線層10b1および第2の遅延配線層10b2のそれぞれ側面m1を直上して横断し、第2の遅延配線層10b2の主面(上面)m6において屈曲形成される。屈曲形状は、分断される以前の屈曲部Kの内側配線と全く同一である。この主面m6から第2の遅延配線層10b2と第1の遅延配線層10b1のそれぞれ側面m2を直下して横断し、他方の接続部h2に至る。   The second delay wiring path 12b crosses the first delay wiring layer 10b1 and the second delay wiring layer 10b2 directly above the side surface m1 from one connection portion h1, and passes through the second delay wiring layer 10b2. The main surface (upper surface) m6 is bent. The bent shape is exactly the same as the inner wiring of the bent portion K before being divided. From the main surface m6, the second delay wiring layer 10b2 and the first delay wiring layer 10b1 are respectively crossed directly below the side surfaces m2 to reach the other connection portion h2.

図2に示す例と相違する点は、複数(3枚)の遅延配線層10b1〜10b3を重ね合わせて遅延配線体10Bを構成することと、第1の遅延配線路11bと第2の遅延配線路12bがともに、第1の遅延配線層10b1と第2の遅延配線層10b2の互いに異なる側面m1,m2に形成されることである。   The difference from the example shown in FIG. 2 is that a plurality of (three) delay wiring layers 10b1 to 10b3 are overlapped to form the delay wiring body 10B, and the first delay wiring path 11b and the second delay wiring are formed. Both of the paths 12b are formed on different side surfaces m1 and m2 of the first delay wiring layer 10b1 and the second delay wiring layer 10b2.

結果として、図2に示す例と同一の作用効果を有するとともに、第1の遅延配線路10b1および第2の遅延配線路10b2が、ともに遅延配線体10Bの側面に露出するので、それぞれの接続部g1,g2と第1の差動信号線Gaの分断端部に対する接続位置と接続状態の確認がし易いとともに、接続部h1,h2と第2の差動信号線Gbの分断端部に対する接続位置と接続状態の確認がし易く、作業性の向上を図ることができる。   As a result, the first delay wiring path 10b1 and the second delay wiring path 10b2 are both exposed to the side surface of the delay wiring body 10B, and have the same effects as the example shown in FIG. It is easy to check the connection position and connection state of g1, g2 and the first differential signal line Ga with respect to the divided end portion, and to the divided end portions of the connection portions h1, h2 and the second differential signal line Gb. It is easy to check the connection position and connection state, and workability can be improved.

前記第3の遅延配線層10b3には、第1、第2の遅延配線路10b1,10b2が設けられていないが、これら第1、第2の遅延配線路10b1,10b2と、第1、第2の遅延配線層10b1,10b2を覆うカバーの機能を有し、電気的な事故を防止する点で有利である。   The third delay wiring layer 10b3 is not provided with the first and second delay wiring paths 10b1 and 10b2. However, the first and second delay wiring paths 10b1 and 10b2 and the first and second delay wiring paths 10b1 and 10b2 are not provided. This is advantageous in that it has the function of a cover that covers the delay wiring layers 10b1 and 10b2 and prevents electrical accidents.

なお、第1の遅延配線路11bの屈曲部位を第1の遅延配線層10b1の上面m5に形成したが、第2の遅延配線層10b2の下面に設けてもよい。また、第2の遅延配線路12bの屈曲部位を第2の遅延配線層10b2の上面に設けたが、第3の遅延配線層10b3の下面に設けてもよい。   Although the bent portion of the first delay wiring path 11b is formed on the upper surface m5 of the first delay wiring layer 10b1, it may be provided on the lower surface of the second delay wiring layer 10b2. Further, although the bent portion of the second delay wiring path 12b is provided on the upper surface of the second delay wiring layer 10b2, it may be provided on the lower surface of the third delay wiring layer 10b3.

図4は、第1の実施の形態に係る第3実施例の、配線基板装置一部を示す斜視図である。第1の電子部品Saと第2の電子部品Sbおよび配線基板1は省略しているが、ここでは配線基板1に対し第1の電子部品Saと第2の電子部品Sbが、互いに同じ位置に実装されている。   FIG. 4 is a perspective view showing a part of the wiring board device of the third example according to the first embodiment. Although the first electronic component Sa, the second electronic component Sb, and the wiring board 1 are omitted, here, the first electronic component Sa and the second electronic component Sb are in the same position with respect to the wiring board 1. Has been implemented.

第1の電子部品Saから第2の電子部品Sbに、第1の差動信号線Gaと第2の差動信号線Gbとからなる2本の差動信号線である差動信号線対Gが接続される。この差動信号線対Gの中途部に分断領域Zが形成され、第1の電子部品Saから分断領域Zに至るまでの差動信号線対Gの線方向と、分断領域Zから第2の電子部品Sbに至るまでの差動信号線対Gの線方向とが互いに平行する。   A differential signal line pair G, which is two differential signal lines including a first differential signal line Ga and a second differential signal line Gb, from the first electronic component Sa to the second electronic component Sb. Is connected. A dividing region Z is formed in the middle portion of the differential signal line pair G, the line direction of the differential signal line pair G from the first electronic component Sa to the dividing region Z, and the second region from the dividing region Z. The line directions of the differential signal line pair G up to the electronic component Sb are parallel to each other.

前記分断領域Zに遅延配線体10Cが当て嵌められ、かつ配線基板1に実装される。遅延配線体10Cは、所定の板厚を有し平面視で矩形状をなすブロック体からなり、後述する第1の遅延配線路11cおよび第2の遅延配線路12cが設けられる。
すなわち、遅延配線体10Cの一側面m1で、かつ幅方向の一端側に第1の遅延配線路11cおよび第2の遅延配線路12cの、それぞれ一方の接続部g1,h1が設けられる。そして、同じ側面m1で、かつ幅方向の他端側に第1の遅延配線路11cと第2の遅延配線路12cの、それぞれ他方の接続部g2,h2が設けられる。
The delay wiring body 10 </ b> C is fitted into the dividing region Z and mounted on the wiring board 1. The delay wiring body 10C is a block body having a predetermined plate thickness and having a rectangular shape in plan view, and is provided with a first delay wiring path 11c and a second delay wiring path 12c described later.
That is, one connection portion g1, h1 of the first delay wiring path 11c and the second delay wiring path 12c is provided on one side surface m1 of the delay wiring body 10C and on one end side in the width direction. The other connection portions g2 and h2 of the first delay wiring path 11c and the second delay wiring path 12c are provided on the same side surface m1 and on the other end side in the width direction.

前記遅延配線体10Cにおいて、第1の遅延配線路11cの両接続部g1,g2相互間は、配線基板1に実装される遅延配線体10Cの主面m3に設けられている。なお説明すると、それぞれの接続部g1,g2から第1の差動信号線Gaの線方向に沿って延長され、かつ所定部位において延出端部相互が連結され、第1の遅延配線路11cは主面m3において略U字状に形成される。   In the delay wiring body 10C, the connection portions g1 and g2 of the first delay wiring path 11c are provided on the main surface m3 of the delay wiring body 10C mounted on the wiring board 1. In other words, the first delay wiring path 11c is extended from the respective connection portions g1 and g2 along the line direction of the first differential signal line Ga, and the extended end portions are connected to each other at a predetermined portion. The main surface m3 is formed in a substantially U shape.

第2の遅延配線路12cの両接続部h1,h2相互間は、側面m1を直上して横断し、さらに主面m3と対向する主面m4に亘って設けられている。それぞれの接続部h1,h2から第2の差動信号線Gbの線方向に沿って延長され、かつ所定部位において延出端部相互が連結される。すなわち、第2の遅延配線路12cは側面m1に2度に亘って設けられるとともに、主面m4において略U字状に形成される。   The connection portions h1 and h2 of the second delay wiring path 12c are provided across the main surface m4 that crosses the side surface m1 directly above and further faces the main surface m3. Each of the connection portions h1 and h2 extends along the line direction of the second differential signal line Gb, and the extended end portions are connected to each other at a predetermined portion. That is, the second delay wiring path 12c is provided twice on the side surface m1, and is formed in a substantially U shape on the main surface m4.

第2の遅延配線路12cは第1の遅延配線路11cの内側に形成されるところから、主面m3と主面m4における略U字形状だけを比較すると、第2の遅延配線路12cの配線路長は第1の遅延配線路11cの配線路長よりも短い。しかしながら、第2の遅延配線路12cは側面m1を2度に亘って横断し、その分の配線路長が加算される。   Since the second delay wiring path 12c is formed inside the first delay wiring path 11c, comparing only the substantially U-shape on the main surface m3 and the main surface m4, the wiring of the second delay wiring path 12c The path length is shorter than the wiring path length of the first delay wiring path 11c. However, the second delay wiring path 12c crosses the side surface m1 twice, and the wiring path length corresponding to the second delay wiring path 12c is added.

すなわち、第1の遅延配線路11cおよび第2の遅延配線路12cの配線路長は互いに同一であり、したがって第1の電子部品Saから遅延配線体10Cを介して第2の電子部品Sbに至る、第1の差動信号線Gaと第2の差動信号線Gbの全配線路長は互いに同一となる。   That is, the lengths of the first delay wiring path 11c and the second delay wiring path 12c are the same, and therefore, the first electronic component Sa reaches the second electronic component Sb via the delay wiring body 10C. The total wiring path lengths of the first differential signal line Ga and the second differential signal line Gb are the same.

結果として、以上説明した例と同一の作用効果を奏する。また、配線基板1に実装される電子部品に対し、配線パターンのレイアウト上、差動信号線対Gを所定の部位においてUターン形成する場合がある。そこで上述したように、Uターン部分の差動信号線対Gを分断し、その分断領域Zに上記遅延配線体10Cを設ける。   As a result, the same operational effects as the example described above are obtained. In addition, a differential signal line pair G may be formed in a U-turn at a predetermined portion in the wiring pattern layout for the electronic component mounted on the wiring board 1. Therefore, as described above, the differential signal line pair G in the U-turn portion is divided, and the delay wiring body 10C is provided in the division region Z.

遅延配線体10Cに設けられる第1の遅延配線路11cと第2の遅延配線路12cは、90°に屈曲された部位を2つ連続形成することで、180°屈曲する形状、すなわちUターン形状を得られ、90°に屈曲された部位を有する配線基板と同一の作用効果を得られる。   The first delay wiring path 11c and the second delay wiring path 12c provided in the delay wiring body 10C are formed in a shape that bends 180 ° by forming two portions bent at 90 °, that is, a U-turn shape. The same effect as that of the wiring board having a portion bent at 90 ° can be obtained.

つぎに、本発明における第2の実施の形態であって、その第1実施例を図5(A)(B)にもとづいて説明する。
図5(A)は、遅延調整体10Dの斜視図である。この遅延調整体10Dは、たとえば合成樹脂材もしくはセラミック材からなり、所定の厚みを有し、平面視が矩形状のブロック体に形成される。
Next, it is 2nd Embodiment in this invention, Comprising: The 1st Example is demonstrated based on FIG. 5 (A) (B).
FIG. 5A is a perspective view of the delay adjusting body 10D. The delay adjusting body 10D is made of, for example, a synthetic resin material or a ceramic material, has a predetermined thickness, and is formed into a block body having a rectangular shape in plan view.

一方の主面m8である、図の上面から下面への厚み方向で、かつ厚みの範囲内に、平面視で略L字状の座ぐり部15aが設けられる。このような遅延配線体10Dを用いる際は、図5(A)に示す状態から上下面を反転させ、座ぐり部15aが設けられる主面m8を下面側とする。   A counterbore 15a having a substantially L shape in plan view is provided in the thickness direction from the upper surface to the lower surface in the figure, which is one main surface m8, and within the thickness range. When using such a delay wiring body 10D, the upper and lower surfaces are reversed from the state shown in FIG. 5A, and the main surface m8 on which the spot facings 15a are provided is the lower surface side.

図5(B)は、配線基板装置一部である、配線基板1に実装される遅延配線体10Dの斜視図である。第1の電子部品Saと第2の電子部品Sbを省略しているが、これらは先に図1(A)(B)で説明したように実装されている。
第1の電子部品Saから第2の電子部品Sbに、第1の差動信号線Gaと第2の差動信号線Gbとからなる差動信号線対Gが配線されている。配線基板1における配線パターンのレイアウトの関係上、この差動信号線対Gの中途部には屈曲部Kが設けられている。そのままでは、第1の差動信号線Gaと第2の差動信号線Gbの互いの配線路長が異なる。
FIG. 5B is a perspective view of a delay wiring body 10D mounted on the wiring board 1, which is a part of the wiring board device. Although the first electronic component Sa and the second electronic component Sb are omitted, they are mounted as described above with reference to FIGS.
A differential signal line pair G including a first differential signal line Ga and a second differential signal line Gb is wired from the first electronic component Sa to the second electronic component Sb. In view of the layout of the wiring pattern on the wiring board 1, a bent portion K is provided in the middle portion of the differential signal line pair G. As they are, the wiring path lengths of the first differential signal line Ga and the second differential signal line Gb are different from each other.

前記遅延調整体10Dを、図5(A)の状態から上下面を反転させて配線基板1上に対向し、かつ実装する。詳しくは、反転した状態で遅延配線体10Dの下面(主面G8)が配線基板1に形成される屈曲部K上に載る。
そして、遅延配線体10Dに設けられる座ぐり部15aを外側配線である第1の差動信号線Gaに沿わせる。座ぐり部15a以外は平坦面15bであるので、内側配線である第2の差動信号線Gbに遅延調整体10Dの平坦面15bが密に接触する。座ぐり部を「第1の対向部15a」と呼び、平坦面を「第2の対向部15b」と呼ぶ。
The delay adjusting body 10D is mounted on the wiring board 1 so that the upper and lower surfaces are reversed from the state shown in FIG. Specifically, the lower surface (main surface G8) of the delay wiring body 10D is placed on the bent portion K formed on the wiring board 1 in an inverted state.
And the counterbore part 15a provided in the delay wiring body 10D is made to follow the 1st differential signal line Ga which is an outer side wiring. Since the flat surface 15b other than the spot facing portion 15a is in close contact with the second differential signal line Gb which is the inner wiring, the flat surface 15b of the delay adjusting body 10D is in close contact. The spot facing portion is referred to as a “first facing portion 15a”, and the flat surface is referred to as a “second facing portion 15b”.

前記屈曲部Kにおいて、外側配線である配線路長の長い第1の差動信号線Gaは、第1の対向部15aで覆われるところから、第1の差動信号線Gaと第1の対向部15aとの距離が大である。したがって、第1の差動信号線Gaは第1の対向部15aに充満する空気層に晒される。   In the bent portion K, the first differential signal line Ga having a long wiring path length, which is the outer wiring, is covered with the first facing portion 15a. The distance to the part 15a is large. Therefore, the first differential signal line Ga is exposed to an air layer that fills the first facing portion 15a.

これに対して、屈曲部Kにおいて、内側配線である配線路長の短い第2の差動信号線Gbは、第2の対向部15bが密着するところから、第2の差動信号線Gbと第2の対向部15bとの距離がゼロ(短い)である。したがって、第2の差動信号線Gbは遅延配線体10Dそのもので覆われる。   On the other hand, in the bent portion K, the second differential signal line Gb having a short wiring path length which is the inner wiring is connected to the second differential signal line Gb from the point where the second facing portion 15b is in close contact. The distance from the second facing portion 15b is zero (short). Therefore, the second differential signal line Gb is covered with the delay wiring body 10D itself.

先に説明したように、2つの電子部品Sa,Sbを接続する差動信号線Ga,Gbに伝播する信号の伝播時間tは、その差動信号線Ga,Gbの配線路長に対する位相速度Vg(m/s)の割合から決定される。前記位相速度は、単位時間当たりに進む位相量であり、配線基板の物性値と配線の線路幅で決まる。   As described above, the propagation time t of the signal propagating to the differential signal lines Ga and Gb connecting the two electronic components Sa and Sb is the phase velocity Vg with respect to the wiring path length of the differential signal lines Ga and Gb. It is determined from the ratio of (m / s). The phase velocity is a phase amount that advances per unit time, and is determined by the physical property value of the wiring board and the line width of the wiring.

配線基板の物性値は、その配線基板を構成する部材の誘電率に影響される。一対の差動信号線相互の配線路長が互いに同じであっても、誘電率が高い(大)部材から構成される配線基板の差動信号線に導かれる信号の伝播時間は、誘電率が低い(小)部材から構成される配線基板の差動信号線に導かれる信号の伝播時間よりも長く(大)なる。   A physical property value of a wiring board is affected by a dielectric constant of a member constituting the wiring board. Even if the wiring path lengths of the pair of differential signal lines are the same, the propagation time of the signal guided to the differential signal line of the wiring board composed of the (large) member having a high dielectric constant is the dielectric constant. It becomes longer (larger) than the propagation time of the signal guided to the differential signal line of the wiring board composed of the low (small) member.

図5の構成では、第1の差動信号線Gaと第2の差動信号線Gbともに、たとえば誘電率4の部材(セラミック材や合成樹脂材)からなる配線基板1に設けられている。そして、遅延配線体10Dもまた、誘電率4の部材から形成されるものとする。なお、空気は誘電率1である。   In the configuration of FIG. 5, both the first differential signal line Ga and the second differential signal line Gb are provided on the wiring board 1 made of a member having a dielectric constant of 4, for example, a ceramic material or a synthetic resin material. The delay wiring body 10D is also formed of a member having a dielectric constant of 4. Air has a dielectric constant of 1.

屈曲部Kにおいて、第1の差動信号線Gaが誘電率4の遅延配線体10Dで覆われるが、実際には、第1の対向部15aが対向し、充満する誘電率1の空気に晒される。その一方で、第2の差動信号線Gbには誘電率4の遅延配線体10Dそのものである第2の対向部15bが密着する。   In the bent portion K, the first differential signal line Ga is covered with the delay wiring body 10D having a dielectric constant of 4, but actually, the first opposing portion 15a faces and is exposed to the air having a dielectric constant of 1 that is filled. It is. On the other hand, the second opposing portion 15b, which is the delay wiring body 10D itself having a dielectric constant of 4, is in close contact with the second differential signal line Gb.

したがって、屈曲部Kにおいては、第1の差動信号線Gaが設けられる配線基板1部分の誘電率よりも、第2の差動信号線Gbが設けられる配線基板1部分の誘電率が小になる。このような誘電率の関係から、第1の差動信号線Ga側の見かけ上の配線路長が短くなる。   Therefore, at the bent portion K, the dielectric constant of the portion of the wiring board 1 where the second differential signal line Gb is provided is smaller than the dielectric constant of the portion of the wiring board 1 where the first differential signal line Ga is provided. Become. Due to such a dielectric constant relationship, the apparent wiring path length on the first differential signal line Ga side is shortened.

したがって、第1の差動信号線Gaに伝送される信号の位相速度が下がって、信号伝播時間が短縮する。外側配線である第1の差動信号線Gaに導かれる信号の伝播時間が、内側配線である第2の差動信号線Gbに導かれる信号の伝播時間と同一になり、スキューの発生がない。   Therefore, the phase speed of the signal transmitted to the first differential signal line Ga is lowered, and the signal propagation time is shortened. The propagation time of the signal guided to the first differential signal line Ga that is the outer wiring is the same as the propagation time of the signal guided to the second differential signal line Gb that is the inner wiring, and there is no occurrence of skew. .

つぎに、本発明における第2の実施の形態であって、第2実施例を図6にもとづいて説明する。
図6は、配線基板装置一部の斜視図である。第1の電子部品Saおよび第2の電子部品Sbは省略しているが、これらは先に図1(A)(B)で説明したように実装されている。
Next, a second embodiment of the present invention will be described with reference to FIG.
FIG. 6 is a perspective view of a part of the wiring board device. Although the first electronic component Sa and the second electronic component Sb are omitted, they are mounted as described above with reference to FIGS.

第1の電子部品Saから第2の電子部品Sbに、第1の差動信号線Gaと第2の差動信号線Gbとからなる差動信号線対Gが配線されている。ここでは、内側配線である第2の差動信号線Gbのみ中途部に屈曲部Kを有し、外側配線である第1の差動信号線Gaにおいては分断領域Zとしている。   A differential signal line pair G including a first differential signal line Ga and a second differential signal line Gb is wired from the first electronic component Sa to the second electronic component Sb. Here, only the second differential signal line Gb, which is an inner wiring, has a bent portion K in the middle, and the first differential signal line Ga, which is an outer wiring, is a divided region Z.

遅延調整体10Eは、その両端部が第1の差動信号線Gaの分断部相互と接続されるが、この両端部相互間は空中配線が架設される。前記空中配線は、第1の差動信号線Gaの分断された屈曲部Kと略同様の屈曲形状をなす。すなわち、遅延配線体10Eの両端部間は、配線基板1との距離が無限大に対向する対向部となっている。   Both ends of the delay adjuster 10E are connected to the divided portions of the first differential signal line Ga, and aerial wiring is provided between the ends. The aerial wiring has a bent shape substantially the same as the bent portion K of the first differential signal line Ga. That is, between both end portions of the delay wiring body 10E is a facing portion where the distance to the wiring board 1 is infinitely opposed.

これに対して、記配線路長が短い第2の差動信号線Gbは、この第2の差動信号線Gbそのものを遅延調整体10Eに兼用させていて、配線基板1との距離がゼロの対向部を備えることになる。   On the other hand, the second differential signal line Gb having a short wiring path length has the second differential signal line Gb itself also used as the delay adjusting body 10E, and the distance from the wiring board 1 is zero. Will be provided.

前記遅延配線体10Eの空中配線は、配線基板1の配線パターン形成面と間隔を存しているので、遅延配線体10Eと配線基板1面との間に空気層が形成される。したがって、遅延配線体10Eは、誘電率1の空気層に影響される。
その一方で、遅延配線体10Eの一部を兼用する第2の差動信号線Gbは全長に亘って配線基板1に形成されているので、たとえば誘電率4の配線基板1部材に影響される。屈曲部Kにおいて第1の差動信号線Gaは誘電率が小になり、第2の差動信号線Gbは配線基板1の物性そのままで誘電率が大である。
Since the aerial wiring of the delay wiring body 10E is spaced from the wiring pattern forming surface of the wiring board 1, an air layer is formed between the delay wiring body 10E and the wiring board 1 surface. Therefore, the delay wiring body 10E is affected by an air layer having a dielectric constant of 1.
On the other hand, since the second differential signal line Gb that also serves as a part of the delay wiring body 10E is formed on the wiring board 1 over the entire length, it is influenced by, for example, the wiring board 1 member having a dielectric constant of 4. . At the bent portion K, the first differential signal line Ga has a low dielectric constant, and the second differential signal line Gb has a high dielectric constant while maintaining the physical properties of the wiring board 1.

第1の差動信号線Gaの誘電率が小さくなることで、信号の位相速度が下がって信号伝播時間が短縮し、見かけ上の配線路長が短くなる。したがって、第1の差動信号線Gaの配線路長は、第2の差動信号線Gbの配線路長と同一にみなされることとなり、互いの差動信号線Ga,Gbに導かれる信号の伝播時間が同一であって、スキューの発生がない。   By reducing the dielectric constant of the first differential signal line Ga, the signal phase speed is lowered, the signal propagation time is shortened, and the apparent wiring path length is shortened. Therefore, the wiring path length of the first differential signal line Ga is considered to be the same as the wiring path length of the second differential signal line Gb, and the signals guided to the mutual differential signal lines Ga and Gb. Propagation time is the same and no skew occurs.

つぎに、本発明における第3の実施の形態を図7にもとづいて説明する。
図7は、配線基板装置一部の分解した斜視図である。第1の電子部品Saおよび第2の電子部品Sbは省略しているが、これらは先に図1(A)(B)で説明したように実装されている。
前記配線基板1Aは、互いに積層される複数枚(ここでは2枚)の積層基板1a,1bから構成され、積層した状態で一体化されている。上部側の第1の積層基板1aに前記第1の電子部品Saと第2の電子部品Sbが実装される。
Next, a third embodiment of the present invention will be described with reference to FIG.
FIG. 7 is an exploded perspective view of a part of the wiring board device. Although the first electronic component Sa and the second electronic component Sb are omitted, they are mounted as described above with reference to FIGS.
The wiring substrate 1A is composed of a plurality (two in this case) of laminated substrates 1a and 1b laminated together, and is integrated in a laminated state. The first electronic component Sa and the second electronic component Sb are mounted on the first laminated substrate 1a on the upper side.

第1の差動信号線Gaと第2の差動信号線Gbには、屈曲部Kが設けられる。第1の差動信号線Gaは、第1の積層基板1aにおける一方の主面(図の上面)m10に屈曲部Kを含めて、全長に亘って形成される。
第2の差動信号線Gbは、屈曲部Kのみ第1の積層基板1aにおける一方の主面m10に設けられる。この屈曲部Kの両端は所定の間隔を存して中断する中断部Yaとなっていて、これら中断部Yaから第1の電子部品Saと第2の電子部品Sbまでは同じ主面m10に設けられる。
A bent portion K is provided in the first differential signal line Ga and the second differential signal line Gb. The first differential signal line Ga is formed over the entire length including the bent portion K on one main surface (upper surface in the drawing) m10 of the first laminated substrate 1a.
In the second differential signal line Gb, only the bent portion K is provided on one main surface m10 of the first multilayer substrate 1a. Both ends of the bent portion K are interrupted portions Ya that are interrupted at a predetermined interval. The first electronic component Sa and the second electronic component Sb are provided on the same main surface m10 from the interrupted portion Ya. It is done.

第1の積層基板1aにおける中断部Yaの両端は、そのまま積層基板1aの板厚を貫通して、前記主面m10と対向する主面(図の下面)m11に突出する。なお、これら貫通部分は、スルーホールに代えてもよい。
下部側の積層基板1bにおける一方の主面(図の上面)m12には、第1の積層基板1aにおける中断部Yaと対応する配線パターンである中断対応部Ybが設けられ、第1の積層基板1aに設けられる貫通部分と接続される。
Both ends of the interrupting portion Ya in the first multilayer substrate 1a pass through the plate thickness of the multilayer substrate 1a as they are, and project to a main surface (lower surface in the figure) m11 facing the main surface m10. These penetrating portions may be replaced with through holes.
One main surface (upper surface in the figure) m12 of the lower layered substrate 1b is provided with an interruption corresponding part Yb which is a wiring pattern corresponding to the interruption part Ya in the first laminated substrate 1a. It connects with the penetration part provided in 1a.

ここでは、第2の差動信号線Gbに、第1の積層基板1aに設けられる4ヶ所の貫通部分と、第2の積層基板1bに設けられる2ヶ所の中断対応部Ybとで構成される迂回部Yが設けられる。迂回部Yの合計長さは、図1で説明したように、屈曲部Kにおける第1の差動信号線Gaの配線路長と、第2の差動信号線Gbの配線路長との差分に相当する。   Here, the second differential signal line Gb includes four through portions provided in the first multilayer substrate 1a and two interruption corresponding portions Yb provided in the second multilayer substrate 1b. A detour part Y is provided. As described in FIG. 1, the total length of the detour portion Y is the difference between the wiring path length of the first differential signal line Ga and the wiring path length of the second differential signal line Gb in the bent portion K. It corresponds to.

換言すれば、配線路長が短い部位を有する第2の差動信号線Gbは、配線路長が長い方の第1の差動信号線Gaと配線路長を同一とする迂回部Yを備えている。互いの差動信号線Ga,Gbの配線路長が同一であるので、これら差動信号線Ga,Gbに導かれる信号の伝播時間が同一になり、スキューの発生がない。   In other words, the second differential signal line Gb having a portion with a short wiring path length includes a detour portion Y having the same wiring path length as the first differential signal line Ga having a longer wiring path length. ing. Since the wiring path lengths of the differential signal lines Ga and Gb are the same, the propagation times of signals guided to the differential signal lines Ga and Gb are the same, and no skew is generated.

なお、本発明は上述した実施の形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。そして、上述した実施の形態に開示されている複数の構成要素の組合せにより、さらに種々の発明を形成できる。   Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by combinations of a plurality of constituent elements disclosed in the above-described embodiments.

本発明の配線基板装置の基本構成を説明する図。The figure explaining the basic composition of the wiring board device of the present invention. 本発明における第1の実施の形態に係る、第1実施例の基板配線装置一部の斜視図と、基板配線装置一部の分解した斜視図。The perspective view of a part of board wiring device of the 1st example concerning the 1st embodiment in the present invention, and the exploded perspective view of a part of board wiring device. 同実施の形態に係る、第2実施例の基板配線装置一部の斜視図。The perspective view of a part of board wiring device of the 2nd example concerning the embodiment. 同実施の形態に係る、第3実施例の基板配線装置一部の斜視図。The perspective view of a part of board wiring device of the 3rd example concerning the embodiment. 本発明における第2の実施の形態に係る、第1実施例の遅延調整体の斜視図と、基板配線装置一部の斜視図。The perspective view of the delay adjustment body of 1st Example based on 2nd Embodiment in this invention, and the perspective view of a part of board | substrate wiring apparatus. 同実施の形態に係る、第2実施例の基板配線装置一部の斜視図。The perspective view of a part of board wiring device of the 2nd example concerning the embodiment. 本発明における第3の実施の形態に係る、基板配線装置一部の斜視図。The perspective view of a part of board | substrate wiring apparatus based on 3rd Embodiment in this invention. 差動信号伝送方式を説明する図。The figure explaining a differential signal transmission system. 差動信号伝送方式を採用した場合の、スキュー現象を説明する図。The figure explaining the skew phenomenon at the time of employ | adopting a differential signal transmission system. スキューにより起こる問題を説明する図。The figure explaining the problem which arises by skew. スキューの原因を説明する図。The figure explaining the cause of skew.

符号の説明Explanation of symbols

Sa…第1の電子部品、Sb…第2の電子部品、1…配線基板、Ga…第1の差動信号線、Gb…第2の差動信号線、G…差動信号線対、Z…分断領域、10…遅延配線体、11…第1の遅延配線路、12…第2の遅延配線路、g1,g2,h1,h2…接続部、15a…第1の対向部、15b…第2の対向部、Y…迂回部。   Sa ... first electronic component, Sb ... second electronic component, 1 ... wiring board, Ga ... first differential signal line, Gb ... second differential signal line, G ... differential signal line pair, Z ... Dividing region, 10... Delay wiring body, 11... First delay wiring path, 12... Second delay wiring path, g 1, g 2, h 1 and h 2. 2 opposing parts, Y ... detour part.

Claims (7)

複数の電子部品が実装される配線基板と、
この配線基板に互いに並行して配線され、中途部に分断された領域を有する一対の差動信号線からなる差動信号線対と、
前記配線基板における、前記差動信号線対の前記分断された領域に実装される遅延配線体と、
この遅延配線体に設けられ、前記分断された差動信号線対を構成する一対の差動信号線のそれぞれ端部に接続されるとともに、互いの配線路長が同一に設定される第1の遅延配線路および第2の遅延配線路と
を具備することを特徴とする配線基板装置。
A wiring board on which a plurality of electronic components are mounted;
A differential signal line pair consisting of a pair of differential signal lines that are wired in parallel to each other on this wiring board and have a region divided in the middle,
A delay wiring body mounted on the divided region of the differential signal line pair in the wiring board;
The delay wiring body is connected to the respective ends of the pair of differential signal lines constituting the divided differential signal line pair, and the wiring path lengths are set to be the same. A wiring board device comprising a delay wiring path and a second delay wiring path.
前記差動信号線対は、
前記分断された領域まで配線される一方の差動信号線対と、前記分断された領域から配線される他方の差動信号線対との、それぞれの差動信号線対相互の線方向が互いに異なって設けられ、
前記遅延配線体は、
この一面に、前記分断された領域まで配線される一方の差動信号線対と接続する接続部を備え、
この接続部が設けられる面とは異なる面に、前記分断された領域から配線される他方の差動信号線対と接続する接続部を備える
ことを特徴とする請求項1記載の配線基板装置。
The differential signal line pair is:
The differential signal line pairs of one differential signal line pair wired up to the divided area and the other differential signal line pair wired from the divided area are in mutual line directions. Provided differently,
The delay wiring body is
On this one side, it is provided with a connecting portion for connecting with one differential signal line pair wired up to the divided region,
2. The wiring board device according to claim 1, further comprising a connection portion connected to the other differential signal line pair wired from the divided region on a surface different from the surface on which the connection portion is provided.
前記差動信号線対は、
前記分断された領域まで配線される一方の差動信号線対と、前記分断された領域から配線される他方の差動信号線対との、それぞれの差動信号線対相互の線方向が互いに平行に設けられ、
前記遅延配線体の一面に、前記分断された領域まで配線される一方の差動信号線対と接続する接続部を備え、
前記遅延配線体の前記接続部が設けられる面と同一の面に、前記分断された領域から配線される他方の差動信号線対と接続する接続部を備える
ことを特徴とする請求項1記載の配線基板装置。
The differential signal line pair is:
The differential signal line pairs of one differential signal line pair wired up to the divided area and the other differential signal line pair wired from the divided area are in mutual line directions. Provided in parallel,
On one surface of the delay wiring body, a connection portion connected to one differential signal line pair wired up to the divided region,
2. The connection portion connected to the other differential signal line pair wired from the divided region is provided on the same surface as the surface where the connection portion of the delay wiring body is provided. Wiring board device.
電子部品が実装される配線基板と、
この配線基板に互いに並行に配線され、中途部に互いの配線路長が異なる部位が形成される、第1の差動信号線および第2の差動信号線からなる差動信号線対と、
前記配線基板における、前記差動信号線対の配線路長の異なる部位に設けられ、差動信号線対を構成する前記第1の差動信号線および前記第2の差動信号線のそれぞれに対する距離を異ならせて対向する対向部を有し、見かけ上の配線路長を同一にする遅延配線体と
を具備することを特徴とする配線基板装置。
A wiring board on which electronic components are mounted;
A differential signal line pair composed of a first differential signal line and a second differential signal line, which are wired in parallel to each other on this wiring board and in which a part having a different wiring path length is formed in the middle part;
Each of the first differential signal line and the second differential signal line, which are provided at different portions of the wiring path length of the differential signal line pair in the wiring board and constitute the differential signal line pair. A wiring board device comprising: a delay wiring body having opposing portions which are opposed to each other at different distances and having the same apparent wiring path length.
前記遅延調整体は、
前記差動信号線対を構成する第1の差動信号線および第2の差動信号線のいずれか配線路長の長い方の差動信号線と距離を存して対向する第1の対向部と、いずれか配線路長の短い方の差動信号線に密着する第2の対向部とを有する
ことを特徴とする請求項4記載の配線基板装置。
The delay adjuster is
A first counter that opposes the differential signal line having a longer wiring path length, either the first differential signal line or the second differential signal line constituting the differential signal line pair, with a distance therebetween 5. The wiring board device according to claim 4, further comprising a second opposing portion that is in close contact with the differential signal line having a shorter wiring path length.
前記遅延調整体は、
前記配線路長が長い方の差動信号線を分断し、かつこの分断部位を連結することで、前記配線基板との距離を無限大とする対向部を有する空中配線と、
前記配線路長が短い方の差動信号線は、前記差動信号線そのものを兼用させて、配線基板との距離がゼロの対向部を備えた
ことを特徴とする請求項4記載の配線基板装置。
The delay adjuster is
By dividing the differential signal line having the longer wiring path length and connecting the divided portions, an aerial wiring having a facing portion that makes the distance to the wiring board infinite,
5. The wiring board according to claim 4, wherein the differential signal line having a shorter wiring path length includes an opposing portion having a distance from the wiring board of zero, which also serves as the differential signal line itself. apparatus.
互いに積層される複数枚の積層基板からなり、最上部の積層基板に電子部品が実装される配線基板と、
この配線基板に互いに並行に配線され、互いに配線路長が異なる部位を有する一対の差動信号線からなる差動信号線対と、
この差動信号線対を構成する一対の差動信号線のうち、配線路長が短い部位を有する差動信号線は、配線路長が長い方の差動信号線と配線路長を同一となすよう、複数の積層基板に亘って迂回部を備える
ことを特徴とする配線基板装置。
A wiring board composed of a plurality of laminated boards stacked on top of each other, with electronic components mounted on the uppermost laminated board,
A differential signal line pair consisting of a pair of differential signal lines that are wired in parallel to each other on this wiring board and have different wiring path lengths;
Of the pair of differential signal lines constituting the differential signal line pair, the differential signal line having a portion with a short wiring path length has the same wiring path length as the differential signal line having the longer wiring path length. A wiring board device comprising a bypass portion across a plurality of laminated substrates so as to achieve this.
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JP2011165910A (en) * 2010-02-10 2011-08-25 Nec Corp Wiring board
CN102683784A (en) * 2011-03-08 2012-09-19 日本光进株式会社 Differential transmission circuit, optical transceiver module, and information processing device
US10356893B1 (en) 2017-12-25 2019-07-16 Japan Aviation Electronics Industry, Limited Circuit board, connector assembly and cable harness
CN112996228A (en) * 2019-12-12 2021-06-18 佳能株式会社 Wiring substrate and electronic device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165910A (en) * 2010-02-10 2011-08-25 Nec Corp Wiring board
CN102683784A (en) * 2011-03-08 2012-09-19 日本光进株式会社 Differential transmission circuit, optical transceiver module, and information processing device
JP2012199904A (en) * 2011-03-08 2012-10-18 Japan Oclaro Inc Differential transmission circuit, optical transceiver module, and information processor
US9112252B2 (en) 2011-03-08 2015-08-18 Oclaro Japan, Inc. Differential transmission circuit, optical module, and information processing system
US10356893B1 (en) 2017-12-25 2019-07-16 Japan Aviation Electronics Industry, Limited Circuit board, connector assembly and cable harness
CN112996228A (en) * 2019-12-12 2021-06-18 佳能株式会社 Wiring substrate and electronic device

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