JP2009224426A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a semiconductor apparatus including a nonvolatile memory. <P>SOLUTION: The semiconductor apparatus includes: a nonvolatile memory cell NVM having a control gate electrode CG formed on a main surface f1 of a silicon substrate 1, a memory gate electrode MG formed beside the control gate electrode CG with a charge accumulation insulating film IS in between, a metal silicide layer SC formed on the upper surfaces of the control gate electrode CG and the memory gate electrode MG, and a side wall insulating film IW formed on the side surface of the control gate electrode CG. The side wall insulating film IW is formed to integrally cover the side surface of the control gate electrode CG and the side surface of the metal silicide layer SC on the upper surface of the control gate electrode CG. The metal silicide layers SC on the upper surfaces of the electrode CG and MG are insulated from each other by the side wall insulating film IW. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device technology, and more particularly to a technology effective when applied to a semiconductor device having a nonvolatile memory.

  As an electrically writable / erasable nonvolatile semiconductor memory device (nonvolatile memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used. These nonvolatile memories have a structure including a floating gate electrode in a floating state (floating state) under a gate electrode of a MIS (Metal Insulator Semiconductor) type field effect transistor (hereinafter simply referred to as MIS transistor), and a charge storage function. The structure has an insulating film. A data writing function or a data erasing function is realized by accumulating electric charges in these floating gate electrodes and the electric charge accumulating insulating film and controlling injection or emission of electric charges to the electric charge accumulating region by the MIS structure.

  The threshold voltage of the MIS transistor changes due to the injection or emission of charges in the charge storage region as described above. The difference in threshold voltage in the MIS transistor appears as a difference in source / drain current that flows in accordance with the applied gate voltage. The charge accumulation state, that is, the data holding state can be read out according to the source / drain current amount of the MIS transistor. The memory operation is realized by the data writing, erasing and reading functions as described above.

  In a nonvolatile memory mixedly mounted on a semiconductor substrate together with a logic circuit or the like, a silicon oxide film (Oxide) / silicon nitride film (Nitride) / silicon oxide film (Oxide) is used as a charge storage insulating film that is an insulating film of a MIS transistor. There is a so-called MONOS type non-volatile memory (hereinafter simply referred to as a MONOS memory) replaced with a laminated film (ONO film). In particular, there is a split gate type MONOS memory (hereinafter simply referred to as a split gate type memory) using two gate electrodes arranged adjacent to each other in one cell.

  For example, Japanese Laid-Open Patent Publication No. 2002-231829 (Patent Document 1) discloses a technique for reducing a short-circuit defect by giving a difference in height to two gate electrodes of a split gate type memory and making it difficult to contact each other. It is disclosed.

  In addition, for example, a technique for improving the insulation resistance between two electrodes by oxidizing the surface of a silicide layer on two gate electrodes of a split gate type memory is disclosed in Japanese Patent Application Laid-Open No. 2007-251079 (Patent Document 2). And the like.

  In addition, for example, a structure in which a silicide layer is not formed on one of the two gate electrodes of the split gate type memory, thereby preventing a short circuit between the two electrodes and improving the pressure resistance. Is disclosed in Japanese Patent Application Laid-Open No. 2007-281092 (Patent Document 3) and the like.

Also, for example, in the ONO film that insulates the two gate electrodes of the split gate type memory from each other, the silicon oxide film at the end is made into a bird's beak shape, and the structure is difficult to contact by separating the distance between the upper portions of both electrodes, A technique for suppressing the occurrence of a short circuit between both electrodes is disclosed in Japanese Patent Application Laid-Open No. 2007-258497 (Patent Document 4).
Japanese Patent Application Laid-Open No. 2002-231829 JP 2007-251079 A JP 2007-281092 A JP 2007-258497 A

  The present inventor has studied a semiconductor device such as a microcomputer having a split gate type memory composed of a control gate electrode and a memory gate electrode and a MIS transistor having various characteristics constituting a peripheral circuit thereof. ing. Hereinafter, the split gate type memory studied by the present inventor will be described with reference to the drawings.

  FIG. 23 is a cross-sectional view showing a main part of a split gate type nonvolatile memory cell NVMa examined by the present inventors. The nonvolatile memory cell NVMa is formed on a silicon substrate 1a made of, for example, n-type single crystal silicon (Si). A p-type memory well pwa, which is a p-type semiconductor region, is formed on the main surface of the silicon substrate 1a, and nonvolatile memory cells NVMa are arranged in the p-type memory well pwa. The nonvolatile memory cell NVMa examined by the present inventors has the following configuration.

  On the main surface of the silicon substrate 1a, a control gate electrode CGa made of conductive polycrystalline silicon (polysilicon) and a memory gate electrode MGa are arranged adjacent to each other. A control gate insulating film IGa made of silicon oxide is formed between the control gate electrode CGa and the silicon substrate 1a, thereby being insulated from each other. In addition, a charge storage insulating film ISa is formed between the memory gate electrode MGa and the silicon substrate 1a, thereby being insulated from each other. The charge storage insulating film ISa is also integrally formed between the memory gate electrode MGa and the control gate electrode CGa, and insulates the electrodes from each other.

  The charge storage insulating film ISa is an insulating film having a function of storing charge carriers (carriers) such as electrons and holes. In the nonvolatile memory cell NVMa examined by the present inventors, the charge storage insulating film ISa is an insulating film having a three-layer structure in which a silicon nitride film is sandwiched between silicon oxide films.

  Sidewall spacers swa made of silicon oxide or the like are formed on the side walls of the control gate electrode CGa and the memory gate electrode MGa, so that the conductive portions such as contact plugs (not shown) and the respective electrodes are insulated. ing.

  A source / drain region sda, which is a high-concentration n-type semiconductor region, is formed on the main surface of the silicon substrate 1a located at the lower side of the sidewall spacer swa. In addition, an n-type semiconductor region is a main surface of the silicon substrate 1a located immediately below the sidewall spacer swa and reaches from the end of the source / drain region sda to the lateral lower side of the gate electrodes CGa and MGa. An extension region exa is formed. The n-type impurity concentration of the extension region exa is lower than the n-type impurity concentration of the source / drain region sda.

  A metal silicide layer SCa is formed on the upper surfaces of the control gate electrode CGa, the memory gate electrode MGa, and the source / drain region sda. The metal silicide layer SCa is a layer having a low resistance value, which is formed in order to realize ohmic connection when electrically conducting to each region from the outside. The metal silicide layer SCa of the nonvolatile memory cell NVMa examined by the present inventor is cobalt silicide.

  As described above, the nonvolatile memory cell NVMa studied by the present inventor has two adjacent MIS structures. That is, the nonvolatile memory cell NVMa has a MIS structure including a control gate electrode CGa, a control gate insulating film IGa, and a p-type memory well pwa, a memory gate electrode MGa, a charge storage insulating film ISa, and a p-type memory well. and a MIS structure made of pwa. By controlling the voltage application conditions to such two adjacent MIS structures, charges are injected into and discharged from the charge storage insulating film ISa.

  Further, the nonvolatile memory cell NVMa studied by the present inventor is a normal MIS transistor provided with a source / drain region sda if two adjacent MIS structures are regarded as one body. The threshold voltage of the MIS transistor changes due to the difference in charge state caused by charge injection into the charge storage insulating film ISa. By discriminating this as a change in the source / drain current value, the storage state can be read out.

  As described above, the nonvolatile memory cell NVMa that can realize the memory operation has been clarified by the inventor's investigations to have the following problems. This is due to a short-circuit failure mainly occurring at the boundary between the upper end portions of the control gate electrode CGa and the memory gate electrode MGa, which is shown in a main part p100 in the drawing.

  In order to form the metal silicide layer SCa on the polycrystalline silicon such as the control gate electrode CGa and the memory gate electrode MGa, a combination reaction (silicide reaction) between the metal film and silicon is used. That is, for example, cobalt (Co) is deposited on each of the electrodes CGa and MGa, and heat treatment is performed to form a metal silicide made of cobalt silicide or the like. Thereafter, the metal silicide layer SCa is formed by removing the unreacted cobalt film. Since this silicide reaction is a chemical reaction by heat treatment, cobalt silicide is formed on the inner side (polycrystalline silicon side) and the outer side (cobalt film side) with respect to the original electrode surface. Therefore, the metal silicide layer SCa is formed so as to rise to a position higher than the original electrode surface when viewed from the main surface of the silicon substrate 1a.

  Here, in the nonvolatile memory cell NVMa examined by the present inventor, the control gate electrode CGa and the memory gate electrode MGa are arranged at relatively close positions with a charge storage insulating film of ten and several nanometers therebetween. Therefore, it is possible that the metal silicide layer SCa formed on both electrodes comes into contact with each other due to a slight deviation in the condition setting in the heat treatment during the silicide reaction.

  In the split gate nonvolatile memory cell NVMa, the memory operation can be completed by controlling the control gate electrode CGa and the memory gate electrode MGa independently. However, as described above, when the metal silicide layer SCa is in contact with the main portion p100, when both the electrodes CGa and MGa are short-circuited, a malfunction occurs. As a result, the reliability of the nonvolatile memory cell NVMa is lowered.

  In order to overcome such problems, the present inventor further examined application of the following technique.

  First, the present inventor examined the application of a technique for forming the memory gate electrode MGa so that its height is lower than that of the control gate electrode CGa. Thereby, the distance between the metal silicide layers SCa on both electrodes can be increased, and short circuit defects can be reduced.

  On the other hand, during the process of manufacturing a semiconductor device, for example, in the step of forming a semiconductor region such as the source / drain region sda by an ion implantation method or the like, the role of an ion implantation mask is applied to various gate electrodes such as the memory gate electrode MGa. There are things to be carried. At this time, if the height of the memory gate electrode MGa is too low, unintended impurity ions may be implanted into the p-type memory well pwa immediately below. Furthermore, the charge storage insulating film ISa under the memory gate electrode MGa may be damaged. This phenomenon becomes more prominent as the element is miniaturized and the memory gate electrode MGa becomes lower. That is, although the technique for lowering the memory gate electrode MGa is effective for reducing short-circuit defects between the electrodes, it is clear from the study of the present inventor that further improvement is necessary for miniaturization of the element. became.

  Second, the present inventor examined the application of a technique for oxidizing the surface of the metal silicide layer SCa. Thereby, even if the metal silicide SCa on both electrodes comes into contact with each other, both are in an insulated state, and the insulation resistance can be improved.

  On the other hand, it has been found by the inventors that when the metal silicide layer SCa is oxidized, the thickness of the oxide film formed varies depending on the ion species and concentration of impurity ions contained therein. The metal silicide layer SCa is formed in order to realize ohmic connection to an external power feeding mechanism. Therefore, the insulating film such as an oxide film needs to be removed by etching or the like in the region where the contact plug or the like is connected. When oxide films having different thicknesses are formed on the metal silicide layer SCa, uniform etching cannot be performed under the same etching conditions, which may cause contact failure. That is, the technology for oxidizing the metal silicide layer SCa is effective for improving the insulation resistance between the electrodes, but it is clear from the study of the present inventor that further improvement is necessary for normal contact formation. became.

  Thirdly, the present inventor examined the application of a technique in which the metal silicide layer SCa is not formed on the memory gate electrode MGa. Thereby, a short circuit between the control gate electrode CGa and the memory gate electrode MGa can be prevented, and the pressure resistance can be improved.

  On the other hand, the metal silicide layer SCa plays a role of reducing the resistivity when power is supplied to each electrode or semiconductor region. Therefore, when the metal silicide layer SCa is not formed on the memory gate electrode MGa, the electrical conduction to the memory gate electrode MGa is increased in resistance. This causes a decrease in the performance of the nonvolatile memory cell NVMa, such as a longer delay time during memory operation. That is, the technology that does not form the metal silicide layer SCa on the memory gate electrode MGa is effective for improving the pressure resistance between the electrodes, but it requires improvement for further improvement of the operation performance of the element. It became clear by examination of this inventor.

  Fourthly, the present inventor examined the application of a technique in which the end portion of the charge storage insulating film ISa located between the metal silicide layers SCa on both electrodes is formed into a bird's beak shape. Thereby, the distance between the metal silicide layers SCa on both electrodes is substantially further increased, and the occurrence of a short circuit can be suppressed.

  On the other hand, in order to form bird's beaks in the silicon oxide film, a thermal oxidation process is required. According to the inventor's study, in order to realize a desired shape, it is necessary to perform a thermal oxidation step of about ˜1100 ° C. Here, at the stage where the charge storage insulating film ISa is formed, other various components have already been formed on the silicon substrate 1a, and heat treatment at a high temperature causes these components to be altered. The influence of the heat treatment on the constituent elements becomes more prominent as the elements are miniaturized and the number of elements and element types formed on the silicon substrate 1a are increased. That is, although the technique for forming a bird's beak at the end of the charge storage insulating film ISa is effective for suppressing the occurrence of a short circuit, further improvements are required when miniaturizing the device. It was revealed.

  As described above, the first to fourth investigation techniques can be configured to hardly cause the contact failure of the metal silicide layer SCa, thereby improving the reliability of the semiconductor device having the nonvolatile memory. Can do. However, when these techniques are applied, for example, it has been clarified by the present inventors that further improvements are required when the elements are miniaturized.

  Therefore, an object of the present invention is to provide a technique for improving the reliability of a semiconductor device having a nonvolatile memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  In the present application, a plurality of inventions are disclosed. An outline of one embodiment of the inventions will be briefly described as follows.

  A first gate electrode formed on a main surface of the semiconductor substrate; a second gate electrode formed on a side of the first gate electrode through a charge storage insulating film; and a first gate electrode and a second gate electrode A semiconductor device including a nonvolatile memory cell having a metal silicide layer formed on an upper surface and a sidewall insulating film formed on a side surface of a first gate electrode, wherein the sidewall insulating film is a side surface of the first gate electrode And the side surface of the metal silicide layer on the upper surface of the first gate electrode are integrally covered, and the metal silicide layers on the upper surfaces of the electrodes are insulated from each other by the sidewall insulating film.

  Of the plurality of inventions disclosed in the present application, effects obtained by the above-described embodiment will be briefly described as follows.

  That is, the reliability of a semiconductor device having a nonvolatile memory can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment)
In the semiconductor device of this embodiment, a structure of a nonvolatile memory included in the semiconductor device will be described in detail with reference to cross-sectional views. FIG. 1 is a fragmentary cross-sectional view of a nonvolatile memory cell NVM according to an embodiment of the present invention. FIG. 2 is an enlarged view of a main part in which the periphery of two gate electrodes (control gate electrode CG, memory gate electrode MG) included in the nonvolatile memory cell NVM of FIG. 1 is enlarged. The semiconductor device of the present embodiment has a plurality of nonvolatile memory cells NVM as shown in FIG. On the same silicon substrate 1, normally known semiconductor elements such as MIS transistors constituting peripheral circuits such as logic circuits are formed.

  Hereinafter, components included in the nonvolatile memory cell NVM of the present embodiment will be described in detail with reference to FIGS. FIG. 1 shows a structure in which two nonvolatile memory cells NVM are arranged symmetrically. They have exactly the same configuration except that they are arranged on the object. Therefore, the configuration of one nonvolatile memory cell NVM will be described below unless otherwise specified. Various semiconductor elements such as MIS transistors constituting peripheral circuits are formed on the same substrate as the silicon substrate 1 on which the nonvolatile memory cells NVM are formed.

  The nonvolatile memory cell NVM is formed on an n-type silicon substrate (semiconductor substrate) 1 made of single crystal silicon (Si). The n-type is a state in which, for example, silicon composed of group IV elements contains more group V elements such as arsenic (As) and phosphorus (P) than group III elements, and the majority carriers are electrons. It represents the conductivity type of a certain semiconductor material. Hereinafter, the same applies to the n-type conductivity type. The following description is the same even when the n-type silicon substrate 1 is viewed as an n-type semiconductor region formed on a p-type substrate. The p-type is a state in which, for example, silicon composed of a group IV element contains more group III elements such as boron (B) than group V elements, and majority carriers are holes. This represents the conductivity type of such a semiconductor material. Hereinafter, the same applies to the p-type conductivity type.

  On the main surface f1 of the n-type silicon substrate 1, a p-type memory well pw1 defined for forming the nonvolatile memory cell NVM is formed. The p-type memory well is a p-type semiconductor region. Further, a separation portion 2 that is an insulator made of shallow groove type silicon oxide is formed on the main surface f1 of the silicon substrate 1. The isolation unit 2 defines regions (active region, active region) for forming individual nonvolatile memory cells NVM on the p-type memory well pw1.

  On the main surface f1 of the silicon substrate 1, a control gate electrode (first gate electrode) CG is formed via a control gate insulating film (first gate insulating film) IG. The control gate insulating film IG is an insulating film mainly composed of silicon oxide, and the control gate electrode CG is a conductor film mainly composed of polycrystalline silicon. A memory gate electrode (second gate electrode) MG is formed on the main surface f1 of the silicon substrate 1 via the charge storage insulating film IS. The charge storage insulating film IS is an insulating film having a function of storing carriers such as electrons and holes. Further, the polycrystalline silicon film as the control gate electrode CG and the memory gate electrode MG may contain impurities. Thereby, each electrode CG and MG is made into the desired electrical conductivity.

  Here, the memory gate electrode MG is formed adjacent to the side of the control gate electrode CG. In addition, the charge storage insulating film IS is integrally disposed from between the silicon substrate 1 and the memory gate electrode MG to between the control gate electrode IG and the memory gate electrode MG. That is, the control gate electrode IG and the memory gate electrode MG are electrically insulated from each other by being arranged adjacent to each other with the charge storage insulating film IS therebetween. A sidewall insulating film IW is formed on the side surface of the control gate electrode CG and between the control gate electrode CG and the charge storage insulating film IS. Therefore, the control gate electrode CG and the memory gate electrode MG are electrically insulated from each other not only by the charge storage insulating film IS but also by the sidewall insulating film IW. Details of the configuration and effects of the sidewall insulating film IW will be described later.

  The charge storage insulating film IS preferably has a three-layer structure of a first insulating film s1, a second insulating film s2, and a third insulating film s3 having the following characteristics. First, as the structure, the second insulating film s2 is disposed so as to be sandwiched between the first insulating film s1 and the third insulating film s3. The second insulating film s2 is an insulating film having a function of accumulating charges. More specifically, the second insulating film s2 is an insulating film that has a relatively large number of crystal defects in the film and can accumulate charges by trapping (trapping) carriers therein. In addition, the first insulating film s1 and the third insulating film s3 sandwiching the second insulating film s2 are insulating films having a function of preventing the charge accumulated in the second insulating film s2 from leaking to the outside. More specifically, the first insulating film s1 and the third insulating film s3 have a so-called barrier property that has a forbidden band up to a higher energy position than the energy level of carriers trapped in the second insulating film s2. It is a high insulating film. By making the charge storage insulating film IS have such a three-layer structure, carriers captured by the second insulating film s2 can be prevented from leaking to the outside. Thereby, the data retention characteristic of the nonvolatile memory cell NVM can be further improved.

  Further, as the charge storage insulating film IS having the above characteristics, the first insulating film s1 and the third insulating film s3 are insulating films mainly composed of silicon oxide, and the second insulating film s2 is mainly composed of silicon nitride. An insulating film is more preferable. The structure in which the second insulating film s2 that is a silicon nitride film is sandwiched between the first insulating film s1 and the third insulating film s3 that are silicon oxide films is a so-called ONO structure. These materials have characteristics required for the insulating films s1, s2, and s3 described above. Furthermore, silicon oxide films, silicon nitride films, and the like have a track record of being used as components of semiconductor devices, and have a lot of formation technology accumulated. Therefore, by using such an insulating film, the charge storage insulating film IS with higher reliability can be formed. Thereby, the reliability of the nonvolatile memory cell NVM can be further improved.

  For example, the first insulating film s1 made of a silicon oxide film is preferably about 4 nm, the second insulating film s2 made of a silicon nitride film is about 8.5 nm, and the third insulating film s3 made of a silicon oxide film is preferably about 5 nm.

  Further, the height of the control gate electrode CG and the height of the memory gate electrode MG viewed from the main surface f1 of the silicon substrate 1 are compared with each other so as not to have a difference in height. It is more preferable that it is a simple structure. This is because such a structure can prevent damage to the charge storage insulating film IS during ion implantation performed on the main surface of the silicon substrate 1 in the manufacturing process of the semiconductor device. The details will be described together with the description of the later manufacturing process. Thereby, the reliability of the nonvolatile memory cell NVM can be further improved.

  Further, the memory gate electrode MG is arranged so as to be adjacent to the side of the control gate electrode CG as described above. However, the memory gate electrode MG is adjacent to one of the side walls of the control gate electrode CG. It is more preferable to adopt a structure in which they are arranged together. This is because, as will be described in detail later, the memory operation of the nonvolatile memory cell NVM of the present embodiment can be completed by using one memory gate electrode MG. In addition, with the structure having one memory gate electrode MG, the cell area of the nonvolatile memory cell NVM can be reduced.

  Side wall spacers sw are formed on the side walls of the control gate electrode CG and the memory gate electrode MG that are not adjacent to each other. The sidewall spacer sw is an insulating film that is formed to make it difficult for the other conductive part and the gate electrodes CG and MG to come into contact with each other.

  In general, an insulating film has an effect of exerting stress on single crystal silicon or the like. In single crystal silicon subjected to stress, carrier mobility changes. For example, when the carrier mobility of the semiconductor layer in the MIS transistor changes, the performance of the MIS transistor changes. This is because the semiconductor layer in the MIS transistor is a layer in which a channel that actually transports carriers is formed.

  Here, the sidewall spacer sw can apply stress to the silicon substrate 1 directly below. That is, by changing the insulating film type of the side wall spacer sw to be formed, the performance of the MIS transistor constituting the nonvolatile memory cell NVM and the peripheral circuit can be controlled. The sidewall spacer sw of the present embodiment is formed by, for example, forming a silicon oxide film sw1, a silicon nitride film sw2, and a silicon oxide film sw3 in order from the side closer to the silicon substrate 1. Actually, the side wall spacer sw may have, for example, a two-layer structure of a silicon nitride film and a silicon oxide film in accordance with the required performance of the MIS transistor.

  A silicide block layer sb made of a silicon oxide film is formed on the side wall of the sidewall spacer sw. The silicide block layer sb is an insulating layer for protecting a region where the silicide layer is not formed from the silicidation reaction in the process of manufacturing the semiconductor device of the present embodiment. The process will be described later in detail together with the entire manufacturing process.

  In the p-type memory well pw1, a memory source / drain region sd1, which is an n-type semiconductor region, is formed on the main surface f1 of the silicon substrate 1 located below the side wall spacer sw. The n-type impurity concentration of the memory source / drain region sd1 is higher than the n-type impurity concentration of the silicon substrate 1.

  In the p-type memory well pw1, a memory extension region ex1 that is an n-type semiconductor region is formed on the main surface f1 of the silicon substrate 1 located on the lower side of the control gate electrode CG and the memory gate electrode MG. . The memory extension region ex1 is formed from the lower side where the electrodes CG and MG are not adjacent to each other to the end of the memory source / drain region sd1, and is electrically connected to the memory source / drain region sd1. ing. The n-type impurity concentration of the memory extension region ex1 is lower than the n-type impurity concentration of the memory source / drain region sd1.

  A metal silicide layer SC is formed on the upper surfaces of the control gate electrode CG and the memory gate electrode MG and on the surface of the memory source / drain region sd1. The metal silicide layer SC is a compound of a metal such as cobalt or nickel (Ni) and silicon, and the metal silicide layer SC of the present embodiment is, for example, cobalt silicide. The metal silicide layer SC is an element necessary for establishing electrical connection from the outside to each element of the nonvolatile memory cell NVM. That is, the metal silicide layer SC has a low resistance itself and is formed in order to realize ohmic connection in contact with the conductor. As described above, the nonvolatile memory cell NVM of the present embodiment needs to have the metal silicide layer SC in view of characteristics.

  However, in the study by the present inventor, as described above, the contact between the metal silicide layers SC between the independent elements causes a malfunction of the nonvolatile memory cell NVM, resulting in a decrease in reliability. . That is, the distance between the control gate electrode CG and the memory gate electrode MG is short, and the metal silicide layers SC formed on the upper surfaces thereof come into contact with each other.

  On the other hand, the non-volatile memory cell NVM of the present embodiment can avoid the contact failure of the metal silicide layer SC by including the sidewall insulating film IW having the following characteristics. The details will be described below.

  The sidewall insulating film IW is formed on the side surface of the control gate electrode CG. That is, the sidewall insulating film IW is in contact with the first insulating film s1 on the side wall in contact with the charge storage insulating film IS, and in contact with the silicon oxide film sw1 on the side wall in contact with the side wall spacer sw. It is formed on the side wall of the electrode CG. The sidewall insulating film IW is formed so as to integrally cover the side surface of the control gate electrode CG and the side surface of the metal silicide layer SC formed on the upper surface of the control gate electrode CG. The sidewall insulating film IW is disposed between the control gate electrode and the charge storage insulating film IS. That is, the control gate electrode CG and the memory gate electrode MG are arranged with the charge storage insulating film IS and the side wall insulating film separated from each other, thereby being electrically insulated from each other. Further, not only the charge storage insulating film IS but also the sidewall insulating film IW is disposed between the metal silicide layer SC on the upper surface of the control gate electrode CG and the metal silicide layer SC on the upper surface of the memory gate electrode MG. .

  Here, in the nonvolatile memory cell NVMa examined by the present inventor as shown in FIG. 23, in the metal silicide layer SCa on the upper surfaces of the electrodes CGa and MGa, elements that physically separate the distance in the lateral direction are: Only the charge storage insulating film IS. For example, the charge storage insulating film ISa having the ONO structure as described above has a thickness of several tens of nanometers, and the two metal silicide layers SCa are liable to cause poor contact, leading to a decrease in reliability. For example, the distance between the two electrodes CGa and MGa can be secured by increasing the thickness of the charge storage insulating film ISa. However, the charge storage insulating film ISa serves as a gate insulating film under the memory gate electrode MGa. Therefore, it is not preferable in terms of characteristics to change the film thickness.

  On the other hand, in the nonvolatile memory cell NVM of the present embodiment, the sidewall insulating film IW is provided on the side surface of the control gate electrode CG (particularly, the side surface adjacent to the memory gate electrode MG). As a result, the physical distance between the metal silicide layer SC on the upper surface of the control gate electrode CG and the metal silicide layer SC on the upper surface of the memory gate electrode MG is provided with the sidewall insulating film IW in addition to the charge storage insulating film IS. It gets longer by minutes. Therefore, the non-volatile memory cell NVM of the present embodiment is unlikely to cause an electrical short circuit due to contact of the metal silicide layer SC on the upper surfaces of both electrodes CG and MG. Furthermore, when this technique is applied, it is not necessary to change the thickness of the charge storage insulating film IS. That is, it is possible to increase a lateral margin for a short circuit between the control gate electrode CG and the memory gate electrode MG without changing the film thickness of the charge storage insulating film IS which is an important parameter of electrical characteristics. it can. As a result, the reliability of the semiconductor device having a nonvolatile memory can be further improved.

  Further, it is more preferable that the sidewall insulating film IW has a structure that does not reach the contact point with the control gate insulating film IG that is the lower end of the control gate electrode CG on the side surface of the control gate electrode CG. This structure and preferred reasons will be described in detail below.

  The sidewall insulating film IW of the nonvolatile memory cell NVM described here is formed so as to integrally cover from the middle of the side surface of the metal silicide layer SC to the middle of the side surface of the control gate electrode CG. That is, above the control gate electrode CG, the side surfaces of the control gate electrode CG and the metal silicide layer SC are integrally covered and disposed between the control gate electrode CG and the charge storage insulating film IS. Sidewall insulating film IW is formed. Further, below the control gate electrode CG, the sidewall insulating film IW is not formed on the side surface of the control gate electrode CG, and the control gate electrode CG and the charge storage insulating film IS are in contact with each other. Note that the sidewall insulating film IW is formed so as to enter the control gate electrode CG side from the boundary between the control gate electrode CG and the charge storage insulating film IS. That is, not the charge storage insulating film IS but the control gate electrode CG exists below the lower end of the side wall insulating film IW arranged partway along the side surface of the control gate electrode CG. The reason why such a structure is more preferable will be described below.

  The control gate electrode CG is an element constituting the MIS structure in the nonvolatile memory cell NVM. Then, at the time of a read operation, it is regarded as an integral part of the memory gate electrode MG and acts as the gate electrode of the MIS transistor. Therefore, the gate length of the control gate electrode CG is determined based on the characteristics required for the MIS transistor. The gate length of the control gate electrode CG is the length of the portion where the control gate electrode CG and the control gate insulating film IG are in contact with each other in the drawing. An inversion layer due to a field effect is formed in the p-type memory well pw1 directly below, and carriers are transported in the inversion layer. Therefore, the gate length is related to the carrier transport distance and is one of important parameters in the characteristics of the MIS transistor.

  As described above, the sidewall insulating film IW of the present embodiment is formed so as not to reach the lower end of the control gate electrode CG, so that the metal silicide is not affected without affecting the gate length of the control gate electrode CG. It is possible to realize a structure that hardly causes contact failure of the layer SC. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved.

  For example, the height of the control gate electrode CG from the control gate insulating film IG is preferably about 200 to 220 nm. For example, the distance from the control gate insulating film IG to the lower end of the sidewall insulating film IW is preferably about 50 to 100 nm. Further, for example, the gate length of the control gate electrode, that is, the lower surface of the control gate electrode CG, the side wall insulating film IW is not formed on the side wall, and the main surface of the silicon substrate 1 is in contact with the control gate insulating film IG. The distance seen in the direction along f1 is preferably about 110 nm. For example, a similar gate length in the memory gate electrode MG is preferably about 55 nm.

  Further, the sidewall insulating film IW has a structure that protrudes higher than the upper surfaces of the metal silicide layers SC on the upper surfaces of the control gate electrode CG and the memory gate electrode MG when viewed from the main surface f1 of the silicon substrate 1. More preferred. The reason will be described below.

  As will be described in detail later when the manufacturing process is described, the metal silicide layer SC is formed so as to grow upward from the upper surface of the control gate electrode CG and the memory gate electrode MG. Here, in the nonvolatile memory cell NVMa examined by the present inventor as shown in FIG. 23, only the charge storage insulating film ISa separates the electrodes CGa and MGa. This charge storage insulating film ISa does not have a structure protruding above the upper surface of the metal silicide layer SC on the upper surfaces of both electrodes CGa and MGa. Therefore, it is easy to contact in the process of forming the metal silicide layer SC on the upper surfaces of both electrodes CGa and MGa, which causes a decrease in reliability.

  On the other hand, in the nonvolatile memory cell NVM of the present embodiment, the sidewall insulating film IW is formed so as to protrude to a position higher than the upper surface of the control gate electrode CG. Further, in the final structure, the sidewall insulating film IW is formed so as to protrude to a position higher than the upper surface of the metal silicide layer SC on the upper surface of the control gate electrode CG. Therefore, the nonvolatile memory cell NVM of the present embodiment has an electrical short circuit in which the metal silicide layers SC on the upper surfaces of both electrodes CG and MG are in contact with each other over the side wall insulating film IW and the charge storage insulating film IS. It is hard to wake up. That is, a margin in the film thickness direction of the metal silicide layer SC with respect to a short circuit between the control gate electrode CG and the memory gate electrode MG can be increased. As a result, the reliability of the semiconductor device having a nonvolatile memory can be further improved.

  For example, the distance from the upper surface of the control gate electrode CG to the apex of the sidewall insulating film IW is preferably about 30 to 50 nm. Therefore, the thickness of the metal silicide layer SC is preferably about 30 to 50 nm or less.

  The sidewall insulating film IW is more preferably an insulating film mainly composed of a silicon nitride film. For example, by forming a silicon nitride film by a low pressure chemical vapor deposition (CVD) method or the like, the sidewall insulating film IW can be made denser than other insulating films. Thereby, it can be set as the structure which can suppress the leak current through the metal silicide layer SC more reliably. As a result, the reliability of the semiconductor device having a nonvolatile memory can be further improved.

  Note that the sidewall insulating film IW of the present embodiment is preferably about 10 to 20 nm in thickness when viewed in the direction along the main surface f1 of the silicon substrate 1. This is because, in consideration of insulation, the thicker the sidewall insulating film IW, the more preferable, but the thicker the sidewall insulating film IW, the narrower the region where the metal silicide SC is formed above the control gate electrode CG. This is because the resistance value as a conduction portion to the control gate electrode CG is increased. Therefore, it is preferable to set the minimum film thickness necessary for improving the short margin between the electrodes CG and MG. The thickness of the sidewall insulating film IW according to the present embodiment is verified by the inventors. The above numerical value was set as a preferable range. A specific forming method will be described in detail together with a description of a later manufacturing process.

  Further, it is sufficient that the sidewall insulating film IW of the present embodiment is provided on at least the side where the memory gate electrode MG is disposed on the side surface of the control gate electrode CG. That is, in order to obtain the above-described effect for reducing contact failure, the sidewall insulating film IW is disposed between the control gate electrode CG and the sidewall spacer sw on the side where the memory gate electrode MG is not disposed. There is no need to be. However, from the viewpoint of the manufacturing process, even when the memory gate electrode MG is formed only on one side of the control gate electrode CG, the sidewall insulating film IW is arranged on both side surfaces of the control gate electrode CG. Is more preferable. Details of the reason will be described together with the explanation of the later manufacturing process. In addition, it has been confirmed by the inventor that the structure having the sidewall insulating films IW on both side surfaces does not affect the characteristics. Further, in the case where the side wall insulating film IW has an effect on the characteristics of the control gate electrode CG (for example, the resistance of the metal silicide layer SC on the upper surface) as the element is miniaturized, the memory A structure in which the sidewall insulating film IW is not disposed on the side surface of the control gate electrode CG on the side where the gate electrode MG is not disposed may be employed.

  The nonvolatile memory cell NVM configured as described above is entirely covered with an etching stop insulating film IB made of a silicon nitride film. Further, an interlayer insulating film IL made of a silicon oxide film is formed so as to cover the etching stop insulating film IB and to embed the configuration of the nonvolatile memory cell NVM. Further, a contact hole CH that is electrically connected to the metal silicide layer SC is formed so as to penetrate the interlayer insulating film IL and the etching stop insulating film IB. Further, the contact hole CH is filled with tungsten (W) or the like to form a contact plug CP. Here, the contact plug CP may include, for example, titanium nitride (TiN) as a barrier metal formed at the interface between the interlayer insulating film IL and tungsten (not shown). Through this contact plug CP, the control gate electrode CG, the memory gate electrode MG, and the memory source / drain region sd1 constituting the nonvolatile memory cell NVM can be electrically supplied from the outside.

  Note that the etching stop insulating film IB is formed to form a contact hole in a self-aligning manner in the interlayer insulating film by a so-called SAC (Self Align Contact) technique. The contact hole processing by the SAC technique will be described in detail together with the description of the subsequent manufacturing process.

  Over the interlayer insulating film IL, an insulating film IM made of a silicon oxide film is formed. In the insulating film IM, for example, a wiring WM made of a conductor such as aluminum (Al) or copper (Cu) is formed. The wiring WM may have, for example, titanium nitride (not shown) as a barrier metal that sandwiches the upper and lower sides of aluminum. The barrier metal is formed to suppress a chemical reaction between the wiring metal and the interlayer insulating film IL. The wiring WM is electrically connected to the contact plug CP, and forms a desired wiring pattern in the insulating film IM. Further, a similar interlayer insulating film IL, contact plug CP (also referred to as a via plug), insulating film IM, wiring WM, and the like are repeatedly formed in an upper layer of the insulating film IM to constitute a multilayer wiring (illustrated). do not do).

  The above is the structure of the semiconductor device including the split-gate nonvolatile memory cell NVM in this embodiment. Hereinafter, the memory operation of the split-gate nonvolatile memory cell NVM in this embodiment will be described in detail with reference to FIG. FIG. 3 is an explanatory view showing a cross section of the main part for explaining the memory operation of the nonvolatile memory cell NVM. Here, a voltage applied to the control gate electrode CG is referred to as a control gate voltage Vcg, and a voltage applied to the memory gate electrode MG is referred to as a memory gate voltage Vmg. In the extension region ex1 that communicates with the memory source / drain region sd1, the voltage applied to the extension region ex1 on the control gate electrode CG side is the drain voltage Vd, and the voltage applied to the extension region ex1 on the memory gate electrode MG side is the source voltage. Called Vs.

  In the write operation, for example, 0.8 V is applied as the drain voltage Vd, 6 V is applied as the source voltage Vs, 12 V is applied as the memory gate voltage Vmg, and 1.5 V is applied as the control gate voltage Vcg. Under such bias conditions, this is performed by injecting hot electrons into the charge storage insulating film IS from the channel formation region under the memory gate electrode MG. Thus, in the nonvolatile memory cell NVM of the present embodiment, so-called SSI in which electrons (electrons) transported from the drain to the source are extracted to the charge storage insulating film IS by a high electric field near the memory gate electrode MG. The write operation is performed by the (Source Side Injection) method.

  In the read operation, for example, 1.5 V is applied as the drain voltage, 0 V as the source voltage Vd, and 1.5 V is applied as the memory gate voltage Vmg and the control gate voltage Vcg, respectively. In the case of a memory cell that has undergone the previous writing operation, electrons are stored in the charge storage insulating film IS under the memory gate electrode MG and are negatively charged, so that the threshold voltage as an n-channel MIS transistor increases. ing. On the other hand, in the case of a memory cell that has not been subjected to a write operation, the charge storage insulating film IS is not negatively charged, so that the threshold voltage does not increase. Therefore, the drain current is smaller in the former state than in the latter state in the state where the write has been received and in the state where the write has not been received. In this way, the write state of the nonvolatile memory cell NVM can be read.

  In the erasing operation, the charge storage insulating film IS that is negatively charged in response to writing may be brought into an electrically neutral state. There are several methods, but here, as an example, a method of injecting positive charge holes into the charge storage insulating film IS will be described. For example, 0 V is applied as the drain voltage Vd and the source voltage Vs, −6 V is applied as the memory gate voltage Vmg, and 0 V is applied as the control gate voltage Vcg. Under such a bias condition, strong inversion occurs in the extension region ex1 at the lower side of the memory gate electrode MG, and holes are generated in the extension region ex1 that is an n-type semiconductor. The generated holes are extracted to the charge storage insulating film IS by the high electric field of the memory gate electrode MG. As described above, the nonvolatile memory cell NVM of the present embodiment has a so-called BTBT (Band To Band) in which holes generated by strong inversion of the extension region ex1 on the memory gate electrode MG side are extracted to the charge storage insulating film IS. The erasing operation is performed by the tunneling method.

  Under the bias conditions as described above, the memory operation of the nonvolatile memory cell NVM of the present embodiment becomes possible. The numerical value is an example and depends on the actual structure.

  Below, the manufacturing method of the semiconductor device of this Embodiment is demonstrated using FIGS. The semiconductor device includes a plurality of nonvolatile memory cells NVM having the configuration described with reference to FIGS. Then, on the same silicon substrate 1, a generally known semiconductor element such as a MIS transistor constituting a peripheral circuit such as a logic circuit is formed. In the present embodiment, these non-volatile memory cells NVM and other semiconductor elements are formed separately by the same process. Therefore, hereinafter, a process of forming the nonvolatile memory cell NVM and elements constituting the peripheral circuit will be described. Steps performed on the three regions of the silicon substrate 1, that is, the memory region Rm for forming the nonvolatile memory cell NVM, the peripheral region Rp for forming the peripheral circuit, and the boundary region Rb serving as a boundary between them will be described in detail. .

  Further, since the plurality of nonvolatile memory cells NVM formed in the memory region Rm on the silicon substrate 1 are all formed in the same process, a manufacturing process of one nonvolatile memory cell NVM will be described as a representative. . Note that the thickness of the film to be formed, the processing dimensions, and the like are the same as those in the numerical examples described with reference to FIGS. 1 and 2, and redundant description is omitted unless otherwise specified. Various semiconductor elements are formed in the peripheral region Rp. As a typical example, a process of forming an n-channel MIS transistor (hereinafter referred to as an n-type MIS transistor) is shown.

  First, as shown in FIG. 4, a single crystal silicon substrate 1 is prepared. The conductivity type of the silicon substrate 1 may be n-type or p-type. In the manufacturing method of the present embodiment, a case where an n-type silicon substrate 1 is used will be described. The following description is the same even when the n-type silicon substrate 1 is viewed as an n-type semiconductor region formed on a p-type substrate.

  A separation portion 2 is formed in a predetermined region of the main surface f1 of the silicon substrate 1. For this, first, a shallow groove is formed in the main surface f1 of the silicon substrate 1 by a photolithography process and an anisotropic etching process. The photolithography process is a series of processes for forming a desired resist pattern on the photoresist film by processes such as coating, exposure and development of the photoresist film. Using such a photoresist film as a mask, the exposed region can be subjected to anisotropic etching or ion implantation. Thereafter, the photolithography process is the same unless otherwise specified.

  Subsequently, an insulating film such as a silicon oxide film is deposited on the silicon substrate 1 including the inside of the shallow groove by a CVD method or the like. Thereafter, an unnecessary silicon oxide film outside the shallow groove is polished and removed by a so-called CMP (Chemical Mechanical Polishing) method or the like, thereby forming a structure in which the silicon oxide film is embedded in the shallow groove. In this way, the separation part 2 having the STI structure is formed. By forming the isolation part 2, an active region whose periphery is defined by the isolation part 2 is formed on the main surface f <b> 1 of the silicon substrate 1.

  Subsequently, a p-type memory well pw1 is formed in the main surface f1 of the silicon substrate 1 in the memory region Rm. In addition, p-type wells pw2 and pw3 are formed on the main surface f1 of the silicon substrate 1 in the boundary region Rb and the peripheral region Rp, respectively. These are formed by a photolithography process, an ion implantation process, a heat treatment process, and the like. First, a photoresist film having a pattern in which a region where a well is to be formed is opened is formed on the main surface f1 of the silicon substrate 1 by a photolithography process. Thereafter, ion implantation is performed on the main surface f1 using the patterned photoresist film as an ion implantation mask. In the case of forming a p-type well, impurity ions (for example, boron ions) that can serve as acceptors are implanted. Thereafter, by performing heat treatment, the introduced impurity ions are diffused and activated at the same time, and a p-type well can be formed. Hereinafter, the process of forming the p-type semiconductor region is the same unless otherwise specified.

  In addition, in order to form an n-type MIS transistor later in the peripheral region Rp, the step of forming the p-type well pw3 in the above-described steps is shown. However, for example, the region where the p-type MIS transistor is formed includes an n-type well. Form. In this case, in the ion implantation step described above, impurity ions that can serve as donors (for example, phosphorus ions and arsenic ions) may be implanted, and the rest can be formed in the same manner. Hereinafter, the process of forming the n-type semiconductor region is the same unless otherwise specified. In the boundary region Rb, if it is not necessary to intentionally form a functional semiconductor element, a p-type well pw2 or an n-type well may be formed. It is not necessary to form a well.

  In the process of forming the p-type memory well pw1, the p-type wells pw2, and pw3, those that can share the process may be formed at the same time depending on the properties of the wells. For example, if the polarity and concentration of the impurity ions to be implanted are the same, it is more preferable to perform the ion implantation step simultaneously. Further, for example, if the heat treatment conditions required from the depth of the well to be formed are the same, it is more preferable to perform the heat treatment simultaneously. This is because the manufacturing process can be simplified by sharing a plurality of processing steps as described above. Hereinafter, the process for forming the semiconductor region is the same.

  Next, as shown in FIG. 5, on the main surface f1 of the silicon substrate 1, a control gate insulating film IG is formed in the memory region Rm, and a gate insulating film 3 is formed in the peripheral region Rp. Note that the gate insulating film 3 formed in the peripheral region will later become a gate insulating film constituting the MIS transistor. Here, in the manufacturing process of the present embodiment, both the control gate insulating film IG and the gate insulating film 3 are insulating films mainly composed of silicon oxide. Therefore, it is more preferable that the gate insulating film 3 formed in the peripheral region Rp is formed in the same process as the control gate insulating film IG formed in the memory region Rm. This is because the manufacturing process can be simplified. In this case, the same gate insulating film 3 is also formed in the boundary region. Here, the control gate insulating film IG and the gate insulating film 3 are formed by a thermal oxidation method or the like.

  The subsequent steps are steps for forming the control gate electrode CG of FIG. 1 on the main surface f1 of the silicon substrate 1 in the memory region Rm via the control gate insulating film IG.

  On the main surface f1 of the silicon substrate 1, a first conductor film 4 and a protective insulating film 5 are sequentially formed so as to cover the control gate insulating film IG and the gate insulating film 3. Here, the first conductor film 4 is a conductor film mainly composed of polycrystalline silicon, and is formed by a CVD method or the like. Since the first conductor film 4 is a conductor film that will later become the control gate electrode CG of the nonvolatile memory cell NVM, as described with reference to FIGS. 1 and 2, the thickness is about 200 to 220 nm. preferable. In order to make the first conductor film 4 which is a polycrystalline silicon film have a desired conductivity, impurities are introduced into the first conductor film 4 by ion implantation or the like before the protective insulating film 5 is formed. May be. The protective insulating film 5 is an insulating film mainly composed of silicon oxide and is formed by a CVD method or the like. The thickness of the protective insulating film 5 is preferably about 30 to 50 nm. Details of the method of forming the protective insulating film 5 will be described later.

  Next, as shown in FIG. 6, a photoresist film 6 is formed on the protective insulating film 5 and patterned by a photolithography method or the like. More specifically, in the memory region Rm, the photoresist film 6 is formed so as to cover a region that will later become the control gate electrode CG of the nonvolatile memory cell NVM and to have a shape that exposes the other. Pattern. Further, in the peripheral region Rp, the photoresist film 6 is patterned so as to cover the entire region. As a result, in the boundary region Rb, the photoresist film 6 is patterned so that the region following the peripheral region Rp is covered and the region following the memory region Rm is exposed.

  Subsequently, the first insulating etching is performed using the photoresist film 6 as an etching mask, thereby removing the protective insulating film 5 in a region not covered with the photoresist film 6 in a plane. Subsequently, second anisotropic etching is performed using the photoresist film 6 as an etching mask, thereby removing the first conductor film 4 in a region that is not planarly covered with the photoresist film 6. In this way, the effect of applying the photoresist film 6 as an etching mask for both the first anisotropic etching and the second anisotropic etching will be described in detail later.

  Here, in the manufacturing process of the present embodiment, the second anisotropic etching is performed so that the first conductive film 4 to be subjected to the second anisotropic etching is not completely removed when viewed in the thickness direction. Stop halfway. That is, in this step, part of the first conductor film 4 in the region that is not planarly covered with the photoresist film 6 is removed in the thickness direction. For this, second anisotropic etching is performed while measuring the remaining film thickness of the first conductor film 4 to be removed by an optical observation method. Then, when the first conductor film 4 having a desired thickness is obtained, the second anisotropic etching is stopped. In the manufacturing process of the present embodiment, it is preferable that the thickness of the portion of the first conductor film 4 to be left by the second anisotropic etching is about 50 to 100 nm. This is because if the first conductor film 4 is left in this numerical range, it will not be removed by over-etching when the side wall insulating film IW described later is processed, and the protective insulating film is protected against the remaining control gate electrode CG. This is because variations in the remaining film of the protective insulating film 5 when processing 5 as a hard mask can be suppressed. Details of the effect of stopping the second anisotropic etching in this way will be described later. After the above process, the photoresist film 6 is removed.

  Next, as shown in FIG. 7, a protective film 7, which is an insulating film, is formed on the main surface f <b> 1 of the silicon substrate 1 so as to cover the configuration formed as described above. Thereafter, as shown in FIG. 8, the entire surface of the silicon substrate 1 is formed by performing anisotropic etching on the entire surface of the protective film 7 (etching back the protective film 7). A sidewall insulating film IW made of the protective film 7 is formed on the sidewall of the step portion. That is, from the protective film 7 so as to integrally cover the side surface of the protective insulating film 5 and the side surface of the first conductor film 4 generated by the first anisotropic etching and the second anisotropic etching. That is, the sidewall insulating film IW is formed. Here, since the protective film 7 is processed into the shape of the sidewall insulating film IW by etch back, the removal rate by the anisotropic etching is higher than that of the first conductor film 4 and the protective insulating film 5 as the base. An insulating film is formed as the protective film 7.

  Next, as shown in FIG. 9, the region of the first conductor film 4 that is not covered by either the protective insulating film 5 or the sidewall insulating film IW is removed by third anisotropic etching. That is, in the description using FIG. 6 above, the portion of the first conductive film 4 to be subjected to the second anisotropic etching that is left off while being etched is removed by the third anisotropic etching. To do. Thus, the control gate electrode CG made of the first conductor film 4 is formed in the memory region Rm. 6 to 9 are arranged on the main surface f1 of the silicon substrate 1 via the control gate insulating film IG, and the protective insulating film 5 on the upper surface and the side wall insulating film IW on the side surface by the steps described with reference to FIGS. A control gate electrode CG provided with is formed.

  Here, in the process described with reference to FIG. 9, the newly patterned photoresist film may be used as an etching mask. However, the first conductive film 4 is formed on the first conductor film 4 using the protective insulating film 5 and the sidewall insulating film IW as an etching mask. It is more preferable to perform 3 anisotropic etching. The reason will be described below.

  In order to protect the convex portion of the first conductor film 4 processed once by the second anisotropic etching (in the memory region Rm, the portion that will later become the control gate electrode CG), a photoresist film is formed at exactly the same location. It is difficult to do. The difficulty in forming the control gate electrode CG having a desired shape causes a reduction in yield and causes a decrease in the reliability of the semiconductor device. Furthermore, when patterning the photoresist film, it is necessary to add a photoresist process, which increases the number of manufacturing processes. On the other hand, in the manufacturing process of the present embodiment, it is not necessary to process the photoresist film again at the time of the third anisotropic etching, and the protective insulating film 5 and the side wall insulation already formed as a so-called hard mask The film IW is applied as an etching mask. Therefore, the control gate electrode CG can be formed with high processing accuracy. Furthermore, since the control gate electrode CG is formed in a self-aligning manner by the third anisotropic etching, the photolithography process can be reduced. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved.

  As described above, in order to perform the third anisotropic etching on the first conductor film 4 using the protective insulating film 5 and the sidewall insulating film IW as an etching mask, the following conditions are required. First, in the process of FIG. 5, an insulating film having a removal rate (also referred to as an etching rate) slower than that of the first conductor film is formed as the protective insulating film 5 with respect to the third anisotropic etching. That is, an insulating film having a selection ratio with respect to the third anisotropic etching lower than that of the first conductor film 4 is formed as the protective insulating film 5. Subsequently, in the process of FIG. 7, an insulating film having a removal rate slower than that of the first conductor film is formed as the protective film 7 to be the sidewall insulating film IW with respect to the third anisotropic etching. That is, an insulating film having a selection ratio with respect to the third anisotropic etching lower than that of the first conductor film 4 is formed as the protective film 7.

  By using the material under the above conditions, the protective insulating film 5 and the sidewall insulating film IW can be used as an etching mask in the third anisotropic etching. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved. Since there are other factors that determine the material used for the protective insulating film 5 and the protective film 7 (later sidewall insulating film IW) and the formation method thereof in this embodiment, they will be described in detail after explaining the factors.

  In the second anisotropic etching in the description with reference to FIG. 6, all of the first conductor film 4 not covered with the photoresist film 6 may be removed. In this case, the sidewall insulating film IW reaching the lower end of the control gate electrode CG is formed after performing the same process as that shown in FIGS.

  On the other hand, as in the manufacturing process of the present embodiment described above, it is more preferable to stop the second anisotropic etching on the first conductor film 4 halfway. This is because the second anisotropic etching is stopped halfway, and then the sidewall insulating film IW is formed as shown in FIGS. 7 to 9, so that the control gate insulating film IG as the lower end of the control gate electrode CG The sidewall insulating film IW can be formed so as not to reach the contact. The effect of the sidewall insulating film IW having such a shape is as described with reference to FIGS. In the manufacturing process of the present embodiment, the sidewall insulating film IW having such an effect can be formed in a self-aligned manner. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved.

  After forming the control gate electrode CG as described above, the control gate insulating film IG and the gate insulating film 3 that are not covered with the control gate electrode CG and the first conductor film 4 are removed.

  Next, as shown in FIG. 10, the protective insulating film 5 formed on the upper surface of the control gate electrode CG, the upper surface of the first conductor film 4 and the like is removed. Here, as described above, the protective insulating film 5 was formed to have a thickness of about 30 to 50 nm. Therefore, by removing the protective insulating film 5 as described above, the sidewall insulating film IW is shaped to protrude to a position at least about 30 to 50 nm higher than the upper surface of the control gate electrode CG. As a result, even if a conductor layer is formed later on the upper surface of the control gate electrode CG, a structure in which poor contact with other conductor layers hardly occurs can be obtained. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved. More specifically, details will be described later.

  As described above, the protective insulating film 5 is formed as an etching mask in the third anisotropic etching and as a component necessary for protruding the sidewall insulating film IW. These all play an important role for forming the nonvolatile memory NVM of the present embodiment, and are not easily conceived by a design change of the prior art.

  In the manufacturing process of the present embodiment, the process of removing the protective insulating film 5 is self-aligned by performing wet etching (isotropic etching) without forming a newly patterned photoresist film or the like. It is more preferable to remove it. This is because the manufacturing process of the semiconductor device can be further simplified by applying a process that does not require a photolithography process. For this purpose, in the process of FIG. 5, as the protective insulating film 5, an insulating film having a higher removal rate than the sidewall insulating film IW and the control gate electrode CG (first conductor film 4) is formed with respect to the wet etching. There is a need to. By using such an insulating film, the manufacturing process of the semiconductor device can be further simplified, and as a result, the reliability of the semiconductor device including the nonvolatile memory can be further improved.

  Of the insulating films having such conditions, it is more preferable to form an insulating film mainly composed of silicon oxide as the protective insulating film 5 of the present embodiment. The reason will be described below.

  When moving to the next step with the main surface f1 of the silicon substrate 1 exposed as in the memory region Rm of FIG. 10 above, cleaning is performed in advance to remove the natural oxide film and contaminants (previous) Washing). More specifically, for example, a natural oxide film is intentionally formed on the silicon substrate 1 by a treatment such as a chemical solution, and then the natural oxide film is removed by wet etching. Thereby, the main surface f1 of the clean silicon substrate 1 is obtained.

  Here, if an insulating film mainly composed of silicon oxide is applied as the protective insulating film 5 in the present embodiment, the wet etching for removing the protective insulating film 5 is shared with the wet etching in the pre-cleaning described above. Can do. This is because the natural oxide film removed by wet etching in the pre-cleaning is an insulating film mainly composed of silicon oxide, and at the same time, the protective insulating film 5 can be removed. That is, if the protective insulating film 5 is simultaneously removed by this pre-cleaning, a self-aligned wet etching process that does not depend on the photolithography process can be performed without newly adding. Therefore, the manufacturing process can be further simplified, and as a result, the reliability of the semiconductor device including the nonvolatile memory can be further improved. As will be described in detail later, the protective insulating film 5 may be removed at least before the formation of the conductor film made of metal silicide on the control gate electrode CG. If so, it is removed after the main surface f1 of the silicon substrate 1 is exposed and before the next step is performed.

  In addition, as described with reference to FIG. 8, the protective film 7 serving as the sidewall insulating film IW has a higher removal rate by anisotropic etching than the first conductor film 4 and the protective insulating film 5. An insulating film is formed. Here, as described above, in this embodiment, a method of forming a conductor film mainly composed of polycrystalline silicon as the first conductor film 4 and forming an insulating film mainly composed of silicon oxide as the protective insulating film 5. Explained. Taking these into consideration, an insulating film mainly composed of silicon nitride is suitable as the protective film 7 (the subsequent sidewall insulating film IW) formed in the step of FIG. By using such a material, a structure in which the sidewall insulating film IW protrudes over the control gate electrode CG can be formed in a self-aligned manner. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved. In view of the structure and characteristics, the side wall insulating film IW is more preferably an insulating film mainly composed of silicon nitride, as described above with reference to FIGS.

Further, as a method for forming an insulating film mainly composed of silicon oxide, there are various known methods such as raw materials and heat treatment conditions, for example, even by the CVD method. Among these, the protective insulating film 5 of the present embodiment is more preferably formed by the following method. That is, in the process of FIG. 5, the insulating film mainly composed of silicon oxide as the protective insulating film 5 is formed by the CVD method using ozone (O ₃ ) and TEOS (Tetra Ethyl Ortho Silicate) as raw materials. More preferably, the heat treatment is not performed until it is removed in the step of FIG. The reason will be described below.

  As in the process described above, the protective insulating film 5 of the present embodiment can be used as an etching mask for the third anisotropic etching in the process of FIG. 9, and in the process of FIG. An insulating film that can be removed simultaneously by wet etching during pre-cleaning is preferable. That is, the protective insulating film 5 is a film having a removal rate as slow as possible in the third anisotropic etching and a removal rate as fast as possible in the isotropic wet etching that can remove the natural oxide film. It is more preferable that

  Here, as described above, since the first conductor film 4 that is the object of the third anisotropic etching is a conductor film mainly composed of polycrystalline silicon, the protective insulating film 5 is mainly composed of silicon oxide. An insulating film is suitable. In addition, according to the inventor's verification, if the silicon oxide film is formed by a CVD method using ozone as a raw material and is not subjected to heat treatment after the formation, the wet etching rate is increased. I found it fast. Therefore, by forming the silicon oxide film as the protective insulating film 5 as described above, the function as an etching mask for the third anisotropic etching is maintained, and it is easily removed by wet etching at the time of pre-cleaning. It becomes possible. Thereby, the structure in which the sidewall insulating film IW protrudes from the control gate electrode CG can be formed in a self-aligned manner, and the manufacturing process can be further simplified. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved.

  In the description using FIG. 6 above, the second anisotropic etching may use the protective insulating film 5 as an etching mask, but the photoresist film 6 is used as an etching mask as in the first anisotropic etching. I mentioned that it is more preferable. The reason will be described in detail below.

  The protective insulating film 5 is used as an etching mask for the third anisotropic etching shown in FIG. 9 before being removed by wet etching during pre-cleaning of the silicon substrate 1. Although the protective insulating film 5 has a low removal rate in the third anisotropic etching, the anisotropic etching is not a little damaged. On the other hand, when the protective insulating film 5 that is a silicon oxide film is removed by isotropic wet etching, the protective insulating film 5 is made as uniform as possible in order to reduce the influence on the underlying control gate electrode CG and the like. It is desirable that Therefore, in order to avoid damage due to anisotropic etching, it is desirable that the number of times that the protective insulating film 5 is used as an etching mask for anisotropic etching is smaller. That is, by applying the photoresist film 6 to the etching masks for the first and second anisotropic etchings, damage to the protective insulating film 5 due to anisotropic etching can be reduced. Thereby, the uniformity of the protective insulating film 5 to be removed by wet etching in the step of FIG. 9 can be improved, and the influence on the control gate electrode CG can be reduced. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved.

  Next, as shown in FIG. 11, a charge storage insulating film IS is formed on the main surface f <b> 1 of the silicon substrate 1 so as to cover the configuration formed by the above steps. In this step, as the charge storage insulating film IS, a first insulating film s1, a second insulating film s2, and a third insulating film s3 are sequentially formed from the side closer to the silicon substrate 1. Here, as the first insulating film s1 and the third insulating film s3, an insulating film mainly composed of silicon oxide is formed by a CVD method or the like, and as the second insulating film s2, an insulating film mainly composed of silicon nitride is formed by a CVD method. And so on. Therefore, in the charge storage insulating film IS of the present embodiment, the second insulating film s2 that is a silicon nitride film is sandwiched between the first insulating film s1 that is a silicon oxide film and the third insulating film s3. So-called ONO structure.

  Subsequently, the second conductor film 8 is formed so as to cover the charge storage insulating film IS. In this step, a conductor film mainly composed of polycrystalline silicon is formed as the second conductor film 8 by a CVD method or the like. Note that an impurity may be introduced into the second conductor film 8 by ion implantation or the like in order to make the second conductor film 8 which is a polycrystalline silicon film have a desired conductivity.

  Next, as shown in FIG. 12, the second conductor film 8 is etched back to form the memory gate electrode MG.

  In the semiconductor device of the present embodiment, as shown in FIG. 13, the memory gate electrode MG formed on the side of one of the side walls of the control gate electrode CG is removed. For this purpose, a photoresist film 9 patterned by a photolithography method is formed so as to cover only one memory gate electrode MG, and the exposed memory gate electrode MG is removed by etching using this as an etching mask. To do. Thereafter, the photoresist film 9 is removed. Thus, the effect of disposing the memory gate electrode MG so as to be adjacent to one of the side walls of the control gate electrode CG has been described with reference to FIGS. Street. Therefore, according to the manufacturing process of the present embodiment, the nonvolatile memory cell NVM having such an effect can be formed. As a result, the cell area of the nonvolatile memory cell NVM can be reduced.

  When the memory gate electrode MG on one side is removed, as described with reference to FIGS. 1 and 2, the sidewall insulating film IW is on the side where the memory gate electrode MG is disposed on the side surface of the control gate electrode CG. It is sufficient to form it between the control gate electrode CG and the charge storage insulating film IS. Therefore, the side wall insulating film IW on the side of the control gate electrode CG from which the memory gate electrode MG has been removed may be removed in any of the subsequent steps. However, in this case, the number of steps for removing the side wall insulating film IW on one side is increased. Therefore, in the manufacturing process of the present embodiment, the sidewall insulating film IW is left without being removed even if it is formed on the side surface of the control gate electrode CG on the side where the memory gate electrode MG is removed. Therefore, the manufacturing process can be further simplified, and as a result, the reliability of the semiconductor device including the nonvolatile memory can be further improved. In addition, it has been confirmed by the inventor that the structure having the sidewall insulating films IW on both side surfaces does not affect the characteristics.

  Next, as shown in FIG. 14, the third insulating film s3 in the region not covered with the memory gate electrode MG or the second conductor film 8 is removed by etching. Here, the silicon oxide film which is the third insulating film s3 is made of a material different from the polycrystalline silicon film which is the memory gate electrode MG and the second conductor film 8, and the silicon nitride film which is the second insulating film s2 which is the base. is there. Therefore, only the third insulating film s3 can be removed by selective etching.

  Thereafter, the second insulating film s2 in the region not covered with the memory gate electrode MG or the second conductor film 8 is removed by etching. Here, the silicon nitride film that is the second insulating film s2 is made of a material different from the polycrystalline silicon film that is the memory gate electrode MG and the second conductor film 8, and the silicon oxide film that is the first insulating film s1 that is the base. is there. Therefore, only the second insulating film s2 can be removed by selective etching. The sidewall insulating film IW is an insulating film mainly composed of silicon nitride similar to the second insulating film s2, but the sidewall insulating film IW is covered with the first insulating film s1 that is a silicon oxide film. 2 Insensitive to etching on the insulating film s2.

  Next, as shown in FIG. 15, the first insulating film s1 in the region not covered with the memory gate electrode MG or the second conductor film 8 is removed by etching. Here, the silicon oxide film that is the first insulating film s1 is a polycrystalline silicon film that is the memory gate electrode MG and the second conductor film 8, a polycrystalline silicon film that is the underlying control gate electrode CG, or the sidewall insulating film IW. This material is different from the silicon nitride film. Therefore, only the first insulating film s1 can be removed by selective etching.

  As described above, the charge storage insulating film IS and the memory gate electrode MG can be formed in the memory region Rm as the nonvolatile memory NVM described with reference to FIGS. 1 and 2 has.

  The first conductor film 4 is formed on the main surface f1 of the silicon substrate 1 in the peripheral region Rp through the gate insulating film 3 even after the above steps. In the manufacturing process of the present embodiment, the MIS structure of the MIS transistor formed in the peripheral region Rp is formed using this. That is, the gate electrode GE is formed by performing anisotropic etching on the first conductor film 4 and the gate insulating film 3 in the peripheral region Rp using the photoresist film 10 patterned into a desired shape as an etching mask. At this time, the memory region Rm is covered with the photoresist film 10 so that the anisotropic etching is not performed on the configuration of the memory region Rm. Accordingly, in the boundary region Rb between the memory region Rm and the peripheral region Rp, the memory region Rm side is covered with the photoresist film 10 and the peripheral region Rp side is exposed. Therefore, the exposed first conductor film 4 is removed by anisotropic etching without being covered with the photoresist film 10 in the boundary region Rb. Thereafter, the photoresist film 10 is removed.

  Next, as shown in FIG. 16, a memory extension region ex1 is formed in the memory region Rm of the main surface f1 of the silicon substrate 1, and an extension region ex2 is formed in the boundary region Rb and the peripheral region Rp, respectively. Formed by. Here, the control gate electrode CG, the memory gate electrode MG, the charge storage insulating film IS, the first conductor film 4, the second conductor film 8, and the gate electrode GE that are already formed on the main surface f1 are ion implantation masks. Then, ion implantation is performed on the main surface f1. As a result, the memory extension region ex1 or the extension region ex2 is formed on the main surface f1 of the silicon substrate 1 that is not covered by any of the above-described elements. In particular, in the memory region Rm, the memory extension region ex1 is formed in the lateral lower portion of the sides of the control gate electrode CG and the memory gate electrode MG that are not adjacent to each other.

  Further, the memory extension region ex1 of the nonvolatile memory cell NVM of the present embodiment is an n-type semiconductor region. The extension region ex2 is also an n-type semiconductor region at the location where the n-type MIS transistor is formed in the peripheral region Rp. Therefore, if these are formed in the same process, the manufacturing process of the semiconductor device can be further simplified. In the portion where the p-type MIS transistor is formed in the peripheral region Rp, a p-type semiconductor region may be formed as the extension region ex2 by another ion implantation process or the like. In the boundary region Rb, the memory extension region ex1 may be formed, the extension region ex2 may be formed, or none may be formed.

  Next, as shown in FIG. 17, for example, sidewall spacers sw are formed on the sidewalls of members that have a protruding shape on the main surface f1 of the silicon substrate 1, such as the control gate electrode CG and the memory gate electrode MG. The sidewall spacer sw in the present embodiment is assumed to have a three-layer structure in which a silicon oxide film sw1, a silicon nitride film sw2, and a silicon oxide film sw3 are formed in order from the side closer to the silicon substrate 1. The effect of applying such a three-layer structure as the sidewall spacer sw is as described above with reference to FIGS.

  Here, a silicon oxide film sw1, a silicon nitride film sw2, and a silicon oxide film sw1 are sequentially formed on the main surface f1 of the silicon substrate 1 by a CVD method or the like so as to cover the configuration formed in the above steps. To do. Thereafter, the formed film is etched back to form a sidewall spacer sw composed of the silicon oxide films sw1 and sw3 and the silicon nitride film sw2.

  Thereafter, in the main surface f1 of the silicon substrate 1, the memory source / drain region sd1 is formed in the memory region Rm, and the source / drain region sd2 is formed in the boundary region Rb and the peripheral region Rp, respectively, by ion implantation or the like. Here, the control gate electrode CG, the memory gate electrode MG, the charge storage insulating film IS, the side wall spacer sw, the first conductor film 4, the second conductor film 8, and the gate electrode which are already formed on the main surface f1 Ion implantation is performed on the main surface f1 using GE as an ion implantation mask. As a result, the memory source / drain region sd1 or the source / drain region sd2 is formed on the main surface f1 of the silicon substrate 1 in a portion not covered with any of the above elements. In particular, in the memory region Rm, the memory source / drain region sd1 is formed in the lower side of the side of the sidewall spacer sw that is not adjacent to the control gate electrode CG or the memory gate electrode MG.

  Further, the memory source / drain region sd1 of the nonvolatile memory cell NVM of the present embodiment is an n-type semiconductor region. And in the location which forms an n-type MIS transistor in the peripheral region Rp, the source / drain region sd2 is also an n-type semiconductor region. Therefore, if these are formed in the same process, the manufacturing process of the semiconductor device can be further simplified. Note that the n-type impurity concentration of the memory source / drain region sd1 and the source / drain region sd2 is higher than the n-type impurity concentration of the memory extension region ex1 and the extension region ex2. In addition, in a portion where the p-type MIS transistor is formed in the peripheral region Rp, a p-type semiconductor region may be formed as another source / drain region sd2 by another ion implantation process or the like. In the boundary region Rb, the memory source / drain region sd1 may be formed, the source / drain region sd2 may be formed, or neither of them may be formed.

  In view of the ion implantation process for forming the memory source / drain region sd1 and the like, it is more preferable to have the following conditions for the height of the memory gate electrode MG. That is, in the process of FIG. 12, the highest part of the height of the memory gate electrode MG viewed from the main surface f1 of the silicon substrate 1 is higher than the highest part of the height of the control gate electrode CG. More preferably, the memory gate electrode MG is formed by adjusting the etch back to the second conductor film 8 so as not to have a difference. The reason will be described below.

  As described above, the control gate electrode CG and the memory gate electrode MG are used as an ion implantation mask for the ion implantation height when the memory extension region ex1 and the memory source / drain region sd1 are formed, for example. In particular, the memory source / drain region sd1 has a higher impurity concentration and a deeper depth from the main surface f1 than the memory extension region ex1 and the like. Therefore, impurity ions accelerated with higher energy are implanted. At this time, if the height of the memory gate electrode MG is low, the function as an ion implantation mask becomes weak, impurities are introduced under the memory gate electrode MG, or the charge storage insulating film IS is damaged. I'll be relaxed.

  On the other hand, as shown in FIG. 12, the memory gate electrode MG is formed by etching back the second conductor film 8. At this time, since the control gate electrode CG and the memory gate electrode MG are electrically insulated by the charge storage insulating film IS, at least the second conductor film 8 covering the control gate electrode CG is completely removed. Therefore, the height of the memory gate electrode MG is almost the same as that of the control gate electrode CG, no matter how high. Therefore, in order to obtain a more effective structure as an ion implantation mask, the memory gate electrode MG of the present embodiment may be formed so that its height is approximately the same as the height of the control gate electrode CG. More preferred. As a result, a structure in which ion implantation into an unintended region and damage to the charge storage insulating film IS are unlikely to occur. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved. Although the upper limit of the height of the memory gate electrode MG is limited by the height of the control gate electrode CG, the height of the control gate electrode CG depends on the thickness of the first conductor film 4 in FIG. Can be controlled.

  Further, as described above, even if the height of the memory gate electrode MG is increased to the same level as that of the control gate electrode CG, the nonvolatile memory cell NVM of the present embodiment has a sidewall insulating film IW between them. Therefore, even if a conductor film such as a metal silicide is formed later, poor contact is unlikely to occur. Details of this point will be described later.

  In the next step, as shown in FIG. 18, a metal silicide layer SC is formed at a location where electrical connection is made from the outside among the components. As will be described in detail later, the metal silicide layer SC is formed in a self-aligned manner in the region of single crystal silicon or polycrystalline silicon exposed at this stage.

  On the other hand, there are places on the silicon substrate 1 where the metal silicide layer SC is not formed even if the silicon is exposed. Therefore, before forming the metal silicide layer SC, an insulating film mainly made of, for example, silicon oxide is formed as the silicide block layer sb and processed so as to cover a region where the metal silicide layer SC is not formed. For the processing, a photolithography method and an anisotropic etching method are used. Here, since the silicide block layer sb is removed by anisotropic etching, the silicide block layer sb remains on, for example, the sidewall of the sidewall spacer sw.

  After forming the silicide block layer sb as described above, the metal silicide layer SC is formed by the following process. For this, first, for example, a cobalt film is deposited on the main surface f1 of the silicon substrate 1 by a sputtering method so as to cover the structure formed by the above steps. Thereafter, heat treatment is performed. At this time, a compound reaction (silicide reaction) occurs at a portion where the semiconductor portion mainly composed of silicon such as single crystal silicon or polycrystalline silicon and the deposited cobalt film are in contact with each other, and metal silicide (cobalt silicide) is formed. It is formed. Thereafter, an extra cobalt film that has not become metal silicide is removed, thereby forming a metal silicide layer SC in a predetermined region. In addition, the metal film that is a target for forming the metal silicide by the silicide reaction may be, for example, a nickel film in addition to the cobalt film. In this case, the formed metal silicide layer SC is a nickel silicide layer.

  The region where the metal silicide layer SC is formed in this step is a place where the silicon and the cobalt film are in contact with each other. That is, in the memory region Rm, the metal silicide layer SC is formed on the upper surface of the control gate electrode CG, the upper surface of the memory gate electrode MG, and the surface of the memory source / drain region sd1. In the peripheral region Rp, a metal silicide layer SC is formed on the upper surface of the gate electrode GE and the surface of the source / drain region sd2. In the boundary region Rb, the metal silicide layer SC is formed on the upper surface of the first conductor film 4, the upper surface of the second conductor film 8, and the surface of the source / drain region sd2. Note that the metal silicide layer SC may or may not be formed in the boundary region Rb.

  Here, in the manufacturing process of the present embodiment, the sidewall insulating film IW is disposed on the sidewall of the control gate electrode CG so as to protrude from the upper surface thereof. Then, on the upper surface of the control gate electrode CG, the metal silicide layer SC is formed in a region surrounded by the sidewall insulating film IW. In other words, as compared with the structure in which only the charge storage insulating film IS is disposed between the control gate electrode CG and the memory gate electrode MG, the sidewall insulating film IW is disposed, thereby providing a more isolated region. A metal silicide layer SC can be formed. That is, a larger margin in the lateral direction can be obtained for a short circuit that may occur between the control gate electrode CG and the memory gate electrode MG. Thereby, contact failure between the control gate electrode CG and the memory gate electrode, which occurs during the process of forming the metal silicide layer SC, can be reduced. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved.

  The metal silicide layer SC is more preferably formed on the upper surface of the control gate electrode CG within a thickness range that does not exceed the height of the sidewall insulating film IW when viewed from the silicon substrate 1. The reason will be described below. In a silicide reaction that occurs at the contact surface between a metal film such as cobalt and silicon, metal silicide is formed so as to spread from the contact surface. Therefore, during the step of forming the metal silicide layer SC on the upper surface of the control gate electrode CG, the metal silicide layer SC is formed so as to grow to a position higher than the upper surface of the control gate electrode CG. At this time, as in the present embodiment, if the metal silicide layer SC is formed within a thickness range that does not exceed the sidewall insulating film IW, the metal silicide layer SC formed simultaneously on the upper surface of the memory gate electrode MG Can be prevented. In other words, in the metal silicide layer SC formed on the upper surfaces of the control gate electrode CG and the memory gate electrode MG, a margin for a short circuit caused by growth in the film thickness direction can be further increased. That is, even if the film thickness varies when the metal silicide layer SC is formed, a structure in which a contact failure between the control gate electrode CG and the memory gate electrode MG hardly occurs can be obtained. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved.

  Here, as described above with reference to FIGS. 5 and 10, the length of the sidewall insulating film IW protruding from the upper surface of the control gate electrode CG depends on the film thickness of the protective insulating film 5. In the present embodiment, the thickness of the protective insulating film 5 is set to 30 to 50 nm. Therefore, the protruding length of the sidewall insulating film IW after the removal of the protective insulating film 5 is also approximately 30 to 50 nm. According to the verification by the present inventor, under such conditions, even if the metal silicide layer SC is formed so as not to get over the sidewall insulating film IW, the thickness is sufficient as a low resistance layer. Therefore, it is possible to reduce the short-circuit failure between the control gate electrode CG and the memory gate electrode MG without causing a conduction failure of the metal silicide layer SC. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved.

  Through the above steps, the basic element configuration of the nonvolatile memory NVM is formed in the memory region Rm and the n-channel type MIS transistor Q1 is formed in the peripheral region Rp. Similarly, the dummy structure D1 is formed in the boundary region Rb.

  By the way, as in the steps described in FIGS. 9 to 11, the protective insulating film 5 formed on the upper surface of the control gate electrode CG is used as a pre-cleaning of the silicon substrate 1 before the charge storage insulating film IS is formed. It was removed by wet etching. As described above, the protective insulating film 5 was formed as an etching mask for the third anisotropic etching for processing the first conductor film 4 into the shape of the control gate electrode CG. Further, it has been described that it is more preferable to remove the protective insulating film 5 simultaneously with the pre-cleaning performed on the main surface f1 of the silicon substrate 1 in order to simplify the manufacturing process.

  On the other hand, as described with reference to FIG. 18, the metal silicide layer SC is formed on the upper surface of the control gate electrode CG. This is because the control gate electrode CG is electrically connected from the outside. Therefore, the protective insulating film 5 may be removed before the metal silicide layer SC is formed on the control gate electrode CG-like surface. Considering the above, the step of removing the protective insulating film 5 by wet etching is after the third anisotropic etching of FIG. 9 is finished and before the step of forming the metal silicide layer SC of FIG. In addition, it may be removed simultaneously with any pre-cleaning applied to the silicon substrate 1.

  For example, the protective insulating film 5 may be removed by the same method without removing the protective insulating film 5 in the step described with reference to FIG. In the process of FIG. 17, the memory source / drain region sd <b> 1 is formed on the main surface f <b> 1 of the silicon substrate 1. Thereafter, in the process of FIG. 18, the metal silicide layer SC is also formed on the main surface f1 of the silicon substrate 1 in the memory source / drain region sd1. Therefore, before the metal silicide layer SC is formed, it is necessary to perform precleaning as precleaning of the silicon substrate 1. The protective insulating film 5 may be removed at the same time as this pre-cleaning step.

  On the other hand, from the viewpoint of other elements formed on the silicon substrate 1, the step of removing the protective insulating film 5 is a step of processing and forming the control gate electrode CG as in the step of FIG. 10 (FIG. 9). It is more preferable that the step is performed before the step of forming the charge storage insulating film IS (FIG. 11). The reason will be described below.

  In the present embodiment, various elements are formed on the silicon substrate 1 in addition to the nonvolatile memory cell NVM and the MIS transistor Q1. One of them is a capacitive element C1 formed in the capacitive region Rc on the silicon substrate 1 as shown in the manufacturing process in FIGS. FIG. 19 is a cross-sectional view of the principal part in the capacitance region Rc on the silicon substrate 1 in the same process as FIG. 9 among the processes following FIG. FIG. 20 is a cross-sectional view of the principal part in the capacitance region Rc in the same process as FIG. 11 in the processes following FIG.

  Here, the normal capacitive element is formed by, for example, a configuration in which a semiconductor region, an insulating film, an electrode material, and the like in the silicon substrate 1 are combined. On the other hand, in the manufacturing process of the semiconductor device having the nonvolatile memory cell NVM according to the present embodiment, the charge storage insulating film IS including the first conductor film 4 serving as the control gate electrode CG and the three insulating films s1 to s3. And the second conductor film 8 to be the memory gate electrode MG is used. Therefore, by forming the capacitive element C1 using these materials, it is possible to form the capacitive element C1 having characteristics different from those of a normal capacitive element.

  Similar to the process of forming the control gate electrode CG according to FIGS. 4 to 9, the first capacitor electrode EC1 made of the first conductor film 4 as shown in FIG. 19 is formed. Thereafter, in the same manner as in the process of FIG. 11, the charge storage insulating film IS made of the first to third insulating films s1 to s3 is formed, and the second capacitor electrode EC2 made of the second conductor film 8 is formed thereon. Form. Thus, the capacitor element C1 having a structure in which the charge storage insulating film IS is sandwiched between the first capacitor electrode EC1 made of the first conductor film 4 and the second capacitor electrode EC2 made of the second conductor film 8 can be formed. it can. In terms of structure, the capacitive element EC1 includes a sidewall insulating film IW on the side surface of the first capacitive electrode EC1. In this regard, the present inventor has verified that the area of the charge storage region that determines the electric capacity is mainly the area of the upper surface of the first capacitor electrode EC1, and therefore the influence of the sidewall insulating film IW on the characteristics is small. is doing.

  Here, when the first conductor film 4 is processed by the process of FIG. 9 to form the first capacitor electrode EC1, the protective insulating film 5 is formed on the upper surface. Accordingly, the protective insulating film 5 is also formed on the upper surface of the first capacitor electrode EC1 in FIG. Since this protective insulating film 5 is formed to have a thickness of about 30 to 50 nm in this embodiment, it becomes a silicon oxide film having a thickness that cannot be ignored as a capacitive film. Therefore, in order to form the capacitive element C1 having realistic characteristics, after forming the first capacitive electrode EC1 in the process of FIG. 19, the charge storage insulating film IS and the second capacitive electrode EC2 are formed in the process of FIG. Before this, the protective insulating film 5 needs to be removed. For the above reasons, in the manufacturing process of the present embodiment, after the third anisotropic etching in the step of FIG. 9 is finished, before the charge storage insulating film IS in FIG. More preferably, the protective insulating film 5 is removed. Thereby, the capacitive element C1 having characteristics independent of other capacitive elements can be formed on the silicon substrate 1. As a result, the performance of the semiconductor device including the nonvolatile memory can be improved.

  Next, as shown in FIG. 21, an etching stop insulating film IB and an interlayer insulating film IL are sequentially deposited on the main surface of the silicon substrate 1 so as to cover the structure formed by the above steps. The interlayer insulating film IL is an insulating film for insulating conductor plugs and conductor wirings to be formed later from each other, and is formed thick enough to embed a configuration such as the nonvolatile memory NVM and the MIS transistor Q1. As such an interlayer insulating film IL, a silicon oxide film is formed by a CVD method or the like. In addition, when the contact hole CH is formed in the interlayer insulating film IL in a later process, the etching stop insulating film IB is formed in order to process in a self-aligned manner by applying a so-called SAC technique. Details are described below.

  In the subsequent process, contact holes CH are formed in the interlayer insulating film IL by photolithography or anisotropic etching. The contact hole CH is a conduction hole for forming an electrical connection to each element formed on the silicon substrate 1. Therefore, the contact hole CH is formed so as to open the upper part of the metal silicide layer SC formed in the step of FIG. At this time, the removal of the interlayer insulating film IL by anisotropic etching needs to be stopped when the metal silicide layer SC is reached. As the anisotropic etching damage to the metal silicide layer SC is increased, the subsequent conduction failure is more likely to occur.

  Therefore, as the base film of the interlayer insulating film IL, an insulating film having a slow removal rate in the interlayer insulating film IL in this anisotropic etching is formed as the etching stop insulating film IB. Thereby, the removal of the interlayer insulating film IL by the anisotropic etching stops in a self-aligned manner when reaching the etching stop insulating film IB. Thereafter, anisotropic etching is performed under conditions with a high selection ratio with respect to the etching stop insulating film IB, and by removing the etching stop insulating film IB, the upper portion of the metal silicide layer SC can be opened. Since this etching stop insulating film IB is thinner than the interlayer insulating film IL, the influence of overetching on the metal silicide layer SC can be reduced. As such an etching stop insulating film IB, a silicon nitride film is formed by a CVD method or the like.

  Next, as shown in FIG. 22, the contact plug CP is formed by filling the contact hole CH with a conductor such as a tungsten film. For this, first, a tungsten film is formed on the silicon substrate 1 by sputtering or the like. Then, the contact plug CP is formed by removing the excess tungsten film by etching or CMP. Note that, for example, titanium nitride may be formed as the barrier film before depositing the tungsten film (not shown).

  Thereafter, an insulating film IM made of a silicon oxide film is formed on the interlayer insulating film IL by a CVD method or the like. Subsequently, a wiring pattern hole MH is formed in the insulating film IM by photolithography or anisotropic etching. Thereafter, the wiring pattern hole MH is filled with a conductor such as aluminum or copper to form the wiring WM. Such a wiring WM is formed in the wiring pattern hole MH in the same manner as the contact plug CP formed in the contact hole CH. The wiring WM is formed so as to be electrically connected to the contact plug CP. Further, a multilayer wiring is formed in the upper layer of the insulating film IM by repeatedly forming a similar interlayer insulating film IL, contact plug CP (also referred to as via plug), insulating film IM, wiring WM, and the like (illustrated). do not do). With these electrical wiring mechanisms, power can be supplied to the nonvolatile memory NVM, the MIS transistor Q1, and the like.

  As described above, a semiconductor device having the nonvolatile memory cell NVM having the structure described with reference to FIGS. 1 and 2 can be manufactured. As a result, the reliability of a semiconductor device including a nonvolatile memory can be further improved. In addition, in description of said manufacturing process, about description of the effect by having the component formed in each process, and description of the effect by having said structure, it is the structure using the said FIGS. 1-2. Items that overlap with the description are omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied, for example, to the semiconductor industry necessary for performing information processing in personal computers, mobile devices, and the like.

It is principal part sectional drawing of the semiconductor device which is one embodiment of this invention. FIG. 2 is an enlarged view of a main part of the semiconductor device shown in FIG. 1. FIG. 2 is an explanatory diagram for explaining electrical characteristics of the semiconductor device shown in FIG. 1. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 17; FIG. 10 is another cross-sectional view of the main part in the same process as FIG. 9 during the manufacturing process of the semiconductor device following FIG. 8; FIG. 12 is another cross-sectional view of the main part in the same process as FIG. 11 during the manufacturing process of the semiconductor device following FIG. 10; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; It is principal part sectional drawing of the semiconductor device which this inventor examined.

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
2 Separating part 3 Gate insulating film 4 First conductor film 5 Protective insulating film 6, 9, 10 Photoresist film 7 Protective film 8 Second conductor film C1 Capacitance element CG Control gate electrode (first gate electrode)
CH contact hole CP contact plug D1 dummy structure EC1 first capacitor electrode EC2 second capacitor electrode ex1 memory extension region ex2 extension region f1 main surface GE gate electrode IB etching stop insulating film IG control gate insulating film (first gate insulating film)
IL Interlayer insulating film IM Insulating film IS Charge storage insulating film IW Side wall insulating film MG Memory gate electrode (second gate electrode)
MH wiring pattern hole NVM nonvolatile memory cell pw1 p-type memory well pw2, pw3 p-type well Q1 MIS transistor Rb boundary region Rc capacitance region Rm memory region Rp peripheral region s1 first insulating film s2 second insulating film s3 third insulating film sb silicide block layer SC metal silicide layer sd1 memory source / drain region sw sidewall spacer sw1, sw3 silicon oxide film sw2 silicon nitride film Vcg control gate voltage Vd drain voltage Vmg memory gate voltage Vs source voltage WM wiring

Claims (18)

(A) a first gate electrode formed on the main surface of the semiconductor substrate;
(B) a first gate insulating film formed between the semiconductor substrate and the first gate electrode;
(C) a second gate electrode formed on the main surface of the semiconductor substrate so as to be adjacent to the side of the first gate electrode;
(D) a charge storage insulating film integrally formed between the semiconductor substrate and the second gate electrode and between the first gate electrode and the second gate electrode;
(E) a metal silicide layer formed on upper surfaces of the first gate electrode and the second gate electrode;
(F) Between the first gate electrode and the charge storage insulating film so as to integrally cover the side surface of the first gate electrode and the side surface of the metal silicide layer on the upper surface of the first gate electrode. And a sidewall insulating film formed on
The first gate electrode and the second gate electrode are electrically insulated from each other by being disposed across the charge storage insulating film and the sidewall insulating film,
The semiconductor device, wherein the metal silicide layer on the upper surface of the first gate electrode and the metal silicide layer on the upper surface of the second gate electrode are electrically insulated from each other by the sidewall insulating film. The semiconductor device according to claim 1,
The side wall insulating film is formed on a side surface of the first gate electrode so as not to reach a contact point with the first gate insulating film which is a lower end of the first gate electrode. . The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the sidewall insulating film is formed so as to protrude to a position higher than the metal silicide layer when viewed from the semiconductor substrate. The semiconductor device according to claim 3.
The semiconductor device according to claim 1, wherein the sidewall insulating film is an insulating film mainly composed of a silicon nitride film. The semiconductor device according to claim 4.
The height of the first gate electrode and the height of the second gate electrode viewed from the semiconductor substrate are not different from each other in comparison with the height of the highest portion. apparatus. The semiconductor device according to claim 5.
The semiconductor device according to claim 1, wherein the second gate electrode is arranged adjacent to one of the side walls of the first gate electrode. The semiconductor device according to claim 6.
The charge storage insulating film includes a first insulating film, a second insulating film, and a third insulating film,
The first insulating film and the third insulating film are insulating films mainly composed of silicon oxide,
The second insulating film is an insulating film mainly composed of silicon nitride,
The second insulating film is disposed so as to be sandwiched between the first insulating film and the third insulating film,
A semiconductor device, wherein the first insulating film, the second insulating film, and the third insulating film are arranged in this order from the side closer to the semiconductor substrate. (A) forming a first gate insulating film on the main surface of the semiconductor substrate;
(B) forming a first gate electrode disposed on the main surface of the semiconductor substrate via the first gate insulating film and having a protective insulating film on the upper surface and a sidewall insulating film on the side surface;
(C) removing the protective insulating film;
(D) forming a second gate electrode on the main surface of the semiconductor substrate via a charge storage insulating film;
(E) forming a metal silicide layer on top surfaces of the first gate electrode and the second gate electrode;
The sidewall insulating film in the step (b) is integrally disposed from the side surface of the first gate electrode to the side surface of the protective insulating film,
The step (c) is performed after the step (b) and before the step (e),
The second gate electrode formed in the step (d) is disposed adjacent to the side of the first gate electrode,
The charge storage insulating film formed in the step (d) is integrally formed from between the semiconductor substrate and the second gate electrode to between the first gate electrode and the second gate electrode. Arranged,
The second gate electrode formed in the step (d) is disposed with the first gate electrode separated from the charge storage insulating film and the sidewall insulating film,
In the step (e),
The metal silicide layer on the upper surface of the first gate electrode and the metal silicide layer on the upper surface of the second gate electrode are formed so as to be electrically insulated from each other by the sidewall insulating film. Production method. The method of manufacturing a semiconductor device according to claim 8.
The step (b)
(B1) forming a first conductor film and the protective insulating film in order so as to cover the first gate insulating film;
(B2) forming a photoresist film on the protective insulating film;
(B3) removing the protective insulating film in a region that is not planarly covered with the photoresist film by performing first anisotropic etching using the photoresist film as an etching mask;
(B4) The second anisotropic etching is performed using the photoresist film as an etching mask, so that the first conductor film in a region not covered in a plane by the photoresist film is in the middle of the thickness direction. Removing the process,
(B5) forming the sidewall insulating film so as to integrally cover the side surface of the protective insulating film and the side surface of the first conductor film, which are generated by the steps (b3) and (b4);
(B6) A region of the first conductor film that is not covered by either the protective insulating film or the sidewall insulating film is removed by third anisotropic etching, thereby removing the first conductive film from the first conductive film. Forming the first gate electrode,
The sidewall insulating film is formed by the steps (b1) to (b6) so as not to reach a contact point with the first gate insulating film which is the lower end of the first gate electrode on the side surface of the first gate electrode. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device. In the manufacturing method of the semiconductor device according to claim 9,
In the step (e),
The metal silicide layer is formed on the upper surface of the first gate electrode within a thickness range that does not exceed the height of the sidewall insulating film when viewed from the semiconductor substrate. Production method. The method of manufacturing a semiconductor device according to claim 10.
In the step (b1), an insulating film having a lower removal rate than the first conductor film is formed as the protective insulating film with respect to the third anisotropic etching in the step (b6).
In the step (b5), an insulating film having a removal rate slower than that of the first conductor film is formed as the sidewall insulating film with respect to the third anisotropic etching in the step (b6).
In the step (b6), by performing the third anisotropic etching using the protective insulating film and the sidewall insulating film as an etching mask, the protective insulating film and the sidewall insulating film of the first conductor film A method of manufacturing a semiconductor device, wherein a region not covered with any of the above is removed to form the first gate electrode. The method of manufacturing a semiconductor device according to claim 11.
In the step (c), the protective insulating film is removed by wet etching,
In the step (b1), an insulating film having a higher removal rate than the sidewall insulating film is formed as the protective insulating film with respect to the wet etching in the step (c). . In the manufacturing method of the semiconductor device according to claim 12,
In the step (b1), an insulating film mainly composed of silicon oxide is formed as the protective insulating film,
In the step (b5), an insulating film mainly composed of silicon nitride is formed as the sidewall insulating film. 14. The method of manufacturing a semiconductor device according to claim 13,
In the step (b1), as the protective insulating film, an insulating film mainly composed of silicon oxide is formed by chemical vapor deposition containing ozone as one of the raw materials, and after the formation, the protective film is formed in the step (c). A method for manufacturing a semiconductor device, wherein heat treatment is not performed until the insulating film is removed. 15. The method of manufacturing a semiconductor device according to claim 14,
The method (c) is performed after the step (b) and before the step (d). In the manufacturing method of the semiconductor device according to claim 15,
In the step (d), the highest portion of the height of the second gate electrode viewed from the semiconductor substrate has a difference in height compared to the highest portion of the height of the first gate electrode. A method of manufacturing a semiconductor device, wherein the second gate electrode is formed. In the manufacturing method of the semiconductor device according to claim 16,
In the step (d), the second gate electrode is disposed so as to be adjacent to one of the side walls of the first gate electrode. . The method of manufacturing a semiconductor device according to claim 17.
In the step (d),
As the charge storage insulating film, a first insulating film, a second insulating film, and a third insulating film are sequentially formed from the side closer to the semiconductor substrate,
Forming an insulating film mainly composed of silicon oxide as the first insulating film and the third insulating film;
Forming an insulating film mainly composed of silicon nitride as the second insulating film;
The method of manufacturing a semiconductor device, wherein the second insulating film is disposed so as to be sandwiched between the first insulating film and the third insulating film.

Images