JP2005294392A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which can improve the writing speed of data. <P>SOLUTION: The nonvolatile semiconductor storage device is provided with a memory array where a plurality of memory cells each enabling electrical update of information are arranged. This memory cell comprises a semiconductor substrate, an element isolating region formed on the semiconductor substrate, an element region divided with the element isolating region, a first insulating film formed on the element region, a floating gate formed on the first insulating film, a second insulating film formed on the floating gate and has the dielectric constant which is higher than that of a silicon nitride film, and a control gate formed on the second insulating film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  In the nonvolatile semiconductor device, a first gate insulating film is formed on a silicon substrate, a charge storage layer (floating gate) is formed on the first gate insulating film, and a second gate insulating film is formed on the charge storage layer. And a control gate is formed on the second gate insulating film.

  In this nonvolatile semiconductor device, in order to write data, for example, a positive voltage is applied to the control gate and the drain region, and the substrate and the source region are grounded. Then, electrons are injected into the charge storage layer, and the threshold voltage of the control gate changes. Thereby, “0” or “1” is distinguished.

In order to write data at high speed, it is necessary to apply a high voltage to the charge storage layer (floating gate) at the time of data writing, but with the recent miniaturization and low operation voltage, the applied voltage decreases, There is a problem that the writing speed becomes slow.
Japanese Patent Laid-Open No. 10-022403

  An object of the present invention is to provide a nonvolatile semiconductor memory device capable of increasing the data writing speed.

  A nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, an element isolation region formed on the semiconductor substrate, an element region partitioned by the element isolation region, and a first insulation formed on the element region. A film, a floating gate formed on the first insulating film, a second insulating film formed on the floating gate and having a dielectric constant higher than that of a silicon nitride film, and the second insulating film A memory cell array having a control gate formed thereon and in which a plurality of electrically rewritable memory cells are arranged.

  According to the present invention, the data writing speed can be increased.

  FIG. 1 is a plan view of a NAND type EEPROM according to an embodiment of the present invention.

  FIG. 2 is an equivalent circuit diagram of the NAND type EEPROM.

  As shown in FIG. 1, a plurality of bit lines BL1 to BL3 are arranged in parallel with each other and extending in the vertical direction in the drawing.

  In the lower part of the figure, the source line SL is arranged extending in the horizontal direction in the figure.

  A plurality of memory cells (transistors) M1 (1) to M1 (n) are connected in series between the bit line BL1 and the source line SL. Similarly, the plurality of memory cells M2 (1) to M2 (n) are between the bit line BL2 and the source line SL, and the plurality of memory cells M3 (1) to M3 (n) are the bit line BL3 and the source line SL. Are connected in series (see FIG. 2).

  Each of the memory cells M1 (1) to M3 (n) has a charge storage layer (floating gate) (shaded portion in the figure) for storing charges and a control gate (described later) for controlling the amount of charge injected into the charge storage layer. A stacked gate structure including:

  The charge storage layers in the memory cells M1 (1) to M3 (n) are in a floating state. In addition, the control gates in the memory cells M1 (1) to M3 (n) are integrally formed as a plurality of word lines (gate lines) WL1 to WLn that are arranged to intersect the bit lines BL1 to BL3.

  One end of selection gates S1 (1) to S1 (3) as switching transistors is connected to one side of the memory cells M1 (1), M2 (1), and M3 (1). The other end of S1 (3) is connected to the bit lines BL1 to BL3 via the bit line contact portion BC, respectively.

  Further, one end of the selection gates S2 (1) to S2 (3) as switching transistors is connected to one side of the memory cells M1 (n), M2 (n), and M3 (n), and each selection gate S2 (1 ) To S2 (3) are connected to source lines SL1 to SL3 through source line contact portions (not shown), respectively.

  Switching control of the selection gates S1 (1) to S1 (3) is performed by the selection gate line SG1, and switching control of the selection gates S2 (1) to S2 (3) is performed by the selection gate line SG2.

  3 is a cross-sectional view taken along line B1-B2 of FIG.

  4 is a cross-sectional view taken along line A1-A2 of FIG.

  As shown in FIG. 4, a gate oxide film 2 and a first charge storage layer 3 made of, for example, polysilicon are formed on a p-type silicon substrate 1, for example. A trench 6 penetrating the surface of the silicon substrate 1 downward from the surface of the first charge storage layer 3 is formed.

  An insulating film is buried inside the trench 6, thereby forming a buried element isolation region (STI) 7 a. A region of the substrate 1 between the STIs 7a is an element region.

  As shown in FIG. 3, source / drain regions 12 are formed on the surface of the element region. The gate oxide film 2 and the first charge storage layer 3 are formed between the source / drain regions 12. A second charge storage layer 8 made of, for example, polysilicon is formed on the first charge storage layer 3.

A ferroelectric film 9 is formed as an insulating film on the second charge storage layer 8. The ferroelectric film 9 is made of a material having a dielectric constant higher than that of silicon nitride, such as TaO ₂ , HfO ₂ —SiO _2, or Al ₂ O ₃ .

  A control gate 10 made of, for example, polysilicon is formed on the ferroelectric film 9.

  On the surface of the control gate 10, the ferroelectric film 9, the first and second charge storage layers 3 and 8, the gate oxide film 2 and the substrate 1, an insulating film 13 made of, for example, silicon oxide is formed, and the stacked gate is formed. An insulating film 14 made of, for example, silicon oxide is formed on the surface of the insulating film 13 on the side wall.

  An insulating film 15 made of, for example, silicon oxide is formed on the insulating films 13 and 14, and an insulating film 16 is formed in a groove formed by the insulating film 15. A metal wiring (bit line) 17 is formed on the insulating films 15 and 16.

  As shown in FIG. 3, in the present embodiment, as described above, a ferroelectric film is used as an insulating film between the first and second charge storage layers 3 and 8 and the control gate 10. 9 is provided. As a result, during the write operation, the potentials of the first and second charge storage layers 3 and 8 can be increased, thereby enabling high-speed writing. This will be explained in more detail below.

FIG. 5 is a diagram schematically showing an equivalent circuit diagram between the control gate 10 and the substrate 1 when the voltage V _CG is applied to the control gate 10 of FIG. 3 and the voltage V _sub is applied to the substrate 1. .

The capacitance C ₁ is the capacitance of the ferroelectric film 9, and the capacitance C ₂ is the capacitance of the gate oxide film 2. The potential V ₁ is the potential of the first and second charge storage layers 3 and 8 (the potential difference between the first and second charge storage layers 3 and 8 is small and is ignored).

In order to increase the writing speed, it is necessary to increase the potential V ₁ when a voltage is applied to the control gate 10.

Here, the potential V ₁ is expressed by the following (formula 1). However, V _sub = 0 is assumed. V ₁ = C ₁ / (C ₁ + C ₂ ) × V _CG (Formula 1)
In general, the capacity C is expressed by the following (Formula 2).

C = εS / d (S: area, d: film thickness, ε: dielectric constant) (Formula 2)
From (Equation 1), it can be seen that the larger potential C ₁ is, the larger potential V ₁ can be obtained.

Here, conventionally, a silicon oxide film or an ONO film (oxide film-nitride film-oxide film) is particularly used as an insulating film between the first and second charge storage layers 3, 8 and the control gate 10. It was. However, with the decrease of the voltage V _CG, it is as described in the Background section is the potential V ₁ is also a problem of reduction.

Here, for example, when a silicon oxide film is used as the insulating film, it is conceivable to increase the cross-sectional area S of the silicon oxide film, for example, from (Equation 2) in order to suppress the decrease in the potential V _1. Is contrary to miniaturization. In addition, for example, it is conceivable to reduce the thickness d of the silicon oxide film, but this has a problem of causing a retention failure (deterioration of charge retention characteristics).

Therefore, the inventor has conceived of using the ferroelectric film 9 having a dielectric constant ε higher than that of the silicon nitride film as the insulating film. By using this ferroelectric film 9 as an insulating film, it is possible to increase the film capacity without violating the miniaturization of the element and without causing a retention failure, that is, without causing a new problem. It was found that the potential V ₁ can be kept high.

  6 to 8 are cross-sectional views showing manufacturing steps of the NAND type EEPROM shown in FIG.

  6 shows a manufacturing process viewed from a direction perpendicular to the cross section taken along line A1-A2 of FIG. 1, and FIGS. 7 and 8 are views seen from a direction perpendicular to the cross section taken along line B1-B2 of FIG. The manufacturing process subsequent to 6 will be described.

  First, as shown in FIG. 6A, after an impurity for controlling the threshold voltage of the control gate is implanted into the channel region on the surface of the p-type semiconductor substrate 1 by a well-known method, the gate is formed on the semiconductor substrate 1. An oxide film 2 is formed. Next, for example, by CVD (Chemical Vapor Deposition), a first charge storage layer (floating gate) 3 made of, for example, polysilicon, and a silicon nitride film 4 as a stopper in the later-described CMP are formed on the gate oxide film 2. Are sequentially deposited. Next, a photoresist is applied on the silicon nitride film 4 and baked, and a photomask pattern 5 for forming STI (Shallow Trench Isolation) is formed by using a photolithography technique.

  Next, as shown in FIG. 6B, by using an etching technique such as reactive ion etching (RIE), the silicon nitride film 4, the first charge storage layer 3, and the gate oxide film are used. 2 and the semiconductor substrate 1 are sequentially etched to form a trench 6. Next, an insulating film 7 made of, for example, a silicon oxide film is deposited on the entire surface of the substrate by a CVD method, and the insulating film 7 is embedded in the trench 6 to form an STI 7a. Next, the insulating film 7 is planarized by CMP using the silicon nitride film 4 as a stopper.

Next, as shown in FIG. 6C, the silicon nitride film 4 as a stopper is removed, and the protruding insulating film 7 is moved back to the surface of the first charge storage layer 3 by wet etching. Next, a second charge storage layer (floating gate) 8 made of, for example, polysilicon is deposited by CVD, and the second charge storage layer 8 is processed using RIE or the like. Next, a ferroelectric film 9 is deposited on the surfaces of the STI 7a and the second charge storage layer 8 by a CVD method. As a material of the ferroelectric film 9, a substance having a dielectric constant higher than that of silicon nitride, such as TaO ₂ , HfO ₂ —SiO _2, or Al ₂ O ₃ is used. Next, a control gate material 10 made of, for example, polysilicon is deposited on the ferroelectric film 9, and a photoresist pattern 11 is formed on the control gate material 10.

  FIG. 7A shows the substrate in the state of FIG. 6C viewed from a direction perpendicular to the cross section taken along line B1-B2 of FIG.

  Next, as shown in FIG. 7B, using the photomask pattern 11, the control gate 10, the ferroelectric film 9, the second charge storage layer 8, the first charge storage layer 3, and the gate oxide film 2 is etched by the RIE method. Then, using the control gate 10 as a mask, adjacent impurities are ion-implanted into the surface region of the semiconductor substrate 1 to form source / drain regions 12.

  Next, as shown in FIG. 7C, an insulating film 13 made of, for example, silicon oxide is deposited, and further, an insulating film 14 made of, for example, silicon nitride or silicon oxide is deposited.

  Next, as shown in FIG. 8A, after processing the insulating film 14 by RIE or the like, an insulating film 15 made of, for example, silicon nitride is deposited on the surfaces of the insulating films 13 and 14.

  Next, as shown in FIG. 8B, for example, an insulating film 16 made of silicon oxide is deposited by CVD, and the surface of the insulating film 16 is planarized by CMP using the insulating film 15 as a stopper. Thereafter, a bit line contact is formed, and a metal wiring (bit line) 17 made of, for example, aluminum is formed on the insulating films 15 and 16.

  In the above-described example, the memory cell applied to the NAND-type EEPROM has been described. However, this memory cell is applicable not only to the NAND-type but also to the NOR-type, for example.

  FIG. 9 is a plan view of a NOR type EEPROM according to another embodiment of the present invention.

  FIG. 10 is an equivalent circuit diagram of a portion T (four memory cells) surrounded by a dotted line in FIG.

  11 is a cross-sectional view (memory cell cross-sectional view) taken along line C1-C2 of FIG.

  As shown in FIG. 9, memory cells M11 (1) to M14 (6) are arranged in a matrix.

  As shown in FIG. 10 showing an equivalent circuit of a portion T indicating four memory cells, one memory cell M11 (1) is provided between the bit line BL10 and a source line SL10 extending in a direction orthogonal to the bit line BL10. Is connected. Similarly, the memory cell M12 (1) is connected between the bit line BL10 and the source line SL11, the memory cell M11 (2) is connected between the bit line BL11 and the source line SL10, and the bit line BL11 and the source are connected. Memory cell M12 (2) is connected between line SL11. A common gate line CG10 is connected to the memory cells M11 (1) and M11 (2), and a common gate line CG11 is connected to the memory cells M12 (1) and M12 (2) (see FIG. 9).

  As shown in FIG. 9, a plurality of gate lines CG9 to CG13 extend in the vertical direction in the drawing and are arranged in parallel to each other.

  On one side of the gate lines CG9 to CG13, source lines SL10 to S12 are arranged in parallel with the gate lines CG9 to CG13.

  A bit line contact portion BC is formed on the other side of the gate lines CG9 to CG13.

  Each memory cell M11 (1) to M14 (6) is connected to a bit line (not shown) (see FIGS. 10 and 11) via a bit line contact portion BC.

  As shown in FIG. 11 showing a cross section of the memory cell, for example, source / drain regions 22 are formed in a surface region of a p-type semiconductor substrate 21 at a predetermined interval. The source / drain regions 22 correspond to, for example, first and second impurity diffusion regions.

  A gate oxide film 23 made of, for example, silicon oxide is formed on the semiconductor substrate 21.

  On the gate oxide film 23 between the source / drain regions 22, a first charge storage layer (floating gate) 24 made of, for example, polysilicon is formed.

  A ferroelectric film 25 made of a material having a dielectric constant higher than that of silicon nitride is formed on the first charge storage layer 24.

  On the ferroelectric film 25, for example, a control gate 27 composed of two layers of an amorphous silicon layer 26a and a tungsten layer 26b is formed.

  A first interlayer insulating film 28 made of, for example, silicon oxide is formed so as to cover the control gate 27, and the first and second layers leading to the source / drain region 22 from the surface of the first interlayer insulating film 28 to the inside. Holes 29a and 29b are formed.

  First and second barrier metals 30a and 30b made of, for example, titanium nitride are formed on inner walls of the first and second holes 29a and 29b, and first and second plugs made of, for example, tungsten are formed inside the first and second holes 29a and 29b. 31a and 31b are formed.

  A second interlayer insulating film 32 is formed on the first interlayer insulating film 28, the first and second plugs 31a and 31b, and the first and second barrier metals 30a and 30b.

  A third hole 33 leading to the first plug 31 from the surface of the second interlayer insulating film 32 to the inside is formed, and a third barrier metal 34 is formed on the inner wall of the third hole 33, A third plug 35 is formed inside.

  On the second interlayer insulating film 32, the third plug 35 and the third barrier metal 34, for example, a bit line electrode 39 having a laminated structure of a Ti / TiN film 36, an Al—Cu film 37 and a TiN film 38 is formed. Is done.

1 is a plan view of a NAND type EEPROM according to an embodiment of the present invention. It is an equivalent circuit diagram of this NAND type EEPROM. It is sectional drawing in the B1-B2 line | wire of FIG. It is sectional drawing in the A1-A2 line | wire of FIG. FIG. 4 is a diagram schematically showing an equivalent circuit diagram between the control gate and the substrate when voltages are respectively applied to the control gate and the substrate of FIG. 3. FIG. 7 is a cross-sectional view showing a manufacturing process of the NAND-type EEPROM of FIG. 1. FIG. 7 is a manufacturing process sectional view following FIG. 6; FIG. 8 is a manufacturing process sectional view following FIG. 7; It is a top view of the NOR type EEPROM according to another embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a NOR type EEPROM in a portion T (four memory cells) surrounded by a dotted line in FIG. 1. It is sectional drawing in the C1-C2 line | wire of FIG.

Explanation of symbols

1 Semiconductor substrate 2 Gate oxide film (tunnel insulating film)
3 First charge storage layer (first floating gate)
7a Element isolation region 8 Second charge storage layer (second floating gate)
9 Ferroelectric film 10 Control gate 12 Source / drain region 17 Metal lines BL1 to BL3 Bit lines SG1 to SG2 Select lines SL, SL10 to SL12 Source lines WL1 to WLn Word lines (gate lines)
CG9 to CG13 Gate line BC Bit contacts M1 (1) to M3 (n), M11 (1) to M14 (6) Memory cells

Claims (4)

A semiconductor substrate;
An element isolation region formed in the semiconductor substrate;
An element region partitioned by the element isolation region;
A first insulating film formed on the element region;
A floating gate formed on the first insulating film;
A second insulating film formed on the floating gate and having a dielectric constant higher than that of the silicon nitride film;
A control gate formed on the second insulating film;
A nonvolatile semiconductor memory device including a memory cell array in which a plurality of electrically rewritable memory cells are arranged.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the second insulating film includes an oxide of at least one metal selected from the group consisting of Ta, Hf, and Al.   3. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array includes a NAND type memory cell array in which a plurality of the memory cells are connected in series between a bit line and a source line. .   3. The NOR memory cell according to claim 1, wherein the memory cell includes a NOR type memory cell in which a source line and a bit line are connected to first and second impurity diffusion regions adjacent to a channel region in the element region. The nonvolatile semiconductor memory device described.

Images