JP2009223455A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a program floating time in a multi-processor system. <P>SOLUTION: This multiprocessor system includes a common control part for storing a program and a plurality of individual control parts for acquiring and executing each program from the common control part through an inter-processor bus. The processor of the common control part reads out a program stored in the program memory of the common control part on the basis of a program loading request from the individual control part, and the address conversion part of the common control part acquires a program which is output from the program memory of the common control part, and converts the address of the program into a loading exclusive address, and outputs the program of the exclusive address to the inter-processor bus, and the loading control part of the individual control part monitors the inter-processor bus whose program loading request has been made, and when detecting the exclusive address in the inter-processor bus, and acquires the program of the exclusive address, and stores it in the local memory of the individual control part. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multiprocessor system, and more particularly to initial program loading in a multiprocessor system including a common control unit having a processor (MPU) and a plurality of individual control units each having an MPU.

  For example, a multiprocessor system, which is a base station device in wireless communication, includes a plurality of individual control card units for each individual function such as an in-device monitoring card, a user data processing card unit, and a control data card unit, and the plurality of individual control card units. And a common control card unit for monitoring and controlling (hereinafter, the card unit is referred to as a card). The common control card and each individual control card each have a processor (MPU), and each function is realized by executing a program stored in each card.

  The programs and system data of each card are stored in a predetermined memory of the common control card at the time of initial startup, and the programs and system data are loaded from the common control card to each individual control card according to a predetermined loading procedure. And stored in the MPU memory of each individual control card (Patent Documents 1 to 3). Also for the common control card, the program and system data are loaded into the MPU memory of the common control card. This program loading is performed not only at the initial startup, but also when the card is reset, such as when adding a card or replacing a failed card.

  FIG. 1 is a diagram showing a configuration example of a common control card and an individual control card in a conventional multiprocessor system. The multiprocessor system includes a common control card 10 and a plurality of individual control cards 20-0 to 20-n (collectively referred to as individual control card 20 when each individual control card is not distinguished). The common control card 10 includes an MPU 11, a local memory 12, a boot memory 13, a common function processing unit 14, a global bus interface (hereinafter referred to as “IF”) 15, a global bus arbitration unit 16, a memory IF 17, and system data. A memory 18 is provided.

  The local memory 12 is a working memory used when executing the program of the MPU 11. The boot memory 13 stores an initial program required when the MPU 11 is started up, and the common function processing unit 14 is a logic circuit that performs processing unique to common control, and also has a memory area. The global bus IF 15 is an inter-processor bus IF with the individual control card 20, and the global bus arbitration unit 16 manages the access right from each individual control card 20 to the common control card 10, as will be described later. The memory IF 17 is an IF between the MPU 12 and the system data memory 18.

  The individual control card 20 includes an MPU 21, a local memory 22, a boot memory 23, an individual function processing unit 24, and a global bus IF 25. The local memory 22 is a working memory used when the MPU 21 executes a program. The boot memory 23 stores an initial program required when the MPU 21 is started up, and the individual function processing unit 24 is a logic circuit that performs processing unique to individual control, and also has a memory area. The global bus IF 25 is an inter-MPU bus IF with the common control card 10.

  System data, a program for the common control card, and a program for each individual control card (hereinafter may be collectively referred to as “program”) are collectively stored in the system data memory 18, and the system is loaded by program loading. The program stored in the data memory 18 is transferred to and stored in the local memories 12 and 22 of the common control card and each individual control card, respectively. Of the loaded programs, the programs necessary for the function of each card are executed.

  FIG. 2 is a diagram showing a memory map of the conventional common control card 10 and individual control card 20. FIG. 2A shows a memory map of the common control card 10, and FIG. 2B shows a memory map of the individual control card 20.

  In the memory map of the common control card 10, the local memory area is a memory area of the local memory 12 and stores loaded programs (system data, common control program, individual control program). The system data area and the common / individual area are memory areas of the system data memory 18 and store system data, a common control program, and an individual control program. The MPU 21-0 area to the MPU 21-n area are communication areas with the MPU 21 of each individual control unit 20 that executes the loaded program, and are memory areas of the MPU 11. The common function processing area is a memory area of the common function processing unit 14, and the boot area is a memory area of the boot memory 13.

  Among these, the system data area, the common / individual area, and each MPU 21 area are called global areas, and are accessible to both the MPU 11 of the common control card 10 and the MPU 21 of each individual control card 20.

  Further, in the memory map of the individual control card 20, the local memory area is the memory area of the local memory 22, and the loaded programs (system data, common control program, individual control program) are stored. The global bus communication area is a communication area with the MPU 11 of the common control card 20 and a memory area of the MPU 21. The individual function processing area is a memory area of the individual function processing unit 24, and the boot area is a memory area of the boot memory 23.

  In the program loading, (1) a method in which the common control card 10 sequentially transfers a program to each individual control card 20 under the control of the common control card 10, and (2) each individual control card 20 is transferred to the common control unit 10. A method of accessing and reading a program from the system data memory 18 (when access from a plurality of individual control cards 20 overlaps, the access right is controlled by the global arbitration unit 16), (3) DMA (Direct Memory Access) This is performed by a method of transferring a program from the common control card 10 to the individual control card 20 by a controller equivalent function.

FIG. 3 is a diagram for explaining access right control by the global bus arbitration unit 16. The global bus arbitration unit 16 assigns an access right (bus master) to each MPU 21 in a time division manner. That is, it is possible to assign access rights to the access requests from the MPU 21-0 to MPU 21-n in order for each read cycle, and the individual control card to which the access rights are assigned can load the program.
Japanese Patent Laid-Open No. 9-73437 JP-A-1-38862 Japanese Patent Laid-Open No. 5-265969

  When a program is loaded from the system memory 18 of the common control card 10 to a plurality of individual control cards 20 by any of the above-described program loading methods, the loading process is performed for each individual control card 20, so that a plurality of individual control cards 20 are loaded. The time required to transfer the program to all the control cards 20 is the number of cards required for one individual control card 20.

  Therefore, there is a problem that it takes time to start up the system when the number of cards that need to be loaded is large. In addition, if a card reset operation is performed during operation after startup, the service will be interrupted. However, when multiple cards are reset, the time required for restarting is also required for the number of cards. It takes time to resume.

  Therefore, an object of the present invention is to shorten the program loading time in a multiprocessor system.

  A multiprocessor system for achieving the above object includes a common control unit having a processor and storing a predetermined program, and an interprocessor bus between the common control unit and the common control unit. In the multiprocessor system having a plurality of individual control units that are acquired and executed via the processor, the processor of the common control unit is configured to execute a program loading request from at least one of the individual control units. Reading the predetermined program stored in the program memory, the common control unit obtains the predetermined program output from the program memory of the common control unit, converts the address of the predetermined program into a loading dedicated address, The address is the loading-only address An address conversion unit that outputs the converted predetermined program to the inter-processor bus is provided, and each of the individual control units makes a program loading request to the common control unit and a program loading request is made. The inter-processor bus is monitored, and when a loading-dedicated address is detected in the inter-processor bus, a loading control unit is provided for acquiring the predetermined program at the loading-dedicated address and storing it in a local memory of the individual control unit.

  By converting the address of the program read by the common control unit into a loading-dedicated address and outputting the program with the address converted to the loading-dedicated address to the interprocessor bus, multiple individual control units obtain the program at the same time Will be able to.

  According to the present multiprocessor, since a program can be loaded simultaneously to a plurality of individual control units, the loading is greatly increased compared to a case where a program is loaded one by one for a plurality of individual controls. Time can be shortened.

  Hereinafter, embodiments will be described with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention.

  FIG. 4 is a diagram showing a configuration example of the multiprocessor system in the present embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals. The multiprocessor system includes a common control card 10 and a plurality of individual control cards 20-0 to 20-n (collectively referred to as individual control card 20 when each individual control card is not distinguished). The common control card 10 includes an MPU 11, a local memory 12, a boot memory 13, a common function processing unit 14, a global bus IF 15, a global bus arbitration unit 16, a memory IF / IPL area IF 19, and a system data memory 18.

  The local memory 12 is a working memory used when executing the program of the MPU 11. The boot memory 13 stores an initial program required when the MPU 11 is started up, and the common function processing unit 14 is a logic circuit that performs processing unique to common control, and also has a memory area. The global bus IF 15 is an inter-MPU bus IF with the individual control card 20, and the global bus arbitration unit 16 manages the access right from each individual control card 20 to the common control card 10. The system data memory 18 collectively stores system data, a common control card program, and a program (program) for each individual control card. A program stored in the system data memory 18 is transferred and stored in the local memories 12 and 22 of the common control card and the individual control cards, respectively, by the initial program loading process in the embodiment of the present invention described later. The memory IF / IPL area IF 19 provides an IF function between the MPU 12 and the system data memory 18 and an IF function in an initial program loading process according to an embodiment of the present invention described later.

  The individual control card 20 includes an MPU 21, a local memory 22, a boot memory 23, an individual function processing unit 24, a global bus IF 25, and an IPL control unit 26. The local memory 22 is a working memory used when the MPU 21 executes a program. The boot memory 23 stores an initial program required when the MPU 21 is started up, and the individual function processing unit 24 is a logic circuit that performs processing unique to individual control, and also has a memory area. The global bus IF 25 is an inter-MPU bus IF with the common control card 10. The IPL control unit 26 controls an initial program loading (IPL) process in the embodiment of the present invention. In the IPL processing in the present embodiment, when the MPU 11 of the common control unit 10 reads a program from the system data memory 18, the address of the program that passes through the memory IF / IPL area IF 19 is converted to a global bus address dedicated to the memory inter IPL. Then, the MPU 21 of the individual control unit 20 can acquire the program all at once by outputting the information from the face / IPL area IF 19 to the global bus IF 15.

  FIG. 5 is a diagram illustrating a configuration example of the IPL control unit, and FIG. 6 is a diagram illustrating a configuration example of the memory IF / IPL area IF 19, and for each component, along with the operation of the IPL processing of the present embodiment. explain. FIG. 7 is a sequence diagram of the IPL process in the present embodiment, and the operation of the IPL process will be described with reference to FIG.

  The MPU 21 of each individual control card 20 executes the initial program in the boot memory 23 at the time of initial startup or reset of the apparatus, initializes the MPU 21 internally, initializes the local memory 22 and the individual function processing unit 24, The individual control card 20 is initialized. Further, after completing the initialization, the MPU 21 outputs an initial program loading (IPL) request to the common control card 10 (S100).

  The IPL request accepting unit 261 accepts an IPL request from the MPU 21 and sets it in the IPL request register 192 of the memory IF / IPL area IF 19 (S102).

  After outputting the IPL request, the MPU 21 periodically polls whether the IPL completion status of the IPL request accepting unit 261 is ON, and holds the idle state until the IPL is completed.

  When detecting that the IPL request is set in the IPL request register 192 (S104), the MPU 11 of the common control card 10 starts reading the program from the system data memory 18 (S106). In order for the MPU 11 to access the system data memory 18, it is necessary to acquire an access right to the global bus. The MPU 11 requests an access right from the global bus arbitration unit 16 based on the IPL request, and the global bus arbitration unit 16 sequentially assigns the access right to the MPU 11 and the MPU 21 that request the access right for each read cycle. .

  The program stored in the system data memory 18 is sent to the MPU 11 via the memory IF / IPL area IF 19. In the memory IF / IPL area IF 19, the program from the system data 18 is sent to the MPU 11 via the memory IF 191, stored in the local memory 12 of the common control card 10, and the global bus address via the memory IF 191. Obtained by the conversion unit 193.

  The global bus address conversion unit 193 converts the read program address from the address corresponding to the storage area of the system memory 18 to the IPL dedicated address based on the address conversion table (S108), and the address is the IPL dedicated address. Is output to the global bus IF15.

  The start address detection unit 262 of the IPL control unit 26 in the individual control card 20 monitors the address of the global bus IF 15 after the IPL request and detects that the address is an IPL dedicated address (S110). Address data, that is, a program is acquired from the global bus IF 15 of the common control card 10. Since the global bus IF 15 is not monitored by the bus access right assigned from the global bus arbitration unit 16, it can be simultaneously performed by a plurality of control cards 20, and a program output to the global bus IF 15 can be a plurality of individual programs. The control card 20 can be acquired simultaneously.

  The start address detection unit 262 sets the IPL dedicated address detected first in the stop address detection unit 263 as a stop address (S112). The start address 262 stores an IPL dedicated address, and compares the stored address with the address output to the global bus IF15. Further, the switching IF 265 is switched so as to be connected to the local memory 22.

  The IPL dedicated address detected first need not be the IPL dedicated address corresponding to the head portion of the program. The whole program is received by continuing to receive the program until the same IPL dedicated address is detected again. The stop address detection unit 263 can recognize that the entire program has been received by detecting the set IPL dedicated address (stop address).

  The start address detection unit 262 permits the memory transfer control unit 264 to transfer data of the received program while receiving a program having an IPL dedicated address for each periodic read cycle, and the memory transfer control unit 264 and the switching IF 265. Then, the program is stored in the local memory 22 (S114).

  When the stop address detection unit 263 detects the set IPL dedicated address (stop address) (S116), it outputs a stop signal to the memory transfer control unit 264 to stop program transfer and connect the switching IF 265 to the MPU 21. Switch to Further, the stop signal (IPL request OFF signal) is output to the IPL request accepting unit 261 (S118), and the IPL request accepting unit 261 receives the stop signal, and the IPL request register 192 of the memory IF / IPL area IF 19 is received. The IPL request stored in is deleted, and the IPL request is canceled (S120). Further, the IPL request accepting unit 261 turns on the IPL completion status based on the reception of the stop signal (S122).

  When the IPL request timing from each individual control card 20 is different, the program is read from the system data memory 28 and the IPL dedicated address conversion is performed based on the first IPL request, so that the IPL control of each individual control card 20 is performed. The IPL dedicated address first detected by the start address detecting unit 262 of the unit 26 may be different. In this case, the stop address also differs depending on the start address, and the output timing of the stop signal is shifted for each individual control card 20. However, the MPU 11 of the common control card 10 has all the IPLs set in the IPL request register 192. When the request is canceled (S124), that is, when all the individual control cards 20 that have made the IPL request have received the entire program, reading of the program from the system data memory 18 is stopped and stored in the local memory 12 The execution of the processing program for the common control card 10 thus started is started (S126). Since the programs are stored in the local memory 12 of the common control unit 10 based on the first IPL request, all the programs are stored in the local memory 12 when all the IPL requests are canceled. Yes.

  On the other hand, the MPU 21 of the individual control card 20 accesses the local memory 22 via the switching IF 265 when the IPL completion status of the IPL request accepting unit 261 of the own card is turned ON, and each individual control card among the stored programs. The execution of the processing program for 10 is started (S128).

  In this way, the IPL dedicated address is defined in the loaded program, and when the MPU 11 of the common control card 10 reads the program, the read program address is converted into the IPL dedicated address and output to the global bus. The IPL control unit 26 of each of the plurality of individual control cards 20 detects the IPL dedicated address, thereby simultaneously recognizing the program flowing on the global bus and simultaneously reading the program corresponding to the IPL dedicated address. Accordingly, it is possible to shorten the time for loading a program onto the plurality of individual control cards 20.

  Since the global bus arbitration unit 16 assigns the access right to the global bus to one of the plurality of individual control cards 20 of the common control card 10 for one read cycle, the plurality of individual control cards 10 simultaneously receive the system data memory. 18 cannot be accessed. In the present embodiment, in the IPL processing, the global bus arbitration unit 16 sets an access right to the MPU 11 of the common control card 10 and the MPU 11 of the common control card 10 accesses the system data memory 18 and reads the program address. Is converted into an IPL dedicated address so that a plurality of individual control cards 20 monitoring the global bus can acquire a program flowing through the global bus by detecting the IPL dedicated address.

  FIG. 8 is a diagram showing a memory map of the common control card 10 and the individual control card 20 in the present embodiment. FIG. 8A shows a memory map of the common control card 10, and FIG. 8B shows a memory map of the individual control card 20. In comparison with FIG. 2A, in FIG. 8A, the common control card 10 has a system data area in which a program is stored and an IPL dedicated memory area (IPL area) corresponding to the common / individual area. . The IPL area is a memory area of the global bus address conversion unit 193.

  FIG. 9 is a diagram for explaining access right control by the global bus arbitration unit 16 in the IPL processing of the present embodiment. FIG. 9A shows access right control at the time of initial device startup, and the global bus arbitration unit 16 receives a common control unit when there is an IPL request from at least one individual control card 10 (IPL request ON). The access right (bus master) is set in the MPU 11 based on the request from the ten MPUs 11. When the apparatus is started before entering the normal operation state, there is no request for access right from the MPU 21 of the individual control unit 20, so that the MPU 11 of the common control unit 10 does not receive an access right request from the MPU 21 of the individual control unit 20. Access rights are acquired continuously.

  The IPL processing is started by reading the program by the MPU 11 of the common control unit 10, and the start address (“zz” in FIG. 9A) of the IPL dedicated address is set as the stop address. Until “zz” is detected as the stop address (when all the individual control cards 10 start IPL processing from the address “zz”), the access right is assigned to the MPU 11 of the common control card 10 and the stop address “ When “zz” is detected, the IPL requests from all the individual control cards are released (IPL request OFF), and the IPL processing ends with the read cycle at the IPL request OFF timing. The normal operation is performed from the next read cycle, and the access right is assigned to one of the MPUs 21 of the individual control card 20 that requests it.

  FIG. 9B shows a case where each individual control card 10 makes an IPL request at different timings by a reset operation or the like during normal operation. In this case, it is necessary to perform IPL processing in parallel with data communication processing in normal operation. Therefore, when there is an IPL request from a predetermined individual control card 20 (in FIG. 9B, the cards 20A and 20B other than the cards 20-0 and 20-1), the individual performing the data communication processing in the normal operation. An access right is assigned to the control card and the common control card 10 in order for each read cycle, and an IPL process is performed in the read cycle in which the access right is assigned to the common control card 10.

  In the example of FIG. 9B, the IPL request ON timing (stop address “zz”) is later than the IPL request ON timing (stop address “yy”) of the individual control card 20A, and is individually detected at the stop address “yy” detection timing. Although the control card 20A turns off the IPL request, since the individual control card 20B performs the IPL process until the stop address is detected in a later read cycle, the access right to the MPU 11 of the common control card 10 is also assigned. Continue. When all IPL requests are turned off, the MPU 11 of the common control card 10 stops the access right request.

  The above-described multiprocessor system can be applied to a base station apparatus of a wireless communication system. The following additional notes are further disclosed with respect to the embodiment including the above examples.

(Appendix 1)
A common control unit that has a processor and stores a predetermined program, and a plurality of individual control units that each have a processor and that acquire and execute the predetermined program from the common control unit via the inter-processor bus with the common control unit In a multiprocessor system having
The processor of the common control unit reads the predetermined program stored in the program memory of the common control unit based on a program loading request from at least one of the individual control units,
The common control unit acquires the predetermined program output from the program memory of the common control unit, converts an address of the predetermined program into a loading-dedicated address, and converts the address into the loading-dedicated address. An address conversion unit for outputting a program to the inter-processor bus;
Each of the individual control units
A program loading request is made to the common control unit, and the interprocessor bus is monitored while the program loading request is being made. When a loading dedicated address is detected in the interprocessor bus, the predetermined loading address is determined. A multiprocessor system comprising a loading control unit that acquires a program and stores it in a local memory of the individual control unit.

(Appendix 2)
In Appendix 1,
The common control unit includes a bus arbitration unit that assigns an access right to the inter-processor bus to any one of a processor of the common control unit and a plurality of processors of the individual control units every predetermined cycle,
The bus arbitration unit assigns an access right corresponding to a program loading request to a processor of the common control unit,
The processor of the common control unit reads the predetermined program stored in the program memory of the common control unit in a cycle in which an access right is acquired while a program loading request is performed,
A multiprocessor system, wherein a plurality of the individual control units acquire the program in a cycle in which an access right is assigned to a processor of the common control unit.

(Appendix 3)
In Appendix 1,
The loading control unit of the individual control unit stores a loading-dedicated address detected first after a program loading request is made, and detects the same address as the stored loading-dedicated address again. The acquisition is stopped, and the loading control unit of the individual control unit cancels the program loading request,
The processor of the common control unit ends reading of the predetermined program when all the program loading requests from the plurality of individual control units are canceled.

(Appendix 4)
In Appendix 1,
The common control unit includes a storage element that stores a program loading request from the loading control unit of the individual control unit,
The multi-processor system according to claim 1, wherein the processor of the common control unit detects a program loading request and cancellation thereof based on whether or not the program loading request is stored in the storage element.

(Appendix 5)
In Appendix 3,
When the loading control unit cancels the program loading request, the processor of the individual control unit executes the predetermined program stored in a local memory of the individual control unit.

(Appendix 6)
In Appendix 3,
The processor of the common control unit stores the predetermined program read from the program memory in the local memory of the common control unit, and stores the predetermined program in the local memory of the common control unit after completing the reading of the predetermined program. A multiprocessor system that executes the predetermined program.

(Appendix 7)
A common control unit that has a processor and stores a predetermined program, and a plurality of individual control units that each have a processor and that acquire and execute the predetermined program from the common control unit via the inter-processor bus with the common control unit In a program loading method in a multiprocessor system having
The loading control unit of the individual control unit makes a program loading request to the common control unit;
When the processor of the common control unit detects a program loading request from at least one of the individual control units, reading the predetermined program stored in the program memory of the common control unit;
The address conversion unit of the common control unit acquires the predetermined program output from the program memory of the common control unit, converts the address of the predetermined program into a loading dedicated address, and converts the address into the loading dedicated address. Outputting the predetermined program to the inter-processor bus;
The loading control unit of the individual control unit monitors the inter-processor bus while a program loading request is being made, and acquires the predetermined program at the loading-dedicated address when a loading-dedicated address is detected in the inter-processor bus. And storing the program in a local memory of the individual control unit.

It is a figure which shows the structural example of the common control card | curd and the individual control card | curd in the conventional multiprocessor system. It is a figure which shows the memory map of the common control card | curd 10 and the individual control card | curd 20 in the past. It is a figure explaining access right control by the global bus arbitration part. It is a figure which shows the structural example of the multiprocessor system in this Embodiment. It is a figure which shows the structural example of an IPL control part. It is a figure which shows the structural example of memory IF / IPL area | region IF19. It is a sequence diagram of IPL processing in the present embodiment. It is a figure which shows the memory map of the common control card | curd 10 and the individual control card | curd 20 in this Embodiment. It is a figure explaining the access right control by the global bus arbitration part 16 in the IPL process of this Embodiment.

Explanation of symbols

  10: common control card, 11: MPU, 12: local memory, 13: boot memory, 14: common function processing unit, 15: global bus IF, 16: global bus arbitration unit, 17: memory IF, 18: system memory, 19: Memory IF / IPL area IF, 20: Individual control card, 21: MPU, 22: Local memory, 23: Boot memory, 24: Individual function processing unit, 25: Global bus IF, 26: IPL control unit, 191: Memory IF, 192: IPL request register, 193: Global bus address conversion unit, 261: IPL request reception unit, 262: Start address detection unit, 263: Stop address detection unit, 264: Transfer control unit, 265: Switching IF

Claims (5)

A common control unit that has a processor and stores a predetermined program, and a plurality of individual control units that each have a processor and that acquire and execute the predetermined program from the common control unit via the inter-processor bus with the common control unit In a multiprocessor system having
The processor of the common control unit reads the predetermined program stored in the program memory of the common control unit based on a program loading request from at least one of the individual control units,
The common control unit obtains the predetermined program output from the program memory of the common control unit, converts an address of the predetermined program into a loading-dedicated address, and converts the address into the loading-dedicated address. An address conversion unit for outputting a program to the inter-processor bus;
Each of the individual control units
A program loading request is made to the common control unit, and the interprocessor bus is monitored while the program loading request is being made. When a loading dedicated address is detected in the interprocessor bus, the predetermined loading address is determined. A multiprocessor system comprising a loading control unit that acquires a program and stores it in a local memory of the individual control unit. In claim 1,
The common control unit includes a bus arbitration unit that assigns an access right to the inter-processor bus to any one of a processor of the common control unit and a plurality of processors of the individual control units every predetermined cycle,
The bus arbitration unit assigns an access right corresponding to a program loading request to a processor of the common control unit,
The processor of the common control unit reads the predetermined program stored in the program memory of the common control unit in a cycle in which an access right is acquired while a program loading request is performed,
A multiprocessor system, wherein a plurality of the individual control units acquire the program in a cycle in which an access right is assigned to a processor of the common control unit. In claim 1,
The loading control unit of the individual control unit stores a loading-dedicated address detected first after a program loading request is made, and detects the same address as the stored loading-dedicated address again. Stop the acquisition, cancel the program loading request,
The processor of the common control unit ends reading of the predetermined program when all the program loading requests from the plurality of individual control units are canceled. In claim 1,
The common control unit includes a storage element that stores a program loading request from the loading control unit of the individual control unit,
The multi-processor system according to claim 1, wherein the processor of the common control unit detects a program loading request and cancellation thereof based on whether or not the program loading request is stored in the storage element. In claim 3,
When the loading control unit cancels the program loading request, the processor of the individual control unit executes the predetermined program stored in a local memory of the individual control unit.

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