JP2009213131A - Pulse width modulation circuit and switching amplifier employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output a pulse width modulation signal accurately corresponding to an input signal even when current values of a DC bias current and a discharging current are varied by a temperature coefficient. <P>SOLUTION: A current generation circuit 14 includes: a voltage source 31 which supplies a voltage Vs2; a voltage/current conversion circuit 33 which generates a discharging current Id based on the voltage Vs2 supplied from the voltage source 31; a diode 32 which supplies a voltage Vm; and a voltage/current conversion circuit (voltage/current conversion circuits 34, 35, a current/voltage conversion circuit 36 and an operational amplifier 37 as an addition means) that generates a charging current Ij=Ic+Δi based on the voltage Vs2 supplied from the voltage source 31, the voltage Vm supplied from the diode 32, and a voltage of an audio signal eS. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a pulse width modulation circuit that converts an audio signal into a pulse width modulation signal having a constant period and a duty ratio that changes in accordance with the amplitude of the audio signal, and a switching amplifier (for example, an audio amplifier) using the same. ).

  2. Description of the Related Art Conventionally, a pulse width modulation circuit that converts an AC voltage signal such as an audio signal into a pulse width modulation signal whose duty ratio changes according to its amplitude has been proposed. For example, Patent Document 1 below proposes a pulse width modulation circuit using a monostable multivibrator. In addition, the applicant has proposed a pulse width modulation circuit that does not use a monostable multivibrator (for example, the following Patent Document 2, a prior application (Japanese Patent Application No. 2007-31386)).

  FIG. 12 is a circuit diagram showing a schematic configuration of a pulse width modulation circuit proposed by the applicant. 13 and 14 are timing charts showing voltage waveforms of signals in the pulse width modulation circuit shown in FIG. 13 and 14 mainly show waveforms in the charge / discharge operation of the first capacitor C11.

  The pulse width modulation circuit 51 shown in FIG. 12 includes a reference clock generation circuit 54, a dead time generation circuit 55, a falling edge detection circuit 56, a charge current generation circuit 57, a discharge current generation circuit 58, and a current bypass circuit. 59, first to fourth switches SW11 to SW14, first and second capacitors C11 and C12, first and second RS flip-flop circuits 60 and 61, and a signal output circuit 62 including a NAND circuit. ing.

  In the pulse width modulation circuit 51 shown in FIG. 12, a current signal Ij (hereinafter referred to as “charging current Ij”) for charging the first and second capacitors C11 and C12 from the audio signal eS by the charging current generation circuit 57. The discharge current generation circuit 58 generates a current Id (hereinafter referred to as “discharge current Id”) for discharging the first and second capacitors C11 and C12, and the reference clock generation circuit 54 generates the reference clock MCLK. Generated.

  The charging current Ij is expressed by Ij = Ic ± Δi. The bias voltage at the output terminal of the operational amplifier 63 is determined by −Vcc and the resistance elements R11 and R12, and the DC bias current Ic (> 0) is determined by the bias voltage, the resistance element R14, the transistor Q11, and the voltage source 64. Is done. Further, ± Δi is a current component obtained by voltage-current conversion of the audio signal eS (AC voltage signal).

  Based on the reference clock MCLK, the dead time generating circuit 55 generates a first switching signal φ1 for controlling the charging operation of the first capacitor C11 and a second switching signal φ2 for controlling the charging operation of the second capacitor C12 (FIG. 13 (b), (c)). The first RS flip-flop circuit 60 generates a third switching signal φ3 that controls the discharge operation of the first capacitor C11 (see FIG. 13F), and the second RS flip-flop circuit 61 controls the discharge operation of the second capacitor C12. A fourth switching signal φ4 is generated.

  The first capacitor C11 is charged by supplying the charging current Ij (= Ic ± Δi) from the charging current generation circuit 57 only during the ON period (high level period) of the first switching signal φ1 by the first switch SW11. Is done. Due to this charging, the first capacitor C11 rises from the voltage Vth to a voltage corresponding to the amplitude E of the audio signal eS during the high level period of the first switching signal φ1 (see the solid line L1 in FIGS. 13B and 13E). ).

  In the off period (low level period) of the first switching signal φ1, the first set signal set1 (falling to the low level for a moment) is detected when the falling edge detection circuit 56 detects the falling (low level inversion) of the first switching signal φ1. Signal) is input to the set terminal of the first RS flip-flop circuit 60, the third switching signal φ3 output from one output terminal of the first RS flip-flop circuit 60 is inverted to a high level, and the third switch SW13 The discharge current Id from the discharge current generation circuit 58 is supplied to the first capacitor C11, thereby starting the discharge of the first capacitor C11 (see the solid lines L1 and (f) in FIGS. 13D and 13E). .

  When the voltage of the first capacitor C11 decreases from the charge end voltage to the threshold voltage Vth (threshold voltage that divides the high level and the low level in the first RS flip-flop circuit 60) after the discharge starts, the voltage becomes the first reset signal res1 as the first RS. Input to the flip-flop circuit 60, the third switching signal φ3 is inverted to a low level, and the discharge current generating circuit 58 is electrically disconnected by the third switch SW13.

  The output rsout1 output from the other output terminal of the first RS flip-flop circuit 60 is inverted to a low level when the first set signal set1 is input, and then high when the first reset signal res1 is input. Invert to level. That is, from the other output terminal of the first RS flip-flop circuit 60, a pulse having the same pulse width as the discharge time of the first capacitor C11 (the time from when the charge end voltage is lowered to the threshold voltage Vth) for each discharge period. An output rsout1 composed of a signal is output (see FIG. 13G).

  The second capacitor C12 is charged and discharged in the same manner as the first capacitor C11, and the second capacitor C12 is discharged from the other output terminal of the second RS flip-flop circuit 61 every discharge period (from the charging end voltage to the threshold value). An output rsout2 composed of a pulse signal having the same pulse width as the time until the voltage Vth is lowered is output.

  Since the charging / discharging operation of the second capacitor C12 is controlled based on the second switching signal φ2, the charging / discharging period is shifted from the charging / discharging period of the first capacitor C11 by a half cycle of the reference clock MCLK. Therefore, the pulse signal of the output rsout1 and the pulse signal of the output rsout2 are alternately generated every half cycle of the reference clock MCLK.

  Then, a pulse width modulation signal PWMout obtained by synthesizing the output rsout1 and the output rsout2 is output from the signal output circuit 62 (see FIG. 13 (h)).

  A solid line L1 shown in FIG. 13 (e) shows the waveform when the audio signal eS is a no-signal (Δi = 0), which is the charge / discharge waveform of the first capacitor C11. When the audio signal eS is no signal (Δi = 0), the first capacitor C11 is charged with the DC bias current Ic. The DC bias current Ic is charged with the power supply voltage of the first RS flip-flop circuit 60. It is set to be a potential Vm (≈ (Vcc−Vth) / 2) at the midpoint between Vcc and the threshold voltage Vth.

  When the amplitude E of the audio signal eS is positive (in the case of Ij = Ic + Δi), the slope of the charging waveform becomes steeper than the solid line L1 according to the magnitude of the amplitude E. On the other hand, when the amplitude E of the audio signal eS is negative (Ij = Ic−Δi), the charging waveform has a gentler slope than the solid line L1 depending on the magnitude of the amplitude E. Therefore, a pulse width modulation signal whose high level period changes according to the audio signal is output.

JP 2007-89122 A JP 2008-206128 A

  As described above, the pulse width modulation circuit 51 discharges the charging current generation circuit 57 for generating the charging current Ij for charging the first and second capacitors C1 and C2, and the first and second capacitors C1 and C2. Discharge current generation circuits 58 for generating the discharge current Id to be generated are independently provided. Further, the pulse width modulation circuit 51 has a pulse width when the current value of the DC bias current Ic and the discharge current Id is Ic: Id = 1: 2 and the amplitude value of the audio signal eS is 0. The modulation degree of the modulation signal PWMout becomes 0 (duty ratio 50%, the period between the high level and the low level coincides). However, since the constant voltage sources 64 and 65 included in the charging current generation circuit 57 and the discharge current generation circuit 58 include semiconductor elements and resistors, the constant voltage sources 64 and 65 depend on the temperature coefficient of the semiconductor elements and resistors. The output voltage value varies according to the temperature. As a result, the current values of the DC bias current Ic and the discharge current Id vary depending on the temperature due to the influence of the temperature coefficient. Even if the current value of each current fluctuates, if the ratio of the DC bias current Ic and the discharge current Id maintains the relationship of Ic: Id = 1: 2, a normal pulse width modulation signal PWMout is output. be able to. However, when the ratio of the DC bias current Ic and the discharge current Id does not maintain the relationship of Ic: Id = 1: 2, a DC offset occurs in the pulse width modulation signal PWMout.

  Details will be described by taking as an example a case where the amplitude of the audio signal eS is zero. First, when the discharge current Id does not vary depending on the temperature and only the DC bias current Ic increases due to the temperature coefficient, the slope of the charging waveform of the capacitor C11 is a solid line as shown by the broken line L2 in FIG. It becomes steeper than L1, and the charge end voltage charged in the capacitor C11 increases during the high level period of the first switching signal φ1. Since the discharge current Id does not fluctuate, the time until the charging voltage of the capacitor C11 reaches the threshold voltage Vth is longer than that of the solid line L1, and the output pulse width modulation signal PWMout has a high level period during the solid line L1. As a result, it becomes longer than that at the time, and the modulation degree changes. On the other hand, when only the DC bias current Ic is decreased by the temperature coefficient without changing the discharge current Id according to the temperature, the slope of the charging waveform of the capacitor C11 is a solid line as shown by the broken line L3 in FIG. Compared to L1, the charge end voltage charged in the capacitor C11 is reduced during the high level period of the first switching signal φ1. Since the discharge current Id has not changed, the time until the charging voltage of the capacitor C11 reaches the threshold voltage Vth is shorter than that of the solid line L1, and the high level period of the output pulse width modulation signal PWMout is shortened. The modulation degree changes.

  Next, when the DC bias current Ic does not change according to the temperature and only the discharge current Id increases due to the temperature coefficient, the high level of the first switching signal φ1 is shown as indicated by the broken line L4 in FIG. The charging end voltage charged in the capacitor C11 during the period is the same as that of the solid line L1, but since the slope of the discharge waveform becomes steep, the time until the charging voltage of the capacitor C11 reaches the threshold voltage Vth is indicated by the solid line L1. , The high level period of the output pulse width modulation signal PWMout is shortened, and the modulation degree changes. On the other hand, when the DC bias current Ic does not fluctuate and only the discharge current Id decreases due to the temperature coefficient, as indicated by the broken line L5 in FIG. The charging end voltage to be charged is the same as that of the solid line L1, but since the slope of the discharge waveform becomes gentle, the time until the charging voltage of the capacitor C11 reaches the threshold voltage Vth becomes longer than that of the solid line L1. The high level period of the output pulse width modulation signal PWMout becomes longer, and the modulation degree changes.

  Even when both the DC bias current Ic and the discharge current Id fluctuate depending on the temperature coefficient, and the ratio of the DC bias current Ic and the discharge current Id deviates from the relationship of 1: 2, either of the above states occurs. End up.

  The present invention has been conceived under the circumstances described above, and in the pulse modulation circuit having the above-described configuration, the current values of the DC bias current Ic and the discharge current Id vary depending on the temperature coefficient. Another object of the present invention is to provide a pulse width modulation circuit that outputs a pulse width modulation signal accurately corresponding to an input signal, and a switching amplifier to which the pulse width modulation circuit is applied.

  A pulse width modulation circuit according to a preferred embodiment of the present invention includes a first charge accumulation unit that accumulates charges, a second charge accumulation unit that accumulates charges, and a current corresponding to an amplitude of the AC voltage from an input AC voltage. Current generating means for generating a first current whose value changes and generating a second current; and a first period in a first period which is a half cycle of a predetermined clock signal based on the first current. The voltage in the charge storage means is changed, and the voltage in the first charge storage means is changed in the first period in a second period following the first period that is shifted from the first period by a half cycle based on the second current. The voltage in the second charge storage means is changed based on the first current, and is shifted by a half cycle from the second period based on the second current. Second Voltage control means for changing the voltage in the second charge storage means in the opposite direction to the increase / decrease direction in the second period in a third period, and in the first charge storage means after the start of the second period. A first detecting means for detecting a time until the voltage reaches a threshold voltage; and a first detecting means for detecting a time from when the third period starts until the voltage at the second charge storage means reaches the threshold voltage. 2 detection means, and a pulse signal generation that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection means and the second detection means every half cycle of the clock signal And a second voltage based on the first power supply voltage supplied from the first voltage source, and the current generating means supplies the first power supply voltage. First voltage-current conversion means for generating current, second voltage-current conversion for generating the first current based on the first power supply voltage supplied from the first voltage source, and the AC voltage Means.

  Since the first current and the second current are generated by the common first power supply voltage, the first power supply voltage varies depending on the temperature coefficient of the first voltage source, and the direct current bias of the first current is changed. Even when the current and the second current fluctuate, the ratio of the DC bias current of the first current to the second current can be made constant. This is because when the current value of the DC bias current of the first current varies due to the variation of the first power supply voltage, the current value of the second current also varies at the same ratio. Therefore, even if the DC bias current of the first current and the second current fluctuate due to the temperature coefficient, it is possible to output a pulse width modulation signal that accurately corresponds to the input signal.

  Preferably, the current generation unit further includes a second voltage source that supplies a second power supply voltage, and the second voltage-current conversion unit is supplied from the first voltage source. The first current is generated based on a power supply voltage, the second power supply voltage supplied from the second voltage source, and the AC voltage.

  The first current and the second current are generated by a common first power supply voltage, and the second power supply voltage is further used to generate the first current, so that the temperature coefficient of each element, etc. Thus, even when the DC bias current of the first current and the second current fluctuate, the ratio of the DC bias current of the first current to the second current can be made constant. Therefore, even if the DC bias current of the first current and the second current fluctuate due to the temperature coefficient, it is possible to output a pulse width modulation signal that accurately corresponds to the input signal.

  Preferably, the second voltage-current conversion unit is based on the first power supply voltage supplied from the first voltage source and the second power supply voltage supplied from the second voltage source. A third voltage-current conversion means for generating a third current; a current-voltage conversion means for generating a third voltage based on the third current supplied from the third voltage-current conversion means; And an AC voltage and an adding means for generating a fourth voltage, and a fourth voltage-current converting means for generating the first current based on the fourth voltage.

  Preferably, the current generation unit further includes a third voltage source that supplies a third power supply voltage, and the second voltage-current conversion unit is supplied from the first voltage source. Third voltage / current conversion means for generating a third current based on a power supply voltage and the second power supply voltage supplied from the second voltage source; and supplied from the third voltage / current conversion means Current-voltage conversion means for generating a third voltage based on the third current, addition means for adding the third voltage and the AC voltage to generate a fourth voltage, and the fourth And a fourth voltage-to-current conversion means for generating the first current based on the third power supply voltage and the third power supply voltage.

  Preferably, the second voltage-current conversion unit generates a third current based on the first power supply voltage supplied from the first voltage source, and the third voltage-current conversion unit. Current voltage conversion means for generating a third voltage based on the third current supplied from the current conversion means, and adding the third voltage and the AC voltage to generate a fourth voltage. Addition means; and fourth voltage-current conversion means for generating the first current based on the fourth voltage and the second power supply voltage.

  Preferably, the second voltage-current converter generates a third current having the same current value as the second current, based on the first power supply voltage supplied from the first voltage source. A third voltage-to-current converter, a differential circuit that generates a fourth current obtained by adding a current based on the AC voltage to a current that is ½ of the third current, and a current value that is the same as the fourth current And a current mirror circuit that generates the first current.

  Preferably, the first and second charge accumulating means are charged with the first current and discharged with the second current.

  Preferably, the first and second charge accumulating means are discharged with the first current and charged with the second current.

  Preferably, a switching signal generating means for generating a switching signal for determining the switching timing of each period based on the clock signal, and a falling detection means for detecting a falling edge of the switching signal generated by the switching signal generating means The first detection means inputs the charge voltage stored in the first charge storage means in the second period as a reset signal, and the fall of the switching signal detected by the fall detection means The first flip-flop means for inputting an edge signal as a set signal, and the second detection means inputs the charging voltage accumulated in the second charge accumulation means in the third period as a reset signal, and The second flip-flop means for inputting the falling edge signal of the switching signal detected by the down detection means as a set signal. , The pulse signal generating means, an output of the first flip-flop means to generate the pulse signal based on the output of the second flip-flop means.

  Preferably, a first voltage maintaining unit that maintains the voltage in the first charge storage unit at the threshold voltage until the third period starts after the voltage in the first charge storage unit reaches the threshold voltage. The voltage in the second charge storage means until the fourth period starting from the third period shifted from the third period after the voltage in the second charge storage means reaches the threshold voltage is started. Is further maintained with the threshold voltage.

  A switching amplifier according to a preferred embodiment of the present invention includes: the voltage width based on any one of the pulse width modulation circuit, a voltage source that outputs a predetermined reference power supply voltage, and a modulation signal output from the pulse width modulation circuit. And a switching circuit for switching the reference power supply voltage supplied from the source.

  When the first current and the second current are generated by the common first power supply voltage, the direct current bias current and the second current of the first current vary depending on the temperature coefficient of each element. Even so, the ratio between the DC bias current of the first current and the second current can be made constant. Therefore, even if the DC bias current of the first current and the second current fluctuate due to the temperature coefficient, it is possible to output a pulse width modulation signal that accurately corresponds to the input signal.

It is a block diagram showing a switching amplifier to which a pulse width modulation circuit according to the present invention is applied. 1 is a block circuit diagram showing a first embodiment of a pulse width modulation circuit according to the present invention. FIG. It is a block diagram showing current generator circuit 14 of a 1st embodiment. It is a circuit diagram showing current generator circuit 14 of a 1st embodiment. It is a figure which shows the time chart which shows operation | movement when the amplitude of an audio signal is 0. It is a figure which shows the time chart which shows operation | movement when the amplitude of an audio signal is positive. It is a circuit diagram which shows the electric current generation circuit 44 of 2nd Embodiment. It is a circuit diagram which shows the electric current generation circuit 54 of 3rd Embodiment. It is a block diagram which shows the electric current generation circuit 60 of 4th Embodiment. It is a circuit diagram which shows the electric current generation circuit 60 of 4th Embodiment. FIG. 9 is a block circuit diagram showing a fifth embodiment of the pulse width modulation circuit according to the present invention. It is a circuit diagram which shows the pulse width modulation circuit which the applicant has proposed. 13 is a timing chart showing voltage waveforms of signals in the pulse width modulation circuit shown in FIG. 12. 13 is a timing chart showing voltage waveforms of signals in the pulse width modulation circuit shown in FIG. 12.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a switching amplifier to which a pulse width modulation (PWM) circuit according to the present invention is applied. FIG. 2 is a block circuit diagram showing the pulse width modulation circuit shown in FIG.

[Configuration of switching amplifier]
This switching amplifier includes a pulse width modulation circuit 1 connected to an audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, a first power supply 4 that supplies positive and negative power supply voltages + EB and -EB, and a second power supply. And a power source 5. A speaker (not shown) as a load RL is connected to the output of the low-pass filter circuit 3.

  The pulse width modulation circuit 1 converts the audio signal eS as an input signal output from the audio signal generation source AU into a pulse width modulation signal PWMout and outputs it. The pulse width modulation signal PWMout output from the pulse width modulation circuit 1 is input to the switching circuit 2.

  The switching circuit 2 includes a switch element SW-A whose on / off operation is controlled by the pulse width modulation signal PWMout, an inverter 2a for inverting the phase of the pulse width modulation signal PWMout output from the pulse width modulation circuit 1, and The switch element SW-B whose on / off operation is controlled by the pulse width modulation signal PWMout ′ whose phase is inverted output from the inverter 2a is connected to both ends of the switch elements SW-A and SW-B. Reverse-current preventing diodes DA and DB are provided.

  In the switching circuit 2, positive and negative power supply voltages + EB and -EB are supplied from the first power supply 4 and the second power supply 5 to the load RL via the switch element SW-A and the switch element SW-B, respectively. Since the SW-A and the switch element SW-B are alternately turned on and off by the pulse width modulation signal PWMout and the pulse width modulation signal PWMout ′, respectively, the power supply voltage + EB is applied to the low-pass filter circuit 3 and the load RL. The power supply voltage -EB is supplied alternately. That is, the load RL is supplied with a rectangular wave voltage having the same duty ratio as that of the pulse width modulation signal PWMout through the low-pass filter circuit 3 while the level changes between + EB and -EB.

  The low-pass filter circuit 3 is configured by an LC circuit including a coil L0 and a capacitor C0. The low-pass filter circuit 3 is a circuit that removes a high-frequency component of the rectangular wave voltage input from the switching circuit 2 and has a cutoff frequency of 60 kHz, for example. The low-pass filter circuit 3 outputs an AC voltage signal (AC voltage signal having substantially the same waveform as that of the audio signal eS) obtained by demodulating the pulse width modulation signal PWMout, and the AC signal is supplied to the load RL. Is output as audio.

[Configuration of pulse width modulation circuit]
As shown in FIG. 2, the pulse width modulation circuit 1 includes a reference clock generation circuit 11, a dead time generation circuit 12, a falling edge detection circuit 13, a charging current / discharge current generation circuit (hereinafter referred to as a current generation circuit). .) 14, first to fourth switches SW1 to SW4, first and second capacitors C1 and C2, current bypass circuit 16, first and second RS flip-flop circuits 17 and 18, and signal output circuit 19 And is composed of.

The pulse width modulation circuit 1
(1) A charging current Ij for charging the first and second capacitors C1 and C2 is generated by the current generation circuit 14 from the audio signal eS input from the outside.
(2) Of the one cycle of the reference clock MCLK, for example, the first half cycle of the first capacitor C1 is a charging period, the latter half cycle is a discharging period, and the first half cycle of the second capacitor C2 is a discharging period. When the second half cycle is a charging period, the first and second capacitors C1 and C2 are charged with the charging current Ij in each charging period, and the accumulated charges of the first and second capacitors C1 and C2 are discharged in each discharging period. Discharge with current Id.
(3) Every discharge period of the first and second capacitors C1 and C2, from the start of discharge (at the end of charging) until the voltage of the first and second capacitors C1 and C2 changes to a predetermined threshold voltage Vth Pulse signals having the same pulse width as the discharge time are generated.
(4) A pulse width modulation signal PWMout is generated by synthesizing pulse signals generated alternately every half cycle of the reference clock MCLK.
The audio signal eS is converted into the pulse width modulation signal PWMout by the operation principle described above.

  The reference clock generation circuit 11 is a circuit that generates the reference clock MCLK. The reference clock MCLK is a clock signal having a constant cycle and a duty ratio of approximately 50%, and first and second switching signals φ1 and φ2 for controlling on / off operations of the first and second switches SW1 and SW2. This is the reference signal. The reference clock MCLK is also a reference signal that defines the period of the pulse width modulation signal PWMout. The reference clock generation circuit 11 outputs the reference clock MCLK to the dead time generation circuit 12. The reference clock generation circuit 11 may be provided outside the pulse width modulation circuit 1 and configured to supply the reference clock MCLK to the pulse width modulation circuit 1 as an external clock signal.

  The dead time generation circuit 12 is a circuit that generates the first switching signal φ1 and the second switching signal φ2 based on the reference clock MCLK from the reference clock generation circuit 11. The second switching signal φ2 has an opposite phase relationship to the first switching signal φ1, but the falling timing and rising timing of the second switching signal φ2 coincide with the rising timing and falling timing of the first switching signal φ1, respectively. As a result, the level inversion timing of the second switching signal φ2 is shifted by a predetermined time ΔT (dead time) with respect to the level inversion timing of the first switching signal φ1.

  That is, as shown in FIGS. 5A and 5B, the first switching signal φ1 changes from the low level to the high level after a predetermined period ΔT from the time when the reference clock MCLK is inverted from the low level to the high level. The signal is inverted, and the reference clock MCLK is inverted from the high level to the low level, and at the same time is inverted from the high level to the low level. On the other hand, as shown in FIGS. 5A and 5C, the second switching signal φ2 is inverted from the high level to the low level at the same time as the reference clock MCLK is inverted from the low level to the high level. This signal is inverted from the low level to the high level after a predetermined period ΔT from when the high level is inverted to the low level.

  By providing a dead time between the first switching signal φ1 and the second switching signal φ2, as shown in FIGS. 5B and 5C, the high level inversion and the second switching of the first switching signal φ1 are performed. Since the low level inversion of the signal φ2 does not occur at the same time and the low level inversion of the first switching signal φ1 and the high level inversion of the second switching signal φ2 do not occur at the same time, the first switch SW1 is turned on by the first switching signal φ1. When switching from the off state to the on state (when the node supplying the charging current Ij of the current generation circuit 14 is connected to the first capacitor C1), the second switch SW2 is already switched to the off state by the second switching signal φ2. (The node supplying the charging current Ij of the current generation circuit 14 is already disconnected from the second capacitor C2) and supplies the charging current Ij of the current generation circuit 14 Are not simultaneously connected to the first and second capacitors C1 and C2. Also, when the second switch SW2 is switched from the off state to the on state by the second switching signal φ2 (when the node supplying the charging current Ij of the current generation circuit 14 is connected to the second capacitor C2), the first switch SW1 has already been switched to the OFF state by the first switching signal φ1 (the node supplying the charging current Ij of the current generation circuit 14 has already been disconnected from the first capacitor C1), and the charging current Ij of the current generation circuit 14 Are not simultaneously connected to the first and second capacitors C1 and C2.

  As a result, the charging current Ij supplied from the current generation circuit 14 to the first capacitor C1 during the charging of the first capacitor C1 is also supplied to the second capacitor C2, and conversely the current during the charging of the second capacitor C2. Since the charging current Ij supplied from the generation circuit 14 to the second capacitor C2 is not supplied to the first capacitor C1, the pulse signals output from the first and second RS flip-flop circuits 17 and 18, respectively. It is possible to prevent an inconvenience that an error occurs in the pulse width of the signal and, as a result, an error occurs in the pulse width of the pulse width modulation signal PWMout. The first and second switching signals φ1 and φ2 are output to the first and second switches SW1 and SW2, respectively, and also output to the falling edge detection circuit 13.

  Note that the dead time provided in the dead time generation circuit 12 is extremely small, and the first switch SW1 is substantially controlled to be turned on and off by the reference clock MCLK, and the second switch SW2 inverts the phase of the reference clock MCLK. It can be said that ON / OFF is controlled by the clock.

  The falling edge detection circuit 13 is a circuit that outputs first and second set signals set1 and set2 supplied to first and second RS flip-flop circuits 17 and 18, which will be described later. That is, the falling edge detection circuit 13 detects the timing at which the first switching signal φ1 falls from the high level to the low level, and as shown in FIG. 5D, the signal that falls to the low level for a moment at the detection timing. Is output to the first RS flip-flop circuit 17 as the first set signal set1. Further, the falling edge detection circuit 13 detects the timing at which the second switching signal φ2 falls from the high level to the low level, and as shown in FIG. 5 (e), the signal that falls to the low level for a moment at the detection timing. Is output to the second RS flip-flop circuit 18 as the second set signal set2.

  The current generation circuit 14 performs voltage-current conversion on the audio signal eS supplied from the audio signal generation source AU to the pulse width modulation circuit 1, and generates a charging current Ij obtained by adding the DC bias current Ic to the converted current Δi. Circuit. The node that outputs the charging current Ij of the current generation circuit 14 is connected to the first and second capacitors C1 and C2 via the first and second switches SW1 and SW2, respectively. When the first switch SW1 is in the on state, The first capacitor C1 is connected to the first capacitor C1 and charged with the charging current Ij. When the second switch SW2 is in the ON state, the second capacitor C2 is connected to charge the second capacitor C2 with the charging current Ij.

  The current generation circuit 14 generates a discharge current Id, and discharges the accumulated charges of the first and second capacitors C1 and C2 with the discharge current Id. That is, the node from which the discharge current Id of the current generation circuit 14 is output is connected to the first and second capacitors C1 and C2 via the third and fourth switches SW3 and SW4, respectively, and the third switch SW3 is When the first capacitor C1 is turned on and connected to the first capacitor C1, the charge accumulated in the first capacitor C1 is discharged by the discharge current Id. When the fourth switch SW4 is turned on and connected to the second capacitor C2, the second capacitor C2 is turned on. The accumulated charge in the capacitor C2 is discharged with the discharge current Id. Details of the current generation circuit 14 will be described later.

  The current bypass circuit 16 includes a diode D2 and a voltage source 23. The current bypass circuit 16 discharges even when the node that outputs the discharge current Id of the current generation circuit 14 is not electrically connected to the first and second capacitors C1 and C2 by the third and fourth switches SW3 and SW4. This is for flowing the current Id. That is, when the node that outputs the discharge current Id of the current generation circuit 14 is not electrically connected to the first and second capacitors C1 and C2 by the third and fourth switches SW3 and SW4, the diode D2 is turned on. The voltage source 23 is connected to the node that outputs the discharge current Id of the current generation circuit 14.

  In this state, for example, when the third switch SW3 is turned on and the first capacitor C1 is connected to the node that outputs the discharge current Id of the current generation circuit 14, the voltage of the first capacitor C1 is the cathode side of the diode D2. Therefore, the diode D2 is turned off, and the path through which the discharge current Id flows is switched from the voltage source 23 to the first capacitor C1. That is, at the same time as the third switch SW3 is turned on, the discharge operation with the discharge current Id of the charge accumulated in the first capacitor C1 is started. The same operation is performed when the fourth switch SW4 is turned on, and at the same time when the fourth switch SW4 is turned on, the discharge operation with the discharge current Id of the charge accumulated in the second capacitor C2 is started.

  The first and second switches SW1 and SW2 are switches for controlling the charging operation by the charging current Ij from the current generation circuit 14 of the first and second capacitors C1 and C2. One end of the first switch SW1 is connected to a node that outputs the charging current Ij of the current generation circuit 14, and the other end of the first switch SW1 is connected to one end of the first capacitor C1 (see point A in FIG. 2). Yes. When the first switch SW1 is turned on (closed), a charging path for the first capacitor C1 is formed. Further, one end of the second switch SW2 is also connected to a node that outputs the charging current Ij of the current generation circuit 14, and the other end of the second switch SW2 is connected to one end of the second capacitor C2 (see point A ′ in FIG. 2). It is connected. When the second switch SW2 is turned on (closed), a charging path for the second capacitor C2 is formed.

  The first and second switches SW1 and SW2 are turned on and off by first and second switching signals φ1 and φ2 output from the dead time generation circuit 12. That is, as shown in FIG. 5B, the first switch SW1 is turned on when the first switching signal φ1 is at a high level, and is turned off when the first switching signal φ1 is at a low level. Further, as shown in FIG. 5C, the second switch SW2 is turned on when the second switching signal φ2 is at a high level, and is turned off when the second switching signal φ2 is at a low level.

  The third and fourth switches SW3 and SW4 are switches for controlling the discharge operation by the discharge current Id from the current generation circuit 14 of the first and second capacitors C1 and C2. One end of the third switch SW3 is connected to a node that outputs the discharge current Id of the current generation circuit 14, and the other end of the third switch SW3 is connected to one end of the first capacitor C1 (see point A in FIG. 2). Yes. When the third switch SW3 is turned on (becomes closed), a discharge path for the first capacitor C1 is formed. Further, one end of the fourth switch SW4 is also connected to a node that outputs the discharge current Id of the current generation circuit 14, and the other end of the fourth switch SW4 is connected to one end of the second capacitor C2 (see point A ′ in FIG. 2). It is connected. When the fourth switch SW4 is turned on (becomes closed), a discharge path for the second capacitor C2 is formed.

  The third and fourth switches SW3 and SW4 are turned on and off by third and fourth switching signals φ3 and φ4 from first and second RS flip-flop circuits 17 and 18, which will be described later. That is, as shown in FIG. 5H, the third switch SW3 is turned on when the third switching signal φ3 is at a high level, and is turned off when it is at a low level. Further, as shown in FIG. 5I, the fourth switch SW4 is turned on when the fourth switching signal φ4 is at a high level, and is turned off when it is at a low level.

  The first and second capacitors C1 and C2 are for generating time according to the amplitude (instantaneous voltage value) of the audio signal eS. Specifically, the first capacitor C1 generates a current when the first switch SW1 is turned on (the third switch SW3 is turned off at this time) during the on period (a certain period) of the first switching signal φ1. By charging with the charging current Ij (= Ic ± Δi, current corresponding to the amplitude (instantaneous voltage value) of the audio signal eS) from the circuit 14, the voltage corresponding to the amplitude of the audio signal eS from the threshold voltage Vth (charging end) Voltage). After the charging operation is completed, the third switch SW3 is turned on (at this time, the first switch SW1 is turned off), so that the accumulated charge is discharged with a constant discharge current Id. In this discharge operation, the discharge time until the voltage of the first capacitor C1 drops from the charge end voltage to the predetermined threshold voltage Vth is generated as a time corresponding to the amplitude (instantaneous voltage value) of the audio signal eS.

  The predetermined threshold voltage Vth is a logic level threshold voltage in the first and second RS flip-flop circuits 17 and 18, and is approximately 1 / V of the power supply voltage + Vcc supplied to the first and second RS flip-flop circuits 17 and 18. 2 voltage. For example, if the drive voltage of the first and second RS flip-flop circuits 17 and 18 is +5 [v], the threshold voltage Vth is approximately +2.5 [v].

  The second capacitor C2 is charged from the current generation circuit 14 when the second switch SW2 is turned on (the fourth switch SW4 is turned off at this time) during the on period (a certain period) of the third switching signal φ3. By charging with the current Ij, the charge start voltage Vth is raised to a voltage (charge end voltage) corresponding to the amplitude of the audio signal eS. After the charging operation is completed, the fourth switch SW4 is turned on (at this time, the second switch SW2 is turned off), so that the accumulated charge is discharged with a constant discharge current Id. In this discharge operation, a discharge time until the voltage of the second capacitor C2 drops from the charge end voltage to the predetermined threshold voltage Vth is generated as a time corresponding to the amplitude (instantaneous voltage value) of the audio signal eS.

  The first RS flip-flop circuit 17 generates a pulse signal having the same pulse width as the discharge time of the first capacitor C1 during each discharge period of the first capacitor C1, and also generates a third switching signal φ3. is there.

  The first RS flip-flop circuit 17 is an RS flip-flop circuit configured by two NAND gates (first NAND circuit NA1 and second NAND circuit NA2). The voltage of the first capacitor C1 is input to the first NAND circuit NA1 as the first reset signal res1, and the output rsout1 is output from the first NAND circuit NA1. Further, the first set signal set1 (a signal that instantaneously falls to a level lower than the threshold voltage Vth) output from the falling edge detection circuit 13 is input to the second NAND circuit NA2, and the third NAND circuit NA2 to the third A switching signal φ3 is output.

  When the first set signal set1 is input, the first RS flip-flop circuit 17 inverts the output rsout1 to low level and the third switching signal φ3 to high level, and the voltage of the first capacitor C1 is low level (threshold voltage Vth or less) In other words, when the first reset signal res1 is input, the output rsout1 is inverted to the high level and the third switching signal φ3 is inverted to the low level. Since the input timing of the first set signal set1 corresponds to the discharge start timing of the first capacitor C1, and the input timing of the first reset signal res1 is the timing when the voltage of the first capacitor C1 drops to the threshold voltage vth, the output rsout1 The low level period corresponds to the discharge time of the first capacitor C1.

  Therefore, from the output terminal of the first NAND circuit NA1 of the first RS flip-flop circuit 17, a pulse signal having the same pulse width as the discharge time of the first capacitor C1 is output as an output rsout1 during each discharge period of the first capacitor C1. Is done.

  The second RS flip-flop circuit 18 generates a pulse signal having the same pulse width as the discharge time of the second capacitor C2 during each discharge period of the second capacitor C2, and generates a fourth switching signal φ4. is there.

  Similarly to the first RS flip-flop circuit 17, the second RS flip-flop circuit 18 is also an RS flip-flop circuit configured by two NAND gates (a third NAND circuit NA3 and a fourth NAND circuit NA4). The voltage of the second capacitor C2 is input to the third NAND circuit NA3 as the second reset signal res2, and the output rsout2 is output from the third NAND circuit NA3. Further, the second set signal set2 (a signal that instantaneously falls to a level lower than the threshold voltage Vth) output from the falling edge detection circuit 13 is input to the fourth NAND circuit NA4, and the fourth NAND circuit NA4 to the fourth NAND circuit NA4. A switching signal φ4 is output.

  When the second set signal set2 is input, the second RS flip-flop circuit 18 inverts the output rsout2 to the low level and the fourth switching signal φ4 to the high level, and the voltage of the second capacitor C2 is low level (threshold voltage Vth or less) In other words, when the second reset signal res2 is input, the output rsout2 is inverted to the high level and the fourth switching signal φ4 is inverted to the low level. Since the input timing of the second set signal set2 corresponds to the discharge start timing of the second capacitor C2, and the input timing of the second reset signal res2 is the timing when the voltage of the second capacitor C2 drops to the threshold voltage vth, the output rsout2 The low level period corresponds to the discharge time of the second capacitor C2.

  Accordingly, a pulse signal having the same pulse width as the discharge time of the second capacitor C2 is output as an output rsout2 during each discharge period of the second capacitor C2 from the output terminal of the third NAND circuit NA3 of the second RS flip-flop circuit 18. Is done.

  The signal output circuit 19 is a circuit that combines the output rsout1 output from the first RS flip-flop circuit 17 and the output rsout2 output from the second RS flip-flop circuit 18. The signal output circuit 19 includes a NAND gate (fifth NAND circuit NA5). The output rsout1 is a signal that generates a pulse signal (a pulse signal having the same pulse width as the discharge time of the first capacitor C1) only during the low level period of the reference clock MCLK, while the output rsout2 is the high level of the reference clock MCLK. Since the pulse signal (the pulse signal having the same pulse width as the discharge time of the second capacitor C2) is generated only during the period, the signal output circuit 19 outputs the pulse signal of the output rsout1 and the pulse signal of the output rsout2. A pulse signal (a pulse train signal having a pulse width corresponding to the eS amplitude (instantaneous voltage value) of the audio signal in the same cycle as the half cycle of the reference clock MCLK) is output as a pulse width modulation PMWout. Is done.

[Configuration of Current Generation Circuit 14]
FIG. 3 is a block diagram showing the current generation circuit 14, and FIG. 4 is a circuit diagram of the current generation circuit 14. The current generation circuit 14 includes voltage sources 31 and 32, a voltage / current conversion circuit (hereinafter referred to as a V / I conversion circuit) 33 to 35, and a current / voltage conversion circuit (hereinafter referred to as an I / V conversion circuit) 36. have. Note that FIG. 3 shows only a part of the charging current Ij that generates only the DC bias current Ic for the sake of simplicity, and an adding means for adding the voltage of the audio signal eS shown in FIG. (The operational amplifier 37 and the resistor R4) are omitted.

  The current generation circuit 14 generates the discharge current Id and the DC bias current Ic of the charging current Ij from the common voltage source 31. Therefore, even when the voltage Vs2 varies due to the temperature coefficient of the voltage source 31 and the DC bias current Ic and the discharge current Id vary, the variation errors between the DC bias current Ic and the discharge current Id are mutually different. Thus, the ratio of the current value of the DC bias current Ic and the discharge current Id can be maintained at a constant ratio (for example, Ic: Id = 1: 2).

  In addition, the current generation circuit 14 generates the discharge current Id and the DC bias current Ic from the common voltage source 31, and further includes a voltage source 32 having a specific temperature coefficient and voltage value, so that the current generation circuit 14 is based on the temperature coefficient. The fluctuation error between the discharge current Id and the DC bias current Ic is canceled, and the ratio of the current value between the DC bias current Ic and the discharge current Id is maintained at a constant ratio (for example, Ic: Id = 1: 2).

The V / I conversion circuit 33 is supplied with the voltage Vs2 from the voltage source 31, and generates a discharge current Id by performing voltage-current conversion on the voltage Vs2. The V / I conversion circuit 33 includes a transistor Q1 and a resistor R1. The transistor Q1 has a base connected to the positive side of the voltage source 31, an emitter connected to the ground potential via the resistor R1, and a collector serving as a node that outputs the discharge current Id. That is, the collector of the transistor Q1 is connected to the first capacitor C1 through the third switch SW3, and is connected to the second capacitor C2 through the fourth switch SW4. If the conversion conductance of the V / I conversion circuit 33 is H, the discharge current Id = HVs2, but actually the voltage source 31 has a temperature coefficient a, and the V / I conversion circuit 33 sets the temperature coefficient b. Therefore, the discharge current Id is expressed by the following formula 1.
Id = abHVs2 (Formula 1)

The voltage source 32 adds a predetermined voltage Vm to the voltage Vs2 supplied from the voltage source 31, and outputs a voltage Vs3. The voltage source 32 includes, for example, a diode D3, the cathode of the diode D3 is connected to the voltage source 31, the anode is connected to the base of the transistor Q2, and is connected to the ground potential via the resistor R6. Actually, since the voltage source 31 has a temperature coefficient a and the voltage source 32 has a temperature coefficient f, the voltage Vs3 is expressed by the following equation 2.
Vs3 = aVs2 + fVm (Formula 2)

The V / I conversion circuit 34 is supplied with the voltage Vs3 from the voltage source 32, and generates a current Ib by performing voltage-current conversion on the voltage Vs3. The V / I conversion circuit 34 includes a transistor Q2 and a resistor R2. The transistor Q2 has a base connected to the anode of the diode D3, an emitter connected to the ground potential via the resistor R2, and a collector connected to the I / V conversion circuit 36 (resistor R3). If the conversion conductance of the V / I conversion circuit 34 is K, the current Ib = KVs3. However, since the V / I conversion circuit 34 actually has the temperature coefficient e, the current Ib is expressed by the following equation 3 become that way.
Ib = eKVs3 (Formula 3)

The I / V conversion circuit 36 is supplied with the current Ib from the V / I conversion circuit 34, and generates a voltage Vo by current-voltage conversion of the current Ib. The I / V conversion circuit 36 includes a resistor R3. One end of the resistor R3 is connected to the collector of the transistor Q2, and the other end is connected to the V / I conversion circuit 35 (resistor R5). If the impedance of the I / V conversion circuit 36 is Z, the voltage Vo = IbZ. However, since the I / V conversion circuit 36 actually has a temperature coefficient d, the voltage Vo is expressed by the following equation 4. It becomes like this.
Vo = dIbZ (Formula 4)

  Further, as shown in FIG. 4, in order to add the current Δi obtained by converting the audio signal eS to voltage / current to the DC bias current Ic, the current generation circuit 14 is further provided with addition means including an operational amplifier 37 and a resistor R4. The audio signal generation source AU is connected to the non-inverting input terminal of the operational amplifier 37, the inverting input terminal is connected to the ground potential via the resistor R4, and is connected to the output terminal of the operational amplifier 37 via the resistor R3. Yes. Therefore, when the amplitude of the audio signal eS is not 0, a voltage obtained by adding a voltage based on the audio signal eS to the voltage Vo is supplied to the V / I conversion circuit 35 in the subsequent stage. On the other hand, when the amplitude of the audio signal eS is 0, only the voltage Vo is supplied to the V / I conversion circuit 35. As described above, in the following description of the current generation circuit 14, a case where the amplitude of the audio signal eS is 0 will be described as an example.

The V / I conversion circuit 35 is supplied with the voltage Vo from the I / V conversion circuit 36 and generates a charging current Ij (DC bias current Ic) by converting the voltage Vo into voltage-current. (As described above, when the amplitude of the audio signal eS is not 0, the V / I conversion circuit 35 generates a current Δi based on the DC bias current Ic + the audio signal eS as the charging current Ij.) V / I The conversion circuit 35 includes a transistor Q3, a resistor R5, and a voltage source 38. The base of the transistor Q3 is connected to the positive side of the voltage source 38, the emitter thereof is connected to the I / V conversion circuit 36 (resistor R3) via the resistor R5, and the collector is a node that outputs the charging current Ij. . That is, the collector of the transistor Q3 is connected to the first capacitor C1 via the first switch SW1, and is connected to the second capacitor C2 via the second switch SW2. If the conversion conductance of the V / I conversion circuit 35 is G, the DC bias current Ic = GVo. However, since the V / I conversion circuit 36 actually has the temperature coefficient c, the DC bias current Ic Is as shown in Equation 5 below.
Ic = cGVo (Formula 5)

  As described above, the discharge current Id is generated by the voltage Vs2 from the voltage source 31, and the charging current Ij (DC bias current Ic) is also generated from the common voltage source 31. Therefore, even if the discharge current Id and the DC bias current Ic fluctuate due to the temperature coefficient, the ratio of the current values of the DC bias current Ic and the discharge current Id can be maintained in the relationship of Ic: Id = 1: 2. That is, even if the DC bias current Ic increases and the charging end voltage of the first and second capacitors C1 and C2 increases, the discharge current Id also increases at the same rate. The time until the voltage of C2 reaches the threshold voltage does not vary with temperature. Even if the discharge current Id increases and the discharge speed of the first and second capacitors C1 and C2 increases, the DC bias current Ic also increases at the same rate, so that the charging of the first and second capacitors C1 and C2 is performed. The time until the end voltage increases and the voltage of the first and second capacitors C1, C2 reaches the threshold voltage due to discharge by the discharge current Id does not vary with temperature. As a result, even if the discharge current Id and the DC bias current Ic fluctuate due to the temperature coefficient, the pulse width modulation signal PWMout that accurately corresponds to the audio signal eS can be output. This effect is further prominent by the provision of a voltage source 32 for canceling the influence of the temperature coefficient.

Hereinafter, conditions of the voltage value Vm and the temperature coefficient f of the voltage source 32 for maintaining the ratio of the DC bias current Ic and the discharge current Id in a 1: 2 relationship will be described. Substituting Equations 2 to 4 into Equation 5 above converts the DC bias current Ic into Equation 6 below.
Ic = (aVs2 + fVm) · cde · KZG (Formula 6)

Subsequently, when the formula 1 is substituted into the formula 6, the relationship between the DC bias current Ic and the discharge current Id is expressed by the following formula 7.

Here, in order not to include each temperature coefficient in the relationship between the DC bias current Ic and the discharge current Id, Ic = XId (where X does not include each temperature coefficient). Therefore, when X = KZG / H and Ic = XId is substituted into the above equation 7, the following equation 8 is obtained.

In order to calculate the condition between the voltage value Vm of the voltage source 32 and the temperature coefficient f, when the above equation 8 is expanded for fVm, the following equation 9 is obtained.

Finally, when the above equation 1 is substituted into the above equation 9, the voltage value Vm and the temperature coefficient f of the voltage source 32 are obtained as the following equation 10.

  Accordingly, the relationship between the voltage value Vm of the voltage source 32 and the temperature coefficient f is set as shown in the above equation 10 and X = KZG / H = 1/2, so that the discharge current Id and the DC bias are changed depending on the temperature. Even when the current Ic fluctuates, the ratio of the DC bias current Ic to the discharge current can be maintained in a 1: 2 relationship.

In the above description, the case where each V / I conversion circuit has conversion conductance has been described. However, depending on the circuit configuration, the current after V / I conversion may be expressed as a function of voltage. At this time, a comprehensive function in each V / I conversion circuit is represented by current f (x) = Ax + B (where x is a voltage). In this case, when the constant term B is taken into consideration and the overall temperature coefficient in each V / I conversion circuit is set to h, the above equation 7 becomes the following equation 7 ′.

Similarly to the above description, the voltage value Vm and the temperature coefficient f of the voltage source 32 are obtained by the following equation 10 ′ using the equation 7 ′. Since the calculation method is the same as above, it is omitted.

[Operation of pulse width modulation circuit]
Next, the operation of the pulse width modulation circuit 1 will be described with reference to the time charts of FIGS.

  FIG. 5 is a time chart when the amplitude of the audio signal is 0 (that is, charging current Ij = DC bias current Ic). 5F and 5G, the solid line N1 is the voltage waveform of the capacitors C1 and C2 when the current values of the discharge current Id and the DC bias current Ic do not vary with temperature, and the broken line N2 The voltage waveforms of the capacitors C1 and C2 when the discharge current Id and the DC bias current Ic increase according to the temperature, and the broken line N3 indicates the capacitors C1 and C1 when the discharge current Id and the DC bias current Ic decrease according to the temperature. It is a voltage waveform of C2. First, the basic operation of the pulse width modulation circuit 1 in the case where the discharge current Id and the DC bias current Ic do not vary with temperature will be described.

  A high level period and a low level period of the first switching signal φ1 are a charging period and a discharging period of the first capacitor C1, respectively. When the first switching signal φ1 is inverted to the high level, the first switch SW1 connects the output node of the charging current Ij of the current generation circuit 14 to the first capacitor C1, and the first capacitor by the charging current Ij from the current generation circuit 14 is connected. Charging of C1 is started. The charging operation is continued until the first switching signal φ1 is inverted to the low level and the first switch SW1 disconnects the current generation circuit 14 (see FIGS. 5B and 5F).

  When the first switching signal φ1 is inverted to a low level and shifts to the discharge period, the third switching signal φ3 output from the first RS flip-flop circuit 17 is set to a high level by the first set signal set1 that detects the low level inversion. As a result, the third switch SW3 connects the output node of the discharge current Id of the current generation circuit 14 to the first capacitor C1, and the discharge of the first capacitor C1 by the discharge current Id from the current generation circuit 14 is started. . The discharging operation continues until the voltage of the first capacitor C1 drops to the threshold voltage Vth, whereby the third switching signal φ3 is inverted to a low level, and the third switch SW3 disconnects the current generating circuit 14 (FIG. 5). (See (b), (d), (f)).

  During the discharge period, the first set signal set1 is input from the first RS flip-flop circuit 17 and at the same time the level is inverted to a low level, and the voltage of the first capacitor C1 input as the first reset signal res1 decreases to the threshold voltage Vth. At the same time, a pulse signal that is inverted to a high level is output as an output rsout1. That is, a pulse signal having a pulse width corresponding to the amplitude of the audio signal eS is generated (see (j) in FIG. 5).

  Further, the high-level period and the low-level period of the second switching signal φ2 are a charging period and a discharging period of the second capacitor C2, respectively. If the dead time is ignored, the second switching signal φ2 is a signal obtained by inverting the phase of the first switching signal φ1, so that the second capacitor C2 is similar to the charge / discharge operation in the first capacitor C1 described above. The charging / discharging operation is performed while being shifted by a half cycle of the first switching signal φ1 (see (c), (e), (g), (i) in FIG. 5).

  Therefore, during the discharge period of the second capacitor C2, the second set signal set2 is input from the second RS flip-flop circuit 18 and at the same time inverted to a low level, and the second capacitor C2 input as the second reset signal res2 A pulse signal that is inverted to a high level at the same time that the voltage drops to the threshold voltage Vth is output as an output rsout2. That is, a pulse signal having a pulse width corresponding to the amplitude of the audio signal eS is generated (see (k) in FIG. 5).

  The output rsout1 and the output rsout2 output from the first and second flip-flop circuits 17 and 18 are synthesized by the signal output circuit 19 to be a pulse width modulation signal PWMout (a signal obtained by synthesizing the waveform of the output rsout1 and the waveform of the output rsout2). (See (l) of FIG. 5).

  As shown in FIG. 6, when the amplitude of the audio signal eS is positive, the magnitude of the charging current Ij = Ic + Δi is large, and the slope of the charging voltage waveform at one end of the first and second capacitors C1 and C2 is increased. Also, the amplitude of the audio signal eS is larger than when the amplitude is zero. Therefore, the terminal voltage of the first and second capacitors C1 and C2 at the time when the level of the first or second switching signal φ1 or φ2 is inverted from the high level to the low level is higher than that when the audio signal eS is no signal. When these are discharged by the discharge current Id, the time to reach the threshold voltage Vth after the discharge is started is longer than when the audio signal eS is no signal. Therefore, as shown in FIG. 6 (l), the pulse width modulation signal PWMout having a long high level time is output compared to the case where the audio signal eS shown in FIG. Thus, the pulse width modulation signal PWMout corresponding to the amplitude of the audio signal eS is output.

  Although not shown, similarly, when the audio signal eS is negative, the magnitude of the charging current Ij = Ic + Δi is small, and the slope of the charging voltage waveform at one end of the first and second capacitors C1, C2 is also small. . Therefore, the terminal voltage of the first and second capacitors C1 and C2 at the time when the level of the first or second switching signal φ1 or φ2 is inverted from the high level to the low level is higher than that when the audio signal eS is no signal. When these are discharged by the discharge current Id, the time to reach the threshold voltage Vth after the start of discharge is shorter than when the audio signal eS is no signal. Accordingly, the pulse width modulation signal PWMout is output with a shorter high level time than when the audio signal eS is not a signal.

  Next, a case where the amplitude of the audio signal is 0 and both the discharge current Id and the DC bias current Ic increase with temperature will be described with reference to the broken line N2 in FIG. As described above, the discharge current Id and the DC bias current Ic both increase due to temperature, but the relationship of Ic: Id = 1: 2 is maintained. Accordingly, when the first capacitor C1 is charged by the DC bias current Ic and the first switching signal φ1 is inverted from the high level to the low level, the charging end voltage of the first capacitor C1 depends on the temperature depending on the DC bias current Ic and the discharge current. Although Id is higher than that in the case of the solid line N1 that does not fluctuate, the discharge current Id also increases at the same ratio as the DC bias current Ic, so the first capacitor C1 is discharged by the discharge current Id, and the threshold value The time until the voltage Vth is reached is the same as in the case of the solid line N1. Note that, as indicated by a broken line N2 in FIG. 5G, the second capacitor C2 is similarly discharged by the discharge current Id, and the time until it reaches the threshold voltage Vth is the same as in the case of the solid line N1. As a result, although both the discharge current Id and the DC bias current Ic increase according to the temperature, a normal pulse width modulation signal PWMout can be output as in the case of the solid line N1.

  Next, a case where the amplitude of the audio signal eS is 0 and both the discharge current Id and the DC bias current Ic decrease according to the temperature will be described with reference to the broken line N3 in FIG. As described above, the discharge current Id and the DC bias current Ic both decrease due to temperature, but the relationship of Ic: Id = 1: 2 is maintained. Accordingly, when the first capacitor C1 is charged by the DC bias current Ic and the first switching signal φ1 is inverted from the high level to the low level, the charging completion voltage of the first capacitor C1 is the DC bias current Ic and the voltage depending on the temperature. Although the discharge current Id is lower than that in the case of the solid line N1 that does not fluctuate, the discharge current Id also decreases at the same rate as the DC bias current Ic, so the first capacitor C1 is discharged by the discharge current Id. The time to reach the threshold voltage Vth is the same as in the case of the solid line N1. Note that, as indicated by the broken line N3 in FIG. 5G, the second capacitor C2 is similarly discharged by the discharge current Id, and the time until the threshold voltage Vth is reached is the same as in the case of the solid line N1. As a result, although the discharge current Id and the DC bias current Ic both decrease according to the temperature, a normal pulse width modulation signal PWMout can be output as in the case of the solid line N1.

[Second Embodiment]
Next, a current generation circuit 44 according to another embodiment of the present invention will be described with reference to FIG. In the current generation circuit 44, a further voltage source 52 (for example, a diode D53) is added between the I / V conversion circuit 36 and the V / I conversion circuit 35, as compared with the current generation circuit 14 of FIG. The anode of the diode D53 is connected to the output terminal of the operational amplifier 37 and the resistor R3, and the cathode is connected to the resistor R5. The voltage source 52 adds a predetermined voltage Vn (here, a negative voltage) to the voltage Vo supplied from the I / V conversion circuit 36, and outputs a voltage Vo2. The V / I conversion circuit 35 performs voltage-current conversion on the voltage Vo2 supplied from the voltage source 52 to generate a DC bias current Ic. The other configuration is the same as that of the current generation circuit 14 in FIG.

  Also in the current generation circuit 44, the discharge current Id is generated by the voltage Vs2 from the voltage source 31, and the DC bias current Ic is generated from the same voltage source 31, and the voltage source for canceling the influence of the temperature coefficient 32 and 52 are provided. Therefore, even if the current values of the discharge current Id and the DC bias current Ic vary depending on the temperature coefficient, the ratio of the DC bias current Ic and the discharge current Id can be maintained in a 1: 2 relationship.

When the voltage value of the voltage source 52 is Vn and the temperature coefficient of the voltage source 52 is g, the voltage value of the voltage source 32 for maintaining the ratio of the DC bias current Ic and the discharge current Id in a 1: 2 relationship. The conditions of Vm, temperature coefficient f, voltage value Vn of the voltage source 52, and temperature coefficient g are as shown in the following equation 11. Since the calculation method of the following formula 11 is the same as the calculation method of the formula 10 in the current generation circuit 14, it is omitted here.

[Embodiment 3]
Next, a current generation circuit 54 according to still another embodiment of the present invention will be described with reference to FIG. In the current generation circuit 54, the voltage source 32 is removed from the current generation circuit 44 of FIG. Other configurations are the same as those of the current generation circuit 44 of FIG. Accordingly, the V / I conversion circuit 34 is supplied with the voltage Vs2 from the voltage source 31, and generates a current Ib by performing voltage-current conversion on the voltage Vs2.

  Also in the current generation circuit 54, the discharge current Id is generated by the voltage Vs2 from the voltage source 31, and the DC bias current Ic is also generated from the same voltage source 31, and the voltage source for canceling the influence of the temperature coefficient 52 is provided. Therefore, even if the discharge current Id and the DC bias current Ic fluctuate due to the temperature coefficient, the ratio of the DC bias current Ic and the discharge current Id can be maintained in a 1: 2 relationship.

[Embodiment 4]
Next, a current generation circuit 60 according to still another embodiment of the present invention will be described with reference to FIGS. 9 and 10. FIG. 9 is a block diagram showing the current generation circuit 60, and FIG. 10 is a circuit diagram showing the current generation circuit 60. The current generation circuit 60 includes a voltage source 61, voltage-current conversion circuits (hereinafter referred to as V / I conversion circuits) 62 and 63, a differential circuit 64, and a current mirror circuit 65. FIG. 9 shows only a part of the charging current Ij that generates the DC bias current Ic for the sake of simplicity. The current Δi corresponding to the audio signal eS shown in FIG. The adding means for adding to (the configuration in which the audio signal generation source AU is connected to the base of the transistor Q63) is omitted.

  The current generation circuit 60 generates the discharge current Id and the DC bias current Ic of the charging current Ij from the common voltage source 61 as in the current generation circuit of the previous embodiment. Therefore, even when the voltage Vs2 varies due to the temperature coefficient of the voltage source 61, and the DC bias current Ic and the discharge current Id vary, the variation error between the DC bias current Ic and the discharge current Id is mutual. Thus, the ratio of the current value of the DC bias current Ic and the discharge current Id can be maintained at a constant ratio (for example, Ic: Id = 1: 2).

  The V / I conversion circuit 62 is supplied with the voltage Vs2 from the voltage source 61, and generates a discharge current Id by performing voltage-current conversion on the voltage Vs2. V / I conversion circuit 62 includes a transistor Q61 and a resistor R61. The transistor Q61 has a base connected to the positive side of the voltage source 61, an emitter connected to the power supply voltage −VCC via a resistor R61, and a collector serving as a node that outputs a discharge current Id. That is, the collector of the transistor Q61 is connected to the first capacitor C1 through the third switch SW3 and is connected to the second capacitor C2 through the fourth switch SW4.

  The V / I conversion circuit 63 is supplied with the voltage Vs2 from the voltage source 61, and generates a reference current Iref by performing voltage-current conversion on the voltage Vs2. The reference current Iref is a current that serves as a reference for the discharge current Id and the DC bias current Ic. V / I conversion circuit 63 includes a transistor Q62 and a resistor R62. The transistor Q62 has a base connected to the positive side of the voltage source 61, an emitter connected to the power supply voltage -VCC via a resistor R62, and a collector connected to the differential circuit 64 (resistors R63 and R64).

  Resistors R61 and R62 employ resistance elements having the same resistance value, and transistors Q61 and Q62 employ transistors having the same characteristics (for example, conduction start voltage and internal resistance). As a result, the discharge current Id generated by the V / I conversion circuit 62 is equal to the reference current Iref generated by the V / I conversion circuit 63.

  The differential circuit 64 is connected to the VI conversion circuit 63 and generates a current Iref / 2 that is ½ of the reference current Iref supplied from the V / I conversion circuit 63 as a DC bias current Ic. Specifically, the differential circuit 64 adds a current Δi obtained by converting the audio signal eS from the audio signal source AU to a DC bias current Ic, and generates a current Iref / 2 + Δi. Differential circuit 64 includes transistors Q63 and Q64 and resistors R63 to R65. The transistor Q63 has an emitter connected to the collector of the transistor Q62 via the resistor R63, a collector connected to the collector of the transistor Q65 of the current mirror circuit 65, and a base connected to the audio signal source AU. Transistor Q64 has an emitter connected to the collector of transistor Q62 via resistor R64, a collector connected to power supply voltage VCC via resistor R65, and a base connected to the ground potential. Resistors R63 and R64 employ resistance elements having the same resistance value, and transistors Q63 and Q64 employ transistors having the same characteristics (for example, conduction start voltage and internal resistance).

  In differential circuit 64, current Iref / 2 + Δi flows from the collector of transistor Q63 toward the emitter, and current Iref / 2−Δi flows from the collector of transistor Q64 toward the emitter. Accordingly, when the amplitude value of the audio signal eS is 0 (no signal), Δi is 0, so that a current Iref / 2 (= Ic) flows from the collector of the transistor Q63 toward the emitter, and the transistor Q64. Current Iref / 2 (= Ic) flows from the collector to the emitter.

  The current mirror circuit 65 is a circuit that supplies a current having the same current value as the current Iref / 2 + Δi flowing through the transistor Q63 of the differential circuit 64 to the capacitors C1 and C2 as the charging current Ij. Current mirror circuit 65 includes transistors Q65 and Q66 and resistors R66 and R67. Transistor Q65 has a collector connected to the collector of transistor Q63, an emitter connected to power supply voltage VCC via resistor R66, and a base connected to the base of transistor Q66. Transistor Q66 has an emitter connected to power supply voltage VCC via resistor R67, and a collector serving as a node for outputting charging current Ij. That is, the collector of the transistor Q66 is connected to the first capacitor C1 through the first switch SW1, and is connected to the second capacitor C2 through the second switch SW2. Resistors R66 and R67 employ resistance elements having the same resistance, and transistors Q65 and Q66 employ transistors having the same characteristics (for example, conduction start voltage and internal resistance).

  With the above configuration, since the discharge current Id = Iref and the DC bias current Ic = Iref / 2 of the charging current Ij, the relationship of DC bias current Ic: discharge current Id = 1: 2 is maintained. Can do. Since the DC bias current Ic and the discharge current Id are generated from the same voltage source 61, the voltage Vs2 from the voltage source 61 fluctuates due to the influence of the temperature coefficient of the voltage source 61. For example, the DC bias current Ic is When it fluctuates, the discharge current Id similarly fluctuates at the same ratio, so that the relationship of DC bias current Ic: discharge current Id = 1: 2 can always be maintained. Even when the conduction start voltage of the transistors Q61 and Q62 varies due to the influence of the temperature coefficient, the transistors Q61 and Q62 have the same characteristics, and therefore the conduction start voltage varies at the same ratio. Even when the resistance values of the resistors R61 and R62 vary due to the influence of the temperature coefficient, the resistors R61 and R62 have the same characteristics, and therefore the resistance values vary at the same ratio. The same applies to the relationship between the transistors Q63 and Q64, the relationship between the resistors R63 and R64, the relationship between the transistors Q65 and Q66, and the relationship between the resistors R66 and R67. Therefore, the relationship of DC bias current Ic: discharge current Id = 1: 2 can always be maintained even under the influence of the temperature coefficient. Note that the operation of the entire pulse width modulation circuit when the current generation circuit 60 is used is the same as the operation described with reference to FIGS.

[Embodiment 5]
Next, a pulse width modulation circuit 1 ′ according to another embodiment of the present invention will be described. FIG. 11 is a block circuit diagram showing the main part of the pulse width modulation circuit 1 ′. In FIG. 11, only the parts different from FIG. 2 are described, and the reference clock generation circuit 11, the dead time generation circuit 12, the falling edge circuit 13, the first RS flip-flop circuit 17, the second RS flip-flop circuit 18, and The signal output circuit 19 is omitted. The pulse width modulation circuit 1 ′ is obtained by reversing the direction of voltage change of the first and second capacitors C1 and C2 during the charge / discharge period. That is, the directions of the charging current Ij (= Ic + Δi) and the discharging current Id are opposite to those of the pulse width modulation circuit 1 of FIG. Is discharged (that is, charged in the negative direction with respect to the ground potential), and the first capacitor C1 is charged with the discharge current Id while the first switching signal φ1 is at the low level (that is, discharged in the positive direction with respect to the ground potential). ) The pulse width modulation circuit 1 ′ is provided with comparison circuits 27 and 28 for comparing the charging voltages of the first and second capacitors C1 and C2 with the reference voltage Vref instead of the threshold voltage. The details of the pulse width modulation circuit 1 ′ are disclosed in the prior applications 1 and 2.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment. In the above embodiment, diodes are used for the voltage sources 32 and 52 in order to simplify the circuit configuration, but a normal voltage source may be used. The constant ratio between the DC bias current Ic and the discharge current Id is not limited to 1: 2, but may be 1: 1 or 2: 3 depending on the circuit configuration.

  The present invention can be suitably applied to a pulse width modulation circuit of an audio switching amplifier.

1, 1 'pulse width modulation circuit 2 switching circuit 3 low-pass filter circuit 4 first power supply 5 second power supply 11 reference clock generation circuit 12 dead time generation circuit 13 falling edge detection circuit 14 current generation circuit 16 current bypass circuit 17 first RS Flip-flop circuit 18 second RS flip-flop circuit 19 signal output circuit 23 voltage source C1 first capacitor C2 second capacitor eS audio signal Ic DC bias current Id discharge current res1 first reset signal res2 second reset signal set1 first set signal set2 Second set signal SW1 First switch SW2 Second switch SW3 Third switch SW4 Fourth switch Vth Threshold voltage φ1 First switching signal φ2 Second switching signal φ3 Third switching signal φ4 Fourth switching signal

Claims (11)

First charge storage means for storing charge;
Second charge storage means for storing charge;
Current generating means for generating a first current whose current value changes according to the amplitude of the AC voltage from the input AC voltage, and generating a second current;
The voltage in the first charge storage means is changed in a first period which is a half cycle of a predetermined clock signal based on the first current, and a half cycle shift from the first period based on the second current. In the second period following the first period, the voltage in the first charge storage means is changed in the direction opposite to the increase / decrease direction in the first period, and the second charge storage means is changed based on the first current. The voltage in the second charge storage means is changed in the second period in the third period following the second period shifted by a half cycle from the second period based on the second current. Voltage control means for changing in the opposite direction;
First detection means for detecting a time from when the second period starts until the voltage in the first charge storage means reaches a threshold voltage;
Second detection means for detecting a time from when the third period starts until the voltage in the second charge storage means reaches the threshold voltage;
A pulse signal generation unit that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection unit and the second detection unit every half cycle of the clock signal;
The current generating means is
A first voltage source for supplying a first power supply voltage;
First voltage-current conversion means for generating the second current based on the first power supply voltage supplied from the first voltage source;
A pulse width modulation circuit comprising: a second voltage-current conversion unit configured to generate the first current based on the first power supply voltage supplied from the first voltage source and the AC voltage. The current generating means further comprises a second voltage source for supplying a second power supply voltage;
The second voltage-to-current conversion means is configured to convert the first power supply voltage supplied from the first voltage source, the second power supply voltage supplied from the second voltage source, and the AC voltage. The pulse width modulation circuit according to claim 1, wherein the first current is generated based on the first current. The second voltage / current conversion means comprises:
Third voltage-to-current conversion for generating a third current based on the first power supply voltage supplied from the first voltage source and the second power supply voltage supplied from the second voltage source Means,
Current-voltage conversion means for generating a third voltage based on the third current supplied from the third voltage-current conversion means;
Adding means for adding the third voltage and the alternating voltage to generate a fourth voltage;
The pulse width modulation circuit according to claim 2, further comprising a fourth voltage-current conversion unit that generates the first current based on the fourth voltage. The current generating means further comprises a third voltage source for supplying a third power supply voltage;
The second voltage / current conversion means comprises:
Third voltage-to-current conversion for generating a third current based on the first power supply voltage supplied from the first voltage source and the second power supply voltage supplied from the second voltage source Means,
Current-voltage conversion means for generating a third voltage based on the third current supplied from the third voltage-current conversion means;
Adding means for adding the third voltage and the alternating voltage to generate a fourth voltage;
3. The pulse width modulation circuit according to claim 2, further comprising a fourth voltage-current conversion unit configured to generate the first current based on the fourth voltage and the third power supply voltage. The second voltage / current conversion means comprises:
Third voltage-current conversion means for generating a third current based on the first power supply voltage supplied from the first voltage source;
Current-voltage conversion means for generating a third voltage based on the third current supplied from the third voltage-current conversion means;
Adding means for adding the third voltage and the alternating voltage to generate a fourth voltage;
3. The pulse width modulation circuit according to claim 2, further comprising a fourth voltage-current conversion unit configured to generate the first current based on the fourth voltage and the second power supply voltage. The second voltage / current conversion means comprises:
Third voltage-current conversion means for generating a third current having the same current value as the second current based on the first power supply voltage supplied from the first voltage source;
A differential circuit for generating a fourth current obtained by adding a current based on the AC voltage to a current that is ½ of the third current;
The pulse width modulation circuit according to claim 1, further comprising: a current mirror circuit that generates the first current having the same current value as the fourth current.   The pulse width modulation circuit according to claim 1, wherein the first and second charge storage units are charged with the first current and discharged with the second current.   The pulse width modulation circuit according to any one of claims 1 to 6, wherein the first and second charge storage units are discharged with the first current and charged with the second current. A switching signal generating means for generating a switching signal for determining the switching timing of each period based on the clock signal;
A falling detection means for detecting a falling edge of the switching signal generated by the switching signal generating means,
The first detection means includes
A first flip-flop that inputs the charging voltage accumulated in the first charge accumulating means in the second period as a reset signal and the falling edge signal of the switching signal detected by the falling detection means as a set signal Configured by
The second detection means includes
A second flip-flop for inputting the charging voltage accumulated in the second charge accumulating means in the third period as a reset signal and inputting the falling edge signal of the switching signal detected by the falling detection means as a set signal Configured by
The pulse signal generation means includes
9. The pulse width modulation circuit according to claim 1, wherein the pulse signal is generated based on an output of the first flip-flop means and an output of the second flip-flop means. First voltage maintaining means for maintaining the voltage in the first charge storage means at the threshold voltage until the third period starts after the voltage in the first charge storage means reaches the threshold voltage;
The voltage in the second charge storage means is maintained until the fourth period following the third period, which is shifted from the third period by half a period after the voltage in the second charge storage means reaches the threshold voltage. The pulse width modulation circuit according to claim 1, further comprising second voltage maintaining means for maintaining the threshold voltage. The pulse width modulation circuit according to any one of claims 1 to 10,
A voltage source that outputs a predetermined reference power supply voltage;
A switching amplifier comprising: a switching circuit that switches the reference power supply voltage supplied from the voltage source based on a modulation signal output from the pulse width modulation circuit.

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