JP2009212299A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for which the cause of trouble in a capacitor is easily estimated, and to provide a manufacturing method thereof. <P>SOLUTION: A ferroelectric capacitor C is formed on an aluminum oxide film 10. On the aluminum oxide film 10, a pair of test terminals 13 are also formed. The test terminals 13 consist of a conductor such as a platinum film. An aluminum oxide film 21 is formed as a protective film for covering the test terminals 13 and the ferroelectric capacitor C. The aluminum oxide films 21 and 10 protect the ferroelectric capacitor C against the infiltration of hydrogen. On the aluminum oxide film 21, a silicon oxide film 22 is formed. The raw material of the silicon oxide film 22 is, for example, TEOS. The test terminals 13 are electrically connected to a portion of an interconnection 28 which serves as an external pad. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device suitable for a ferroelectric memory and a manufacturing method thereof.

  In recent years, with the progress of digital technology, there is an increasing tendency to process or store a large amount of data at high speed. For this reason, high integration and high performance of semiconductor devices used in electronic devices are required.

Therefore, semiconductor memory devices using a ferroelectric film as a capacitor insulating film for capacitors have been put into practical use. Such a semiconductor memory device is called a ferroelectric memory (Ferro-electric Random Access Memory). As the material of the ferroelectric film, metal oxides such as PZT (Pb (Zr _x , Ti _1−x ) O ₃ ) and BiT (Bi ₄ Ti ₃ O ₁₂ ) are used.

However, if the heat treatment is performed with the ferroelectric capacitor adsorbing moisture or in the vicinity of the ferroelectric capacitor, the ferroelectric film is reduced by the hydrogen contained in the moisture, and the ferroelectric characteristics are reduced. Will fall. When an interlayer insulating film is formed using TEOS (tetraethylorthosilicate) after the formation of the ferroelectric capacitor, the amount of inversion polarization of the ferroelectric film is reduced (FIG. 4), or the hysteresis loop is moved to the positive voltage side. Or shift (FIG. 5). That is, the characteristic indicated by the solid hysteresis loop in FIGS. 4 and 5 changes to the characteristic indicated by the dashed hysteresis loop. In addition, such a deterioration in characteristics may occur not only during manufacturing but also after manufacturing. If the characteristics of the ferroelectric film deteriorate, a malfunction occurs in the ferroelectric memory. That is, normal writing and reading cannot be performed. However, it cannot be said that all causes of malfunction are deterioration of characteristics of the ferroelectric film. According to Non-Patent Document 1, the hydrogen content is preferably 5 × 10 ¹⁹ atoms / cm ³ or less, but in the interlayer insulating film formed using TEOS, 5 × 10 ²⁰ atoms / cm 3 is used. ^{About 3} hydrogen is contained.

  Therefore, conventionally, in order to determine whether the cause of the malfunction of the ferroelectric memory is the deterioration of the characteristics of the ferroelectric film, polishing is performed from the surface of the ferroelectric memory to expose the ferroelectric film, The moisture content is measured above.

  However, this method requires a lot of processing necessary for inspection, and takes a lot of time and money. Although it is conceivable to measure the water content by secondary ion mass spectroscopy (SIMS), in many ferroelectric memories, the upper electrode and a plurality of wirings and interlayer insulation are formed on the ferroelectric film. Due to the presence of the membrane, the water and hydrogen content cannot be measured accurately. In addition, the extremely small planar shape of the ferroelectric capacitor is a cause of hindering accurate measurement. That is, a lot of noise is detected.

  Such a problem exists not only in a ferroelectric capacitor but also in a semiconductor device including a capacitor having a dielectric other than a ferroelectric as a capacitive insulating film.

J.S. Cross et al, Jpn. J. Appl. Phys. Vol. 41 (2002) 698

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can easily estimate the cause of an abnormality of a capacitor.

  As a result of intensive studies to solve the above problems, the present inventor has come up with various aspects of the invention described below.

  One embodiment of a semiconductor device includes a substrate and a capacitor that is located above the substrate and includes a dielectric film sandwiched between two electrodes. Further, a pair of inspection terminals located at the same height as the capacitor with respect to the surface of the substrate, an insulating film covering the capacitor and the pair of inspection terminals, and a conductive portion provided in the insulating film And a pair of external pads electrically connected to the pair of inspection terminals.

  In one aspect of the method for manufacturing a semiconductor device, a capacitor formed by sandwiching a dielectric film between two electrodes and a pair of inspection terminals above the substrate are placed at the same height with respect to the surface of the substrate. Then, an insulating film is formed to cover the capacitor and the pair of inspection terminals. Then, a pair of external pads are formed which are electrically connected to the pair of inspection terminals via a conductive portion provided in the insulating film.

  According to the semiconductor device or the like, the electrical characteristics between the pair of inspection terminals can be easily measured, and the state around the capacitor can be estimated based on this measurement. Therefore, the cause of the abnormality of the capacitor can be easily estimated.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing the structure of a ferroelectric memory (semiconductor device) according to an embodiment of the present invention.

  In this ferroelectric memory, an element isolation insulating film 2 that partitions an element active region is formed on the surface of a semiconductor substrate 1 such as a Si substrate. A transistor T including a gate insulating film 3, a gate electrode 4, a silicide layer 5, and sidewalls 6 is formed in the element active region partitioned by the element isolation insulating film 2. The transistor (MOSFET) T is also provided with a source / drain diffusion layer including a low concentration diffusion layer 51 and a high concentration diffusion layer 52. A silicon oxynitride film 7 covering the transistor T is formed on the entire surface, and a silicon oxide film 8 is formed thereon. The surface of the silicon oxide film 8 is flattened. Further, a silicon oxynitride film 9 and an aluminum oxide film 10 are formed in this order on the silicon oxide film 8.

  On the aluminum oxide film 10, a ferroelectric capacitor C including a lower electrode 12, a capacitive insulating film 16 and an upper electrode 17 is formed. The lower electrode 12 is made of platinum, for example. The capacitor insulating film 16 is made of a ferroelectric material such as a PZT film. The upper electrode 17 is made of, for example, iridium oxide. A pair of inspection terminals 13 are formed on the aluminum oxide film 10. The inspection terminal 13 is made of a conductor such as a platinum film, and has an impedance of about 50Ω. The aluminum oxide film 10 functions as an adhesion film between the lower electrode 12 and the inspection terminal 13 and the silicon oxynitride film 9.

An aluminum oxide film 21 covering the inspection terminal 13 and the ferroelectric capacitor C is formed as a protective film. The aluminum oxide films 21 and 10 protect the ferroelectric capacitor C from intrusion of hydrogen. The diffusion coefficient of hydrogen in aluminum oxide is very low, about 1 × 10 ⁻¹⁶ cm ² / sec at 300 ° C. A silicon oxide film 22 is formed on the aluminum oxide film 21. The silicon oxide film 22 is made of, for example, TEOS, and the hydrogen concentration in the silicon oxide film 22 is 1 × 10 ¹⁹ atoms / cm ³ or more. Further, the surface of the silicon oxide film 22 is planarized.

  A hole reaching the transistor T is formed in the silicon oxide film 22, the aluminum oxide film 21, the aluminum oxide film 10, the silicon oxynitride film 9, the silicon oxide film 8, and the silicon oxynitride film 7, and a conductive plug 23 is formed therein. Form. The conductive plug 23 is made of, for example, tungsten and a barrier metal (titanium, titanium nitride, etc.). Furthermore, a hole reaching the ferroelectric capacitor C and a hole reaching the inspection terminal 13 are also formed in the silicon oxide film 22 and the aluminum oxide film 21. A conductive plug 25 is formed in the hole reaching the inspection terminal 13. The upper end of the conductive plug 25 extends to the silicon oxide film 22. A wiring 24 is formed in the hole reaching the lower electrode 12 of the ferroelectric capacitor C and in the hole reaching the upper electrode 17. A part of the wiring 24 electrically connects the upper electrode 17 and the conductive plug 23. The wiring 24 and the conductive plug 25 are made of, for example, aluminum.

  A silicon oxide film 26 covering the wiring 24 and the conductive plug 25 is formed on the silicon oxide film 22 as an interlayer insulating film. The silicon oxide film 26 is made of, for example, TEOS. Further, the surface of the silicon oxide film 26 is planarized. A hole reaching the wiring 24 and the conductive plug 25 is formed in the silicon oxide film 26, and the conductive plug 25 is embedded in these holes. The conductive plug 25 is made of, for example, tungsten and barrier metal (titanium, titanium nitride, etc.).

  A wiring 28 electrically connected to the conductive plug 27 is formed on the silicon oxide film 26. A plurality of wiring layers including the silicon oxide film 26, the conductive plugs 27, and the wirings 28 are provided to form a multilayer wiring structure. A cover film 31 is formed to cover the whole. The cover film 31 has a plurality of openings that expose a part of the wiring 28 located in the uppermost layer. And the part exposed from the opening part of the wiring 28 is used as an external pad (external terminal). A pair of external pads are provided corresponding to the pair of inspection terminals 13.

  In the ferroelectric memory configured as described above, the electrical characteristics (the magnitude of electrical resistance and the magnitude of capacitance) between the pair of test terminals 13 change according to the amount of water in the aluminum oxide films 21 and 10. . Therefore, the relationship between the amount of moisture in the aluminum oxide films 21 and 10 and the electrical characteristics (the magnitude of the electrical resistance and the magnitude of the capacitance, etc.) is previously determined using the ferroelectric memory manufactured through the same processing. If acquired, the amount of water in the aluminum oxide films 21 and 10 can be recognized only by measuring the electrical characteristics between the inspection terminals 13. That is, the amount of moisture in the aluminum oxide films 21 and 10 located in the immediate vicinity of the ferroelectric capacitor C can be recognized. Therefore, it is possible to easily determine whether or not the cause of the abnormality that has occurred after the start of use is the lack of protection by the aluminum oxide films 21 and 10.

  Further, unlike SIMS, the characteristics of the aluminum oxide films 21 and 10 are directly measured, so that measurement with high accuracy is possible.

  Note that the position in plan view where the pair of inspection terminals 13 are provided is not particularly limited. However, when the memory cell array includes dummy word lines and dummy bit lines, each dummy word line and dummy bit line is provided. It is preferably located in the vicinity thereof. Further, when there are few area restrictions, it may be provided for each memory cell.

  In the present embodiment, the inspection terminal 13 is sandwiched between the aluminum oxide films 21 and 10. However, even if only one of the aluminum oxide films is present, the amount of moisture in the vicinity of the ferroelectric capacitor C is reduced. It is possible to guess.

  The material of the inspection terminal 13 is not limited, but when measurement is performed using a high frequency signal in the MHz band, it is preferable to use a material having an impedance of about 50Ω in order to suppress ringing and the like.

  Next, a method for manufacturing the above-described ferroelectric memory will be described. 2A to 2G are cross-sectional views showing a method of manufacturing a ferroelectric memory (semiconductor device) in the order of steps.

First, as shown in FIG. 2A, an element isolation insulating film 2 is formed on the surface of a semiconductor substrate 1 by, for example, a LOCOS (Local Oxidation of Silicon) method. Next, the transistor T is formed in the element active region partitioned by the element isolation insulating film 2. As the gate insulating film 3, for example, a SiO ₂ film having a thickness of about 100 nm is formed by thermal oxidation. Thereafter, a silicon oxynitride film 7 is formed on the entire surface so as to cover the MOSFET, and a silicon oxide film 8 is further formed on the entire surface. The silicon oxynitride film 7 is formed to prevent hydrogen deterioration of the gate insulating film 3 and the like when the silicon oxide film 8 is formed. The silicon oxide film 8 is formed by a CVD method using TEOS as a raw material, and the thickness thereof is about 700 nm.

Subsequently, the silicon oxide film 8 is degassed by performing an annealing process at 650 ° C. for 30 minutes in an N ₂ atmosphere. Next, a silicon oxynitride film 9 is formed on the silicon oxide film 8, and an aluminum oxide film 10 having a thickness of about 10 nm to 100 nm is formed thereon as an adhesion film by, eg, sputtering. Thereafter, a platinum film 11 having a thickness of about 150 nm is formed on the aluminum oxide film 10 by, eg, sputtering.

  Subsequently, the platinum film 11 is patterned to form a lower electrode 12 and a pair of inspection terminals 13 as shown in FIG. 2B. Following the patterning of the platinum film 11, the aluminum oxide film 10 may be patterned.

Next, as shown in FIG. 2C, a PZT film 14 covering the lower electrode 12 and the inspection terminal 13 is formed on the entire surface, and further an iridium oxide film 15 is formed thereon. In forming the PZT film 14, for example, after deposition in an amorphous state by a sputtering method, heat treatment (RTA: Rapid Thermal Annealing) at 650 ° C. or less is performed in an atmosphere containing Ar and O _2. Then, RTA is performed at 750 ° C. in an oxygen atmosphere. As a result, a crystallized PZT film 14 is obtained, and the platinum film constituting the lower electrode 12 and the inspection terminal 13 is densified, and Pt and O in the vicinity of the interface between the lower electrode 12 and the inspection terminal 13 and the PZT film 14 are obtained. And mutual diffusion are suppressed. The iridium oxide film 15 is formed by sputtering, for example, and the thickness thereof is about 150 nm to 300 nm.

  Thereafter, the iridium oxide film 15 is patterned to form the upper electrode 17 as shown in FIG. 2D. Subsequently, heat treatment is performed in an atmosphere containing oxygen for recovering damage caused by patterning. Next, by patterning the PZT film 14, a capacitive insulating film 16 is formed as shown in FIG. 2D. Thereafter, oxygen annealing for preventing peeling of an aluminum oxide film to be formed later is performed. A ferroelectric capacitor C is composed of the lower electrode 12, the capacitive insulating film 16 and the upper electrode 17.

Subsequently, as shown in FIG. 2E, an aluminum oxide film 21 is formed on the entire surface by sputtering. The thickness of the aluminum oxide film 21 is about 10 nm to 100 nm. Next, oxygen annealing is performed in order to reduce damage caused by sputtering. The aluminum oxide film 21 prevents hydrogen from entering the ferroelectric capacitor C from the outside. Next, a silicon oxide film 22 is formed as an interlayer insulating film on the entire surface by a high density plasma method. When TEOS is used as a raw material for the silicon oxide film 22, the hydrogen concentration in the silicon oxide film 22 is 1 × 10 ¹⁹ atoms / cm ³ or more. The thickness of the silicon oxide film 22 is, eg, about 1.5 μm. Thereafter, the silicon oxide film 22 is planarized by a CMP (Chemical Mechanical Polishing) method. Subsequently, plasma processing using N ₂ O gas is performed. As a result, the surface layer portion of the silicon oxide film 22 is slightly nitrided, making it difficult for moisture to enter the inside. This plasma treatment is effective if a gas containing at least one of N and O is used.

  Next, as shown in FIG. 2F, the holes reaching the silicide layer 5 on the high-concentration diffusion layer 52 of the transistor T are formed into silicon oxide film 22, aluminum oxide film 21, aluminum oxide film 10, silicon oxynitride film 9, silicon An oxide film 8 and a silicon oxynitride film 7 are formed. Then, a barrier metal film (not shown) is formed by continuously forming a Ti film and a TiN film in the hole by sputtering. Subsequently, a conductive film 23 is formed by embedding a W film in the hole by CVD (chemical vapor deposition) and planarizing the W film by CMP.

  Next, a silicon oxynitride film (not shown) is formed as an antioxidant film for the conductive plug 23 by, for example, a plasma enhanced CVD method. Subsequently, a hole reaching the upper electrode 17, a hole reaching the lower electrode 12, and a hole reaching the inspection terminal 13 are formed in the silicon oxynitride film, the silicon oxide film 22, and the aluminum oxide film 21. Thereafter, oxygen annealing is performed to recover the damage. Subsequently, the surface of the conductive plug 23 is exposed by removing the silicon oxynitride film over the entire surface by etching back. Subsequently, a conductive film is formed in a state where a part of the surface of the upper electrode 17, a part of the surface of the lower electrode 12, a part of the surface of the inspection terminal 13, and the surface of the conductive plug 23 are exposed. By performing the patterning, the wiring 24 and the conductive plug 25 are formed. At this time, for example, the conductive plug 23 and the upper electrode 17 are connected to each other by a part of the wiring 24. As the conductive film, for example, an Al film and a conductive barrier film are formed. As the conductive barrier film, for example, a TiN film, TiSiN film, TaN film, CrN film, HfN film, ZrN film, TiAlN film, TaAlN film, CrAlN film, HfAlN film, or the like can be used. Moreover, you may laminate | stack these. Further, a silicide film such as a TiSi film or CoSi may be used as the conductive barrier film.

  Next, as shown in FIG. 2G, a silicon oxide film 26 is formed as an interlayer insulating film on the entire surface by a high density plasma method, and the surface thereof is flattened. Thereafter, a hole reaching the wiring 24 and the conductive plug 25 is formed in the silicon oxide film 26, and the conductive plug 27 is embedded therein. Subsequently, a wiring 28 electrically connected to the conductive plug 27 is formed on the silicon oxide film 26. Thereafter, a plurality of wiring layers including the silicon oxide film 26, the conductive plug 27, and the wiring 28 are formed.

  Then, a cover film 31 is formed on the entire surface, and an opening that exposes a part of the wiring 28 located in the uppermost layer is formed in the cover film 31 as an external pad opening. In this way, a ferroelectric memory having a ferroelectric capacitor is completed.

  According to such a method, it is possible to easily determine whether or not the cause of the abnormality that has occurred after the start of use is the lack of protection by the aluminum oxide films 21 and 10. A capacitor can be obtained.

  In addition, although the measurement of the amount of water after the start of use is not necessary, the measurement of the amount of water before the start of use may be required. In other words, it may be sufficient to know only whether the manufacturing process is suitable for suppressing the diffusion of hydrogen. In such a case, the inspection terminal 13 may be formed on the scribe line. In the case where the inspection terminal 13 is provided on the scribe line, if the moisture content is measured before dicing, the inspection terminal 13 does not remain in the ferroelectric memory. Is possible.

  Further, as shown in FIG. 3, the aluminum oxide film 21 may be removed from the periphery of the inspection terminal 13, and only the aluminum oxide film 10 may be in contact with the inspection terminal 13. Further, when the aluminum oxide film 10 is not formed, the aluminum oxide film 21 may be formed so as to cover the inspection terminal 13. Further, if a correlation of electrical characteristics with the amount of moisture in the insulating film (for example, aluminum oxide film) directly covering the ferroelectric capacitor C can be obtained, it is electrically present between the pair of inspection terminals 13. The material of the insulating film is not limited to aluminum oxide.

  Further, the structure of the ferroelectric capacitor need not be a planar structure, but may be a stack structure.

  Furthermore, the present invention can also be applied to a semiconductor device provided with a capacitor formed using a capacitor insulating film made of a dielectric other than a ferroelectric.

1 is a cross-sectional view showing a structure of a ferroelectric memory according to an embodiment. It is sectional drawing which shows the manufacturing method of the ferroelectric memory which concerns on embodiment. FIG. 2B is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. FIG. 2B is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 2B. FIG. 2D is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 2C. FIG. 2D is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 2D. FIG. 2E is a cross-sectional view showing a method for manufacturing the ferroelectric memory, following FIG. 2E. FIG. 2F is a cross-sectional view showing the manufacturing method of the ferroelectric memory, following FIG. 2F. It is sectional drawing which shows the structure of the ferroelectric memory which concerns on other embodiment. It is a graph which shows the fall of the amount of inversion polarizations. It is a graph which shows the shift of a hysteresis loop.

Explanation of symbols

C: Ferroelectric capacitor T: Transistor 12: Lower electrode 16: Capacitance insulating film 17: Upper electrode 10, 21: Aluminum oxide film 13: Inspection terminal

Claims (6)

A substrate,
A capacitor positioned above the substrate and having a dielectric film sandwiched between two electrodes;
A pair of inspection terminals located at the same height as the capacitor with respect to the surface of the substrate,
An insulating film covering the capacitor and the pair of inspection terminals;
A pair of external pads electrically connected to the pair of inspection terminals via a conductive portion provided in the insulating film;
A semiconductor device comprising: A first aluminum oxide film directly covering the capacitor;
A second aluminum oxide film in contact with the pair of inspection terminals;
The semiconductor device according to claim 1, comprising: Forming a capacitor formed by sandwiching a dielectric film between two electrodes and a pair of inspection terminals above the substrate at the same height with respect to the surface of the substrate;
Forming an insulating film covering the capacitor and the pair of inspection terminals;
Forming a pair of external pads electrically connected to the pair of inspection terminals via a conductive portion provided in the insulating film;
A method for manufacturing a semiconductor device, comprising: Forming a first aluminum oxide film directly covering the capacitor;
Forming a second aluminum oxide film in contact with the pair of inspection terminals;
The method of manufacturing a semiconductor device according to claim 3, wherein:   5. The method according to claim 3, further comprising a step of measuring electrical characteristics between the pair of inspection terminals via the pair of external pads after the step of forming the pair of external pads. A method for manufacturing a semiconductor device. Forming the pair of inspection terminals on a scribe line;
6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of dicing along the scribe line after the step of measuring the electrical characteristics.

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