JP2005116976A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the characteristics of a ferroelectric capacitor element for characteristic evaluation, which is formed on the same substrate in order to monitor the characteristic of the ferroelectric capacitor of stack type structure composing a ferroelectric memory device, from varying in a manufacturing process. <P>SOLUTION: A semiconductor device comprises a conductive layer 3 formed on a semiconductor substrate 1; a first insulating film 4 formed so as to cover the conductive layer 3 on the semiconductor substrate; a conductive plug 5 which is formed in the first insulating film 4 and whose lower end is electrically connected with the conductive layer 3; a capacitor lower electrode 6 which is formed on the first insulating film 4 and is electrically connected with the upper end of the conductive plug 5; a capacitor insulating film 7 which is composed of a ferroelectric insulating film formed on the capacitor lower electrode 6; and a capacitor upper electrode 8 which is formed on the capacitor insulating film 7. Between the semiconductor substrate 1 and the conductive layer 3, an insulating layer 2, which cuts off an electrical connection between the semiconductor substrate and the conductive layer 3, is provided. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a ferroelectric capacitor element for characteristic evaluation using a capacitive insulating film made of a ferroelectric material and a manufacturing method thereof.

  In recent years, with the progress of digital technology, the trend of high-speed processing or storage of large volumes of information has progressed, and higher integration and higher performance of semiconductor memory devices used in electronic devices are required. Yes. Under such circumstances, a ferroelectric memory device using a ferroelectric film having spontaneous polarization characteristics as a capacitive insulating film of a capacitive element constituting a semiconductor memory device has been actively researched and developed.

  A ferroelectric memory device uses the property that the polarization direction of a ferroelectric capacitor element is easily reversed by applying a relatively small external voltage, so that a certain polarization direction is represented by data “0” and vice versa. Information is stored with the polarization direction as data “1”, and has a feature of enabling a high-speed writing and reading operation at a low operating voltage that has not been conventionally available. In addition, by utilizing the property that the polarization of the ferroelectric capacitor remains as remanent polarization even if the external voltage is removed, it is possible to realize a nonvolatile memory that retains stored information for a long time even when the power is turned off. Is possible.

  In order to further realize high integration of the ferroelectric memory device, it is indispensable to reduce the size of the memory cell which is a data storage unit. In order to reduce the cell size of the memory cell, it is most effective to reduce the area occupied by the ferroelectric capacitor element constituting the memory cell. Therefore, in the current ferroelectric memory device, in order to realize high integration, it is a mainstream to adopt a structure called a stack type structure in which a ferroelectric capacitor element is formed on a contact plug.

  By the way, when a semiconductor device is manufactured on a semiconductor substrate, for the purpose of checking whether or not the semiconductor device can exhibit a desired performance, or for investigating the cause when the desired performance is not exhibited. Therefore, it is necessary to independently evaluate the characteristics of the individual elements constituting the semiconductor device. Therefore, in general, a characteristic evaluation element for monitoring the characteristics of the constituent elements of the semiconductor device is separately formed on the semiconductor substrate in addition to the semiconductor device as a product. These are generally called PCM (Process Control Monitor) or the like.

  Accordingly, when a ferroelectric memory device is manufactured on a semiconductor substrate, the characteristics of individual elements (for example, a transistor or a ferroelectric capacitor element) constituting the ferroelectric memory device are similarly set independently. A characteristic evaluation element for evaluation is formed on the same semiconductor substrate.

  As one of characteristic evaluation elements, a semiconductor device for monitoring the characteristics of a ferroelectric capacitor element that determines the performance of a ferroelectric memory device is disclosed (for example, see Patent Document 1). When manufacturing a ferroelectric memory device having a stack type structure, as is apparent from the purpose of characteristic evaluation, a ferroelectric memory having a stack type structure as an element for characteristic evaluation on the same semiconductor substrate. A device needs to be formed.

  A structure of a conventional semiconductor device formed on the same semiconductor substrate as that on which a ferroelectric memory device having a stack type structure is formed will be described below with reference to FIG.

  As shown in FIG. 6, a conductive layer 101 is formed on the surface portion of the semiconductor substrate 100, and a first insulating film 102 is formed on the semiconductor substrate 100 and the conductive layer 101. Formed on the first insulating film 102 is a first conductive plug 103 extending through the first insulating film 102 and having a lower end reaching the upper surface of the conductive layer 101. On the first insulating film 102, a capacitor lower electrode 104 connected to the first conductive plug 103, a capacitor insulating film 105 made of a ferroelectric film, and a capacitor upper electrode 106 are sequentially stacked from the bottom. A capacitor element 107 is formed.

  A second insulating film 108 is formed on the first insulating film 102 so as to cover the capacitor 107. The first and second insulating films 102 and 108 have a second conductive plug 109 extending through the first and second insulating films 102 and 108 and having a lower end reaching the upper surface of the conductive layer 101. Is formed. The second insulating film 108 is formed with a third conductive plug 110 extending through the second insulating film 108 and having a lower end connected to the capacitor upper electrode 106.

  On the second insulating film 108, a first wiring layer 111 that is electrically connected to the upper end of the second conductive plug 109, and a first wiring layer that is electrically connected to the upper end of the third conductive plug 110 are provided. 3 wiring layers 112 are formed. Note that the second insulating film 108, the first wiring layer 111, and the second wiring layer 112 are connected to an external measurement device (for example, probing a measurement probe) when actually evaluating the characteristics. It is formed to make it easier.

  As described above, the first wiring layer 111 is electrically connected to the conductive layer 101 through the second conductive plug 109, and the second wiring layer 112 is connected through the third conductive plug 110. The capacitor upper electrode 106 is electrically connected.

  In addition, a protective insulating film 113 is formed on the second insulating film 108, the first wiring layer 111, and the second wiring layer 112, and the first wiring layer is formed on the protective insulating film 113. A first opening 114 a that exposes a part of the upper surface of the first wiring layer 11 and a second opening 114 b that exposes a part of the upper surface of the second wiring layer 112 are formed.

  Next, a conventional method for manufacturing a semiconductor device will be described with reference to FIGS. 7 (a) to (c) and FIGS. 8 (a) to (c).

  First, as shown in FIG. 7A, a conductive layer 101 is formed on the surface portion of the semiconductor substrate 100, and then a first insulating film 102 is formed on the semiconductor substrate 100 and the conductive layer 101. Note that the conductive layer 101 is formed at the same time when a source region and a drain region of a transistor (not shown) included in the semiconductor device are formed by ion implantation or the like.

  Next, as shown in FIG. 7B, after forming a first opening portion communicating with the conductive layer 101 in the first insulating film 102, the lower end of the first opening portion is connected to the conductive layer 101. A first conductive plug 103 to be connected is formed.

  Next, as shown in FIG. 7C, on the first insulating film 102, a capacitor lower electrode 104 connected to the upper end of the first conductive plug 103, and a capacitor insulating film 105 made of a ferroelectric film. And the capacitor upper electrode 106 are formed in order from the bottom, thereby forming the capacitor element 107 including the capacitor lower electrode 104, the capacitor insulating film 105 and the capacitor upper electrode 106. Next, a second insulating film 108 is formed over the first insulating film 102 so as to cover the capacitor 107.

  Next, as shown in FIG. 8A, after forming a second opening communicating with the conductive layer 101 in the first insulating film 102 and the second insulating film 108, the inside of the second opening is formed. Then, a second conductive plug 109 whose lower end is connected to the conductive layer 101 is formed. In addition, after forming a third opening communicating with the capacitor upper electrode 105 in the first insulating film 102, a third conductive plug whose lower end is connected to the capacitor upper electrode 106 in the third opening. 110 is formed.

  Next, as shown in FIG. 8B, the first wiring layer 111 connected to the upper end of the second conductive plug 109 is formed on the second insulating film 108 and the third conductive film is formed. A second wiring layer 112 connected to the upper end of the conductive plug 110 is formed.

  Next, as shown in FIG. 8C, a protective insulating film 113 is formed on the second insulating film 108, the first wiring layer 111, and the second wiring layer 112, and then the protective insulating film is formed. A first opening 114 a that exposes a part of the upper surface of the first wiring layer 111 is formed in 113, and a second opening 114 b that exposes a part of the upper surface of the second wiring layer 112 is formed in 113. To do.

  As shown in FIG. 6, the conventional semiconductor device has a stacked structure in which the capacitor element 107 is formed on the first conductive plug 103, and is a ferroelectric memory device whose characteristics are to be evaluated. It has the same structure as the capacitive element formed inside.

  The first wiring layer 111 is electrically connected to the capacitor lower electrode 104 via the second conductive plug 109, the conductive layer 101, and the first conductive plug 103, while the second wiring The layer 112 is electrically connected to the capacitor upper electrode 106 through the third conductive plug 110. For this reason, the first wiring layer 111 is used as a terminal on the capacitor lower electrode 104 side, and the second wiring layer 112 is used as a terminal on the capacitor upper electrode 106 side. By applying a voltage, a voltage is applied between the capacitor upper electrode 106 and the capacitor lower electrode 104, and the characteristics of the capacitor 107 can be measured.

  Incidentally, as a characteristic of the capacitive element 107 having a capacitive insulating film made of a ferroelectric film, a polarization-voltage characteristic (hysteresis characteristic) is measured in order to confirm the spontaneous polarization performance of the capacitive element 107. In general, the polarization-voltage characteristic of a capacitive element is measured by fixing one of a capacitive upper electrode and a capacitive lower electrode at 0 V and applying a voltage waveform in both positive and negative directions to the other electrode. In this case, if the other electrode to which a voltage in both positive and negative directions is applied is connected to the semiconductor substrate, a current is generated between the other electrode and the semiconductor substrate depending on the direction of the applied voltage. The polarization-voltage characteristic cannot be measured correctly. Therefore, in the semiconductor device, at least one of the capacitor upper electrode and the capacitor lower electrode needs to be in a floating state that is not electrically connected to the semiconductor substrate.

  Therefore, in the semiconductor device illustrated in FIG. 6, the second wiring layer 112 must be in a floating state in which the second wiring layer 112 is not connected to the semiconductor substrate 100 in order to correctly measure the polarization-voltage characteristics of the capacitor 107.

  In the conventional semiconductor device shown in FIG. 6, since the capacitor element 107 has a stack type structure, the first wiring layer 111 that is a terminal on the capacitor lower electrode 104 side is connected to the semiconductor via the second conductive plug 109. The conductive layer 101 on the substrate 100 is electrically connected and is in a non-floating state. Therefore, the second wiring layer 112 that is a terminal on the capacitor upper electrode 106 side must be in a floating state in which it is not electrically connected to the semiconductor substrate 100.

With the configuration as described above, in the conventional semiconductor device, the first wiring layer 111 is fixed to 0 V, and a voltage in both positive and negative directions is applied to the second wiring layer 112, whereby the polarization-voltage characteristics of the capacitor 107 are obtained. Is measured to evaluate the characteristics of the capacitive element of the stack type structure constituting the ferroelectric memory device.
Japanese Patent No. 3194375

  In general, in the semiconductor device manufacturing process, as shown in FIG. 8C, a protective insulating film is formed on the first and second wiring layers 111 and 112 formed on the second insulating film 108. After forming 113, first and second openings 114 a and 114 b that expose the upper surfaces of the first and second wiring layers 111 and 112 are formed in the protective insulating film 113.

  The first and second openings 114a and 114b are generally formed by plasma etching such as RIE (Reactive Ion Ecthing), but plasma charges such as electrons and ions in the plasma are first generated during plasma etching. A phenomenon called charge-up accumulated on the first and second wiring layers 111 and 112 is well known. Accumulated charges on the first and second wiring layers 111 and 112 move into the element through conductive paths electrically connected to the first and second wiring layers 111 and 112.

  FIG. 9 shows the first and second openings 114a and 114b in the protective insulating film 113, in which the first and second openings 114a and 114b exposing the upper surfaces of the first and second wiring layers 111 and 112 are formed. It is the figure which showed typically a mode that the plasma charge accumulate | stored on the wiring layers 111 and 112 moved to the inside of a semiconductor device. FIG. 9 shows a case where negative plasma charges are accumulated on the first and second wiring layers 111 and 112 as an example.

  First, as a path through which the accumulated charge moves from the second wiring layer 112 to the inside of the capacitor element 107, there is a conductive path that reaches the capacitor upper electrode 106 through the third conductive plug 110. Accordingly, the accumulated charge on the second wiring layer 112 moves to the capacitor upper electrode 106 via the third conductive plug 110 as shown by the arrow b1 in FIG.

  On the other hand, as a path for the accumulated charge to move from the first wiring layer 111 to the inside of the capacitor 107, the capacitor lower electrode 104 is connected via the second conductive plug 109, the conductive layer 101, and the first conductive plug 103. There is a conductive path leading to However, after the accumulated charge on the first wiring layer 111 has moved to the conductive layer 101 via the second conductive plug 109 as shown by the arrow b2 in FIG. It moves into the semiconductor substrate 100 without moving to one conductive plug 103. The reason why such movement occurs is that the accumulated charge flows preferentially into the semiconductor substrate 100 because the semiconductor substrate 100 having a large volume has an extremely large capacity (charge accumulation capability).

  That is, in the conventional semiconductor device, the first wiring layer 111 is in a non-floating state in which the first wiring layer 111 is electrically connected to the conductive layer 100 on the semiconductor substrate 100, while the second wiring layer 112 is in the semiconductor substrate. It is in a floating state that is not electrically connected to 100. As a result, the accumulated charge on the first wiring layer 111 does not move to the capacitor lower electrode 104, but the accumulated charge on the second wiring layer 112 reaches the capacitor upper electrode 106.

  This difference causes a potential imbalance between the capacitor upper electrode 106 and the capacitor lower electrode 104. For example, in the case of the semiconductor device shown in FIG. 9, since negative charges move and accumulate only in the capacitor upper electrode 106, the potential of the capacitor upper electrode 106 is relative to the potential of the capacitor lower electrode 105. Lower. That is, a potential difference is generated between the capacitor upper electrode 106 and the capacitor lower electrode 104.

  Accordingly, spontaneous polarization occurs in the direction of eliminating the potential imbalance in the ferroelectric film constituting the capacitive insulating film 105 existing between the capacitive upper electrode 106 and the capacitive lower electrode 104. For example, in the case of the semiconductor device shown in FIG. 9, the potential imbalance that the potential of the capacitor upper electrode 106 is lower than that of the capacitor lower electrode 104 has occurred. Then, as indicated by an arrow b3 shown in FIG. 9, spontaneous polarization occurs in a direction in which the extreme on the positive side faces the capacitive upper electrode 106 side. That is, unintentional spontaneous polarization occurs during the manufacturing process of the semiconductor device.

  In general, a ferroelectric film has a property called imprint in which a tendency to fix the polarization direction becomes strong when the state where spontaneous polarization is maintained is maintained. When imprinting occurs, the polarization-voltage curve is deformed so that the voltage axis shifts to the positive side or negative side according to the direction of spontaneous polarization at the time of imprinting, and the ferroelectric film becomes a capacitive insulating film. It is known that the polarization characteristics of the used capacitive element change. Further, it is known that the progress of imprinting becomes faster as the temperature rises.

  Accordingly, when the unintentional spontaneous polarization as described above occurs in the manufacturing process of the semiconductor device, the spontaneous polarization is maintained in the subsequent process, so that the ferroelectric constituting the capacitor insulating film 105 Since imprinting occurs in the film, the characteristics of the capacitor 107 change when the semiconductor device manufacturing process is completed. Further, in the subsequent process, for example, a process of performing a high temperature process such as a drying process after cleaning the substrate is included, so that if the temperature of the ferroelectric film is increased by the high temperature process, the imprint is further performed. Since this progresses, a relatively large characteristic variation occurs in the semiconductor device.

  On the other hand, in the capacitive element constituting the ferroelectric memory device to be monitored by the above-described semiconductor device, characteristic variation due to imprinting in the above-described semiconductor device does not occur. This is because, in the capacitive element constituting the ferroelectric memory device to be monitored, a drive circuit comprising a transistor (not shown) in which a wiring layer corresponding to the second wiring layer 112 is formed on the semiconductor substrate 100. Therefore, the accumulated charge on the wiring layer corresponding to the second wiring layer 112 is not connected to the semiconductor substrate 100 in the same manner as the first wiring layer 111. 100, and does not accumulate in the capacitor upper electrode corresponding to the capacitor upper electrode 106, and no potential imbalance occurs between the capacitor upper electrode and the capacitor lower electrode in the capacitor element to be monitored. Because. As described above, the above-described characteristic variation occurs only in the above-described semiconductor device for characteristic evaluation, and the characteristic variation does not occur in the ferroelectric memory device to be subjected to characteristic evaluation.

  As described above, in the conventional semiconductor device for characteristic evaluation, only the second wiring layer 112 is used in order to correctly measure the polarization-voltage characteristic of the capacitive element 107 made of the ferroelectric film having the stack type structure. By making the floating state, accumulation of plasma charges generated during the manufacturing process of the semiconductor device differs between the capacitor upper electrode 106 and the capacitor lower electrode 104. For this reason, an imprint is generated due to a potential imbalance between the capacitor upper electrode 106 and the capacitor lower electrode 104. Therefore, the characteristics of the capacitor element 107 fluctuate in the manufacturing process of the semiconductor device. When the manufacturing process is completed, the characteristics of the capacitive element constituting the ferroelectric memory device to be monitored are different from each other. Therefore, it is difficult to perform the function as the capacitive element in the semiconductor device for characteristic evaluation. there were.

  In view of the foregoing, an object of the present invention is to provide a semiconductor capable of correctly monitoring the characteristics of a capacitive element having a stack structure that constitutes a ferroelectric memory device by preventing the occurrence of characteristic fluctuations in the manufacturing process of the semiconductor device. An apparatus and a method for manufacturing the same are provided.

  To achieve the above object, a semiconductor device according to the present invention includes a conductive layer formed on a semiconductor substrate, and a first insulating film formed on the semiconductor substrate so as to cover the conductive layer. A conductive plug formed in the first insulating film and having a lower end connected to the conductive layer; and a capacitor formed on the first insulating film and electrically connected to the upper end of the conductive plug. In a semiconductor device comprising a lower electrode, a capacitor insulating film made of a ferroelectric film formed on the capacitor lower electrode, and a capacitor upper electrode formed on the capacitor insulating film, a semiconductor substrate and a conductive layer An insulating layer for blocking electrical connection between the semiconductor substrate and the conductive layer is provided between the semiconductor substrate and the conductive layer.

  According to the semiconductor device of the present invention, since the insulating layer is formed between the conductive layer and the semiconductor substrate, the capacitor upper electrode and the capacitor lower electrode are not electrically connected to the semiconductor substrate. Therefore, the plasma charges accumulated in the capacitor upper electrode and the capacitor lower electrode are equal to each other, which is caused by the difference in plasma charge accumulation between the capacitor upper electrode and the capacitor lower electrode during the manufacturing process. It is possible to prevent a potential imbalance between the capacitor upper electrode and the capacitor lower electrode. Therefore, since imprint does not occur in the ferroelectric film, it is possible to prevent fluctuations in the characteristics of the semiconductor device. Therefore, by using the semiconductor device according to the present invention, the characteristics of the capacitive element to be evaluated can be correctly set. Can be monitored.

  In the semiconductor device according to the present invention, the second insulating film formed on the first insulating film so as to cover the capacitor upper electrode, the conductive film formed on the second insulating film, It is preferable to further include a first wiring layer that is electrically connected and a second wiring layer that is formed on the second insulating film and is electrically connected to the capacitor upper electrode. .

  In this case, the first wiring layer serving as the terminal on the capacitor lower electrode side and the second wiring layer serving as the terminal on the capacitor upper electrode side are both in a floating state in which they are not electrically connected to the semiconductor substrate. Since the plasma charge accumulated in each of the upper electrode and the capacitor lower electrode is equal, the capacitor upper electrode generated due to the difference in the accumulation of plasma charge between the capacitor upper electrode and the capacitor lower electrode during the manufacturing process It is possible to prevent potential imbalance between the capacitor and the lower electrode. For this reason, since imprint does not occur in the ferroelectric film, it is possible to prevent fluctuations in the characteristics of the semiconductor device. Therefore, the characteristics of the capacitive element to be subjected to characteristic evaluation are correctly monitored by the semiconductor device according to the present invention. be able to.

  In the semiconductor device according to the present invention, the stacked body formed of the insulating layer and the conductive layer preferably has the same structure as the stacked body formed of the gate insulating film and the gate electrode constituting the transistor formed over the semiconductor substrate.

  This makes it possible to form the insulating layer and the conductive layer simultaneously with the formation of the gate insulating film and the gate electrode constituting the transistor formed on the semiconductor substrate. Therefore, for the purpose of forming the insulating layer and the conductive layer. It is possible to realize a structure of a semiconductor device in which a new process is not added and a new material is not selected and a characteristic variation is not generated during the manufacturing process.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a conductive layer on a semiconductor substrate, a step of forming a first insulating film on the semiconductor substrate so as to cover the conductive layer, Forming a conductive plug in the insulating film so that the lower end is connected to the conductive layer, and forming a capacitor lower electrode on the first insulating film so as to be electrically connected to the upper end of the conductive plug In a method for manufacturing a semiconductor device, comprising: a step of forming a capacitor insulating film made of a ferroelectric film on a capacitor lower electrode; and a step of forming a capacitor upper electrode on the capacitor insulating film. Prior to the step of forming the layer, the method includes a step of forming an insulating layer on the semiconductor substrate that blocks electrical connection between the semiconductor substrate and the conductive layer.

  According to the method of manufacturing a semiconductor device according to the present invention, by forming an insulating layer between the conductive layer and the semiconductor substrate, the capacitor upper electrode and the capacitor lower electrode are both not electrically connected to the semiconductor substrate. Therefore, the plasma charge accumulated in each of the capacitor upper electrode and the capacitor lower electrode becomes the same, which is caused by the difference in plasma charge accumulation between the capacitor upper electrode and the capacitor lower electrode during the manufacturing process. Thus, it is possible to prevent potential imbalance between the capacitor upper electrode and the capacitor lower electrode. Therefore, since imprint does not occur in the ferroelectric film, it is possible to prevent fluctuations in characteristics of the semiconductor device. Therefore, by using the semiconductor device formed by the method for manufacturing a semiconductor device according to the present invention, the characteristic evaluation can be performed. The characteristics of the target capacitive element can be correctly monitored.

  In the method of manufacturing a semiconductor device according to the present invention, a step of forming a second insulating film on the first insulating film so as to cover the capacitor upper electrode, a conductive layer on the second insulating film, and A step of forming a first wiring layer so as to be electrically connected; and a step of forming a second wiring layer so as to be electrically connected to the capacitor upper electrode on the second insulating film. It is preferable to provide.

  In this case, the first wiring layer serving as the terminal on the capacitor lower electrode side and the second wiring layer serving as the terminal on the capacitor upper electrode side are both in a floating state in which they are not electrically connected to the semiconductor substrate. Since the plasma charge accumulated in each of the upper electrode and the capacitor lower electrode is equal, the capacitor upper electrode generated due to the difference in the accumulation of plasma charge between the capacitor upper electrode and the capacitor lower electrode during the manufacturing process It is possible to prevent potential imbalance between the capacitor and the lower electrode. For this reason, since imprint does not occur in the ferroelectric film, it is possible to prevent fluctuations in the characteristics of the semiconductor device. Therefore, the characteristics of the capacitive element to be subjected to characteristic evaluation are correctly monitored by the semiconductor device according to the present invention. be able to.

  In the semiconductor device according to the present invention, the stacked body including the insulating layer and the conductive layer is preferably formed in the same step as the step of forming the gate insulating film and the gate electrode of the transistor formed over the semiconductor substrate.

  In this case, since the insulating layer and the conductive layer can be formed simultaneously with the formation of the gate insulating film and the gate electrode constituting the transistor formed on the semiconductor substrate, the purpose is to form the insulating layer and the conductive layer. It is possible to provide a semiconductor device in which a new process is not added and a new material is not selected and a characteristic variation is not generated during the manufacturing process.

  According to the semiconductor device and the method for manufacturing the same according to the present invention, the insulating layer for cutting off the electrical connection between the semiconductor substrate and the conductive layer is formed between the semiconductor substrate and the conductive layer. Since the capacitor lower electrode is in a floating state in which both the capacitor lower electrode and the capacitor lower electrode are not electrically connected, the plasma charges accumulated in the capacitor upper electrode and the capacitor lower electrode are equal to each other. It is possible to prevent the occurrence of potential imbalance between the capacitor upper electrode and the capacitor lower electrode due to the difference in plasma charge accumulation between the electrode and the capacitor lower electrode. Therefore, since imprint does not occur in the ferroelectric film, it is possible to prevent fluctuations in the characteristics of the semiconductor device. Therefore, by using the semiconductor device according to the present invention, the characteristics of the capacitive element to be evaluated can be correctly set. Can be monitored.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

  First, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, an insulating layer 2 made of silicon oxide and a conductive layer 3 made of polycrystalline silicon are formed in order from the bottom on the semiconductor substrate 1, and on the semiconductor substrate 1, A first insulating film 4 made of silicon oxide is formed so as to cover the insulating layer 2 and the conductive layer 3. The insulating layer 2 has a role of blocking the electrical connection between the semiconductor substrate 1 and the conductive layer 3.

  Formed on the first insulating film 4 is a first conductive plug 5 made of tungsten that extends through the first insulating film 4 and whose lower end reaches the upper surface of the conductive layer 3. On the first insulating film 4, a capacitive lower electrode 6 made of platinum that is electrically connected to the first conductive plug 5, a capacitive insulating film 7 made of strontium bismuth tantalate as a ferroelectric film, and platinum A capacitor element 9 is formed by stacking a capacitor upper electrode 8 made of layers in order from the bottom.

  A second insulating film 10 made of silicon oxide is formed on the first insulating film 4 so as to cover the capacitive element 9. The first and second insulating films 4 and 10 have a second conductivity made of tungsten which extends through the first and second insulating films 4 and 10 and whose lower end reaches the upper surface of the conductive layer 3. A plug 12 is formed. The second insulating film 10 is formed with a third conductive plug 11 made of tungsten which extends through the second insulating film 10 and whose lower end is electrically connected to the capacitor upper electrode 8. Yes.

  On the second insulating film 10, a first wiring layer 13 made of aluminum connected to the upper end of the second conductive plug 11, and a first wiring layer made of aluminum connected to the upper end of the third conductive plug 12. 3 wiring layers 14 are formed. The second insulating film 10, the first wiring layer 13, and the second wiring layer 14 are connected to an external measurement device (for example, probing a measurement probe) when actually evaluating the characteristics. It is formed to make it easier.

  As described above, the first wiring layer 13 is electrically connected to the capacitor lower electrode 6 through the second conductive plug 11 and the conductive layer 3, and the second wiring layer 14 is connected to the third conductive layer. The capacitor upper electrode 8 is electrically connected through the conductive plug 12.

  A protective insulating film 15 made of silicon nitride is formed on the second insulating film 10, the first wiring layer 13, and the second wiring layer 14, and the protective insulating film 15 includes A first opening 16 a that exposes a part of the upper surface of one wiring layer 13 and a second opening 16 b that exposes a part of the upper surface of the second wiring layer 14 are formed.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2 (a) to (c) and FIGS. 3 (a) to (c).

  First, as shown in FIG. 2A, an insulating layer 2 made of silicon oxide is formed on a semiconductor substrate 1 and then a conductive layer 3 made of polycrystalline silicon is formed on the insulating layer 2. Thereafter, a first insulating film 4 made of silicon oxide is formed on the semiconductor substrate 1 so as to cover the insulating layer 2 and the conductive layer 3. The insulating layer 2 has a role of blocking the electrical connection between the semiconductor substrate 1 and the conductive layer 3.

  Next, as shown in FIG. 2 (b), after forming a first opening communicating with the conductive layer 3 in the first insulating film 4, the lower end is connected to the conductive layer 3 in the first opening. A first conductive plug 5 made of tungsten to be connected is formed.

  Next, as shown in FIG. 2 (c), on the first insulating film 4, a capacitor lower electrode 6 made of platinum and electrically connected to the upper end of the first conductive plug 5, a ferroelectric film As a capacitive element 9, a capacitive insulating film 7 made of strontium bismuth tantalate and a capacitive upper electrode 8 made of platinum are sequentially laminated from the bottom. Next, a second insulating film 10 made of silicon oxide is formed on the first insulating film 4 so as to cover the capacitor element 9.

  Next, as shown in FIG. 3 (a), a second opening communicating with the conductive layer 3 is formed in the first insulating film 4 and the second insulating film 10, and then the second opening is formed. Then, a second conductive plug 11 made of a tungsten film whose lower end is connected to the conductive layer 3 is formed. In addition, after forming a third opening communicating with the capacitor upper electrode 8 in the second insulating film 10, the lower end is made of tungsten whose lower end is electrically connected to the capacitor upper electrode 8. A third conductive plug 12 is formed.

  Next, as shown in FIG. 3B, a first wiring layer 13 made of aluminum connected to the upper end of the second conductive plug 11 is formed on the second insulating film 10, and the first A second wiring layer 14 made of aluminum connected to the upper ends of the three conductive plugs 12 is formed.

  As described above, the first wiring layer 13 is electrically connected to the capacitor lower electrode 6 through the second conductive plug 11 and the conductive layer 3, and the second wiring layer 14 is connected to the third conductive layer. The capacitor upper electrode 8 is electrically connected through the conductive plug 12.

  Next, as shown in FIG. 3C, after forming a protective insulating film 15 made of silicon oxide on the second insulating film 10, the first wiring layer 13, and the second wiring layer 14, A first opening 16a exposing a part of the upper surface of the first wiring layer 13 is formed in the protective insulating film 15, and a second opening exposing a part of the upper surface of the second wiring layer 14 is formed. A portion 16b is formed.

  Hereinafter, in the semiconductor device according to the embodiment of the present invention, the manner in which the plasma charge moves into the semiconductor device will be described with reference to FIGS. 4 and 9 while comparing with the case of the conventional semiconductor device.

  FIG. 4 shows a step of forming first and second openings 16a and 16b in the protective insulating film 15 to expose the upper surfaces of the first and second wiring layers 13 and 14 in the first and second openings 16a and 16b. It is the figure which showed typically a mode that the plasma charge accumulate | stored on the wiring layers 13 and 14 moved to the inside of a semiconductor device. FIG. 4 shows a case where negative plasma charges are accumulated on the first and second wiring layers 13 and 14 as an example.

  First, there is a conductive path from the second wiring layer 14 to the inside of the capacitive element 9 to reach the capacitor upper electrode 8 through the third conductive plug 12. Accordingly, the accumulated charge on the second wiring layer 14 moves to the capacitor upper electrode 8 through the third conductive plug 12 as indicated by an arrow a1 in FIG. As described above, the path through which the accumulated charge on the second wiring layer 14 moves to the capacitor upper electrode 8 is the same as that of the conventional semiconductor device as shown in FIG.

  On the other hand, there is a conductive path from the first wiring layer 13 to the inside of the capacitive element 9 to reach the capacitor lower electrode 6 via the second conductive plug 11, the conductive layer 3, and the first conductive plug 5. . In this case, in the semiconductor device according to the embodiment of the present invention, the insulating layer 2 that cuts off the electrical connection between the semiconductor substrate 1 and the conductive layer 3 is formed between the semiconductor substrate 1 and the conductive layer 3. As a result, the first wiring layer 13 is in a floating state that is not electrically connected to the semiconductor substrate 1 as a result. Therefore, unlike the conventional semiconductor device shown in FIG. 9, the accumulated charge on the first wiring layer 13 moves to the conductive layer 3 via the second conductive plug 11 and then moves into the semiconductor substrate 1. All the charges move to the capacitor lower electrode 8 through the first conductive plug 5 as shown by an arrow a2 in FIG.

  That is, in the semiconductor device according to the embodiment of the present invention, the first wiring layer 13 serving as the terminal on the capacitor lower electrode 6 side and the second wiring layer 14 serving as the terminal on the capacitor upper electrode 8 side are both included in the semiconductor substrate 1. As a result, the accumulated charge on the first wiring layer 13 moves to the capacitor upper electrode 6 and the accumulated charge on the second wiring layer 14 moves to the capacitor lower electrode 8. To do. Accordingly, since an equal amount of negative charges is accumulated in the capacitor lower electrode 6 and the capacitor upper electrode 8, no potential imbalance occurs between the capacitor lower electrode 6 and the capacitor upper electrode 8. .

  As a result, no potential difference is generated between the capacitor lower electrode 6 and the capacitor upper electrode 8. Therefore, unintended spontaneous polarization occurs in the ferroelectric film constituting the capacitor insulating film 7 during the manufacturing process of the semiconductor device. Since it does not occur, imprinting can be prevented from occurring in the ferroelectric film. Therefore, since the characteristic variation of the semiconductor device can be prevented, by using the semiconductor device according to the present invention, it is possible to correctly monitor the characteristic of the capacitive element to be subjected to characteristic evaluation.

  In addition, according to the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, the stacked body including the insulating layer 2 and the conductive layer 3 constitutes a ferroelectric memory device formed on the semiconductor substrate 1. It is preferable to have the same material and the same structure as the stacked body including the gate insulating film and the gate electrode in the transistor that is not formed. For this reason, the stacked body formed of the insulating layer 2 and the conductive layer 3 can be formed in the same process as the stacked body formed of the gate insulating film and the gate electrode constituting the transistor formed over the semiconductor substrate 1. Therefore, there is no characteristic variation without adding a new process and selecting a new material for the purpose of forming the insulating layer 2 and the conductive layer 3 for bringing the conductive layer 3 into a floating state with respect to the semiconductor substrate 1. Capacitance elements for characteristic evaluation can be obtained very easily.

  Hereinafter, with respect to the polarization-voltage characteristics of the capacitive element having the ferroelectric film measured by the semiconductor device according to one embodiment of the present invention, the polarization-voltage of the capacitive element having the ferroelectric film measured by the conventional semiconductor device is described. This will be described with reference to FIG.

  As shown in FIG. 5, the polarization-voltage characteristic of the capacitive element measured using a conventional semiconductor device is shifted to the positive voltage side due to the imprint generated in the ferroelectric film. Although the polarization characteristics of the element fluctuate, the polarization-voltage characteristics of the capacitive element measured using the semiconductor device according to one embodiment of the present invention are not shifted. For this reason, in the semiconductor device according to one embodiment of the present invention, occurrence of imprint in the ferroelectric film constituting the capacitive insulating film 7 is prevented, and in the semiconductor device according to one embodiment of the present invention, the characteristic variation It can be seen that is not occurring.

  In the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, the first wiring layer 13 serving as a terminal on the capacitor lower electrode 6 side and the second wiring layer 14 serving as a terminal on the capacitor upper electrode 8 side are provided. Although formed, it is also possible to adopt a structure in which the conductive layer 3 or the capacitor upper electrode 8 can be used as a measurement terminal. In this case, the first wiring layer 13 and the second wiring layer 14, and the second conductive plug 11 and the third conductive plug 12 connected to them may be omitted.

  In the semiconductor device according to the embodiment of the present invention, as described above, the stacked body including the insulating layer 2 and the conductive layer 3 forms the gate insulating film and the gate electrode of the transistor formed on the semiconductor substrate 1. However, it is needless to say that the gate oxide film and the gate electrode of the transistor may be formed in different steps for convenience of the manufacturing process.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, the insulating layer 2 that cuts off the electrical connection between the semiconductor substrate 1 and the conductive layer 3 is formed between the semiconductor substrate 1 and the conductive layer 3. Therefore, both the first wiring layer 13 serving as the terminal on the capacitor lower electrode 6 side and the second wiring layer 14 serving as the terminal on the capacitor upper electrode 8 side are not electrically connected to the semiconductor substrate 1. Therefore, the plasma charges stored in the capacitor upper electrode 8 and the capacitor lower electrode 6 are equal to each other. Therefore, there is a difference in plasma charge storage between the capacitor lower electrode 6 and the capacitor upper electrode 8 during the manufacturing process. Thus, potential imbalance between the lower capacitor electrode 6 and the upper capacitor electrode 8 can be prevented. Therefore, since imprint does not occur in the ferroelectric film constituting the capacitor insulating film 7, the characteristic variation of the semiconductor device can be prevented, so that the semiconductor device is manufactured by the method for manufacturing a semiconductor device according to the embodiment of the present invention. If the semiconductor device is used, it is possible to correctly monitor the characteristics of the capacitive element to be evaluated.

  As described above, in the first semiconductor device according to the present invention, the insulating layer 2 that cuts off the electrical connection between the semiconductor substrate 1 and the conductive layer 3 is formed between the semiconductor substrate 1 and the conductive layer 3. Therefore, the first wiring layer 13 serving as the terminal on the capacitor lower electrode 6 side and the second wiring layer 14 serving as the terminal on the capacitor upper electrode 8 side are both in a floating state where they are not electrically connected to the semiconductor substrate 1. Therefore, the plasma charges stored in the capacitor lower electrode 6 and the capacitor upper electrode 8 are equal to each other. Therefore, the difference in plasma charge storage between the capacitor lower electrode 6 and the capacitor upper electrode 8 during the manufacturing process is caused. Thus, potential imbalance between the lower capacitor electrode 6 and the upper capacitor electrode 8 can be prevented. For this reason, since imprint does not occur in the ferroelectric film constituting the capacitive insulating film 7, the characteristic variation of the semiconductor device can be prevented. Therefore, the semiconductor device according to the present embodiment is subjected to characteristic evaluation. The characteristics of the capacitive element 9 can be monitored correctly.

  According to the present invention, since a semiconductor device for characteristic evaluation can be formed without causing characteristic fluctuations during the manufacturing process, the characteristics of a capacitive element having a stack type structure constituting a ferroelectric memory device can be correctly monitored. Therefore, it is useful for the characteristic evaluation of a capacitor element to be subjected to characteristic evaluation using a capacitive insulating film made of a ferroelectric material.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention. (a)-(c) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (a)-(c) is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a schematic diagram showing a state of movement of charges accumulated on the first and second wiring layers in the semiconductor device according to the first embodiment of the present invention. It is a figure which shows the polarization-voltage characteristic of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device. (a)-(c) is process sectional drawing which shows the manufacturing method of the conventional semiconductor device. (a)-(c) is process sectional drawing which shows the manufacturing method of the conventional semiconductor device. It is a schematic diagram which shows the mode of the movement of the electric charge accumulate | stored on the 1st and 2nd wiring layer in the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating layer 3 Conductive layer 4 1st insulating film 5 1st electroconductive plug 6 Capacitor lower electrode 7 Capacitor insulating film 8 Capacitor upper electrode 9 Capacitance element 10 2nd insulating film 11 2nd electroconductive plug 12 3rd conductive plug 13 1st wiring layer 14 2nd wiring layer 15 Protective insulating film 16a 1st opening part 16b 2nd opening part

Claims (6)

A conductive layer formed on a semiconductor substrate;
A first insulating film formed on the semiconductor substrate so as to cover the conductive layer;
A conductive plug formed in the first insulating film and having a lower end connected to the conductive layer;
A capacitor lower electrode formed on the first insulating film and electrically connected to an upper end of the conductive plug;
A capacitive insulating film made of a ferroelectric film formed on the capacitive lower electrode;
In a semiconductor device comprising a capacitor upper electrode formed on the capacitor insulating film,
A semiconductor device characterized in that an insulating layer for blocking electrical connection between the semiconductor substrate and the conductive layer is provided between the semiconductor substrate and the conductive layer. A second insulating film formed on the first insulating film so as to cover the capacitor upper electrode;
A first wiring layer formed on the second insulating film and electrically connected to the conductive layer;
2. The semiconductor device according to claim 1, further comprising a second wiring layer formed on the second insulating film and electrically connected to the capacitor upper electrode.   2. The stacked body made of the insulating layer and the conductive layer has the same structure as the stacked body made of a gate insulating film and a gate electrode constituting a transistor formed on the semiconductor substrate. 2. The semiconductor device according to 2. Forming a conductive layer on a semiconductor substrate;
Forming a first insulating film on the semiconductor substrate so as to cover the conductive layer;
Forming a conductive plug in the first insulating film such that a lower end is connected to the conductive layer;
Forming a capacitor lower electrode on the first insulating film so as to be electrically connected to an upper end of the conductive plug;
Forming a capacitive insulating film made of a ferroelectric film on the capacitive lower electrode;
Forming a capacitor upper electrode on the capacitor insulating film, and a method for manufacturing a semiconductor device,
Before the step of forming the conductive layer, a step of forming an insulating layer on the semiconductor substrate that blocks electrical connection between the semiconductor substrate and the conductive layer is provided. Production method. Forming a second insulating film on the first insulating film so as to cover the capacitor upper electrode;
Forming a first wiring layer on the second insulating film so as to be electrically connected to the conductive layer;
The method of manufacturing a semiconductor device according to claim 4, further comprising: forming a second wiring layer on the second insulating film so as to be electrically connected to the capacitor upper electrode. Method.   6. The stacked body formed of the insulating layer and the conductive layer is formed by the same process as the process of forming a gate insulating film and a gate electrode of a transistor formed on the semiconductor substrate. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.

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