JP2009212170A - Thin film transistor and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor that operates at a high speed by supplying a sufficient ON current while reducing an OFF current. <P>SOLUTION: A semiconductor layer of one conductivity type forming a source region and a drain region is provided to have one end portion thereof overlapping with a buffer layer, and then while the ON current of the thin film transistor is maintained, the OFF current is decreased. The film thickness of the buffer layer is larger than those of a microcrystal semiconductor layer and an amorphous semiconductor layer. The buffer layer is 500 to 3,000 nm thick, although the amorphous semiconductor layer is 50 to <500 nm thick. The film thickness of the buffer layer is thus set to reduce parasitic capacity between a source or drain, and a gate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a thin film transistor or a display device using the thin film transistor.

As a kind of field effect transistor, a thin film transistor in which a channel region is formed in a semiconductor layer formed over a substrate having an insulating surface is known. A technique using amorphous silicon, microcrystalline silicon, or polycrystalline silicon as a semiconductor layer used in a thin film transistor is disclosed (see Patent Documents 1 to 5). A typical application example of a thin film transistor is a liquid crystal television device, which is put into practical use as a switching transistor of each pixel constituting a display screen.
JP 2001-053283 A JP-A-5-129608 JP 2005-049832 A Japanese Patent Laid-Open No. 7-131030 JP 2005-191546 A

A thin film transistor in which a channel is formed in an amorphous silicon layer can obtain a field-effect mobility of only about 0.4 to 0.8 cm ² / V · sec and has a problem of low on-current. A thin film transistor in which a channel is formed in a microcrystalline silicon layer has a problem in that the field-effect mobility is improved but the off-current is increased and sufficient switching characteristics cannot be obtained as compared with a thin film transistor using amorphous silicon. There is.

A thin film transistor in which a polycrystalline silicon layer serves as a channel formation region has characteristics that field effect mobility is significantly higher than that of the two types of thin film transistors, and a high on-state current can be obtained. Due to the above-described characteristics, this thin film transistor can constitute not only a switching transistor provided in a pixel but also a driver circuit that requires high-speed operation.

However, a thin film transistor using a polycrystalline silicon layer requires a crystallization process of a semiconductor layer as compared with a case where a thin film transistor is formed using an amorphous silicon layer, which increases the manufacturing cost. For example, a laser annealing technique necessary for manufacturing a polycrystalline silicon layer has a problem that a large area liquid crystal panel cannot be efficiently produced with a small laser beam irradiation area.

Therefore, an object of the present invention is to solve the above-described problems relating to the on-state current and off-state current of a thin film transistor. Another object of the present invention is to provide a thin film transistor capable of high-speed operation.

The thin film transistor according to the present invention includes a microcrystalline semiconductor layer which overlaps with the gate electrode with the gate insulating layer interposed therebetween. A buffer layer is provided over the microcrystalline semiconductor layer. This buffer layer is provided so as to substantially overlap with the microcrystalline semiconductor layer. The side surfaces of the buffer layer and the microcrystalline semiconductor layer are covered with an amorphous semiconductor layer. A semiconductor layer of one conductivity type that forms a source region and a drain region in a thin film transistor is provided over an amorphous semiconductor layer. The one conductivity type semiconductor layer is provided so as to be divided corresponding to each region so as to form a source region and a drain region. The one conductivity type semiconductor layer is provided so that one end portion thereof overlaps the buffer layer.

In the thin film transistor, carriers (electrons or holes) flowing between the source region and the drain region are controlled by a voltage applied to the gate electrode. However, in the thin film transistor according to the present invention, the carriers flowing between the source region and the drain region are controlled. Flows through a microcrystalline semiconductor layer provided so as to overlap with the gate electrode and an amorphous semiconductor layer provided in contact with the microcrystalline semiconductor layer.

The electrical conductivity of the microcrystalline semiconductor layer is 1 × 10 ⁻⁵ S / cm to 5 × 10 ⁻² S / cm, and the electrical conductivity of the amorphous semiconductor layer is lower than that of the microcrystalline semiconductor layer. The microcrystalline semiconductor layer extends at least in the channel length direction of the thin film transistor and can have a high on-state current by having the above-described electrical conductivity. Here, the thickness of the amorphous semiconductor layer is smaller than the thickness of the buffer layer provided over the microcrystalline semiconductor layer, and the thickness is sufficient to reduce the off current while maintaining the on current of the thin film transistor. Have.

The one-conductivity-type semiconductor layer that forms the source region and the drain region is provided so that one end portion thereof overlaps with the buffer layer, so that the on-state current of the thin film transistor is maintained and the off-state current is reduced. The buffer layer is provided thicker than each of the microcrystalline semiconductor layer and the amorphous semiconductor layer. The buffer layer has a film thickness of 500 nm to 3000 nm, whereas the film thickness of the amorphous semiconductor layer is 50 nm to less than 500 nm. By setting the thickness of the buffer layer in this way, the parasitic capacitance between the source or drain and the gate is reduced.

In the present invention, the length in the channel length direction of the amorphous semiconductor layer inserted between the source region and the drain region in order to reduce off current is set by the film thickness of the amorphous semiconductor layer. This makes it possible to create a nanometer-sized fine structure in a thin film transistor in a self-aligning manner without using photolithographic techniques to align the photomask with submicron level accuracy.

That is, the channel length of a thin film transistor in which at least one amorphous semiconductor layer substantially becomes a channel formation region is determined by the film thickness of the amorphous semiconductor layer, and is a nanometer-level length as described above. The present invention solves the problem by simultaneously forming a deep sub-micron thin film transistor while performing a thin film transistor manufacturing process based on a design rule of several micron level.

An impurity semiconductor refers to a semiconductor supplied from an impurity to which most of carriers involved in electrical conduction are added. An impurity is an element that can be a donor that supplies electrons as carriers or an acceptor that supplies holes. Typically, a donor corresponds to a Group 15 element of the periodic table, and an acceptor corresponds to a Group 13 element of the periodic table.

A microcrystalline semiconductor exemplarily has a crystal grain size of 2 nm to 200 nm, preferably 10 nm to 80 nm, more preferably 20 nm to 50 nm, and an electric conductivity of approximately 10 ⁻⁷ S / cm to 10 nm. ^{What is −4} S / cm refers to a semiconductor that can be increased to about 10 ¹ S / cm by valence electron control. However, in the present invention, the concept of the microcrystalline semiconductor is not limited to the above-mentioned crystal grain size and electrical conductivity values, but can be replaced with other semiconductor materials as long as they have equivalent physical property values. You can also.
An amorphous semiconductor refers to a semiconductor having no crystal structure (no long-range order in the arrangement of atoms). Note that amorphous silicon includes those containing hydrogen.

The “on-current” is a current that flows through the channel formation region when an appropriate gate voltage is applied to the gate electrode in order to pass a current through the channel formation region (that is, when the thin film transistor is in an on state).
The “off-state current” is a current that flows between the source and the drain when the gate voltage is lower than the threshold voltage of the thin film transistor (that is, when the thin film transistor is in the off state).

According to the present invention, carriers flowing between the source region and the drain region flow in the microcrystalline semiconductor layer provided so as to overlap with the gate electrode and the amorphous semiconductor layer provided in contact with the microcrystalline semiconductor layer. With the configuration, it is possible to allow a sufficient on current to flow while reducing the off current.

According to the present invention, a buffer layer is provided over a microcrystalline semiconductor layer, and an upper surface of the buffer layer and an amorphous semiconductor layer that is in contact with the side surfaces of the buffer layer and the microcrystalline semiconductor layer are provided in a self-aligning manner. A thin structure having a small size can be formed in the thin film transistor, a sufficient on current can be supplied while reducing the off current, and the thin film transistor can be operated at high speed.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In the structure of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
In this embodiment mode, off-state current is lower than that of a thin film transistor having a microcrystalline semiconductor layer in a channel formation region, high-speed operation is possible compared to a thin film transistor having an amorphous semiconductor layer in a channel formation region, and on-current The structure of the thin film transistor will be described with reference to FIGS.

In the thin film transistor illustrated in FIG. 1A, a gate electrode 101 is provided over a substrate 100, a gate insulating layer 102a and a gate insulating layer 102b are provided over the gate electrode 101, and a gate insulating layer 102a and a gate insulating layer 102b are provided. The microcrystalline semiconductor layer 104 is provided, and the buffer layer 105 is provided over the microcrystalline semiconductor layer 104. This buffer layer 105 is provided so as to substantially overlap with the microcrystalline semiconductor layer 104. In addition, a pair of amorphous semiconductor layers 106 and 107 that cover the side surfaces of the microcrystalline semiconductor layer 104 and the buffer layer 105 are provided, and the pair of amorphous semiconductor layers 106 and 107 is formed over the pair of amorphous semiconductor layers 106 and 107. In addition, a pair of impurity semiconductor layer 108 and impurity semiconductor layer 109 to which an impurity element imparting one conductivity type is added to form a source region and a drain region are provided, and an impurity element to which an impurity element imparting one conductivity type is added A wiring 110 and a wiring 111 are provided over the semiconductor layer 108 and the impurity semiconductor layer 109. One end portion of the pair of impurity semiconductor layers to which the impurity element imparting one conductivity type is added overlaps with the buffer layer 105.

The substrate 100 is a heat-resistant material that can withstand the processing temperature of this manufacturing process, in addition to an alkali-free glass substrate, a ceramic substrate, or the like manufactured by a fusion method or a float method, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass. A plastic substrate or the like having the above can be used. Alternatively, a substrate in which an insulating layer is provided on the surface of a metal substrate such as a stainless alloy may be used. When the substrate 100 is mother glass, the size of the substrate is the first generation (320 mm × 400 mm), the second generation (400 mm × 500 mm), the third generation (550 mm × 650 mm), the fourth generation (680 mm × 880 mm, or 730mm x 920mm), 5th generation (1000mm x 1200mm or 1100mm x 1250mm), 6th generation 1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160mm x 2460mm), 9th generation (2400mm x 2800 mm, 2450 mm × 3050 mm), 10th generation (2950 mm × 3400 mm), or the like can be used.

The electric conductivity of the microcrystalline semiconductor layer 104 is 1 × 10 ⁻⁵ S / cm to 5 × 10 ⁻² S / cm. The microcrystalline semiconductor layer 104 is provided to have a thickness of 5 nm to 50 nm, preferably 5 nm to 30 nm. The microcrystalline semiconductor layer 104 extends at least in the channel length direction of the thin film transistor and can have a high on-state current by having the above-described electrical conductivity. The microcrystalline semiconductor layer 104 is formed using a microcrystalline silicon layer, a microcrystalline silicon germanium layer, a microcrystalline germanium layer, or the like.

The oxygen concentration and nitrogen concentration of the microcrystalline semiconductor layer 104 are typically less than 3 × 10 ¹⁹ atoms / cm ³ , more preferably less than 3 × 10 ¹⁸ atoms / cm ³ , and the carbon concentration is 3 × 10 ^18. It is preferable to be atoms / cm ³ or less. By reducing the concentration of oxygen, nitrogen, and carbon mixed in the microcrystalline semiconductor layer 104, generation of defects in the microcrystalline semiconductor layer 104 can be suppressed.

The buffer layer 105 is formed using an amorphous semiconductor. The thickness of the buffer layer 105 is set to 500 nm to 3000 nm. By setting the thickness of the buffer layer to such a thickness, the parasitic capacitance generated between the source or drain electrode and the gate electrode is reduced. The amorphous semiconductor is formed of amorphous silicon or amorphous silicon / germanium. By providing the buffer layer 105 over the microcrystalline semiconductor layer 104, the microcrystalline semiconductor layer 104 can be prevented from being exposed to the atmosphere and oxidized. Accordingly, defects in which carriers are captured or a region that hinders carrier progress can be reduced, so that a thin film transistor can operate at high speed and an on-state current can be increased.

The amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 are formed with a thickness greater than or equal to 50 nm and less than 500 nm. The amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 are preferably formed using amorphous silicon. The amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 are provided so as to cover the side surface of the buffer layer 105 and form a semiconductor junction with the microcrystalline semiconductor layer 104. Further, the amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 cover the gate insulating layer 102b where the microcrystalline semiconductor layer 104 is not formed.

With this structure, the microcrystalline semiconductor layer 104 and the pair of impurity semiconductor layers 108 and 109 to which an impurity element imparting one conductivity type is added are isolated from each other. Leakage current generated between the impurity semiconductor layer 108 and the impurity semiconductor layer 109 to which the impurity element to be added is added can be reduced. In addition, end portions of the amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 preferably overlap with the buffer layer 105. The end portions of the amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 overlap with the buffer layer 105, whereby the impurity semiconductor layer 108 to which an impurity element imparting one conductivity type is added, the impurity semiconductor layer 109, and the buffer layer Since 105 does not contact directly, leakage current can be reduced.

In the structure in which the amorphous semiconductor layer 106, the amorphous semiconductor layer 107, the buffer layer 105, and the microcrystalline semiconductor layer 104 are in contact, the side surfaces of the buffer layer 105 and the microcrystalline semiconductor layer 104 are inclined at an angle of 30 to 60 degrees. It is preferable to make it. That is, the side surfaces of the buffer layer 105 and the microcrystalline semiconductor layer 104 are tapered to prevent the amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 from being thinned at the side surface portions. Can do.

The gate electrode 101 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, or the like is applied. A preferred example of the gate electrode 101 is formed of aluminum or a laminated structure of aluminum and a barrier metal. As the barrier metal, a refractory metal such as titanium, molybdenum, or chromium is used. The barrier metal is preferably provided to prevent hillocks and oxidation of aluminum.

The gate electrode 101 is formed with a thickness of 50 nm to 300 nm. When the thickness of the gate electrode 101 is greater than or equal to 50 nm and less than or equal to 100 nm, it is possible to prevent disconnection of a semiconductor layer or a wiring formed later. Further, by setting the thickness of the gate electrode 101 to 150 nm to 300 nm, the resistance of the gate electrode 101 can be reduced and the area can be increased.

The gate insulating layer 102a and the gate insulating layer 102b are each formed using a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer with a thickness of 50 nm to 150 nm. In this embodiment, a structure in which a silicon nitride layer or a silicon nitride oxide layer is formed as the gate insulating layer 102a and a silicon oxide layer or a silicon oxynitride layer is formed and stacked as the gate insulating layer 102b is illustrated. Note that the gate insulating layer is not a two-layer structure, and the gate insulating layer is formed using a single layer of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer.

When the gate insulating layer 102a is formed using a silicon nitride layer or a silicon nitride oxide layer, adhesion between the substrate 100 and the gate insulating layer 102a is increased. When a glass substrate is used as the substrate 100, impurities from the substrate 100 However, diffusion into the microcrystalline semiconductor layer 104, the buffer layer 105, the amorphous semiconductor layer 106, and the amorphous semiconductor layer 107 can be prevented, and further, the gate electrode 101 can be prevented from being oxidized. . In addition, it is preferable that each of the gate insulating layer 102a and the gate insulating layer 102b has a thickness of 50 nm or more because reduction in coverage due to unevenness of the gate electrode 101 can be reduced.

Here, the silicon oxynitride layer has a higher oxygen content than nitrogen, and has a Rutherford backscattering method (RBS) and a hydrogen forward scattering method (HFS). ) In the range of 50 to 70 atomic% oxygen, 0.5 to 15 atomic% nitrogen, 25 to 35 atomic% Si, and 0.1 to 10 atomic% hydrogen. It means what is included. Further, the silicon nitride oxide layer has a nitrogen content higher than that of oxygen as a composition. When measured using RBS and HFS, the concentration range of oxygen is 5 to 30 atomic%, nitrogen. In the range of 20 to 55 atomic%, Si in the range of 25 to 35 atomic%, and hydrogen in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, Si, and hydrogen is included in the above range.

The pair of impurity semiconductor layers 108 and 109 to which an impurity element imparting one conductivity type is added may be formed by adding phosphorus as a typical impurity element in the case of forming an n-channel thin film transistor. An impurity gas such as PH ₃ may be added to silicon hydride. In the case of forming a p-channel thin film transistor, boron may be added as a typical impurity element, and an impurity gas such as B ₂ H ₆ may be added to silicon hydride. By setting the concentration of phosphorus or boron to 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ , ohmic contact with the wiring 110 and the wiring 111 is possible and functions as a source region and a drain region. The pair of impurity semiconductor layers 108 and 109 to which an impurity element imparting one conductivity type is added can be formed using a microcrystalline semiconductor layer or an amorphous semiconductor layer. The pair of impurity semiconductor layers 108 and 109 to which an impurity element imparting one conductivity type is added is formed to a thickness of 10 nm to 100 nm, preferably 30 nm to 50 nm. By reducing the thickness of the pair of impurity semiconductor layers 108 and 109 to which an impurity element imparting one conductivity type is added, throughput can be improved.

The wiring 110 and the wiring 111 are preferably formed using a single layer or a stacked layer of aluminum or an aluminum alloy to which a heat resistance improving element such as copper, silicon, titanium, neodymium, scandium, or molybdenum or a hillock prevention element is added. In addition, a layer in contact with the impurity semiconductor layer to which an impurity element imparting one conductivity type is added is formed using titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, over which aluminum or an aluminum alloy is formed. It is good also as the laminated structure which formed. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed. Here, a stacked conductive layer of a titanium layer, an aluminum layer, and a titanium layer can be used as the conductive layer.

In addition, in the thin film transistor illustrated in FIG. 1A, the amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 are not in contact with the wiring 110 and the wiring 111 and an impurity element imparting one conductivity type is added. Although the wiring 110 and the wiring 111 are formed over the buffer layer 105 with the impurity semiconductor layer 108 and the impurity semiconductor layer 109 interposed therebetween, as shown in FIG. 1B, the amorphous semiconductor layer 106 and A structure in which the side surface of the amorphous semiconductor layer 107 is in contact with the wiring 110 and the wiring 111 can be employed.

In the thin film transistor of this embodiment mode, the length in the channel length direction of the amorphous semiconductor layer inserted between the source region and the drain region in order to reduce off-state current is set by the thickness of the amorphous semiconductor layer. This makes it possible to create a nanometer-sized fine structure in a thin film transistor in a self-aligning manner without using photolithographic techniques to align the photomask with submicron level accuracy.

That is, the channel length of a thin film transistor in which at least one amorphous semiconductor layer substantially becomes a channel formation region is determined by the film thickness of the amorphous semiconductor layer, and is a nanometer-level length as described above. In the thin film transistor of this embodiment, a manufacturing process is performed based on a design rule of several micron level, and a deep submicron thin film transistor is formed at the same time, so that a sufficient on current flows while reducing an off current. In addition, the thin film transistor can be operated at high speed.

Further, since the buffer layer 105 is thick, in the case of a channel-etched thin film transistor, even when the amorphous semiconductor layer is over-etched when the source region, the drain region, and the wiring are etched, the film thickness is large. Since the buffer layer 105 is formed, the channel formation region is not divided and the yield can be improved. In addition, since the buffer layer 105 is thick, leakage current flowing from the source region and the drain region to the microcrystalline semiconductor layer 104 can be reduced. For this reason, off-current can be reduced.

Further, in addition to the gate insulating layer, the amorphous semiconductor layer 106, the amorphous semiconductor layer 108, and the impurity semiconductor layer 109 to which the impurity element imparting one conductivity type is added are added between the gate electrode 101 and the impurity semiconductor layer 108. A semiconductor layer 107 is formed, and a distance between the gate electrode 101 and the impurity semiconductor layer 108 to which the impurity element imparting one conductivity type is added and the impurity semiconductor layer 109 is increased. Therefore, parasitic capacitance generated between the gate electrode 101, the impurity semiconductor layer 108 to which the impurity element imparting one conductivity type is added, and the impurity semiconductor layer 109 can be reduced. In particular, the thin film transistor can reduce a voltage drop on the drain side. For this reason, the display device using the structure can improve the response speed of the pixel. In particular, in the case of a thin film transistor formed in a pixel of a liquid crystal display device, the voltage drop of the drain voltage can be reduced, so that the response speed of the liquid crystal material can be increased.

(Embodiment 2)
In this embodiment, other shapes of the microcrystalline semiconductor layer 104 and the buffer layer 105 are described with reference to FIGS.

FIG. 2A illustrates a thin film transistor in which the sidewalls of the microcrystalline semiconductor layer 104a and the buffer layer 105 are substantially vertical or have side surface inclination angles of 80 to 100 degrees, preferably 85 to 95 degrees. By making the sidewalls of the microcrystalline semiconductor layer 104 and the buffer layer 105 substantially vertical, the area occupied by the thin film transistor can be reduced. Therefore, the aperture ratio of a transmissive display device using the thin film transistor for a pixel can be increased.

FIG. 2B illustrates a thin film transistor in which a buffer layer 105 is formed inside the microcrystalline semiconductor layer 104. That is, a thin film transistor in which a buffer layer 105 having a smaller area than the microcrystalline semiconductor layer 104 is formed and a part of the microcrystalline semiconductor layer 104 is exposed from the buffer layer 105. With such a structure, the microcrystalline semiconductor layer 104, the amorphous semiconductor layer 106, and the amorphous semiconductor layer 107 can be provided closer to each other, so that junction leakage current can be reduced. .

(Embodiment 3)
In this embodiment mode, another mode of the buffer layer is shown with reference to FIG. In this embodiment mode, a structure in which the buffer layer 112 is formed using an insulating layer is illustrated.

In the thin film transistor illustrated in FIG. 3A, a gate electrode 101 is formed over a substrate 100, a gate insulating layer 102a and a gate insulating layer 102b are formed over the gate electrode 101, and a gate insulating layer 102a and a gate insulating layer 102b are formed. The microcrystalline semiconductor layer 104 is formed, and the buffer layer 105 is formed over the microcrystalline semiconductor layer 104. This buffer layer 105 is provided so as to substantially overlap with the microcrystalline semiconductor layer 104. In addition, a pair of amorphous semiconductor layers 106 and 107 covering the side surfaces of the microcrystalline semiconductor layer 104 and the buffer layer 112 are formed, and the pair of amorphous semiconductor layers 106 and 107 is formed over the pair of amorphous semiconductor layers 106 and 107. A pair of the impurity semiconductor layer 108 and the impurity semiconductor layer 109 to which an impurity element imparting one conductivity type is added are formed, and the impurity semiconductor layer 108 and the impurity semiconductor layer 109 to which an impurity element imparting one conductivity type is added are formed. Wiring 110 and wiring 111 are formed. One end portion of the pair of impurity semiconductor layers to which the impurity element imparting one conductivity type is added overlaps with the buffer layer 105.

In this embodiment, the buffer layer 112 is formed using an insulating material. As the insulating material, an insulating material containing silicon as a component such as silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride is preferably used. Alternatively, it can be formed using polyimide, acrylic resin, epoxy resin, or other organic insulating layers. The thickness of the buffer layer 112 is set to 500 nm to 3000 nm. By forming the buffer layer 112 with a large thickness and an insulating layer, the amorphous semiconductor layer 106 and the non-conductive semiconductor layer 108 and the impurity semiconductor layer 109 to which the impurity element imparting one conductivity type is added are added. Since the leak current flowing through the crystalline semiconductor layer 107 can be blocked by the buffer layer 112, the leak current can be reduced. In addition, off-state current can be reduced.

As illustrated in FIG. 3B, a buffer layer 105 formed using a semiconductor layer is provided over the microcrystalline semiconductor layer 104, and a buffer layer 113 formed using an insulating layer is provided over the buffer layer 105. The buffer layer 113 is formed using a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, a silicon oxynitride layer, or another inorganic insulating layer. Alternatively, polyimide, acrylic resin, epoxy resin, or another organic insulating layer is used.

In FIG. 3B, the buffer layer 105 formed using a semiconductor layer is thicker than the buffer layer 113 formed using an insulating layer; however, the buffer layer 113 may be thicker than the buffer layer 105. . Note that the total film thickness of the buffer layer 105 and the buffer layer 113 is set to 500 nm to 3000 nm. When the buffer layer 105 formed using a semiconductor layer is formed over the microcrystalline semiconductor layer 104, oxidation of the microcrystalline semiconductor layer 104 can be reduced and reduction in resistivity of the microcrystalline semiconductor layer 104 is suppressed. be able to. In addition, by providing the buffer layer 113 formed using an insulating layer over the buffer layer 105 formed using a semiconductor layer, a pair of impurity semiconductor layers 108 and impurity semiconductor layers 109 to which an impurity element imparting one conductivity type is added are provided. The leakage current flowing from the amorphous semiconductor layer 106 to the amorphous semiconductor layer 107 can be blocked by the buffer layer 112, so that the leakage current can be reduced. In addition, off-state current can be reduced.

(Embodiment 5)
In this embodiment mode, another mode of a thin film transistor structure is shown.

4 includes a gate electrode 101 formed over a substrate 100, a gate insulating layer 102a and a gate insulating layer 102b formed over the gate electrode 101, and a microcrystalline structure over the gate insulating layer 102a and the gate insulating layer 102b. The semiconductor layer 104a, the microcrystalline semiconductor layer 104b, and the microcrystalline semiconductor layer 104c are formed, and the buffer layer 105a, the buffer layer 105b, and the buffer layer 105c are formed over the microcrystalline semiconductor layer 104a, the microcrystalline semiconductor layer 104b, and the microcrystalline semiconductor layer 104c. It is formed. The buffer layer 105a, the buffer layer 105b, and the buffer layer 105c are provided to overlap with the microcrystalline semiconductor layer 104a. In addition, the microcrystalline semiconductor layer 104a, the microcrystalline semiconductor layer 104b, the microcrystalline semiconductor layer 104c, the buffer layer 105a, the buffer layer 105b, a pair of amorphous semiconductor layers 106 that cover the side surfaces of the buffer layer 105c, and the amorphous semiconductor layer 107 Are formed, and a pair of impurity semiconductor layers 108 and 109 doped with an impurity element imparting one conductivity type are formed over the pair of amorphous semiconductor layers 106 and 107. A wiring 110 and a wiring 111 are formed over the impurity semiconductor layer 108 and the impurity semiconductor layer 109 to which an impurity element imparting a type is added. One end portion of the pair of impurity semiconductor layers to which the impurity element imparting one conductivity type is added overlaps with the buffer layer 105a. In addition, a stack of the microcrystalline semiconductor layer 104a, the buffer layer 105a, the buffer layer 105b, and the buffer layer 105c, a stack of the microcrystalline semiconductor layer 104b and the buffer layer 105b, and a stack of the microcrystalline semiconductor layer 104c and the buffer layer 105c are provided. Each is separated.

5 includes a gate electrode 101 formed over a substrate 100, a gate insulating layer 102a and a gate insulating layer 102b formed over the gate electrode 101, and a microcrystalline structure over the gate insulating layer 102a and the gate insulating layer 102b. The semiconductor layer 104d is formed in a ring shape, and the buffer layer 105d is formed in a ring shape over the microcrystalline semiconductor layer 104d. This buffer layer 105d is provided so as to substantially overlap with the microcrystalline semiconductor layer 104d. In addition, a pair of amorphous semiconductor layers 106 and 107 that cover the side surfaces of the microcrystalline semiconductor layer 104d and the buffer layer 105d are formed. A pair of the impurity semiconductor layer 108 and the impurity semiconductor layer 109 to which an impurity element imparting one conductivity type is added are formed over the pair of amorphous semiconductor layers 106 and 107 so that the one conductivity type is imparted. A wiring 110 and a wiring 111 are formed over the impurity semiconductor layer 108 and the impurity semiconductor layer 109 to which the impurity element to be added is added. In addition, one end portions of the pair of impurity semiconductor layers 108 and the impurity semiconductor layer 109 to which an impurity element imparting one conductivity type is added overlap the buffer layer 105d. The thin film transistor illustrated in FIG. 5 is characterized in that a channel formation region where a source region and a drain region face each other is circular.

Note that one of the pair of amorphous semiconductor layer 106, the amorphous semiconductor layer 107, the pair of impurity semiconductor layers 108 to which the impurity element imparting one conductivity type is added, and the impurity semiconductor layer 109 are annular, and the pair The other of the amorphous semiconductor layer 106, the amorphous semiconductor layer 107, the pair of impurity semiconductor layers 108 to which an impurity element imparting one conductivity type is added, and the impurity semiconductor layer 109 is circular. That is, one of the source region and the drain region surrounds the other of the source region and the drain region with a certain interval.

(Embodiment 6)
In this embodiment, a manufacturing process of the thin film transistor illustrated in FIG. 1A will be described with reference to FIGS. 6 and 7, the left side is a cross-sectional view taken along line AB in FIG. 9, showing a cross section of a region where a thin film transistor is formed, and the right side is a cross-sectional view taken along line CD in FIG. The cross section of the area | region where wiring and source wiring cross | intersect is shown.

As shown in FIG. 6A, a conductive film 103 is formed over the substrate 100. The conductive film 103 can be formed using any of the materials listed for the gate electrode 101 described in Embodiment 1. The conductive film 103 is formed by a sputtering method, a CVD method, or a vacuum evaporation method.

Next, after applying a resist over the conductive film 103, the conductive film 103 is etched into a desired shape using a resist mask formed by a photolithography process using a first photomask. As shown in B), the gate electrode 101 is formed. Thereafter, the resist mask is removed.

Next, the gate insulating layer 102 is formed over the gate electrode 101 and the substrate 100. The gate insulating layer 102 can be formed using any of the materials listed for the gate insulating layers 102a and 102b described in Embodiment 1. The gate insulating layer 102 is formed by a CVD method, a sputtering method, or the like.

Next, a microcrystalline semiconductor layer 104 and a buffer layer 105 are stacked over the gate insulating layer 102. Silane, dichlorosilane, or disilane and hydrogen are mixed in a reaction chamber of a plasma CVD apparatus, and a microcrystalline semiconductor layer is deposited over the gate insulating layer 102 by glow discharge plasma. The microcrystalline semiconductor layer is formed by diluting the flow rate of hydrogen 10 to 2000 times, preferably 50 to 200 times the flow rate of silane, dichlorosilane, or disilane. The heating temperature of the substrate is 100 ° C to 300 ° C, preferably 120 ° C to 220 ° C. In addition, the electrical conductivity of the microcrystalline semiconductor layer 104 can be controlled by mixing a gas containing phosphorus, arsenic, antimony, or the like with the source gas.

When the buffer layer 105 is formed using a semiconductor material such as amorphous silicon, amorphous silicon germanium, or amorphous silicon carbide, a film of the semiconductor material is deposited by a plasma CVD method or a sputtering method. Since the buffer layer 105 preferably has a low electric conductivity, the electric conductivity of the film made of the semiconductor material is set to 10 ⁻⁷ S / cm or less. In the case where the buffer layer 105 is formed using an insulating material, a film of an insulating material containing silicon as a component such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide is formed by a plasma CVD method or a sputtering method. In addition, as an insulating material for forming the buffer layer 105, polyimide, an acrylic resin, an epoxy resin, or other raw materials for an organic insulating layer can be applied and then baked to form the insulating layer.

In the above step, after the microcrystalline semiconductor layer 104 is formed, the buffer layer 105 is preferably formed at a temperature of 300 ° C. to 400 ° C. by a plasma CVD method. By this film formation treatment, hydrogen is supplied to the microcrystalline semiconductor layer 104, and an effect equivalent to that obtained by hydrogenating the microcrystalline semiconductor layer 104 is obtained. That is, by depositing the buffer layer 105 over the microcrystalline semiconductor layer 104, hydrogen can be diffused into the microcrystalline semiconductor layer 104 to terminate dangling bonds.

In the case where the microcrystalline semiconductor layer 104 is formed using a microcrystalline semiconductor layer, the buffer layer 105 is formed over the surface of the microcrystalline semiconductor layer 104 so that the surface of the crystal grains included in the microcrystalline semiconductor layer 104 is naturally oxidized. It is possible to prevent. In a display device with a high applied voltage to the thin film transistor, typically a liquid crystal display device with a driving voltage of about 15 V, when the buffer layer 105 is formed thick, the withstand voltage between the source or drain electrode and the gate electrode is increased. Even when a high voltage is applied to the thin film transistor, the thin film transistor can be prevented from deteriorating.

Next, after a resist is applied over the buffer layer 105, the buffer layer 105 and the microcrystalline semiconductor layer 104 are etched into a desired shape by using a resist mask formed by a photolithography process using a second photomask. . Then, as illustrated in FIG. 6C, a microcrystalline semiconductor layer 104 and a buffer layer 105 are formed in a region where a thin film transistor is formed. In a region where the gate wiring and the source wiring intersect, the microcrystalline semiconductor layer 104 and the buffer layer 105 are formed. Thereafter, the resist mask is removed.

Next, as illustrated in FIG. 6D, an amorphous semiconductor layer 114 and an impurity semiconductor layer 115 to which an impurity element imparting one conductivity type is added are formed. As the amorphous semiconductor layer 114, silane or an amorphous silicon film deposited by a plasma CVD method using silane and hydrogen gas is preferably used. As the impurity semiconductor layer 115, an n-type amorphous silicon film or an n-type microcrystalline silicon film deposited by a plasma CVD method is used.

As the conductive film 116, a metal film such as chromium, molybdenum, titanium, tantalum, or tungsten formed by a sputtering method is used. Alternatively, an aluminum film may be stacked on the metal film.

Next, a resist is applied over the conductive film 116. As the resist, a positive resist or a negative resist can be used. Here, a positive resist is used. Next, using a multi-tone mask as a third photomask, the resist is irradiated with light and then developed to form a resist mask 117.

Here, exposure using the multi-tone mask 159 will be described with reference to FIG. A multi-tone mask is a mask capable of performing three exposure levels on an exposed portion, an intermediate exposed portion, and an unexposed portion, and a plurality of (typically two types) can be obtained by one exposure and development process. It is possible to form a resist mask having a region with a thickness of. Therefore, the number of photomasks can be reduced by using a multi-tone mask.

Typical examples of the multi-tone mask include a gray tone mask 122a as shown in FIG. 8A and a halftone mask 122b as shown in FIG. 8C.

As shown in FIG. 8A, the gray tone mask 122a includes a light-transmitting substrate 123, a light shielding portion 124 formed thereon, and a diffraction grating 125. In the light shielding portion 124, the amount of transmitted light is 0%. On the other hand, the diffraction grating 125 can control the amount of transmitted light by setting the interval between the light transmitting portions such as slits, dots, and meshes to be equal to or less than the resolution limit of light used for exposure. Note that the diffraction grating 125 can use either a periodic slit, a dot, or a mesh, or an aperiodic slit, a dot, or a mesh.

As the light-transmitting substrate 123, a light-transmitting substrate such as quartz can be used. The light shielding portion 124 and the diffraction grating 125 are formed using a light shielding material that absorbs light such as chromium or chromium oxide.

When the gray-tone mask 122a is irradiated with exposure light, as shown in FIG. 8B, the light transmission amount 126 is 0% in the light shielding portion 124, and the light shielding portion 124 and the diffraction grating 125 are not provided. In the region, the light transmission amount 126 is 100%. The diffraction grating 125 can be adjusted in the range of 10 to 70%. The amount of light transmitted through the diffraction grating 125 can be adjusted by adjusting the spacing and pitch of slits, dots, or meshes of the diffraction grating.

As shown in FIG. 8C, the halftone mask 122b includes a light-transmitting substrate 123, a semi-transmissive portion 127 and a light-shielding portion 128 formed thereon. For the semi-transmissive portion 127, MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like can be used. The light shielding portion 128 can be formed using a light shielding material that absorbs light, such as chromium or chromium oxide.

When exposure light is irradiated to the halftone mask 122b, as shown in FIG. 8D, the light transmission amount 129 is 0% in the light shielding portion 128, and the light shielding portion 128 and the semi-transmissive portion 127 are provided. In the absence region, the light transmission amount 129 is 100%. Moreover, in the semi-transmissive part 127, it can adjust in 10 to 70% of range. The amount of light transmitted through the semi-transmissive portion 127 can be adjusted by adjusting the material of the semi-transmissive portion 127. By developing after exposure using a multi-tone mask, a resist mask 117 having regions with different thicknesses can be formed as shown in FIG. 6D.

Next, the amorphous semiconductor layer 114, the impurity semiconductor layer 115, and the conductive film 116 are etched and separated by the resist mask 117. As a result, as shown in FIG. 6E, the amorphous semiconductor layer 114, the amorphous semiconductor layer 114, the semiconductor layer 115 to which an impurity imparting one conductivity type is added, the semiconductor layer 115, and the conductive film 116 are formed. Can be formed.

Next, the resist mask 117 is ashed. As a result, the resist area is reduced and the thickness is reduced. At this time, the resist in a thin region (a region overlapping with part of the gate electrode 101) is removed, and a separated resist mask 117 can be formed as illustrated in FIG.

Next, the conductive film 116 is etched and separated using the separated resist mask 117. As a result, the wiring 110 and the wiring 111 as illustrated in FIG. 6E can be formed. When the conductive film 116 and the conductive layer 43 are wet-etched using the separated resist mask 117, the end portions of the conductive film 116 and the conductive layer 43 are selectively etched. As a result, the wiring 110 and the wiring 111 having a smaller area than the separated resist mask 117 can be formed.

At the intersection of the gate electrode 101 and the impurity semiconductor layer 115 to which an impurity element imparting one conductivity type is added, in addition to the gate insulating layer 102, the microcrystalline semiconductor layer 104, the buffer layer 105, and the amorphous semiconductor layer 114 is formed, and the distance between the gate electrode 101 and the impurity semiconductor layer 115 is increased. Therefore, parasitic capacitance in a region where the gate electrode 101 and the impurity semiconductor layer 115 intersect can be reduced.

Next, the impurity semiconductor layer 115 is etched using the separated resist mask 117, so that the pair of impurity semiconductor layers 108 and 109 are formed. Note that part of the amorphous semiconductor layer 114 is also etched in the etching step, so that a pair of the amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 are formed. In addition, a part of the buffer layer is etched. A partially etched buffer layer is referred to as a buffer layer 105. Note that a concave portion is formed in the buffer layer 105. The step of forming the source region and the drain region and the concave portion of the buffer layer 105 can be formed in the same step.

Here, the ends of the wiring 110 and the wiring 111 and the ends of the pair of impurity semiconductor layers 108 and 109 are not aligned with each other. End portions of the impurity semiconductor layer 108 and the impurity semiconductor layer 109 are formed. Thereafter, the separated resist mask 117 is removed.

Next, the exposed buffer layer 113 may be irradiated with H ₂ O plasma. Typically, radicals generated by discharging vaporized water with plasma are irradiated to the exposed portions of the buffer layer 105, the impurity semiconductor layer 108, the impurity semiconductor layer 109, the wiring 110, and the wiring 111, so that high-speed operation of the thin film transistor is achieved. Operation is possible, and the on-current can be further increased. In addition, off-state current can be reduced. Through the above process, a thin film transistor can be formed.

Next, as illustrated in FIG. 7B, a passivation layer 119 is formed over the wiring 110, the wiring 111, and the gate insulating layer 102. The passivation layer 119 can be formed using a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, or a silicon oxynitride layer. Note that the passivation layer 119 is for preventing intrusion of contaminant impurities such as organic substances, metal substances, and water vapor floating in the air, and is preferably a dense film.

Next, the planarization layer 120 may be formed over the passivation layer 119. The planarizing layer 120 can be formed using an organic insulating layer such as acrylic resin, polyimide, epoxy resin, or siloxane polymer. Here, the planarization layer 120 is formed using a photosensitive organic resin. Next, after the planarization layer 120 is exposed to light and developed using a fourth photomask, the passivation layer 119 is exposed as shown in FIG. 7C. Next, the passivation layer 119 is etched using the planarization layer 120 to form a contact hole exposing a part of the wiring 111.

Next, the pixel electrode 121 is formed in the contact hole. Here, after a conductive layer is formed over the planarization layer 120, a resist is applied over the conductive layer. Next, the conductive layer is etched using a resist mask formed by a photolithography process using a fifth photomask, so that the pixel electrode 121 is formed.

The pixel electrode 121 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, and silicon oxide. A light-transmitting conductive material such as indium tin oxide can be used.

The pixel electrode 121 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less. As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

In this embodiment, as the pixel electrode 121, an ITO film is formed by a sputtering method, and then a resist is applied on the ITO. Next, the resist is exposed and developed using a sixth photomask to form a resist mask. Next, the pixel electrode 121 is formed by etching ITO using a resist mask. Thereafter, the resist mask is removed. Note that FIG. 7C corresponds to a cross-sectional view taken along lines AB and CD in FIG. 9 has a C-shaped (U-shaped) upper surface shape of a channel formation region where a source region and a drain region face each other. Instead, a thin film transistor in which the upper surface shape of a channel formation region is a parallel type is manufactured. May be.

Through the above steps, a thin film transistor with low off-state current, high on-state current, and high-speed operation can be manufactured. In addition, an element substrate having the thin film transistor as a switching element of a pixel electrode can be manufactured. Note that in this embodiment, one photomask for etching the microcrystalline semiconductor layer and the buffer layer into a predetermined shape is added as compared with a manufacturing process of a normal inverted staggered thin film transistor. Since a multi-tone mask is used as an amorphous semiconductor layer, a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, and a photomask for etching a wiring into a predetermined shape, the process Thus, since the number of photomasks can be reduced by one, the number of masks does not increase in the entire manufacturing process.

(Embodiment 7)
In this embodiment mode, a manufacturing process of a thin film transistor which is more effective in reducing off-state current than the thin film transistor illustrated in FIG. Note that the left side of FIG. 10 is a cross-sectional view taken along the line AB of FIG. 11 and shows a cross section of a region where a thin film transistor is formed, and the right side is a cross-sectional view taken along the line CD of FIG. The cross section of the area | region where wiring cross | intersects is shown.

Through the process of FIG. 6A described in Embodiment 6, the gate electrode 101 is formed. Next, the gate insulating layer 102 is formed over the gate electrode 101 and the substrate 100.

Next, the microcrystalline semiconductor layer 104 and the buffer layer 105 are sequentially stacked over the gate insulating layer 102 through the step of FIG. Next, a resist is applied on the buffer layer 105. Next, the microcrystalline semiconductor layer 104 and the buffer layer 105 are etched using a resist mask formed by a photolithography process, so that the microcrystalline semiconductor layer 104 and the microcrystalline semiconductor layer are formed as illustrated in FIG. 104, the buffer layer 105, and the buffer layer 105 are formed. Then, an amorphous semiconductor layer 114 and an impurity semiconductor layer 115 are formed.

Next, after applying a resist over the impurity semiconductor layer 115, the impurity semiconductor layer 115 and the amorphous semiconductor layer 114 are etched into a desired shape using a resist mask formed by a photolithography process. As shown in FIG. 10B, an amorphous semiconductor layer 114 and an impurity semiconductor layer 115 are formed in a region where a thin film transistor is formed. In addition, in a region where the gate wiring and the source wiring intersect, an amorphous semiconductor layer 114 and an impurity semiconductor layer 115 to which an impurity element imparting one conductivity type is added are formed. Thereafter, the resist mask is removed. Note that side surfaces of the microcrystalline semiconductor layer 104 and the microcrystalline semiconductor layer 104 are covered with the amorphous semiconductor layer 114 and the amorphous semiconductor layer 114.

A conductive film 116 is formed as illustrated in FIG. Then, after applying a resist over the conductive film 116, the conductive film 116 is etched into a desired shape using a resist mask formed by a photolithography process, so that a wiring 110 is formed as shown in FIG. And the wiring 111 is formed.

In addition to the gate insulating layer 102, a microcrystalline semiconductor layer 104, a buffer layer 105, and an amorphous semiconductor layer 114 are formed at the intersection of the gate wiring 101b and the wiring 110, and the distance between the gate wiring 101b and the wiring 110 is spread. Therefore, the parasitic capacitance in the region where the gate wiring 101b and the wiring 110 intersect can be reduced.

The impurity semiconductor layer 115 is etched using the resist mask, so that the impurity semiconductor layer 108 and the impurity semiconductor layer 109 are formed. In the etching step, the amorphous semiconductor layer 114 is also etched, so that a pair of the amorphous semiconductor layer 106 and the amorphous semiconductor layer 107 are formed. In addition, a part of the buffer layer 105 is also etched. A buffer layer partially etched and having a recess is referred to as a buffer layer 105. The step of forming the source region and the drain region and the concave portion of the buffer layer 105 can be formed in the same step. Thereafter, the resist mask is removed.

Next, the exposed buffer layer 105 may be irradiated with H ₂ O plasma. Typically, radicals generated by discharging vaporized water with plasma are irradiated to the exposed portions of the buffer layer 105, the impurity semiconductor layer 108, the impurity semiconductor layer 109, the wiring 110, and the wiring 111, whereby the thin film transistor. High-speed operation is possible, and the on-current can be further increased. In addition, off-state current can be reduced.

Through the above steps, a thin film transistor that can operate at high speed, has high on-state current, and low off-state current is formed.

Through the steps shown in FIGS. 7B and 7C, a passivation layer 119, a planarization layer 120, and a pixel electrode 121 connected to the drain electrode are formed as shown in FIG. 10E. Note that FIG. 10E corresponds to a cross-sectional view taken along AB and CD in FIG. In the thin film transistor illustrated in FIG. 11, the top surface shape of the channel formation region where the source region and the drain region face each other is C-shaped (U shape). May be.

Through the above steps, a thin film transistor with low off-state current, high on-state current, and high-speed operation can be manufactured. In addition, an element substrate having the thin film transistor as a switching element of a pixel electrode can be manufactured.

(Embodiment 8)
In this embodiment mode, structures of a scanning line input terminal portion and a signal line input terminal portion provided in the periphery of the element substrate 130 illustrated in FIG. 12 are described below with reference to FIGS. FIG. 13 is a cross-sectional view of a thin film transistor in a scan line input terminal portion, a signal line input terminal portion, and a pixel portion provided in the peripheral portion of the substrate 100.

Note that in the case of an active matrix display device in which a thin film transistor that controls the potential of a pixel electrode is provided in a pixel provided in a pixel portion, a scanning line is connected to a gate electrode. Alternatively, part of the scan line functions as a gate electrode. Therefore, hereinafter, the scanning line is also referred to as a gate wiring 101b. Since the signal line is connected to the source of the thin film transistor, the signal line is also referred to as a wiring 110 hereinafter. However, when the signal line is connected to the drain of the thin film transistor, the signal line can be a drain wiring.

In FIG. 12, a pixel portion 131 is provided, and protective circuits 132 and 322, a signal line 133, and a scanning line 134 are provided between the pixel portion 131 and the peripheral portion of the substrate 100. Although not shown, signal lines and scanning lines are formed from the protection circuits 132 and 139 to the pixel portion 131. A signal line input terminal portion 137 and a scanning line input terminal portion 138 are provided at end portions of the signal line 133 and the scanning line 134. FPC 140 and FPC 141 are connected to terminals of the signal line input terminal portion 137 and the scanning line input terminal portion 138, respectively, and a signal line driving circuit 135 and a scanning line driving circuit 136 are provided in the FPC 140 and FPC 141, respectively. In the pixel portion 131, pixels 142 are arranged in a matrix.

In FIG. 13A, the scan line input terminal 138a is connected to the gate wiring 101b of the thin film transistor 146. The signal line input terminal 137 a is connected to the wiring 110.

Terminal surfaces of the signal line input terminal 137 a and the scanning line input terminal 138 a are formed in the same layer as the pixel electrode 121. Further, the signal line input terminal 137 a and the scanning line input terminal 138 a are formed in the planarization layer 120 formed over the signal line 133. On the planarization layer 120, the signal line input terminal 137 a and the scanning line input terminal 138 a are connected to the FPC 140 and the wiring 145 of the FPC 141 through the conductive particles 144 of the anisotropic conductive layer 143.

Note that although the gate wiring 101b and the signal line input terminal 137a are connected here, a conductive layer formed using the same layer as the wiring 110 may be provided between the gate wiring 101b and the signal line input terminal 137a.

In FIG. 13B, the scan line input terminal 138 b is connected to the gate wiring 101 b of the thin film transistor 146. In addition, the signal line input terminal 137 b is connected to the wiring 110 of the thin film transistor 146.

The scan line input terminal 138b and the signal line input terminal 137b are each formed using the same layer as the pixel electrode 121 of the thin film transistor 146 in the pixel portion. Further, the scan line input terminal 138 b and the signal line input terminal 137 b are formed over the planarization layer 120 and the passivation layer 119. In addition, in the openings of the planarization layer 120 and the passivation layer 119, the scanning line input terminal 138 b and the signal line input terminal 137 b are connected to the wiring 145 of the FPC 140 and FPC 141 through the conductive particles of the anisotropic conductive layer 143. The

The signal line input terminal 137 b connected to the wiring 110 is formed with an amorphous semiconductor layer 114 and an impurity semiconductor layer 115 in addition to the gate insulating layer 102 between the substrate 100 and the wiring 110, and the thickness thereof is increased. This facilitates the connection between the signal line input terminal 137b and the wiring 145 of the FPC 141.

(Embodiment 9)
Next, a structure of a display panel which is one embodiment of the display device of the present invention is described below.

FIG. 14 illustrates a mode of a display panel in which only the signal line driver circuit 148 is separately formed and connected to the pixel portion 147 formed over the substrate 100. The element substrate over which the pixel portion 147, the protection circuit 153, and the scan line driver circuit 151 are formed is formed using the element substrate described in the above embodiment mode. Operation of a signal line driver circuit that requires a higher driving frequency than a scanning line driver circuit by forming the signal line driver circuit with a thin film transistor that can obtain higher field-effect mobility than a thin film transistor that uses an amorphous semiconductor layer Can be stabilized. Note that the signal line driver circuit 148 may be a transistor using a single crystal semiconductor, a thin film transistor using a polycrystalline semiconductor, or a transistor using SOI. The transistor using SOI includes a transistor using a single crystal semiconductor layer provided over a glass substrate. The pixel portion 147, the signal line driver circuit 148, and the scanning line driver circuit 151 are supplied with a potential of a power source, various signals, and the like through the FPC 152, respectively. The protective circuit 153 formed using the thin film transistor described in the above embodiment may be provided between the signal line driver circuit 148 and the FPC 152 or between the signal line driver circuit 148 and the pixel portion 147. The protective circuit 153 is provided with a protective circuit including one or more elements selected from a thin film transistor, a diode, a resistor, a capacitor, and the like instead of the protective circuit formed using the thin film transistor described in the above embodiment. May be. Note that both the signal line driver circuit and the scan line driver circuit may be formed over the same substrate as the pixel portion.

When the driver circuit is separately formed, the substrate on which the driver circuit is formed does not necessarily have to be attached to the substrate on which the pixel portion is formed, and may be attached to, for example, an FPC. In FIG. 14B, only the signal line driver circuit 148 is separately formed, and the element substrate on which the pixel portion 147, the protection circuit 153, and the scan line driver circuit 151 formed over the substrate 100 are connected to the FPC. The form of the display device panel is shown. The pixel portion 147, the protection circuit 153, and the scan line driver circuit 151 are formed using the thin film transistor described in the above embodiment. The signal line driver circuit 148 is connected to the pixel portion 147 through the FPC 152, the protection circuit, and 153. The pixel portion 147, the signal line driver circuit 148, and the scanning line driver circuit 151 are supplied with a potential of a power source, various signals, and the like through the FPC 152, respectively. A protection circuit 153 formed using the thin film transistor described in the above embodiment may be provided between the FPC 152 and the pixel portion 147. The protective circuit 153 is provided with a protective circuit including one or more elements selected from a thin film transistor, a diode, a resistor, a capacitor, and the like instead of the protective circuit formed using the thin film transistor described in the above embodiment. May be.

Only part of the signal line driver circuit or part of the scan line driver circuit is formed over the same substrate as the pixel portion by using the thin film transistor described in the above embodiment mode, and the rest is separately formed to be electrically connected to the pixel portion. You may make it connect. 14C, the analog switch 149 included in the signal line driver circuit is formed over the same substrate 100 as the pixel portion 147 and the scan line driver circuit 151, and the shift register 150 included in the signal line driver circuit is provided over a different substrate. The form of the display device panel formed and bonded is shown. The pixel portion 147, the protection circuit 153, and the scan line driver circuit 151 are formed using the thin film transistor described in the above embodiment. The shift register 150 included in the signal line driver circuit is connected to the pixel portion 147 through the FPC 152 and the protection circuit 153. The pixel portion 147, the signal line driver circuit, and the scan line driver circuit 151 are supplied with the potential of the power source, various signals, and the like through the FPC 152, respectively. A protection circuit 153 formed using the thin film transistor described in the above embodiment may be provided between the shift register 150 and the analog switch 149. The protective circuit 153 is provided with a protective circuit including one or more elements selected from a thin film transistor, a diode, a resistor, a capacitor, and the like instead of the protective circuit formed using the thin film transistor described in the above embodiment. May be.

As shown in FIG. 14, in the display device of this embodiment, part or all of the driver circuit can be formed over the same substrate as the pixel portion using the thin film transistor described in the above embodiment.

A method for connecting a separately formed substrate is not particularly limited, and a known COG method, wire bonding method, TAB method, or the like can be used. Further, the connection position is not limited to the position illustrated in FIG. 14 as long as electrical connection is possible. In addition, a controller, a CPU, a memory, and the like may be separately formed and connected.

The signal line driver circuit used in the present invention includes a shift register and an analog switch. Alternatively, in addition to the shift register and the analog switch, other circuits such as a buffer, a level shifter, and a source follower may be included. The shift register and the analog switch are not necessarily provided. For example, another circuit that can select a signal line such as a decoder circuit may be used instead of the shift register, or a latch or the like may be used instead of the analog switch. May be.

(Embodiment 10)
The element substrate obtained by the present invention, a display device using the element substrate, and the like can be used for an active matrix display device panel. That is, the present invention can be implemented in all electronic devices in which they are incorporated in the display portion.

Such electronic devices include cameras such as video cameras and digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) ) And the like. An example of these is shown in FIG.

FIG. 15A illustrates a television device. As shown in FIG. 15A, a television device can be completed by incorporating a display panel into a housing. A main screen 203 is formed by the display panel, and a speaker unit 209, operation switches, and the like are provided as other accessory equipment. In this manner, a television device can be completed.

As shown in FIG. 15A, a display panel 202 using a display element is incorporated in a housing 201, and a receiver 205 starts receiving general television broadcasts, and is wired or wirelessly via a modem 204. By connecting to a communication network, information communication in one direction (from the sender to the receiver) or in both directions (between the sender and the receiver or between the receivers) can be performed. The television device can be operated by a switch incorporated in the housing or a separate remote controller 206, and this remote controller is also provided with a display unit 207 for displaying information to be output. Also good.

In addition, the television device may have a configuration in which the sub screen 208 is formed on the second display panel in addition to the main screen 203 to display channels, volume, and the like. In this configuration, the main screen 203 may be formed using a liquid crystal display panel with an excellent viewing angle, and the sub-screen may be formed using a light-emitting display panel that can display with low power consumption. In order to prioritize low power consumption, the main screen 203 may be formed of a light emitting display panel, the sub screen may be formed of a light emitting display panel, and the sub screen may be blinkable.

FIG. 16 is a block diagram illustrating a main configuration of the television device. A pixel portion 245 is formed on the display panel 900. The signal line driver circuit 246 and the scan line driver circuit 247 may be mounted on the display panel 900 by a COG method.

As other external circuit configurations, on the input side of the video signal, among the signals received by the tuner 235, the video signal amplification circuit 236 that amplifies the video signal, and the signal output from the signal is red, green, and blue. And a control circuit 238 for converting the video signal into the input specifications of the driver IC. The control circuit 238 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 239 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

Of the signals received by the tuner 235, the audio signal is sent to the audio signal amplification circuit 240, and the output is supplied to the speaker 244 via the audio signal processing circuit 241. The control circuit 242 receives receiving station (reception frequency) and volume control information from the input unit 243, and sends a signal to the tuner 235 and the audio signal processing circuit 241.

Of course, the present invention is not limited to a television device, but can be applied to various applications such as personal computer monitors, information display boards at railway stations and airports, and advertisement display boards on streets. can do.

By applying the element substrate described in the above embodiment and the display device including the element substrate in the main screen 203 and the sub screen 208, mass productivity of a television device with improved image quality such as contrast can be increased. .

FIG. 15B illustrates an example of a mobile phone 210. The cellular phone 210 includes a display unit 211, an operation unit 212, and the like. In the display portion 211, by using the element substrate described in the above embodiment and a display device including the element substrate, mass productivity of mobile phones with improved image quality such as contrast can be increased.

A portable computer illustrated in FIG. 15C includes a main body 213, a display portion 214, and the like. By applying the element substrate described in any of the above embodiments and a display device including the element substrate to the display portion 214, the mass productivity of a computer with improved image quality such as contrast can be increased.

FIG. 15D illustrates a table lamp, which includes a lighting unit 215, an umbrella 216, a variable arm 217, a column 218, a table 219, and a power source 220. It is manufactured by using the light emitting device of the present invention for the lighting portion 215. The lighting fixture includes a ceiling-fixed lighting fixture or a wall-mounted lighting fixture. By applying the element substrate described in any of the above embodiments and a display device including the element substrate, mass productivity can be increased and an inexpensive desk lamp can be provided.

FIG. 17 shows an example of the configuration of a smartphone mobile phone to which the present invention is applied. FIG. 17A is a front view, FIG. 17B is a rear view, and FIG. The smart phone mobile phone is composed of two housings 221 and 1002. A smart phone mobile phone is a so-called smart phone that has both functions of a mobile phone and a portable information terminal, has a built-in computer, and can perform various data processing in addition to voice calls.

The mobile phone is configured with two casings 221 and 1002. The housing 221 includes a display portion 223, a speaker 224, a microphone 225, operation keys 226, a pointing device 227, a front camera lens 228, an external connection terminal jack 229, an earphone terminal 230, and the like. 231, an external memory slot 232, a rear camera 233, a light 234, and the like. An antenna is incorporated in the housing 221. In addition to the above structure, a non-contact IC chip, a small recording device, or the like may be incorporated.

The housings 221 and 222 which overlap with each other (FIG. 17A slides and expands as illustrated in FIG. 17C. The display portion 223 can incorporate the display device described in the above embodiment mode. The display direction can be changed as appropriate according to the usage pattern, and since the front camera lens 228 is provided on the same surface as the display portion 223, a videophone can be used. A still image and a moving image can be taken with the rear camera 233 and the light 234 using the unit 223 as a viewfinder.

The speaker 224 and the microphone 225 can be used not only for voice calls but also for videophone, recording, reproduction, and the like. The operation keys 226 can be used for making and receiving calls, inputting simple information such as e-mails, scrolling the screen, moving the cursor, and the like.

In addition, it is convenient to use the keyboard 231 when there is a lot of information to be handled, such as creation of a document or use as a portable information terminal. Further, the housing 221 and the housing 222 (FIG. 17A) which overlap with each other are slid and deployed as shown in FIG. 17C. When the portable information terminal can be used, the keyboard 231 and the pointing device 227 are attached. The mouse can be operated with smooth operation. The external connection terminal jack 229 can be connected to an AC adapter and various cables such as a USB cable, and charging and data communication with a personal computer or the like are possible. Further, a recording medium can be inserted into the external memory slot 232 to cope with storing and moving a larger amount of data.

The rear surface of the housing 222 (FIG. 17B) is provided with a rear camera 233 and a light 234, and a still image and a moving image can be taken using the display portion 223 as a viewfinder.

Further, in addition to the above functional configuration, an infrared communication function, a USB port, a TV one-segment reception function, a non-contact IC chip, an earphone jack, and the like may be provided.

By applying the display device described in the above embodiment, mass productivity can be improved.

1 is a cross-sectional view illustrating a thin film transistor of the present invention. 1 is a cross-sectional view illustrating a thin film transistor of the present invention. 1 is a cross-sectional view illustrating a thin film transistor of the present invention. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor of the present invention. 4A and 4B are a cross-sectional view and a top view illustrating a thin film transistor of the invention. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor of the present invention. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor of the present invention. It is a figure explaining the multi-tone mask applicable to this invention. FIG. 10 is a top view illustrating a manufacturing process of a thin film transistor of the present invention. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor of the present invention. FIG. 10 is a top view illustrating a manufacturing process of a thin film transistor of the present invention. It is a top view explaining the element substrate of the present invention. It is sectional drawing explaining the terminal part and pixel part of the element substrate of this invention. FIG. 11 is a perspective view illustrating a display panel of the present invention. FIG. 11 is a perspective view illustrating an electronic device using the display device of the invention. It is a diagram illustrating an electronic device using a display device of the present invention. FIG. 11 is a perspective view illustrating an electronic device using the display device of the invention.

Explanation of symbols

100 substrate 101 gate electrode 101b gate wiring 102 gate insulating layer 102a gate insulating layer 102b gate insulating layer 103 conductive film 104 microcrystalline semiconductor layer 104a microcrystalline semiconductor layer 104b microcrystalline semiconductor layer 104c microcrystalline semiconductor layer 104d microcrystalline semiconductor layer 105 buffer Layer 105 a buffer layer 105 b buffer layer 105 c buffer layer 105 d buffer layer 106 amorphous semiconductor layer 107 amorphous semiconductor layer 108 impurity semiconductor layer 109 impurity semiconductor layer 110 wiring 111 wiring 112 buffer layer 113 buffer layer 114 amorphous semiconductor layer 115 Impurity semiconductor layer 116 Conductive film 117 Resist mask 119 Passivation layer 120 Planarization layer 121 Pixel electrode 122a Gray tone mask 122b Half tone mask 123 Substrate 124 Light shielding portion 1 5 Diffraction grating 126 Light transmission amount 127 Semi-transmission portion 128 Light shielding portion 129 Light transmission amount 130 Element substrate 131 Pixel portion 132 Protection circuit 133 Signal line 134 Scan line 135 Signal line drive circuit 136 Scan line drive circuit 137 Signal line input terminal portion 137a Signal line input terminal 137b Signal line input terminal 138 Scan line input terminal portion 138a Scan line input terminal 138b Scan line input terminal 139 Protection circuit 140 FPC
141 FPC
142 pixel 143 anisotropic conductive layer 144 conductive particle 145 wiring 146 thin film transistor 147 pixel portion 148 signal line driver circuit 149 analog switch 150 shift register 151 scan line driver circuit 152 FPC
153 Protection circuit 201 Case 202 Display panel 203 Main screen 204 Modem 205 Receiver 206 Remote controller 207 Display unit 208 Sub screen 209 Speaker unit 210 Mobile phone 211 Display unit 212 Operation unit 213 Main body 214 Display unit 215 Illumination unit 216 Umbrella 217 Variable arm 218 Post 219 Unit 220 Power supply 221 Housing 222 Housing 223 Display unit 224 Speaker 225 Microphone 226 Operation key 227 Pointing device 228 Front camera lens 229 External connection terminal jack 230 Earphone terminal 231 Keyboard 232 External memory slot 233 Back camera 234 Light 235 Tuner 236 Video signal amplification circuit 237 Video signal processing circuit 238 Control circuit 239 Signal division circuit 240 Audio signal amplification circuit 241 Voice signal processing circuit 242 control circuit 243 input unit 244 speaker 245 pixel unit 246 a signal line drive circuit 247 scanning-line drive circuit

Claims (7)

A microcrystalline semiconductor layer overlapping with the gate electrode through the gate insulating layer;
A buffer layer provided over the microcrystalline semiconductor layer;
An amorphous semiconductor layer covering side surfaces of the buffer layer and the microcrystalline semiconductor layer;
One end portion overlaps the buffer layer, and is provided on the amorphous semiconductor layer, and has a pair of impurity semiconductor layers forming a source region and a drain region,
A thin film transistor, wherein the buffer layer is thicker than the amorphous semiconductor layer. In claim 1,
A thin film transistor, wherein the microcrystalline semiconductor layer has an electric conductivity of 1 × 10 ⁻⁵ S / cm to 5 × 10 ⁻² S / cm. In claim 2,
The thin film transistor, wherein the microcrystalline semiconductor is microcrystalline silicon. In any one of Claims 1 thru | or 3,
A thin film transistor, wherein the amorphous semiconductor layer is amorphous silicon. In claim 1,
The thin film transistor is characterized in that the buffer layer is thicker than each of the microcrystalline semiconductor layer and the amorphous semiconductor layer. In claim 1,
A thin film transistor, wherein the buffer layer has a thickness of 500 nm to 3000 nm, and the amorphous semiconductor layer has a thickness of 50 nm to less than 500 nm. A display device, wherein the thin film transistor according to claim 1 is provided in each pixel of a pixel portion.

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