JP2009207047A - Frame length variable transmitter and transmission timing correction processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct transmission timing in accordance with a transmission timing signal without destroying transmission data with respect to a frame length variable transmission frame, regarding a frame length variable transmitter and a transmission timing correction processing method. <P>SOLUTION: Each time a reference timing signal is input, only one of '0' side and '1' side is brought into an enable state alternately by an enable signal generation section 21 that alternately outputs '0' and '1', and a pattern comparison section 24 compares cyclic prefixes to determine whether it is a frame header or not. A phase difference between reference timing and transmission timing is detected by a phase difference detection section 28 and in accordance with a signal indicating presence of phase variation in transmission timing, based on a comparison result of the pattern comparison section 24, a switching control section 26 allows a selector 30 to select a timing signal, delayed by a half frame, from a timing generation section 29. In accordance with the timing signal, a timing correction section 31 corrects the transmission timing at a header position of the frame. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a transmitter having a variable frame length and a transmission timing correction processing method, and in particular, a mobile radio communication system that includes a cyclic prefix (CP) pattern and transmits a transmission frame having a variable frame length. And a timing correction processing method for correcting the transmission timing of the transmission frame. The cyclic prefix (CP) is obtained by copying (copying) several bits of the last data of the transmission frame to the head position of the transmission frame.

  FIG. 5 shows a configuration example of a transmission frame timing correction unit in a conventional transmitter. The conventional transmission frame timing correction unit includes a write address generation unit 11, a phase difference detection unit 12, a read address generation unit 13, and a timing correction memory (RAM) 14, and temporarily stores input data in the memory (RAM) 14. The transmission timing of the transmission frame is corrected by correcting the address stored in the memory and read out as transmission data from the memory (RAM) 14.

  More specifically, a write address is generated by the write address generation unit 11 so as to be stored in the timing correction memory (RAM) 14 in order from the first input data of the transmission frame in synchronization with the reference timing signal, and the input data is The data are sequentially stored in a timing correction memory (RAM) 14.

  On the other hand, the phase difference between the transmission timing signal and the reference timing signal (that is, the generation timing of the first write address) is detected by the phase difference detection unit 12, and the phase difference is notified to the read address generation unit 13 to generate the read address. The unit 13 generates a read address according to the phase difference, reads out the transmission data from the read address, and outputs it, thereby correcting the timing according to the transmission timing signal and transmitting the transmission frame.

  A time chart of an operation example of the above-described conventional transmission frame timing correction is shown in FIGS. Here, if the frame length is, for example, 0.5 ms, a reference timing signal is input every 0.5 ms. Conventionally, the phase difference between the reference timing signal and the transmission timing signal is detected, and the phase difference is Accordingly, only by generating a read address of the memory (RAM) 14, the transmission frame is output in phase with the transmission timing signal. This is based on the premise that the frame length of a transmission frame does not change, and is used to correct the transmission timing of a transmission frame of one type of frame length.

  An operation example of conventional transmission frame timing correction will be described with reference to FIGS. FIG. 6 shows an example of operation when the transmission timing fluctuates by 2 bits on the plus side (delayed by 2 bits), and FIG. 7 shows the case where the transmission timing fluctuates by 2 bits on the minus side (2 bits earlier). An example of the operation is shown. 6 and 7, (a) is a reference timing signal, (b) is input data, (c) is a transmission timing signal, (d) is a write address, (e) is a read address, and (f) is a transmission timing. The transmission data after correction is shown.

  As shown in FIG. 6C, when the transmission timing fluctuates to the plus side by 2 bits (delayed by 2 bits), the final address (n) of the frame data is set as shown in FIG. As shown in FIG. 5F, the last bit (DTn) of the frame data is repeatedly read twice, and the last bit (DTn) is added to the end of the frame for 2 bits. Output transmission data.

  Also, as shown in FIG. 7C, when the transmission timing fluctuates to the minus side by 2 bits (accelerated by 2 bits), as shown in FIG. Read by skipping the read address of the bits (DT1, DT2) of the click prefix (CP), and delete and transmit the two bits (DT1, DT2) of the cyclic prefix (CP) as shown in FIG. Output data. Note that even if the cyclic prefix (CP) bit is deleted, the exact same data is present at the rear of the frame data, so that there is no effect on the data reproduction on the receiving side.

In this way, memory is provided to read data from a predetermined read address while writing data to a predetermined write address, and the write address is updated cyclically within a predetermined range while incrementing every clock from the predetermined write side initial address. A technique for correcting the transmission timing of transmission data by cyclically updating the read address within a predetermined range while incrementing every predetermined clock from the initial address on the read side is disclosed in Patent Document 1 below. Yes.
Japanese Patent No. 2850875

  However, in addition to the conventional transmission frame with a frame length of 0.5 ms, a 1.0 ms transmission channel (RACH: Random Access Channel) having a frame length twice that of the transmission frame is introduced, and the variable length of 0.5 ms and 1.0 ms is introduced. Also for a transmission frame having a frame length, it is necessary to correct the transmission timing in accordance with the phase variation of the transmission timing signal, as in the prior art.

  However, as shown in FIG. 8, even when the frame length is 1.0 ms, the input reference timing signal and the transmission timing signal are input at a period of 0.5 ms, which is half that of the conventional case. When the phase variation of the transmission timing signal occurs, the phase variation of the transmission timing signal occurs at the timing when the cyclic prefix (CP) near the head of the frame appears (for example, timing (A) in FIG. 8). In this case, transmission timing correction similar to the conventional one can be performed.

  However, when a phase variation of the transmission timing signal occurs at the transmission timing of the central data of the frame (for example, the timing shown in FIG. 8B), the cyclic prefix (CP) bit insertion / extraction is performed. If the transmission timing cannot be corrected and the transmission timing is corrected by inserting / extracting the central data bit of the frame, the transmission data is destroyed and the transmission data cannot be restored correctly on the receiving side. There was a problem that.

  The present invention provides a transmitter and a transmission timing correction processing method capable of correcting a transmission timing according to a phase variation of a transmission timing signal without destroying transmission data for a transmission frame having a variable frame length. .

  The transmission frame timing correction unit that solves the above problem includes a frame head position determination unit that compares a cyclic prefix data pattern with a transmission frame having a variable frame length and determines whether or not the frame is the head position. A transmission timing signal phase fluctuation detecting means for detecting whether or not a phase fluctuation has occurred in the transmission timing signal by detecting a phase difference between the reference timing signal and the transmission timing signal; and transmitting by the transmission timing signal phase fluctuation detecting means When the timing at which the phase variation of the timing signal is detected is determined not to be the start position of the frame by the frame start position determination means, based on the transmission timing signal that is delayed by half the frame length. And means for correcting the transmission timing of the transmission frame. The requirement that there were example.

  The transmission timing correction processing method stores each input data of a transmission frame in a timing correction memory in synchronization with the reference timing signal, and transmits the transmission timing based on the phase difference between the reference timing signal and the transmission timing signal. In the transmission timing correction processing method for correcting the first and second system components, one system component is enabled and the other system component is disabled, and the reference timing is set. Configuration of a system in which a step of alternately switching between an enable state and a non-enable state every time a signal is input, a phase difference between a reference timing signal and a transmission timing signal are detected, and whether or not the phase difference varies is enabled Informing the element and notifying the timing generator of the amount of variation in the phase difference; and the first or second In the enabled state, each input data is stored in the memory for detecting the head position in synchronization with the reference timing signal, and the data stored in the memory for detecting the head position is twice the cycle of the reference timing. Input data that is read at the timing when the copy source data of the cyclic prefix of the transmission frame of the frame length is input and the data pattern read from the head position detection memory is input at the timing of reading the data When a pattern mismatch is detected by the comparison and a notification that there is a variation in phase difference is received, an instruction is given to select a generation timing signal output from the timing generation unit. Outputting a switching control signal; and in the timing generation unit, the notification Generating a generation timing signal obtained by adding a delay corresponding to one period of a reference timing to the fluctuation amount of the phase difference, and the generation timing input from the timing generation unit when the switching control signal is input A signal is selected, and when the switching control signal is not input, the transmission timing signal is selected and output, and the timing correction memory is selected according to the generation timing signal or transmission timing signal that is selected and output. Generating a read address and reading transmission data.

  According to the present invention, a frame length can be obtained by recognizing the start position of a frame using a cyclic prefix (CP) and correcting the transmission timing at the start position of the frame for a transmission frame having a variable frame length. The transmission timing can be corrected according to the phase variation of the transmission timing signal even for a transmission frame having a variable.

  FIG. 1 shows a configuration example of a first embodiment of a transmission frame timing correction unit of a transmitter according to the present invention. The transmission frame timing correction unit according to the present invention includes an enable signal generation unit 21 that alternately outputs a high level signal and a low level signal each time a reference timing signal is input.

  In response to the enable signal, two components are provided in which one is enabled and the other is not enabled. The components of the two systems are represented in FIG. 1 as an enable '0' side and an enable '1' side. Each component on the enable '0' side is denoted by a symbol '_0', and the enable '1' Each component on the side is given a symbol “_1”.

  Each of the two system components includes head position detection memories (RAM) 24_0 and 24_1 for storing input data, write address generation units 22_0 and 22_1, and read address generation units 23_0 and 23_1. Data reading means is configured.

  The two systems of components include pattern comparison units 25_0 and 25_1 that compare read data from input position data and read data from memory (RAM) 24_0 and 24_1 for head position detection, and generation of transmission timing signals in the selector 30. And switching control units 26_0 and 26_1 that generate switching control signals for instructing selection of timing signals.

  Then, a logical sum (OR) unit 27 that outputs a logical sum (OR) signal of the switching control signals output from the switching control units 26_0 and 26_1, and a phase difference between the reference timing signal and the transmission timing signal are detected. And a phase difference detector 28 for detecting the presence or absence of phase fluctuations in the transmission timing signal and the amount of phase fluctuation.

  Furthermore, a timing generation unit 29 that generates a generation timing signal obtained by delaying the phase variation amount of the transmission timing signal by one cycle of the reference timing, and either the transmission timing signal or the generation timing signal is changed according to the switching control signal. A selector 30 for selecting and outputting is added to the conventional transmission frame timing correction unit 31.

  2 and 3 show time charts of an operation example of the transmission timing correction processing according to the present invention shown in FIG. In the operation example shown in FIGS. 2 and 3, the reference timing signal and the transmission timing signals (1) to (5) are input every 0.5 ms (see (a) and (c) in the figure), and the transmission frame It is assumed that the frame length is 1.0 ms (see (b) in the figure). Even when the frame length is 1.0 ms, the position where the cyclic prefix (CP) is arranged is the head of the frame, and the last few bits of data of one frame (1.0 ms) are copied (copied). This is stored here (see (b) of the figure).

  In FIG. 2, the phase of the transmission timing signal fluctuates near the center (about 0.5 ms timing position) of the transmission frame (at 1.0 ms). As an example, the phase fluctuation of the transmission timing signal (4) occurred. An example of the case is shown. The enable signal generation unit 21 alternately outputs a high level (“1”) and low level (“0”) enable signal at each reference timing (0.5 ms) (see FIG. 4D). Is at the low level ('0'), the write address generation unit 22_0 on the '0' side is used. When the enable signal is at the high level ('1'), the write address generation unit 22_1 on the '1' side is Write addresses are generated and output, and input data (several bits) is stored in head position detection memories (RAM) 24_0 and 24_1 in synchronization with the reference timing signal.

  The data stored in the memories (RAM) 24_0 and 24_1 is cyclic prefix (CP) data (data obtained by copying the last few bits of the 1.0 ms frame) or the center of the 1.0 ms frame. It is nearby data. Therefore, the read address generators 23_0 and 23_1 generate and output read addresses for reading data stored in the memories (RAM) 24_0 and 24_1 at the timing when the last few bits of the 1.0 ms frame appear as input data. .

  The pattern comparison units 25_0 and 25_1 compare the pattern of data read from the memory (RAM) 24_0 and 24_1 with the pattern of input data. In the case of the operation example of FIG. 2, since the cyclic prefix (CP) is input together with the input of the reference timing signal on the enable “0” side, the patterns compared by the pattern comparison unit 25_0 match (FIG. 2G). reference). However, on the enable ‘1’ side, the transmission data is input when the reference timing signal is input, so the patterns compared by the pattern comparison unit 25 </ b> _ <b> 1 do not match (see (h) in the figure).

  Further, the phase difference detecting unit 28 notifies the enable state switching control units 26_0 and 26_1 of the presence / absence (p) of occurrence of the phase variation of the transmission timing by the phase comparison between the reference timing and the transmission timing. For example, when there is a phase variation in the transmission timing when the enable signal is at a low level ('0'), p = '01 'is output, and when the enable signal is at a high level (' 1 '), the phase of the transmission timing is output. When there is a fluctuation, p = '10 'is output.

  In the case of the operation example of FIG. 2, since the transmission timing signal of (4) has a phase fluctuation and the enable signal is at a high level ('1') at that time, the signal of p = '10 'is switched to the switching control unit 26_0. , 26_1. Since there is no fluctuation except for the transmission timing signal of (4), p = '00 'indicating that there is no fluctuation is transmitted. Further, the phase difference detection unit 28 notifies the timing generation unit 29 of the phase fluctuation amount (q) of the transmission timing by comparing the phase between the reference timing and the transmission timing (see (f) in the figure).

  The enable state switching control units 26_0 and 26_1 receive the information (p) indicating that the transmission timing phase is changed and the comparison results of the pattern comparison units 25_0 and 25_1. The switching control unit 26_0 on the enable “0” side receives information (p = “01”) indicating that there is a phase variation of the transmission timing when the enable signal is at a low level (“0”), and When the mismatch comparison result is input from the pattern comparison unit 25_0, a switching control signal ('1') for selecting a generation timing signal obtained by delaying the transmission timing by 0.5 ms is output. When the above condition is not satisfied, “0” is output as the switching control signal.

  Further, the switching control unit 26_1 on the enable '1' side receives information (p = '10 ') indicating that there is a phase variation of the transmission timing when the enable signal is at a high level (' 1 '). When a mismatch comparison result is input from the pattern comparison unit 25_1, a switching control signal ('1') for selecting a generation timing signal obtained by delaying the transmission timing by 0.5 ms is output. When the above condition is not satisfied, “0” is output as the switching control signal.

  That is, each of the switching control units 26_0 and 26_1 in the enabled state has a variation in transmission timing when in the enabled state, and the variation in the transmission timing is near the beginning of the frame where the cyclic prefix (CP) appears. If it occurs at the center of the frame, a switching control signal ('1') is output. In other cases, “0” is output as the switching control signal.

  In the operation example of FIG. 2, since the phase variation occurs in the transmission timing of (4), the transmission timing variation occurs when the enable signal is “1”, and the transmission timing of (4) is a frame. Since the pattern comparison result by the pattern comparison unit 25_1 does not match, the enable control unit 26_1 that switches to the “1” side outputs the switching control signal “1” (see (j) of FIG. 2). .

  The switching control signal ‘0’ is still output from 26 _ 0 of the switching control unit for enabling ‘0’ side switching (see (i) of FIG. 2). The logical sum operation (OR) unit 27 calculates the logical sum of the switching control signals “0” and “1” output from the replacement control unit 26_0 and the replacement control unit 26_1, and the operation result “1” is obtained. Input to the selector 30.

  On the other hand, the timing generation unit 29 receives the information (q) of the phase fluctuation amount detected by the phase difference detection unit 28, and generates a generation timing signal that gives a delay of 0.5 ms to the phase fluctuation amount. The generation timing signal is output to the selector 30 (see FIG. 2 (k)). The selector 30 selects and outputs the generation timing signal when the switching control signal input via the logical sum (OR) unit 27 is “1”, and when the switching control signal is “0”. The conventional transmission timing signal is selected and output.

  The transmission timing signal or the generation timing signal output from the selector 30 is given to the transmission frame timing correction unit 31, and the transmission frame timing correction unit 31 performs the transmission timing correction similar to the conventional one described with reference to FIG. The transmission timing is corrected at the boundary.

  That is, in the case of the operation example of FIG. 2, with respect to the transmission timing fluctuation of (4), transmission is performed at the timing position (6) of the frame boundary as shown in (k) of the figure by the generation timing signal. Timing correction is performed. Thereby, since the transmission timing is corrected by inserting and removing the cyclic prefix, the transmission timing can be corrected without destroying the transmission data.

  FIG. 3 shows an example of the operation when the transmission timing varies in (3), that is, when the transmission timing varies near the frame boundary of the input data (at 1.0 ms). When the transmission timing fluctuates at the timing position (3), the operation up to the pattern comparison is the same as the case of the transmission timing fluctuation at the position (4) described above.

  When the transmission timing fluctuates at the timing position (3), the change of the transmission timing is detected by the switching control unit 26_0 on the enable '0' side (see FIG. 3 (e)). At this time, the pattern comparison unit 25_0 Since the pattern comparison results obtained by the above are coincident (see (g) in the figure), the switching control signal output from the switching control unit 26_0 is “0” (see (i) in the figure).

  Further, the switching control unit 26_1 on the enable ‘1’ side outputs a switching control signal ‘0’ because a signal with a change in transmission timing is not input (see (j) in the figure). The logical sum '0' of the switching control signals '0' from the switching control unit 26_0 and the switching control unit 26_1 is output from the logical sum operation (OR) unit 27, and the switching control signal '0' is input to the selector 30. .

  The selector 30 selects the conventional transmission timing signal by the switching control signal “0” and outputs it to the transmission timing correction unit 31 (see (k) in the figure). That is, the transmission timing is corrected at the timing position (7) in (k) in FIG. 9, that is, at the frame boundary, with respect to the variation in the transmission timing (3).

  The transmission timing correction unit 31 performs a transmission timing correction process similar to the conventional one described in FIG. 5 according to the transmission timing signal. Thereby, since the transmission timing is corrected by inserting and removing the cyclic prefix, the transmission timing can be corrected without destroying the transmission data.

  FIG. 4 shows a configuration example of a transmission frame timing correction unit according to the second to fourth embodiments of the present invention. In the configuration example shown in FIG. 4, the comparison data amount in the pattern comparison units 25_0 and 25_1 can be set in the configuration example shown in FIG. 1, and the phase difference comparison range in the phase difference detection unit 28 is set. In addition, a transmission data protection function corresponding to the phase difference comparison result in the phase difference detection unit 28 is added.

  In the configuration for setting the comparison data amount in the pattern comparison units 25_0 and 25_1, the setting information (r) of the comparison data amount is input to the pattern comparison units 25_0 and 25_1, and the pattern comparison units 25_0 and 25_1 are for detecting the head position. The data read from the memories (RAM) 24_0 and 24_1 and the input data are subjected to pattern comparison with respect to the data of the comparison data amount specified by the setting information (r), and the comparison result is output to the switching control units 26_0 and 26_1. . As a result, the comparison data amount can be changed by setting the comparison data amount from the section, and even when the length of the cyclic prefix (CP) is changed, it is possible to flexibly cope with the change.

  Further, in the configuration for setting the phase difference comparison range in the phase difference detection unit 28, the setting information (s) of the timing range for performing the phase difference comparison is input to the phase difference detection unit 28, and the phase difference detection unit 28 is set to the reference timing. When the phase difference between the transmission timing and the transmission timing is equal to or greater than the value of the setting information (s), the phase fluctuation amount (q) is regarded as zero, and the timing generation unit 29 is notified that the phase difference fluctuation amount is zero. Is output.

  When the transmission timing fluctuation amount is equal to or larger than the value of the setting information (s), the timing generation unit 29 sets the phase fluctuation amount (q) to zero and generates a transmission timing signal having a phase before the occurrence of the phase difference fluctuation. And output. Therefore, the selector 30 outputs the transmission timing in the state before the transmission timing fluctuation occurs, and operates as if there was no fluctuation in the transmission timing. However, since the transmission timing actually fluctuates, a phase difference occurs between the transmission timing and the transmission data, but normal transmission data can be sent to the receiving side.

  Note that this function can detect the start position of a frame by comparing and determining cyclic prefix (CP) patterns when the phase variation of the transmission timing occurs beyond the range of the cyclic prefix (CP). If the transmission timing is corrected in the middle of the frame and transmission data is corrected, the transmission data is destroyed. Therefore, a transmission data protection function is provided to prevent this. Except for this function, the second embodiment is the same as the first embodiment.

  When the transmission data protection function described above is provided, a phase difference occurs between the actual transmission timing signal and the transmission data, and it is not desirable that this phase difference continues for a long time. Therefore, the phase difference comparison protection setting information (t) The number of frames that are input to the phase difference detection unit 28 and the phase difference between the reference timing signal and the transmission timing signal in the phase difference detection unit 28 is equal to or greater than the value of the setting information (s) is counted. When the set value (t) of the phase difference comparison protection setting is exceeded, a notification of the variation amount (q) of the phase difference is output to the timing generation unit 29, and the timing generation unit 29 outputs the variation amount (q). The transmission timing signal according to the above is output. Other functions are the same as those in the first embodiment.

  Thus, when the number of frames in which the phase difference from the transmission timing signal is equal to or greater than the value of the setting information (s) is equal to or greater than the predetermined number (t), the transmission timing signal output from the selector 30 Is forced to be the original transmission timing signal, the transmission timing is corrected to the phase of the original transmission timing signal, and the phase difference between the transmission timing signal and the transmission data is eliminated.

  However, if the transmission timing is corrected forcibly beyond the range of the cyclic prefix in this way, data destruction occurs in the frame for which the transmission timing correction has been performed, but in frames subsequent to that frame, The phase difference between the transmission timing signal and the transmission data is eliminated, and it is possible to prevent the phase difference between the transmission data and the transmission timing signal from occurring for a long time.

  In the above embodiment, transmission timing correction of a transmission frame having a frame length of 1.0 ms has been described. However, in the case of a transmission frame of 0.5 ms, the cyclic prefix comparison by the pattern comparison units 25_0 and 25_1 is Since this is a comparison with the last data bit of the next frame, a non-matching comparison result is output, '1' is output as a switching control signal from the switching control units 26_0 and 26_1, and a transmission timing signal delayed by 0.5 ms The transmission timing will be corrected at this point. However, the transmission timing correction is delayed by one cycle of the reference timing, so there will be no problem in actual operation, and transmission data will be corrected without destroying the transmission data. Processing can be performed.

It is a figure which shows the structural example of 1st Embodiment of the transmission frame timing correction | amendment part of the transmitter of this invention. It is a time chart of the operation example of the transmission timing correction process by this invention. It is a time chart of the operation example of the transmission timing correction process by this invention. It is a figure which shows the structural example of the transmission frame timing correction | amendment part of the 2nd-4th embodiment of this invention. It is a figure which shows the structural example of the transmission frame timing correction | amendment part in the conventional transmitter. It is a time chart of the operation example of the timing correction of the conventional transmission frame. It is a time chart of the operation example of the timing correction of the conventional transmission frame. It is explanatory drawing of the problem of the timing correction of the conventional transmission frame.

Explanation of symbols

11 Write Address Generation Unit 12 Phase Difference Detection Unit 13 Read Address Generation Unit 14 Timing Correction Memory (RAM)
21 Enable signal generation unit 22_0, 22_1 Write address generation unit 23_0, 23_1 Read address generation unit 24_0, 24_1 Memory for detecting the start position (RAM)
25 — 0, 25 — 1 Pattern comparison unit 26 — 0, 26 — 1 Switching control unit 27 OR operation unit (OR) unit 28 Phase difference detection unit 29 Timing generation unit 30 Selector 31 Transmission frame timing correction unit

Claims (6)

A frame head position determination means for comparing a cyclic prefix data pattern with respect to a transmission frame having a variable frame length and determining whether or not it is the head position of the frame;
A transmission timing signal phase fluctuation detecting means for detecting whether a phase fluctuation has occurred in the transmission timing signal by detecting a phase difference between the reference timing signal and the transmission timing signal;
When the timing at which the phase variation of the transmission timing signal is detected by the transmission timing signal phase variation detection means is determined not to be the head position of the frame by the frame head position determination means, the transmission timing signal is half the frame length. Means for correcting the transmission timing of the transmission frame based on the transmission timing signal delayed by the timing;
A transmitter for correcting transmission timing. In a transmitter that stores each input data of a transmission frame in a memory for timing correction in synchronization with a reference timing signal, and corrects transmission timing based on a phase difference between the reference timing signal and the transmission timing signal.
With respect to the components of the first and second systems, the components of one system are enabled, the components of the other system are disabled, and each time the reference timing signal is input, An enable signal generator for generating an enable signal for alternately switching between the non-enable states;
Phase difference detection that detects the phase difference between the reference timing signal and the transmission timing signal, notifies the enabled system components of the presence or absence of the variation in the phase difference, and notifies the timing generator of the amount of variation in the phase difference With
Each of the first and second systems includes
Each input data is stored in a head position detection memory in synchronization with the reference timing signal, and the data stored in the head position detection memory is a transmission frame having a frame length twice the period of the reference timing. Leading data reading means for reading at the timing when copy source data of the cyclic prefix is input,
A pattern comparison unit that compares the pattern of data read by the head data reading means with the pattern of input data input at the timing of reading the data;
Switching for instructing to select a generation timing signal output from the timing generation unit when a pattern mismatch is detected by the pattern comparison unit and a notification that there is a variation in phase difference is received from the phase difference detection unit A switching control unit that outputs a control signal,
A timing generation unit that generates a generation timing signal in which a delay of one cycle of a reference timing is given to the variation amount of the phase difference notified from the phase difference detection unit;
Transmission timing selection that selects the generation timing signal input from the timing generation unit when the switching control signal is input from the switching control unit, and outputs the transmission timing signal when the switching control signal is not input And
In accordance with the generation timing signal or transmission timing signal output from the transmission timing selection unit, a timing correction unit that generates a read address of the timing correction memory and reads transmission data;
A transmitter for correcting transmission timing.   The transmitter for correcting transmission timing according to claim 2, wherein the pattern comparison unit has a configuration for comparing a pattern with data having a data amount set from the outside.   When the phase difference detection unit detects a phase difference variation exceeding a set value of a phase difference range set from the outside, the phase difference detection unit outputs a notification that the phase difference variation amount is zero to the timing generation unit, and the timing generation unit The transmitter for correcting the transmission timing according to claim 2, wherein the transmitter has a configuration for generating and outputting a transmission timing signal of a phase before the occurrence of the phase difference fluctuation.   When the number of occurrences of phase difference fluctuation exceeding the set value of the phase difference range set from the outside exceeds the set number of times set from outside, the phase difference detection unit notifies the amount of fluctuation of the phase difference. The transmitter for correcting transmission timing according to claim 4, wherein the transmitter is configured to output to the timing generation unit, and the timing generation unit outputs a transmission timing signal according to the variation amount. In a transmission timing correction processing method for storing each input data of a transmission frame in a timing correction memory in synchronization with a reference timing signal and correcting a transmission timing based on a phase difference between the reference timing signal and the transmission timing signal.
With respect to the components of the first and second systems, the components of one system are enabled, the components of the other system are disabled, and each time the reference timing signal is input, Alternately switching between non-enabled states;
Detecting a phase difference between a reference timing signal and a transmission timing signal, notifying the presence or absence of a variation in the phase difference to a system component in an enabled state, and notifying the timing generation unit of the variation amount in the phase difference;
In the first or second enable state system, each input data is stored in a head position detection memory in synchronization with the reference timing signal, and the data stored in the head position detection memory is Read the cyclic prefix copy source data of the transmission frame having a frame length twice the cycle of the reference timing at the input timing, and read the data pattern read from the head position detection memory. A step of comparing with a pattern of input data input at timing;
Outputting a switching control signal for instructing to select a generation timing signal output from a timing generation unit when a pattern mismatch is detected by the comparison and a notification of the presence or absence of the phase difference variation is received; ,
In the timing generation unit, generating a generation timing signal in which a delay of one period of a reference timing is given to the notified variation amount of the phase difference;
Selecting the generation timing signal input from the timing generator when the switching control signal is input, and selecting and outputting the transmission timing signal when the switching control signal is not input;
Generating a read address of the memory for timing correction and reading out transmission data in accordance with the generation timing signal or the transmission timing signal selected and output, and a transmission timing correction processing method.

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