JP2009206293A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2009206293A
JP2009206293A JP2008046973A JP2008046973A JP2009206293A JP 2009206293 A JP2009206293 A JP 2009206293A JP 2008046973 A JP2008046973 A JP 2008046973A JP 2008046973 A JP2008046973 A JP 2008046973A JP 2009206293 A JP2009206293 A JP 2009206293A
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wiring board
wiring
semiconductor device
semiconductor element
opening
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Japanese (ja)
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Yutaka Kato
豊 加藤
Katsumi Otani
克実 大谷
Hiroaki Suzuki
宏明 鈴木
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-profile semiconductor device while suppressing degradation in the characteristics of the semiconductor device. <P>SOLUTION: A semiconductor element 3 is connected with a first wiring substrate 22, which is mounted on a second wiring substrate 23 so that the semiconductor element 3 may be accommodated in an opening 5 formed on the second wiring substrate 23. This mounting can achieve the electrical connection between the semiconductor element 3 and the second wiring substrate 23 using a shorter wiring length of a wiring pattern 27 formed on the first wiring substrate 22 without using any metallic thin wires. As a result, a low-profile size of a semiconductor device 21 can be achieved while suppressing degradation in the characteristics of the semiconductor device 21. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、配線基板に半導体素子を装着して形成される半導体装置、およびその製造方法に関するものである。   The present invention relates to a semiconductor device formed by mounting a semiconductor element on a wiring board, and a manufacturing method thereof.

近年の電子機器の多機能化、小型・薄型化に伴い、半導体装置においても、小型化・薄型化が進んでいる。このような目的を達成する半導体装置の１種として、半導体装置の下面側に電気的接続を行うための外部端子としての半田ボールをマトリクス状に配置した、いわゆるＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｌｌａｙ）型のパッケージや、外部端子をマトリクス状に配置したＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｌｌａｙ）型のパッケージなどが知られている。   In recent years, with the increase in functionality, miniaturization, and thinning of electronic devices, semiconductor devices are also becoming smaller and thinner. As one type of semiconductor device that achieves such an object, a so-called BGA (Ball Grid Array) type package in which solder balls as external terminals for electrical connection are arranged in a matrix on the lower surface side of the semiconductor device. In addition, an LGA (Land Grid Array) type package in which external terminals are arranged in a matrix is known.

このようなＢＧＡ、ＬＧＡ型の半導体装置において、半導体装置のさらなる薄型化を実現するには、半導体素子を搭載する配線基板を改良する必要がある。
ここで、従来の半導体装置を、図４〜図６を参照しながら説明する。図４は従来の半導体装置を示す断面図、図５は従来の半導体装置を示す斜視図、図６は従来の半導体装置の製造工程を説明する工程断面図である。なお、図５においては、封止樹脂体４を省略して示す。 In such BGA and LGA type semiconductor devices, it is necessary to improve the wiring board on which the semiconductor elements are mounted in order to realize further thinning of the semiconductor device.
Here, a conventional semiconductor device will be described with reference to FIGS. FIG. 4 is a cross-sectional view showing a conventional semiconductor device, FIG. 5 is a perspective view showing the conventional semiconductor device, and FIG. 6 is a process cross-sectional view illustrating a manufacturing process of the conventional semiconductor device. In FIG. 5, the sealing resin body 4 is omitted.

図４、図５に示すように、従来の半導体装置１は、絶縁性樹脂からなり、その両面にビアホール９を介して互いに電気的に接続された配線パターン８が形成されている配線基板２と、配線基板２の中央部に半導体素子３より一回り大きなサイズおよび貫通状態で設けられた開口部５に収納された半導体素子３と、半導体素子３の電極パッド（図示せず）と配線基板２の半導体素子３の電極パッドがある面（以下、半導体素子の主面とも称す）と同一面（以下、配線基板２の主面とも称す）の配線パターン８とを電気的に接続した金属細線７と、配線基板２における主面と反対側の面にマトリクス状に配置され、配線基板２の配線パターン８と電気的に接続したボール電極１０と、金属細線７と配線基板２の主面および開口部の一部と半導体素子３の主面を覆うように封止した封止樹脂体４とにより構成されたものである。   As shown in FIGS. 4 and 5, the conventional semiconductor device 1 includes a wiring substrate 2 made of an insulating resin and having wiring patterns 8 electrically connected to each other via via holes 9 on both surfaces thereof. The semiconductor element 3 housed in the opening 5 provided in the central portion of the wiring board 2 in a size and a size larger than the semiconductor element 3, the electrode pad (not shown) of the semiconductor element 3, and the wiring board 2 The thin metal wire 7 electrically connected to the wiring pattern 8 on the same surface (hereinafter also referred to as the main surface of the wiring substrate 2) and the surface (hereinafter also referred to as the main surface of the semiconductor element) of the semiconductor element 3 of FIG. The ball electrodes 10 arranged in a matrix on the surface opposite to the main surface of the wiring substrate 2 and electrically connected to the wiring pattern 8 of the wiring substrate 2, the metal thin wires 7, the main surface of the wiring substrate 2, and the openings. Part of the semiconductor element So as to cover the third main surface is one that is constituted by a sealing resin member 4 sealed.

次に、従来の半導体装置の製造方法について説明する。
図６（ａ）に示すように、両面に配線パターン８が形成され、中央部に半導体素子３を収納するための開口部５を設けた配線基板２を用意し、図６（ｂ）に示すように、配線基板２の開口部５に半導体素子３を保持する。 Next, a conventional method for manufacturing a semiconductor device will be described.
As shown in FIG. 6A, a wiring board 2 having wiring patterns 8 formed on both surfaces and having an opening 5 for housing the semiconductor element 3 in the center is prepared, as shown in FIG. 6B. As described above, the semiconductor element 3 is held in the opening 5 of the wiring board 2.

次に、図６（ｃ）に示すように、配線基板２の開口部５に保持した半導体素子３の電極パッドと配線基板２の主面側に設けられた配線パターン８とを金属細線７により電気的に接続する。ワイヤーボンディング後、半導体素子３は金属細線７の張力により宙吊り状態となっている。   Next, as shown in FIG. 6C, the electrode pads of the semiconductor element 3 held in the opening 5 of the wiring board 2 and the wiring pattern 8 provided on the main surface side of the wiring board 2 are connected by the fine metal wires 7. Connect electrically. After the wire bonding, the semiconductor element 3 is suspended by the tension of the fine metal wires 7.

次に、図６（ｄ）に示すように、金属細線７の張力により宙吊り状態にある半導体素子３および配線基板２を、真空吸着装置（図示せず）の吸着孔６によって半導体素子３の主面に対する反対側の面から真空吸着固定し、スクリーン印刷技術にて、封止樹脂体４を転写させる。   Next, as shown in FIG. 6 (d), the semiconductor element 3 and the wiring board 2 that are suspended by the tension of the fine metal wires 7 are connected to the main element of the semiconductor element 3 through the suction holes 6 of a vacuum suction device (not shown). Vacuum sealing is performed from the surface opposite to the surface, and the sealing resin body 4 is transferred by screen printing technology.

その際使用する樹脂は、表面張力により半導体素子３と配線基板２間から流れ落ちない程度の物性を有する。さらに、真空吸着したままベークして樹脂を硬化させることにより半導体素子３を規定の位置に保持したまま固定、および、半導体素子３の保護がなされる。   The resin used at that time has such physical properties that it does not flow down between the semiconductor element 3 and the wiring board 2 due to surface tension. Further, the semiconductor element 3 is fixed while being held in a prescribed position and the semiconductor element 3 is protected by baking the resin while being vacuum-adsorbed to cure the resin.

次に、図６（ｅ）に示すように、封止樹脂体４で封止された配線基板２に対して、回転ブレード（図示せず）により各半導体素子単位に切断して個片化する。
最後に、個片化した配線基板２の主面と反対側の面の配線パターン８に半田ボールを付設してボール電極１０を形成し、外部端子を構成することにより、図４に示すような半導体装置１を製造することができる（例えば、特許文献１参照）。
特開２０００−９１４６８号公報 Next, as shown in FIG. 6E, the wiring board 2 sealed with the sealing resin body 4 is cut into individual semiconductor elements by a rotating blade (not shown). .
Finally, a solder ball is attached to the wiring pattern 8 on the surface opposite to the main surface of the separated wiring board 2 to form a ball electrode 10 and an external terminal is formed as shown in FIG. The semiconductor device 1 can be manufactured (see, for example, Patent Document 1).
JP 2000-91468 A

このように、従来の半導体装置１は、配線基板２の開口部５に半導体素子３を収納することで、半導体装置の薄型化を実現するものである。
しかしながら、従来の半導体装置１において、更なる薄型化が求められた場合には、半導体素子３の電極パッドと配線基板２の配線パターン８を接続する金属細線７は断線、ショートなどの不良を避けるため、ループ高さを確保し、金属細線７を封止樹脂体４で覆っているので、半導体素子３の主面および配線基板２の主面側二形成される封止樹脂体４の薄型化は困難である。 As described above, the conventional semiconductor device 1 realizes a reduction in thickness of the semiconductor device by housing the semiconductor element 3 in the opening 5 of the wiring substrate 2.
However, in the conventional semiconductor device 1, when further thinning is required, the fine metal wires 7 connecting the electrode pads of the semiconductor element 3 and the wiring pattern 8 of the wiring substrate 2 avoid defects such as disconnection and short circuit. Therefore, the loop height is ensured and the fine metal wires 7 are covered with the sealing resin body 4, so that the thickness of the sealing resin body 4 formed on the main surface side of the semiconductor element 3 and the main surface side of the wiring board 2 is reduced. It is difficult.

そこで、配線基板２および半導体素子３の薄型化が考えられる。ところが、半導体素子３の厚さを薄くすることは、ウエハの強度低下による輸送時の割れの発生などが問題となるともに、薄くできる厚さにも限界があるため難しい。したがって、従来の半導体装置１での更なる薄型化は困難である。   Therefore, it is conceivable to make the wiring board 2 and the semiconductor element 3 thinner. However, it is difficult to reduce the thickness of the semiconductor element 3 because there is a problem of cracking during transportation due to a decrease in the strength of the wafer, and the thickness that can be reduced is limited. Therefore, it is difficult to further reduce the thickness of the conventional semiconductor device 1.

また、従来の半導体装置１の金属細線７はループ高さを確保しているため、半導体素子３の電極パッドから第２の樹脂配線基板のボール電極１０までの距離、つまり配線長が長くなるので、ノイズ発生による高周波特性の低下が懸念される。   Further, since the metal thin wire 7 of the conventional semiconductor device 1 has a loop height, the distance from the electrode pad of the semiconductor element 3 to the ball electrode 10 of the second resin wiring board, that is, the wiring length becomes long. There is a concern about the deterioration of the high frequency characteristics due to the generation of noise.

さらに、従来の半導体装置１の製造工程において、ワイヤーボンディング後に半導体素子３は金属細線の７の張力により宙吊り状態となっているため、半導体素子３は不安定な状態であり、震動などで半導体素子３が動くことにより、金属細線７の変形が起こり、断線やショートなどの不良を起こす恐れがある。   Further, in the manufacturing process of the conventional semiconductor device 1, since the semiconductor element 3 is suspended by the tension of the thin metal wire 7 after wire bonding, the semiconductor element 3 is in an unstable state, and the semiconductor element 3 is caused by vibration or the like. By moving 3, the metal thin wire 7 is deformed, and there is a possibility of causing defects such as disconnection or short circuit.

本発明は、かかる点に鑑みてなされたものであり、半導体装置の特性低下を抑制しながら、半導体装置を薄型化することを目的とする。   The present invention has been made in view of this point, and an object of the present invention is to reduce the thickness of a semiconductor device while suppressing deterioration in characteristics of the semiconductor device.

前記目的を達成するため、請求項１記載の半導体装置は、第２の配線基板に半導体装置を搭載し、前記第２の配線基板と前記半導体素子との電気的接続を第１の半導体基板を介して行う半導体装置であって、前記半導体素子が主面に複数の電極パッドを備え、前記第１の配線基板が主面に複数の第１の配線パターンを備え、前記第２の配線基板が、前記半導体素子の搭載領域となる開口部と、主面に形成されて少なくとも一部が露出する複数の第２の配線パターンと、前記第２の配線パターンが形成される主面に対する裏面に形成される複数の外部端子と、前記第２の配線パターンと前記外部端子を１対１で電気的に接続するビアホールとを備え、前記半導体素子が前記第２の配線基板の開口部に収納され、前記電極パッドと前記第２の配線パターンとが前記第１の配線パターンを介して１対１で電気的に接続されるように前記第１の配線基板が前記半導体素子および前記第２の配線基板上に接続されることを特徴とする。   In order to achieve the above object, a semiconductor device according to claim 1, wherein a semiconductor device is mounted on a second wiring board, and electrical connection between the second wiring board and the semiconductor element is performed on the first semiconductor substrate. The semiconductor element includes a plurality of electrode pads on a main surface, the first wiring substrate includes a plurality of first wiring patterns on the main surface, and the second wiring substrate includes: , An opening serving as a mounting region for the semiconductor element, a plurality of second wiring patterns formed on the main surface and exposed at least partially, and formed on the back surface with respect to the main surface on which the second wiring pattern is formed. A plurality of external terminals, via holes that electrically connect the second wiring pattern and the external terminals in a one-to-one relationship, and the semiconductor element is housed in an opening of the second wiring board, The electrode pad and the second wiring The first wiring board is connected to the semiconductor element and the second wiring board so that a turn is electrically connected in a one-to-one manner via the first wiring pattern. To do.

請求項２記載の半導体装置は、請求項１記載の半導体装置において、前記第１の配線パターンが略直線状に形成されることを特徴とする。
請求項３記載の半導体装置は、請求項１または請求項２のいずれかに記載の半導体装置において、前記電極パッドと前記第１の配線パターンとの接続面および前記第２の配線パターンと前記第１の配線パターンとの接続面が、略同一平面上となることを特徴とする。 According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first wiring pattern is formed in a substantially linear shape.
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the connection surface between the electrode pad and the first wiring pattern, the second wiring pattern, and the first The connection surface with one wiring pattern is substantially on the same plane.

請求項４記載の半導体装置は、請求項１〜請求項３のいずれかに記載の半導体装置において、前記第１の配線基板の外形形状が、前記開口部の開口形状よりも大きいことを特徴とする。   The semiconductor device according to claim 4 is the semiconductor device according to any one of claims 1 to 3, wherein an outer shape of the first wiring board is larger than an opening shape of the opening. To do.

請求項５記載の半導体装置は、請求項１〜請求項４のいずれかに記載の半導体装置において、前記第１の配線基板の外形形状が、前記第２の配線基板の外形形状よりも小さいことを特徴とする。   The semiconductor device according to claim 5 is the semiconductor device according to any one of claims 1 to 4, wherein an outer shape of the first wiring board is smaller than an outer shape of the second wiring board. It is characterized by.

請求項６記載の半導体装置は、請求項１〜請求項５のいずれかに記載の半導体装置において、前記第１の配線基板を絶縁性材料で形成することを特徴とする。
請求項７記載の半導体装置は、請求項１〜請求項６のいずれかに記載の半導体装置において、前記第１の配線パターンを金属箔で形成することを特徴とする。 A semiconductor device according to a sixth aspect is the semiconductor device according to any one of the first to fifth aspects, wherein the first wiring board is formed of an insulating material.
A semiconductor device according to a seventh aspect is the semiconductor device according to any one of the first to sixth aspects, wherein the first wiring pattern is formed of a metal foil.

請求項８記載の半導体装置は、請求項１〜請求項７のいずれかに記載の半導体装置において、前記第１の配線パターンを金属板で形成することを特徴とする。
請求項９記載の半導体装置は、請求項１〜請求項８のいずれかに記載の半導体装置において、前記半導体素子と前記第１の配線基板とを接着剤により固着することを特徴とする。 The semiconductor device according to claim 8 is the semiconductor device according to any one of claims 1 to 7, wherein the first wiring pattern is formed of a metal plate.
A semiconductor device according to a ninth aspect is the semiconductor device according to any one of the first to eighth aspects, wherein the semiconductor element and the first wiring substrate are fixed by an adhesive.

請求項１０記載の半導体装置は、請求項１〜請求項９のいずれかに記載の半導体装置において、前記第１の配線パターンと前記第２の配線パターンおよび前記電極パッドとの電気的接続部分より外周の領域で、前記第１の配線基板と前記第２の配線基板とを接着剤を用いて固着することを特徴とする。   The semiconductor device according to claim 10 is the semiconductor device according to any one of claims 1 to 9, wherein an electrical connection portion between the first wiring pattern, the second wiring pattern, and the electrode pad. In the outer peripheral region, the first wiring board and the second wiring board are fixed using an adhesive.

請求項１１記載の半導体装置は、請求項１〜請求項１０のいずれかに記載の半導体装置において、前記開口部が前記第２の配線基板を貫通することを特徴とする。
請求項１２記載の半導体装置は、請求項１〜請求項１０のいずれかに記載の半導体装置において、前記第１の配線基板と前記第２の配線基板との間および前記半導体素子が収納されている前記開口部が樹脂封止されることを特徴とする。 A semiconductor device according to an eleventh aspect is the semiconductor device according to any one of the first to tenth aspects, wherein the opening penetrates through the second wiring board.
A semiconductor device according to a twelfth aspect is the semiconductor device according to any one of the first to tenth aspects, wherein the semiconductor element is housed between the first wiring board and the second wiring board. The opening is sealed with resin.

請求項１３記載の半導体装置は、請求項１〜請求項１０のいずれかに記載の半導体装置において、前記開口部が前記第２の配線基板を貫通し、前記第１の配線基板と前記第２の配線基板の間および前記半導体素子が収納されている前記開口部が樹脂封止されることを特徴とする。   A semiconductor device according to a thirteenth aspect is the semiconductor device according to any one of the first to tenth aspects, wherein the opening penetrates through the second wiring board, and the first wiring board and the second wiring board. The openings between the wiring boards and the semiconductor elements are sealed with resin.

請求項１４記載の半導体装置の製造方法は、請求項１〜請求項１１のいずれかに記載の半導体装置の製造方法であって、前記第１の配線パターンと前記電極パッドとが１対１で対応して電気的に接続するように前記半導体素子を前記第１の配線基板に固着する工程と、前記半導体素子が前記開口部に収納されると共に前記第１の配線パターンと前記第２の配線パターンとが１対１で対応して電気的に接続するように前記第１の配線基板を前記第２の配線基板に固着する工程とを有することを特徴とする。   A method for manufacturing a semiconductor device according to claim 14 is the method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein the first wiring pattern and the electrode pad are in a one-to-one relationship. A step of fixing the semiconductor element to the first wiring board so as to be electrically connected correspondingly; and the semiconductor element is housed in the opening and the first wiring pattern and the second wiring A step of fixing the first wiring board to the second wiring board so that the pattern is electrically connected to the pattern in a one-to-one correspondence.

請求項１５記載の半導体装置の製造方法は、請求項１２記載の半導体装置の製造方法であって、前記第１の配線パターンと前記電極パッドとが１対１で対応して電気的に接続するように前記半導体素子を前記第１の配線基板に固着する工程と、前記半導体素子が前記開口部に収納されると共に前記第１の配線パターンと前記第２の配線パターンとが１対１で対応して電気的に接続するように前記第１の配線基板を前記第２の配線基板に固着する工程と、前記第１の配線基板と前記第２の配線基板の間および前記半導体素子が収納されている前記開口部を樹脂封止する工程とを有することを特徴とする。   The method for manufacturing a semiconductor device according to claim 15 is the method for manufacturing a semiconductor device according to claim 12, wherein the first wiring pattern and the electrode pad are electrically connected in a one-to-one correspondence. In this way, the step of fixing the semiconductor element to the first wiring board corresponds to the first wiring pattern and the second wiring pattern in a one-to-one correspondence with the semiconductor element being housed in the opening. And fixing the first wiring board to the second wiring board so as to be electrically connected, the first wiring board and the second wiring board, and the semiconductor element are housed. And the step of resin-sealing the opening.

請求項１６記載の半導体装置の製造方法は、請求項１３記載の半導体装置の製造方法であって、前記第１の配線パターンと前記電極パッドとが１対１で対応して電気的に接続するように前記半導体素子を前記第１の配線基板に固着する工程と、前記半導体素子が前記開口部に収納されると共に前記第１の配線パターンと前記第２の配線パターンとが１対１で対応して電気的に接続するように前記第１の配線基板を前記第２の配線基板に固着する工程と、前記第１の配線基板と前記第２の配線基板の間および前記半導体素子が収納されている前記開口部を前記第２の配線基板の裏面側の開口部から樹脂を充填することにより樹脂封止する工程とを有することを特徴とする。   The semiconductor device manufacturing method according to claim 16 is the semiconductor device manufacturing method according to claim 13, wherein the first wiring pattern and the electrode pad are electrically connected in a one-to-one correspondence. In this way, the step of fixing the semiconductor element to the first wiring board corresponds to the first wiring pattern and the second wiring pattern in a one-to-one correspondence with the semiconductor element being housed in the opening. And fixing the first wiring board to the second wiring board so as to be electrically connected, the first wiring board and the second wiring board, and the semiconductor element are housed. And the step of sealing the resin by filling the resin from the opening on the back side of the second wiring board.

請求項１７記載の半導体装置の製造方法は、請求項１４〜請求項１６のいずれかに記載の半導体装置の製造方法において、前記半導体素子の前記第１の配線基板への固着を接着剤により行うことを特徴とする。   A method for manufacturing a semiconductor device according to claim 17 is the method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein the semiconductor element is fixed to the first wiring board with an adhesive. It is characterized by that.

請求項１８記載の半導体装置の製造方法は、請求項１４〜請求項１７のいずれかに記載の半導体装置の製造方法において、前記第１の配線基板の前記第２の配線基板への固着を前記第１の配線パターンと前記第２の配線パターンおよび前記電極パッドとの電気的接続部分より外周の領域で接着剤により行うことを特徴とする。   The method for manufacturing a semiconductor device according to claim 18 is the method for manufacturing a semiconductor device according to any one of claims 14 to 17, wherein the first wiring substrate is fixed to the second wiring substrate. It is characterized in that it is performed by an adhesive in a region outside the electrical connection portion between the first wiring pattern, the second wiring pattern, and the electrode pad.

以上により、半導体装置の特性低下を抑制しながら、半導体装置を薄型化することができる。   As described above, the semiconductor device can be thinned while suppressing deterioration in characteristics of the semiconductor device.

以上のように、第１の配線基板に半導体素子を接続し、第２の配線基板に形成された開口部に半導体素子が収納されるように第１の配線基板を第２の配線基板に設置することにより、半導体素子と第２の配線基板との電気的接続が、金属細線を用いることなく、第１の配線基板に形成された配線パターンにより短い配線長で実現させることができるため、半導体装置の特性低下を抑制しながら、半導体装置を薄型化することができる。   As described above, the semiconductor element is connected to the first wiring board, and the first wiring board is installed on the second wiring board so that the semiconductor element is accommodated in the opening formed in the second wiring board. As a result, the electrical connection between the semiconductor element and the second wiring board can be realized with a short wiring length by the wiring pattern formed on the first wiring board without using a metal thin wire. The semiconductor device can be thinned while suppressing deterioration of the characteristics of the device.

以下、本発明の半導体装置２１について図１〜図３を参照しながら説明する。また、従来の半導体装置１と略同機能の構成要素には同じ符号を付す。図１は本発明の半導体装置を説明する断面図、図２は本発明の半導体装置を説明する概略斜視図、図３は本発明における半導体装置の製造工程を説明する工程断面図である。なお、図２において封止樹脂体２４は省略する。   Hereinafter, the semiconductor device 21 of the present invention will be described with reference to FIGS. Components having substantially the same functions as those of the conventional semiconductor device 1 are denoted by the same reference numerals. 1 is a cross-sectional view illustrating a semiconductor device according to the present invention, FIG. 2 is a schematic perspective view illustrating the semiconductor device according to the present invention, and FIG. 3 is a process cross-sectional view illustrating a manufacturing process of the semiconductor device according to the present invention. In FIG. 2, the sealing resin body 24 is omitted.

図１、図２に示すように、本発明の半導体装置２１は、第２の配線基板２３の開口部５に半導体素子３が収納され、第１の配線基板２２により半導体素子３と第２の配線基板２３との電気的接続が実現されており、半導体素子３を収納した開口部５を含む第１の配線基板２２下部が封止樹脂体２４により樹脂封止される構造である。第２の配線基板２３は絶縁性樹脂で形成された板状の配線基板であり、主面の中央部には半導体素子３が収納できる大きさで裏面まで貫通する開口部５が形成されている。また、第２の配線基板２３の主面に対する裏面には半導体装置２１の外部端子となるボール電極１０がマトリクス状に配置されている。さらに、第２の配線基板２３の主面にはボール電極１０と対応する配線パターン８が形成され、ビアホール９を介して対応するボール電極１０と電気的に接続されている。半導体素子３は主面にボール電極１０に対応する複数の電極パッド（図示せず）が形成されており、電極パッドが形成された主面が第２の配線基板２３の主面側にくるように開口部５に収納されている。第１の配線基板２２には配線パターン２７が形成されており、配線パターン２７が形成された面を下にして、主面が上になるように第２の配線基板２３に収納された半導体素子３および第２の配線基板２３の上に第１の配線基板２２を設置することにより、配線パターン２７を介して半導体素子３の電極パッドと第２の配線基板２３の配線パターン８とが１対１に対応して電気的に接続される構造である。   As shown in FIGS. 1 and 2, in the semiconductor device 21 of the present invention, the semiconductor element 3 is accommodated in the opening 5 of the second wiring board 23, and the semiconductor element 3 and the second wiring board 22 are accommodated by the first wiring board 22. Electrical connection with the wiring board 23 is realized, and the lower part of the first wiring board 22 including the opening 5 in which the semiconductor element 3 is accommodated is sealed with a sealing resin body 24. The second wiring board 23 is a plate-like wiring board formed of an insulating resin, and an opening 5 that penetrates to the back surface is formed in a size that can accommodate the semiconductor element 3 at the center of the main surface. . Further, ball electrodes 10 serving as external terminals of the semiconductor device 21 are arranged in a matrix on the back surface of the second wiring substrate 23 with respect to the main surface. Further, a wiring pattern 8 corresponding to the ball electrode 10 is formed on the main surface of the second wiring board 23 and is electrically connected to the corresponding ball electrode 10 through the via hole 9. The semiconductor element 3 has a plurality of electrode pads (not shown) corresponding to the ball electrodes 10 formed on the main surface, and the main surface on which the electrode pads are formed is on the main surface side of the second wiring substrate 23. In the opening 5. A wiring pattern 27 is formed on the first wiring board 22, and a semiconductor element housed in the second wiring board 23 with the surface on which the wiring pattern 27 is formed facing down and the main surface facing up. By installing the first wiring board 22 on the third wiring board 23 and the second wiring board 23, the electrode pads of the semiconductor element 3 and the wiring pattern 8 of the second wiring board 23 are paired via the wiring pattern 27. 1 is an electrically connected structure corresponding to 1.

第１の配線基板２２の配線パターン２７において、内端は接続部材２６を介して半導体素子３の電極パッド、外端は接続部材２５を介して第２の配線基板２３の配線パターン８とに接続されるとともに、接続部材２６を介して半導体素子３に固定され、接続部材２５を介して第２の配線基板２３に固定されている。また、接続部材２６および接続部材２５は金バンプなどの導電性材料を用いる。   In the wiring pattern 27 of the first wiring board 22, the inner end is connected to the electrode pad of the semiconductor element 3 through the connection member 26, and the outer end is connected to the wiring pattern 8 of the second wiring board 23 through the connection member 25. At the same time, it is fixed to the semiconductor element 3 via the connection member 26 and is fixed to the second wiring board 23 via the connection member 25. The connection member 26 and the connection member 25 are made of a conductive material such as a gold bump.

第１の配線基板２２の外形形状は、第２の配線基板２３の開口部５よりも大きく、第２の配線基板２３の外形形状よりも小さく形成する。
第１の配線基板２２と接続部材２５との接続部群の外周と第２の配線基板２３との隙間は接着剤２８により固定することが望ましいが、後の製造方法で説明する封止時に封止樹脂体２４が第１の配線基板２２の外周かつ第２の配線基板２３の主面に漏れ出さず、接続部材２５により第１の配線基板２２と第２の配線基板２３を確実に固定出来れば、必ずしも接着剤２８を用いなくてもよい。同様に、第１の配線基板２２と半導体素子３との隙間も接着剤（図示せず）により固定することが望ましいが、封止樹脂体２４や接続部材２６により第１の配線基板２２と半導体素子３を確実に固定出来れば、必ずしも接着剤を用いなくてもよい。 The outer shape of the first wiring board 22 is larger than the opening 5 of the second wiring board 23 and smaller than the outer shape of the second wiring board 23.
The gap between the outer periphery of the connecting portion group of the first wiring board 22 and the connecting member 25 and the second wiring board 23 is preferably fixed by an adhesive 28, but it is sealed at the time of sealing described in a later manufacturing method. The stop resin body 24 does not leak into the outer periphery of the first wiring board 22 and the main surface of the second wiring board 23, and the first wiring board 22 and the second wiring board 23 can be securely fixed by the connecting member 25. For example, the adhesive 28 is not necessarily used. Similarly, it is desirable that the gap between the first wiring board 22 and the semiconductor element 3 is also fixed by an adhesive (not shown), but the first wiring board 22 and the semiconductor are sealed by the sealing resin body 24 and the connecting member 26. If the element 3 can be securely fixed, an adhesive may not necessarily be used.

ここで、半導体装置２１を薄型化する目的から、第１の配線基板２２はポリイミドやポリエステルなどのフィルムで出来た極薄の絶縁性材料をベースとし、銅箔など導電性の金属箔の配線パターン２７を持ち、表面を保護するために絶縁フィルムなどで被覆されている。また、接続部材２６および接続部材２５は第１の配線基板の配線パターン２７との接触面が同一平面上にあるとともに、高さを低く抑えることが望ましい。   Here, for the purpose of reducing the thickness of the semiconductor device 21, the first wiring board 22 is based on an extremely thin insulating material made of a film such as polyimide or polyester, and a wiring pattern of conductive metal foil such as copper foil. 27, and is covered with an insulating film or the like to protect the surface. Further, it is desirable that the connecting member 26 and the connecting member 25 have a contact surface with the wiring pattern 27 of the first wiring board on the same plane and keep the height low.

また、半導体装置２１の高周波特性を向上させる目的から、上記接続部材２６および接続部材２５の構成とともに、第１の配線基板２２の配線パターン２７を略直線状に形成することで、半導体素子３の電極パッドから第２の配線基板２３の配線パターン８までの配線長を短くしている。   Further, for the purpose of improving the high frequency characteristics of the semiconductor device 21, the wiring pattern 27 of the first wiring board 22 is formed in a substantially linear shape together with the configuration of the connecting member 26 and the connecting member 25. The wiring length from the electrode pad to the wiring pattern 8 of the second wiring board 23 is shortened.

次に、図３を参照しながら、この半導体装置２１の製造方法について説明する。
本実施の形態における半導体装置２１の製造方法は、まず、図３（ａ）に示すように、両面に配線パターン８が形成され、中央部に半導体素子３を収納するための開口部５を設けた第２の配線基板２３と、半導体素子３の電極パッドとの接続部を内端とし、第１の配線基板の配線パターンの主面の配線パターン２７との接続部を外端とする配線パターン２７が形成された第１の配線基板とを用意する。 Next, a method for manufacturing the semiconductor device 21 will be described with reference to FIG.
In the manufacturing method of the semiconductor device 21 in the present embodiment, first, as shown in FIG. 3A, the wiring pattern 8 is formed on both surfaces, and the opening 5 for housing the semiconductor element 3 is provided in the center. A wiring pattern having a connection portion between the second wiring board 23 and the electrode pad of the semiconductor element 3 as an inner end and a connection portion with the wiring pattern 27 on the main surface of the wiring pattern of the first wiring board as an outer end. A first wiring board on which 27 is formed is prepared.

次に、図３（ｂ）に示すように、接続部材２６により第１の配線基板２２の配線パターン２７の内端と半導体素子３の電極パッドとを電気的に接続するとともに、半導体素子３を第１の配線基板２２に接着固定して搭載する。   Next, as shown in FIG. 3B, the inner end of the wiring pattern 27 of the first wiring board 22 and the electrode pad of the semiconductor element 3 are electrically connected by the connecting member 26, and the semiconductor element 3 is The first wiring board 22 is mounted by being adhesively fixed.

次に、図３（ｃ）に示すように、第２の配線基板２３の開口部５に半導体素子３を収納し、第１の配線基板２２の配線パターン２７の外端と第２の配線基板２３の主面側に設けられた配線パターン８とを接続部材２５により電気的に接続する。同時に、第１の配線基板２２における第１の配線基板の配線パターン２７の電気的接続部の外周流域と第２の配線基板２３とを接着剤２８により固定する。このとき、半導体素子３は、第１の配線基板２２を介して、第２の配線基板２３の開口部５に固定されている。   Next, as shown in FIG. 3C, the semiconductor element 3 is accommodated in the opening 5 of the second wiring board 23, and the outer end of the wiring pattern 27 of the first wiring board 22 and the second wiring board. The wiring pattern 8 provided on the main surface side of the wiring 23 is electrically connected by the connecting member 25. At the same time, the outer peripheral flow area of the electrical connection portion of the wiring pattern 27 of the first wiring board in the first wiring board 22 and the second wiring board 23 are fixed by the adhesive 28. At this time, the semiconductor element 3 is fixed to the opening 5 of the second wiring board 23 via the first wiring board 22.

次に、図３（ｄ）に示すように、半導体素子３の主面を下にして接続した状態で第１の配線基板２２の半導体素子３の主面と対向する面と、半導体素子３の主面，第２の配線基板２３の主面および開口部５の一部とを覆うように、半導体素子３，第１の配線基板２２，第２の配線基板２３で形成される隙間を封止樹脂体２４により封止する。その後ベークして封止樹脂体２４を硬化させることにより半導体素子３の保護がなされる。この時、開口部５の裏面側から封止樹脂体２４を充填することにより容易に樹脂封止を行うことができる。   Next, as shown in FIG. 3D, the surface of the first wiring substrate 22 facing the main surface of the semiconductor element 3 with the main surface of the semiconductor element 3 facing down, The gap formed by the semiconductor element 3, the first wiring substrate 22, and the second wiring substrate 23 is sealed so as to cover the main surface, the main surface of the second wiring substrate 23, and a part of the opening 5. The resin body 24 is sealed. Thereafter, the semiconductor element 3 is protected by baking and curing the sealing resin body 24. At this time, the resin sealing can be easily performed by filling the sealing resin body 24 from the back side of the opening 5.

次に、図３（ｅ）に示すように、封止樹脂体２４で封止された第２の配線基板２３を、回転ブレード（図示せず）を用いて各半導体素子単位に切断して個片化する。
最後に、個片化した第２の配線基板２３の主面と反対側の面の配線パターン８に半田ボールを付設してボール電極１０を形成し、外部端子を構成することにより、図１に示すような半導体装置２１を製造することができる。 Next, as shown in FIG. 3E, the second wiring board 23 sealed with the sealing resin body 24 is cut into individual semiconductor element units using a rotating blade (not shown). Tidy up.
Finally, solder balls are attached to the wiring pattern 8 on the surface opposite to the main surface of the separated second wiring board 23 to form a ball electrode 10 and an external terminal is formed as shown in FIG. A semiconductor device 21 as shown can be manufactured.

なお、本発明では、封止樹脂体２４で第１の配線基板２２の半導体素子３との対向面と第２の配線基板２３の主面および開口部５の一部と半導体素子３の主面を覆い保護すると説明したが、必ずしも封止樹脂体２４で保護する必要はなく、保護の必要性がなければ、封止樹脂体２４を用いなくてもよいし、封止樹脂体２４で覆う代わりに第２の配線基板２３の開口部５に板状の蓋をするだけでも構わない。   In the present invention, the surface of the first wiring substrate 22 facing the semiconductor element 3, the main surface of the second wiring substrate 23, a part of the opening 5, and the main surface of the semiconductor element 3 in the sealing resin body 24. However, it is not always necessary to protect with the sealing resin body 24. If there is no need for protection, the sealing resin body 24 may not be used. In addition, the opening 5 of the second wiring board 23 may be simply covered with a plate.

以下に、本発明における半導体装置２１および半導体装置２１の製造方法が奏する効果を示す。
上述したように、本発明における半導体装置２１は、半導体素子３を収納するための開口部５を形成した第１の配線基板２２を備え、従来の半導体装置の金属細線の機能を、接続部材２６と極薄の第１の配線基板２２に形成した配線パターン２７と接続部材２５に変更した。これにより、従来からの、第１の配線基板２２の開口部５への半導体素子３を収納することによる薄型化を維持しつつ、第２の配線基板２３の主面側、つまり第１の配線基板２２と接続部材２５あるいは接続部材２６を合わせた厚みが、従来の半導体装置１の配線基板２の主面側の封止樹脂体４の厚みより薄くすることができるので、半導体装置２１の特性低下を抑制しながら、半導体装置２１を薄型化することができる。 Below, the effect which the semiconductor device 21 in this invention and the manufacturing method of the semiconductor device 21 show | plays is shown.
As described above, the semiconductor device 21 according to the present invention includes the first wiring substrate 22 in which the opening 5 for housing the semiconductor element 3 is formed, and the function of the metal thin wire of the conventional semiconductor device is connected to the connecting member 26. The wiring pattern 27 and the connection member 25 are formed on the first wiring substrate 22 that is very thin. As a result, the main surface side of the second wiring board 23, that is, the first wiring is maintained while maintaining the thinning by storing the semiconductor element 3 in the opening 5 of the first wiring board 22 from the conventional method. The total thickness of the substrate 22 and the connection member 25 or the connection member 26 can be made thinner than the thickness of the sealing resin body 4 on the main surface side of the wiring substrate 2 of the conventional semiconductor device 1. The semiconductor device 21 can be thinned while suppressing the decrease.

また、従来の半導体装置において金属細線でループ高さを確保しつつ接続されていたのに対し、この半導体装置２１では、接続部材２６と極薄の第１の配線基板２２に形成した配線パターン２７と接続部材２５とにより接続されることにより、半導体素子３の電極パッドと第２の配線基板２３の配線パターン８との配線長が短くなる。これにより、高周波特性が向上する。   In contrast to the conventional semiconductor device, which is connected with a thin metal wire while securing the loop height, in this semiconductor device 21, the wiring pattern 27 formed on the connection member 26 and the very thin first wiring substrate 22. Are connected by the connecting member 25, the wiring length between the electrode pad of the semiconductor element 3 and the wiring pattern 8 of the second wiring substrate 23 is shortened. Thereby, the high frequency characteristics are improved.

また、この半導体装置２１では、金属細線を使用しないので、製造工程中に、金属細線のショートあるいは断線が発生しない。従って、本発明にかかる半導体装置２１の製造方法では、電気的接続機能の低下および喪失を招来することなく半導体装置２１を製造することができるため、製造歩留まりが高い半導体装置２１を製造することができる。   In addition, since the semiconductor device 21 does not use the fine metal wire, the metal fine wire is not short-circuited or disconnected during the manufacturing process. Therefore, in the method for manufacturing the semiconductor device 21 according to the present invention, the semiconductor device 21 can be manufactured without causing a reduction and loss of the electrical connection function. Therefore, the semiconductor device 21 with a high manufacturing yield can be manufactured. it can.

以上をまとめると、本発明における半導体装置２１および半導体装置２１の製造方法によれば、厚みが薄いこと、配線長が短いので高周波特性が向上するなど半導体装置２１として性能がよいこと、製造工程において、金属細線を使用しないので、金属細線のショートあるいは断線などの不良が発生せず、製造歩留まりが高いという効果を得られることから、従来の半導体装置１よりも、半導体装置の特性低下を抑制しながら、半導体装置を薄型化することができる。   In summary, according to the semiconductor device 21 and the manufacturing method of the semiconductor device 21 of the present invention, the semiconductor device 21 has good performance such as a small thickness and improved high-frequency characteristics because the wiring length is short. Since no fine metal wires are used, defects such as short-circuiting or disconnection of the fine metal wires do not occur, and the production yield is high. Therefore, the deterioration of the characteristics of the semiconductor device can be suppressed more than that of the conventional semiconductor device 1. However, the semiconductor device can be thinned.

なお、以上の説明では、ＢＧＡパッケージについて説明したが、これに限られるものではなく、ＬＧＡパッケージや、配線基板としてフィルム／テープ等を使用するＣＯＦなど、配線基板を使用する半導体装置ならば、適用可能である。   In the above description, the BGA package has been described. However, the present invention is not limited to this, and the present invention is applicable to any semiconductor device using a wiring board, such as an LGA package or a COF using a film / tape as a wiring board. Is possible.

また、第１の配線基板の配線パターン２７は金属箔を使用すると説明したが、これに限定されるものではなく、導電性材料で薄型化ができれば、金属板などを用いても構わない。また、電極パッドおよび第２の配線基板の配線パターンとの接続を端部で行う場合について説明したが、端部に限らず、第１の配線基板の配線パターンの任意の位置で接続する構成でもかまわない。また、接続に接続部材を用いても直接接続する構成にしてもかまわない。   The wiring pattern 27 of the first wiring board has been described as using a metal foil. However, the present invention is not limited to this, and a metal plate or the like may be used as long as it can be thinned with a conductive material. In addition, the case where the connection between the electrode pad and the wiring pattern of the second wiring board is performed at the end has been described. However, the connection is not limited to the end, but may be performed at an arbitrary position on the wiring pattern of the first wiring board. It doesn't matter. Further, a connection member may be used for connection or a direct connection may be used.

また、開口部が第２の配線基板を貫通する態様について説明したが、半導体装置の厚みを十分薄くできるのであれば、貫通せずにボール電極が形成される底面がふさがっている形状であっても差し支えない。   In addition, the mode in which the opening penetrates the second wiring board has been described. However, if the thickness of the semiconductor device can be made sufficiently thin, the bottom surface on which the ball electrode is formed without being penetrated is blocked. There is no problem.

本発明は、半導体装置の特性低下を抑制しながら、半導体装置を薄型化することができ、配線基板に半導体素子を装着して形成される半導体装置、およびその製造方法等に有用である。   INDUSTRIAL APPLICABILITY The present invention can reduce the thickness of a semiconductor device while suppressing deterioration in characteristics of the semiconductor device, and is useful for a semiconductor device formed by mounting a semiconductor element on a wiring board, a manufacturing method thereof, and the like.

本発明の半導体装置を説明する断面図Sectional drawing explaining the semiconductor device of this invention 本発明の半導体装置を説明する概略斜視図Schematic perspective view illustrating a semiconductor device of the present invention 本発明における半導体装置の製造工程を説明する工程断面図Process sectional drawing explaining the manufacturing process of the semiconductor device in this invention 従来の半導体装置を説明する断面図Sectional drawing explaining the conventional semiconductor device 従来の半導体装置を説明する斜視図A perspective view illustrating a conventional semiconductor device 従来の半導体装置の製造工程を説明する工程断面図Process sectional view explaining the manufacturing process of a conventional semiconductor device

符号の説明Explanation of symbols

１、２１ 半導体装置
２ 配線基板
３ 半導体素子
４、２４ 封止樹脂体
５ 開口部
６ 吸着孔
７ 金属細線
８、２７ 配線パターン
９ ビアホール
１０ ボール電極
２２ 第１の配線基板
２３ 第２の配線基板
２５、２６ 接続部材
２８ 接着剤 DESCRIPTION OF SYMBOLS 1, 21 Semiconductor device 2 Wiring board 3 Semiconductor element 4, 24 Sealing resin body 5 Opening part 6 Adsorption hole 7 Metal fine wire 8, 27 Wiring pattern 9 Via hole 10 Ball electrode 22 1st wiring board 23 2nd wiring board 25 26 Connecting member 28 Adhesive

Claims (18)

第２の配線基板に半導体装置を搭載し、前記第２の配線基板と前記半導体素子との電気的接続を第１の半導体基板を介して行う半導体装置であって、
前記半導体素子が主面に複数の電極パッドを備え、
前記第１の配線基板が主面に複数の第１の配線パターンを備え、
前記第２の配線基板が、
前記半導体素子の搭載領域となる開口部と、
主面に形成されて少なくとも一部が露出する複数の第２の配線パターンと、
前記第２の配線パターンが形成される主面に対する裏面に形成される複数の外部端子と、
前記第２の配線パターンと前記外部端子を１対１で電気的に接続するビアホールと
を備え、
前記半導体素子が前記第２の配線基板の開口部に収納され、前記電極パッドと前記第２の配線パターンとが前記第１の配線パターンを介して１対１で電気的に接続されるように前記第１の配線基板が前記半導体素子および前記第２の配線基板上に接続されることを特徴とする半導体装置。 A semiconductor device in which a semiconductor device is mounted on a second wiring substrate, and electrical connection between the second wiring substrate and the semiconductor element is performed via the first semiconductor substrate,
The semiconductor element comprises a plurality of electrode pads on the main surface,
The first wiring board includes a plurality of first wiring patterns on a main surface,
The second wiring board is
An opening serving as a mounting region of the semiconductor element;
A plurality of second wiring patterns formed on the main surface and at least partially exposed;
A plurality of external terminals formed on the back surface of the main surface on which the second wiring pattern is formed;
A via hole that electrically connects the second wiring pattern and the external terminal on a one-to-one basis;
The semiconductor element is accommodated in the opening of the second wiring board, and the electrode pad and the second wiring pattern are electrically connected one-on-one via the first wiring pattern. The semiconductor device, wherein the first wiring board is connected to the semiconductor element and the second wiring board. 前記第１の配線パターンが略直線状に形成されることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the first wiring pattern is formed in a substantially linear shape. 前記電極パッドと前記第１の配線パターンとの接続面および前記第２の配線パターンと前記第１の配線パターンとの接続面が、略同一平面上となることを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。   The connection surface between the electrode pad and the first wiring pattern and the connection surface between the second wiring pattern and the first wiring pattern are substantially on the same plane. Item 3. The semiconductor device according to any one of Items 2 above. 前記第１の配線基板の外形形状が、前記開口部の開口形状よりも大きいことを特徴とする請求項１〜請求項３のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein an outer shape of the first wiring substrate is larger than an opening shape of the opening. 前記第１の配線基板の外形形状が、前記第２の配線基板の外形形状よりも小さいことを特徴とする請求項１〜請求項４のいずれかに記載の半導体装置。   5. The semiconductor device according to claim 1, wherein an outer shape of the first wiring board is smaller than an outer shape of the second wiring board. 前記第１の配線基板を絶縁性材料で形成することを特徴とする請求項１〜請求項５のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first wiring board is formed of an insulating material. 前記第１の配線パターンを金属箔で形成することを特徴とする請求項１〜請求項６のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first wiring pattern is formed of a metal foil. 前記第１の配線パターンを金属板で形成することを特徴とする請求項１〜請求項７のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first wiring pattern is formed of a metal plate. 前記半導体素子と前記第１の配線基板とを接着剤により固着することを特徴とする請求項１〜請求項８のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor element and the first wiring substrate are fixed with an adhesive. 前記第１の配線パターンと前記第２の配線パターンおよび前記電極パッドとの電気的接続部分より外周の領域で、前記第１の配線基板と前記第２の配線基板とを接着剤を用いて固着することを特徴とする請求項１〜請求項９のいずれかに記載の半導体装置。   The first wiring board and the second wiring board are fixed with an adhesive in a region outside the electrical connection portion between the first wiring pattern, the second wiring pattern, and the electrode pad. The semiconductor device according to claim 1, wherein: 前記開口部が前記第２の配線基板を貫通することを特徴とする請求項１〜請求項１０のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the opening penetrates through the second wiring board. 前記第１の配線基板と前記第２の配線基板との間および前記半導体素子が収納されている前記開口部が樹脂封止されることを特徴とする請求項１〜請求項１０のいずれかに記載の半導体装置。   11. The resin-sealed portion between the first wiring board and the second wiring board and the opening in which the semiconductor element is housed is resin-sealed. The semiconductor device described. 前記開口部が前記第２の配線基板を貫通し、前記第１の配線基板と前記第２の配線基板の間および前記半導体素子が収納されている前記開口部が樹脂封止されることを特徴とする請求項１〜請求項１０のいずれかに記載の半導体装置。   The opening penetrates through the second wiring board, and the opening between the first wiring board and the second wiring board and the opening in which the semiconductor element is stored are resin-sealed. The semiconductor device according to claim 1. 請求項１〜請求項１１のいずれかに記載の半導体装置の製造方法であって、
前記第１の配線パターンと前記電極パッドとが１対１で対応して電気的に接続するように前記半導体素子を前記第１の配線基板に固着する工程と、
前記半導体素子が前記開口部に収納されると共に前記第１の配線パターンと前記第２の配線パターンとが１対１で対応して電気的に接続するように前記第１の配線基板を前記第２の配線基板に固着する工程と
を有することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to any one of claims 1 to 11,
Fixing the semiconductor element to the first wiring substrate so that the first wiring pattern and the electrode pad are electrically connected in a one-to-one correspondence;
The first wiring board is placed in the first wiring board so that the semiconductor element is accommodated in the opening and the first wiring pattern and the second wiring pattern are electrically connected in a one-to-one correspondence. And a step of adhering to the wiring substrate. 請求項１２記載の半導体装置の製造方法であって、
前記第１の配線パターンと前記電極パッドとが１対１で対応して電気的に接続するように前記半導体素子を前記第１の配線基板に固着する工程と、
前記半導体素子が前記開口部に収納されると共に前記第１の配線パターンと前記第２の配線パターンとが１対１で対応して電気的に接続するように前記第１の配線基板を前記第２の配線基板に固着する工程と、
前記第１の配線基板と前記第２の配線基板の間および前記半導体素子が収納されている前記開口部を樹脂封止する工程と
を有することを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 12,
Fixing the semiconductor element to the first wiring substrate so that the first wiring pattern and the electrode pad are electrically connected in a one-to-one correspondence;
The first wiring board is placed in the first wiring board so that the semiconductor element is accommodated in the opening and the first wiring pattern and the second wiring pattern are electrically connected in a one-to-one correspondence. Fixing to the wiring board of 2;
And a step of resin-sealing the opening between the first wiring board and the second wiring board and the opening in which the semiconductor element is housed. 請求項１３記載の半導体装置の製造方法であって、
前記第１の配線パターンと前記電極パッドとが１対１で対応して電気的に接続するように前記半導体素子を前記第１の配線基板に固着する工程と、
前記半導体素子が前記開口部に収納されると共に前記第１の配線パターンと前記第２の配線パターンとが１対１で対応して電気的に接続するように前記第１の配線基板を前記第２の配線基板に固着する工程と、
前記第１の配線基板と前記第２の配線基板の間および前記半導体素子が収納されている前記開口部を前記第２の配線基板の裏面側の開口部から樹脂を充填することにより樹脂封止する工程と
を有することを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device according to claim 13, comprising:
Fixing the semiconductor element to the first wiring substrate so that the first wiring pattern and the electrode pad are electrically connected in a one-to-one correspondence;
The first wiring board is placed in the first wiring board so that the semiconductor element is accommodated in the opening and the first wiring pattern and the second wiring pattern are electrically connected in a one-to-one correspondence. Fixing to the wiring board of 2;
Resin sealing is achieved by filling the opening between the first wiring board and the second wiring board and the opening in which the semiconductor element is stored from the opening on the back side of the second wiring board. A method for manufacturing a semiconductor device. 前記半導体素子の前記第１の配線基板への固着を接着剤により行うことを特徴とする請求項１４〜請求項１６のいずれかに記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 14, wherein the semiconductor element is fixed to the first wiring board with an adhesive. 前記第１の配線基板の前記第２の配線基板への固着を前記第１の配線パターンと前記第２の配線パターンおよび前記電極パッドとの電気的接続部分より外周の領域で接着剤により行うことを特徴とする請求項１４〜請求項１７のいずれかに記載の半導体装置の製造方法。   The first wiring board is fixed to the second wiring board with an adhesive in an outer peripheral region from an electrical connection portion between the first wiring pattern, the second wiring pattern, and the electrode pad. A method for manufacturing a semiconductor device according to claim 14, wherein:
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016040799A (en) * 2014-08-12 2016-03-24 国立研究開発法人産業技術総合研究所 Mounting substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016040799A (en) * 2014-08-12 2016-03-24 国立研究開発法人産業技術総合研究所 Mounting substrate

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