JP2009205707A - Shift register circuit, display unit, and electronic system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve performance stability by alleviating a load of clock wiring, reducing power consumption, and regulating voltage variation in a transistor gate. <P>SOLUTION: In a shift register circuit comprising a first transistor Tr1 in which a gate is provided with an input signal, a source is provided with a clock signal, and a drain is connected with an output line, the first transistor Tr1 has a gate-drain capacity larger than a gate-source capacity. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a shift register circuit and a display device, and more particularly to a shift register circuit, a display device, and an electronic device each including a transistor whose clock is input to a source.

  In a display device in which an electro-optical element such as a liquid crystal element or an organic EL (Electro Luminescence) element is applied to a pixel array unit, a signal for sequentially driving each pixel of the pixel array unit is generated by a shift register circuit (for example, , See Patent Document 1).

  Here, in the horizontal drive circuit among the drive circuits of the display device, a shift register is used to sequentially write the video signal serially transferred to the common signal line to the latch circuit provided in each signal line of the pixel array unit. The generated pulse signal is used. In the vertical drive circuit, a pulse signal generated by a shift register is used to sequentially select each horizontal scanning line in one vertical scanning period.

JP 2005-149624 A

  However, in a conventional shift register circuit in which a clock is input to the source of a transistor, it is difficult to reduce power consumption due to the time constant of the clock wiring. In a single channel shift register circuit using the same conductivity type as a plurality of transistors constituting the shift register circuit, the gate of the transistor that performs switching between the clock and the output due to coupling noise from the clock Malfunctions due to potential fluctuations are a problem. Further, in a single channel type shift register circuit, means for avoiding leakage may be provided due to the presence of a node in which the gate of the transistor is floating at ON potential. A circuit using a clock is used as the means for avoiding leakage. In some cases, there is a problem that the load on the clock wiring becomes large.

  Therefore, an object of the present invention is to provide a shift register circuit, a display device, and an electronic device that reduce the load on the clock wiring and have high operational stability.

  The present invention provides a shift register circuit including a transistor in which an input signal is applied to a gate, a clock is input to a source, and an output line is connected to a drain. This is a shift register circuit having a larger capacity.

  According to the present invention, in a shift register circuit including a transistor in which a clock is input to the source, since the gate-drain capacitance is larger than the gate-source capacitance of the transistor, the source and drain of the transistor Therefore, it is possible to adopt a capacitance asymmetric structure in which the capacitance on the source side to which the clock is input becomes smaller than the capacitance on the drain side, and the addition of the clock wiring connected to the source can be reduced.

  The present invention also provides a transistor in which an input signal is applied to the gate, a clock is input to the source, and an output line is connected to the drain, and a means for setting the gate of the transistor to the floating state of the ON potential by the output of the previous stage; The basic circuit includes means for resetting the gate of the transistor to the floating state of the OFF potential by the output of the subsequent stage, and a potential holding function for keeping the gate of the transistor at the OFF potential until the next output of the previous stage is input. A shift register circuit having a larger gate-drain capacitance than a gate-source capacitance is used.

  In such a present invention, in a shift register circuit including a transistor whose clock is input to the source in a basic circuit, the gate-drain capacitance is larger than the gate-source capacitance of the transistor. In the source and drain, it is possible to take a capacitance asymmetric structure in which the capacitance on the source side to which the clock is input becomes smaller than the capacitance on the drain side, and the addition of the clock wiring connected to the source can be reduced.

  The present invention also includes a pixel array unit in which a plurality of pixels are arranged in a matrix, and a shift register circuit that transfers a signal to be sent to each pixel of the pixel array unit, and a drive circuit that drives the pixel by this signal The shift register circuit includes a transistor in which an input signal is applied to the gate, a clock is input to the source, and an output line is connected to the drain. As this transistor, a gate-source capacitance is provided. A display device having a larger gate-drain capacitance is used.

  In such a present invention, in the shift register circuit used in the drive circuit of the display device, the gate-drain capacitance is larger than the gate-source capacitance of the transistor whose clock is input to the source. In the source and drain of the transistor, a capacitance asymmetric structure in which the capacitance on the source side to which the clock is input becomes smaller than the capacitance on the drain side can be taken, and the addition of the clock wiring connected to the source can be reduced. .

  The present invention also includes a pixel array unit in which a plurality of pixels are arranged in a matrix, and a shift register circuit that transfers a signal to be sent to each pixel of the pixel array unit, and a drive circuit that drives the pixel by this signal In the display device, the shift register circuit includes a transistor in which an input signal is supplied to the gate, a clock is input to the source, an output line is connected to the drain, and the transistor gate is floated at the ON potential by the output of the previous stage. The basic circuit includes means for setting the state, means for resetting the gate of the transistor to the floating state of the OFF potential by the output of the subsequent stage, and a potential holding function for keeping the gate of the transistor at the OFF potential until the next output of the previous stage is input. As a transistor, the gate-drain capacitance is greater than the gate-source capacitance. A display device as the larger of is used.

  In the present invention as described above, in the basic circuit of the shift register circuit used in the drive circuit of the display device, the gate-drain capacitance is larger than the gate-source capacitance of the transistor whose clock is input to the source. Therefore, the source and drain of the transistor can have a capacitance asymmetric structure in which the capacitance on the source side to which the clock is input becomes smaller than the capacitance on the drain side, and the addition of the clock wiring connected to the source can be reduced. It becomes like this.

  In addition, the present invention includes a display device including a shift register circuit that transfers a signal to be sent to each pixel of the pixel array portion, a drive circuit that drives the pixel by this signal, and a housing in which the display device is incorporated. In an electronic device, a shift register circuit includes a transistor in which an input signal is supplied to a gate, a clock is input to a source, and an output line is connected to a drain. As the transistor, a gate- An electronic device having a larger drain-to-drain capacitance is used.

  According to the present invention, in the shift register circuit used in the drive circuit of the display device incorporated in the housing of the electronic device, the gate-drain capacitance is more than the gate-source capacitance of the transistor whose clock is input to the source. Therefore, the source and drain of the transistor can have a capacitance asymmetric structure in which the capacitance on the source side to which the clock is input becomes smaller than the capacitance on the drain side, and the clock wiring connected to the source Can be reduced.

  In addition, the present invention includes a display device including a shift register circuit that transfers a signal to be sent to each pixel of the pixel array portion, a drive circuit that drives the pixel by this signal, and a housing in which the display device is incorporated. In an electronic device, a shift register circuit sets a transistor in which an input signal is supplied to a gate, a clock is input to a source, an output line is connected to a drain, and a gate of the transistor is set to a floating state of an ON potential by an output of the previous stage. And a means for resetting the gate of the transistor to a floating state of an OFF potential by a subsequent output, and a potential holding function for keeping the gate of the transistor at an OFF potential until the next previous output is input as a basic circuit, This transistor has a gate-drain capacitance rather than a gate-source capacitance. Which is an electronic device that is what is used the larger of.

  In the present invention, in the basic circuit of the shift register circuit used in the drive circuit of the display device incorporated in the housing of the electronic device, the gate-drain capacitance is determined by the gate-source capacitance of the transistor whose clock is input to the source. Since the capacitance is larger, the source and drain of the transistor can have a capacitance asymmetric structure in which the capacitance on the source side to which the clock is input is smaller than the capacitance on the drain side, and is connected to the source. It is possible to reduce the addition of clock wiring.

  According to the present invention, by using a capacitor asymmetric transistor as a transistor to which a clock is input to a source in a shift register circuit, it is possible to reduce the addition of clock wiring and to reduce power consumption. In addition, since fluctuations in the potential of the gate of the transistor can be suppressed and the number of nodes in which the ON potential is floating for a long time can be reduced, it is possible to improve the stability of the circuit and increase the leakage margin. Accordingly, it is possible to provide a shift register circuit, a display device, and an electronic device with low power consumption and high stability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Example of overall configuration of shift register circuit>
FIG. 1 is a block diagram illustrating a configuration example of the shift register circuit according to the present embodiment. As shown in FIG. 1, the shift register circuit according to the present embodiment is configured by a single channel (same conductivity type) transistor on an insulating substrate (not shown) by a polysilicon process or an amorphous silicon process. The shift register circuit includes N-stage registers (S / R) 11-1 to 11-N and two transfer gate circuits 12 and 13 as necessary, and some data is parallelized. The data is stored and output in series in a predetermined order, and the data stored in each of the registers 11-1 to 11-N is added one bit at a time from the least significant digit.

  The shift register circuit receives an input pulse ST and two-phase clock pulses CK1 and CK2. FIG. 2 shows an input pulse (input signal) ST, clock pulses CK1 and CK2, and inputs / outputs IN1 (1), IN2 (N), and OUT (1) to OUT (N) of the registers 11-1 to 11-N. The timing relationship is shown. As is clear from FIG. 2, the input pulse ST is activated twice in one field period, specifically, at the start and end parts of one field period. Here, for the sake of convenience, the input pulse ST that is active at the start of one field period is ST1, and the input pulse ST that is active at the end of one field period is ST2.

  The N-stage registers 11-1 to 11-N will be described with reference to a certain n-th register 11-n. The register 11-n outputs the output OUT (n-1) of the previous-stage register 11-n-1. Is the first input IN1, and the output OUT (n + 1) of the subsequent register 11-n + 1 is the second input IN2. Then, a transfer (shift) operation is performed in synchronization with the two-phase clock pulses CK1 and CK2 by the input of the output OUT (n-1) at the previous stage, and initialization is performed by the input of the output OUT (n + 1) at the subsequent stage.

  When the positive side power supply voltage is VDD and the negative side power supply voltage is VSS, the pulse amplitudes of the input pulse ST and the clock pulses CK1 and CK2 are VDD to VSS, and the transfer gate circuit 12 includes the input pulse ST and the clock pulse CK1. The first input pulse ST is selected by becoming active at the falling edge of the signal, and the pulse ST is supplied to the first-stage register 11-1 as the first input IN1. The transfer gate circuit 13 becomes active at the falling edge of the input pulse ST and the clock pulse CK2 to select the second input pulse ST, and the pulse ST is input to the final stage register 11-N as the second input IN2. Give as. In order to realize this input / output relationship, the total number of stages N of this shift register circuit needs to be an even number.

  Here, the pulse ST generated by the transfer gate circuit 12 is given to the first-stage register 11-1 as the first input IN1, and the pulse ST generated by the transfer gate circuit 13 is supplied to the second-stage register 11-N. However, it is not necessary to provide the transfer gate circuits 12 and 13 when adopting a configuration in which these pulses ST are given from the outside. Also, the total number N of shift registers need not be an even number.

  In the shift register circuit having such a configuration, in the present embodiment, among the transistors constituting the shift register circuit, an input signal is applied to the gate, a clock is input to the source, and an output line is connected to the drain. This is characterized in that the gate-source capacitance and the gate-drain capacitance are asymmetric.

<Configuration example of basic circuit of shift register circuit>
FIG. 3 is a diagram illustrating a configuration example of a basic circuit of the shift register circuit according to the present embodiment. The basic circuit 1 corresponds to one stage of the register shown in FIG. 1, and includes a control circuit 2 that receives the output signal from the previous stage and the output signal from the next stage and controls the potential of the node A, and The configuration includes a potential holding circuit 3 for holding a potential, a first transistor Tr1 to which an input signal is applied to the gate, a clock is input to the source, and an output line is connected to the drain.

  The control circuit 2 includes a means for setting the gate (node A) of the first transistor Tr1 to the floating state of the ON potential by the output of the previous stage, and the OFF potential of the gate (node A) of the first transistor Tr1 by the output of the subsequent stage. Means for resetting to a floating state. Further, the potential holding circuit 3 has a function of keeping the gate (node A) of the first transistor Tr1 at the OFF potential from the time when the output signal of the next stage is input to the time when the next output of the previous stage is input.

  In the first transistor Tr1, the output of the control circuit 2 is input to the gate, the clock is input to the source, and the output line is connected to the drain. The gate is controlled by the signal output from the control circuit 2, An output signal is generated at the drain according to the timing of the clock input to the source.

  FIG. 4 is a timing chart for explaining the operation of the basic circuit shown in FIG. Here, the channel type of the first transistor constituting the basic circuit is an N channel, and H and L indicate power supply voltages having a relationship of H> L.

  First, after the node A is charged to H-Vth by an OUTpre pulse (corresponding to OUT (n-1) in FIGS. 1 and 2) which is an output signal from the previous stage, the floating state of the H potential (ON potential) is set. Become. Here, Vth is the threshold voltage of the first transistor Tr1. Next, at the same time as the clock CK1 changes from L to H, the potential of the node A rises through the capacitance of the first transistor, and the H potential of the clock CK1 is output to the output line OUT without dropping by Vth.

  Next, the clock CK1 changes from H to L, and the output line OUT also changes from H to L. At the same time, the potential of the node A also returns to H-Vth. Thereafter, the node A is reset to L by an OUTnext pulse (corresponding to OUT (n + 1) in FIGS. 1 and 2) which is an output signal from the next stage. After the fall of the OUTnext pulse, the node A is in a floating state with an L potential (OFF potential). This L potential is held by the potential holding circuit until the next output signal of the previous stage is input.

  In this embodiment, by using a capacitor asymmetric transistor as the first transistor Tr1, when the node A is in the floating state at the L potential (OFF potential), the amount of coupling received from the clock CK1 can be reduced, and a margin for malfunction is provided. Can be increased.

  Here, when the capacitor asymmetric transistor is applied to the first transistor, since the clock CK1 is input to the source, the gate-drain capacitance is set to be larger than the gate-source capacitance. As a result, the gate-source capacitance is reduced as compared with the case of using the transistor having the same channel region size and the capacitance target, and the coupling of the clock CK1 input to the source with the gate node A floating at the L potential is performed. The influence of can be suppressed.

<Specific configuration example of basic circuit of shift register circuit>
FIG. 5 is a circuit diagram illustrating a specific configuration example of the basic circuit of the shift register circuit according to the present embodiment. This circuit diagram is one of the specific circuit configurations of the basic circuit shown in FIG. 3, and corresponds to one stage of the register shown in FIG. The specific circuit configuration of the basic circuit described below is an example, and the present invention is not limited to this.

  That is, in this shift register circuit, an input signal is supplied to the gate, a clock (here, CK1) is input to the source, and an output line is connected to the drain, and the gate of the first transistor Tr1 Is set to the floating state of the ON potential by the output of the previous stage, the means of resetting the gate of the first transistor Tr1 to the floating state of the OFF potential by the output of the subsequent stage, and the first until the next previous stage output is input. And a capacitor C that keeps the gate of the transistor Tr1 at an OFF potential. As the first transistor Tr1, the capacitor asymmetric transistor described above is applied.

  The means for setting the gate of the first transistor Tr1 to the floating state of the ON potential by the output of the previous stage includes, for example, a fourth transistor Tr4 and a third transistor Tr3, and is a diode-connected fourth transistor Tr4. The output signal OUTpre from the previous stage is input to the gate of the first stage. Further, the ON potential is applied to the gate of the third transistor Tr3, and the drain is connected to the gate of the first transistor Tr1.

  The means for resetting the gate of the first transistor Tr1 to the floating state of the OFF potential by the output of the subsequent stage includes, for example, the fifth transistor Tr5 and the third transistor Tr3, and the gate of the fifth transistor Tr5 is connected to the gate from the subsequent stage. Output signal OUTnext is input. The source of the fifth transistor Tr5 is connected to the drain of the fourth transistor Tr4, and the drain of the fifth transistor Tr5 is connected to the OFF potential.

  The capacitor C1 having a potential holding function is connected between the gate and the drain of the first transistor Tr1, and plays a role of holding the potential of the node A. The second transistor Tr2 is connected to the drain of the first transistor Tr1, and the signal of the output line OUT is inverted and input to the gate of the second transistor Tr2 via the inverter Inv.

  FIG. 6 is a timing chart for explaining the operation of the basic circuit shown in FIG. Here, the channel type of the first transistor constituting the basic circuit is an N channel, and H and L indicate power supply voltages having a relationship of H> L.

  First, when OUTpre, which is an output signal from the previous stage, becomes H, an H signal is output from the drain of the fourth transistor. As a result, the nodes A and B are charged to H-Vth, and the first transistor is turned on. After the nodes A and B are charged, the H potential is in a floating state.

  Next, when the output signal OUTpre at the previous stage becomes L, the nodes A and B are kept at H-Vth because the fourth transistor is diode-connected. After that, when the clock CK1 becomes H, since the node A is floating, the potential rises due to the coupling as the potential of the clock CK1 rises. As a result, the first transistor can keep the gate-source potential Vgs equal to or higher than the threshold, and can pass the H signal (ON potential) of the clock CK1 to the output line OUT on the drain side (bootstrap structure).

  At this time, since the node A and the node B are not conductive, the node B is not affected by the coupling. As a result, a high Vds potential is not applied to the fourth and fifth transistors. When the output line OUT is in the H state, the node C is in the L state, and the second transistor is in the OFF state.

  Next, when the clock CK1 becomes L, the node A whose potential has risen returns to H-Vth, the node C rises to H as the output line OUT falls to L, and the second transistor is turned on.

  Next, when the output signal OUTnext of the next stage becomes H, the fifth transistor is turned on and connected to the OFF potential, so that the nodes A and B become L. Thereafter, when the output signal OUTnext of the next stage becomes L, the fifth transistor is turned OFF, and the nodes A and B are in a floating state at the L potential. This floating state at the L potential is held by the capacitor C until the output signal OUTpre from the next previous stage becomes H.

  In the shift register circuit of the present embodiment having such a circuit configuration, the input of the clock CK1 is only the source of the first transistor, so that the load on the clock wiring can be reduced. In addition, there is no node that floats at the ON potential for a long period of time, and the leakage destination from the transistor connected to the node that floats at the OFF potential for a long period of time is the same OFF potential. It becomes possible to simplify the circuit.

<Configuration example of capacitive asymmetric transistor>
7A and 7B are schematic cross-sectional views illustrating the structure of a capacitor asymmetric transistor applied in the shift register circuit of this embodiment. FIG. 7A is a bottom gate structure, and FIG. 7B is a top gate structure.

  In the bottom gate structure shown in FIG. 7A, the polysilicon 40 is formed on the gate electrode 10g via the insulating film 30, and the source electrode 10s and the drain are formed in the source region and the drain region formed in the polysilicon 40, respectively. An electrode 10d is formed. In the present embodiment, a structure is adopted in which a shield metal (see the broken line in the figure) 20 that is electrically connected to the drain electrode 10d is extended over the channel, while the source electrode 10s is not provided with the shield metal 20. Due to such a structure of the shield metal 20, the drain-gate capacitance (Cgd + Cgd2) is larger than the source-gate capacitance Cgs.

  In the top gate structure shown in FIG. 7B, the gate electrode 10g is formed on the polysilicon 40 via the insulating film 30, and the source electrode 10s and the drain electrode are formed in the source region and the drain region formed in the polysilicon 40. 10d is formed. In the present embodiment, a structure is adopted in which the shield metal 20 (see the broken line in the figure) 20 that is electrically connected to the drain electrode 10d extends to the gate electrode 10g, while the source electrode 10s is not provided with the shield metal 20. Due to such a structure of the shield metal 20, the drain-gate capacitance (Cgd + Cgd2) is larger than the source-gate capacitance Cgs.

  FIG. 8 is a schematic plan view illustrating the structure of the capacitor asymmetric transistor. The example shown in FIG. 8A is a plan view of the shield metal structure shown in FIG. 7, and the shield metal connected to the drain electrode extends over the channel region (gate electrode). Yes.

  Here, the source-gate capacitance Cgs and the drain-gate capacitance Cgd when the transistor is OFF are mainly generated in the fringe portion of the gate electrode. Therefore, in order to reduce the source-gate capacitance Cgs when the transistor is OFF, the source-side gate length may be reduced. At this time, in order not to reduce the ON current of the transistor, it is necessary to increase the gate length on the drain side. This example is shown in FIG. In FIG. 8B, the gate length on the source electrode side is shortened and the gate length on the drain electrode side is lengthened in the channel region when viewed in a plan view. As a result, a transistor having a small source-gate capacitance Cgs and a large drain-gate capacitance Cgd is obtained.

  FIG. 8C shows a structure in which the gate length on the source electrode side in the channel region is short, the gate length on the drain electrode side is long, and the shield metal connected to the drain electrode extends to the channel region. . In addition to the structure in which the gate length on the source side is short and the shield metal on the drain side is extended long, the source-gate capacitance Cgs can be made smaller than the drain-gate capacitance Cgd.

  FIG. 8D shows a structure in which the shape of the gate electrode is a donut shape, and the source electrode is arranged inside the donut shape and the drain electrode is arranged outside. 8E has a structure in which the drain side shield metal is enlarged in addition to the structure of FIG. 8D. Even with such a structure, the drain-gate capacitance Cgd can be made larger than the source-gate capacitance Cgs.

  The structure of the capacitor asymmetric transistor described above is an example, and the present invention is not limited to these structures.

  FIG. 9 is a diagram illustrating a circuit example of the inverting unit shown in FIG. The inversion unit is a circuit that switches between the output OUTpre of the previous stage and the output OUTnext of the next stage input to the shift register circuit, and is used when inverting the signal transfer direction. 9A and 9B, when the output OUTpre of the previous stage is input to in1 and the output OUTnext of the next stage is input to in2, for example, “H” of the inversion of the DWN signal and the DWN signal. , “L” can switch the output to out1 and out2.

  FIG. 10 is a diagram for explaining a circuit example of the inverter shown in FIG. The inverter is connected to the gate of the second transistor shown in FIG. 5, and inverts the signal of the output line OUT and inputs it to the gate of the second transistor. 10A and 10B, when the output line OUT of FIG. 5 is input to the in side and becomes “H”, out can be latched to “L”.

<Application example: Display device>
The shift register circuit according to the present embodiment described above includes a liquid crystal display device, a panel display device typified by an organic EL (Electro Luminescence) or LED (Light Emitting Diode) display device, and an X typified by a CMOS image sensor. In a −Y address type solid-state imaging device, it can be used as a shift register circuit constituting a vertical drive circuit or a horizontal drive circuit for selecting a pixel. However, this application example is only an example, and the shift register circuit according to the present invention is not limited to this application example, and can be widely used as a general shift register circuit.

  As shown in FIG. 11, an active matrix liquid crystal display device according to an application example of the present invention includes a pixel array unit 1002 in which a large number of pixels 1001 are arranged in a matrix, and each pixel 1001 of the pixel array unit 1002 is arranged in a row. The configuration includes at least a vertical drive circuit 1003 that sequentially selects in units, and a horizontal drive circuit 1004 that writes a video signal to each pixel in a row selected by the vertical drive circuit 1003. The vertical drive circuit 1003 and the horizontal drive circuit 1004 constitute a drive circuit that is integrated on the display panel 1005 together with the pixel array unit 1002 and drives the pixel array unit 1002.

  A vertical start pulse VST, vertical clock pulses VCK and xVCK, a horizontal start pulse HST, and horizontal clock pulses HCK and xHCK are input to the display panel 1005 from the outside of the panel. The vertical start pulse VST and the horizontal start pulse HST are given to the vertical drive circuit 1003 and the horizontal drive circuit 1004 after passing through the level shift (L / S) circuit group 1006 and the inverter circuit group 1007.

  The vertical clock pulses VCK and xVCK and the horizontal clock pulses HCK and xHCK pass through the level shift circuit group 1006 and the inverter circuit group 1007, and then directly pass through the buffer circuits 1008 and 1009 and the buffer circuits 1010 and 1011 and the horizontal drive pulse 1003 and the horizontal circuit. This is supplied to the drive circuit 1004. The level shift circuit group 1006 performs level shift (level conversion) on each of the low voltage amplitude vertical start pulse VST, the vertical clock pulses VCK and xVCK, the horizontal start pulse HST, and the horizontal clock pulses HCK and xHCK to a high voltage amplitude pulse signal. )

  In this example, the vertical start pulse VST, the vertical clock pulses VCK and xVCK, the horizontal start pulse HST, and the horizontal clock pulses HCK and xHCK are input from the outside of the display panel 1005. The generated timing generator is integrated on the display panel 1005, and the vertical start pulse VST and the horizontal start pulse HST are directly supplied from the timing generator to the vertical drive circuit 1003 and the horizontal drive circuit 1004, and the vertical clock pulses VCK, xVCK and horizontal The clock pulses HCK and xHCK may be provided to the vertical drive circuit 1003 and the horizontal drive circuit 1004 via the buffer circuits 1008 to 1011.

  In the display panel 1005, in the pixel array unit 1002, scanning lines 1012 (1012-1 to 1012) corresponding to the number m of rows of the pixel array unit 1002 are formed on one of two transparent insulating substrates (for example, glass substrates). -M) and signal lines 1013 (1013-1 to 1013 -n) corresponding to the number n of columns are wired in a matrix, and a liquid crystal layer is held between the other substrate opposed to each other with a predetermined gap For example, the backlight is arranged on the back side. Then, the pixel 1001 is arranged at the intersection of the scanning line 1012 and the signal line 1013.

  As is apparent from FIG. 11, the pixel 1001 has a pixel transistor TFT composed of a thin film transistor having a gate connected to the scanning line 1012 and a source connected to the signal line 1013, and a pixel electrode connected to the drain of the pixel transistor TFT. The liquid crystal cell LC and the storage capacitor CS having one electrode connected to the drain of the pixel transistor TFT are provided. Here, the liquid crystal cell LC means a capacitance generated between a pixel electrode formed by the pixel transistor TFT and a counter electrode formed facing the pixel electrode. The counter electrode of the liquid crystal cell LC is connected to the common line 1014 together with the other electrode of the storage capacitor CS, for example.

  FIG. 12 is a block diagram illustrating an example of a specific configuration of the vertical drive circuit. As is apparent from FIG. 12, the vertical drive circuit 1003 includes a shift register 1021 and the like. When the vertical start pulse VST is given, the vertical start pulse VST is sequentially shifted in synchronization with the vertical clock pulse VCK, and the pixel array Vertical scanning pulses φV1 to φVm for sequentially selecting each pixel 1001 of the unit 1002 in units of rows are output from each stage. The vertical scanning pulses φV1 to φVm are applied to the scanning lines 1022-1 to 1022-m of the pixel array unit 102 through the buffer circuits 1022-1 to 1022-m.

  The horizontal drive circuit 104 is also configured to include at least a shift register. In the horizontal drive circuit 1004, when a horizontal start pulse HST is given to the shift register, the horizontal start pulse HST is sequentially shifted in synchronization with the horizontal clock pulse HCK, and sampling pulses are sequentially output from each stage. The horizontal driving circuit 1004 samples a video signal supplied from the outside of the display panel 1005 using this sampling pulse, and performs dot sequential processing for each pixel 1001 in the row selected by the vertical driving circuit 1003, or An operation of writing in line sequential order is performed.

  In the liquid crystal display device having the above-described configuration, for example, the shift register 1021 that outputs the vertical scanning pulses φV1 to φVm for sequentially selecting the pixels 1001 of the pixel array unit 1002 in units of rows is used as the shift register 1021 in the above-described embodiment. Such a shift register circuit is used. In the shift register circuit according to this embodiment, as described above, a capacitive asymmetric transistor is applied as the first transistor, and the potential fluctuation of the gate of the transistor is suppressed, thereby improving the stability of the circuit and reducing the addition of the clock wiring. Low power consumption can be achieved. Therefore, by using the shift register circuit according to this embodiment as the shift register 1021 of the vertical drive circuit 1003, the scanning lines 1012-1 to 1012-m can be driven with low power consumption and stable operation. Therefore, it is possible to reduce power consumption and improve operation reliability of the liquid crystal display device.

  In this application example, the case where the shift register circuit according to this embodiment is used as the shift register 1021 constituting the vertical drive circuit 1003 has been described as an example. However, this application example is only an example, and the horizontal drive circuit It can also be used as a shift register constituting 1004.

  In this application example, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as a display element of the pixel 1001 has been described as an example. However, the application example is not limited thereto, and the display element of the pixel 1001 is used as a display element. For example, the present invention can be similarly applied to other active matrix display devices such as an organic EL display device using organic EL elements.

<Application example: Electronic equipment>
A display device to which the shift register circuit according to this embodiment is applied includes a flat module-shaped display as shown in FIG. For example, a pixel array portion 2002a in which pixels made up of a liquid crystal element, a thin film transistor, a thin film capacitor, a light receiving element and the like are integrated and formed in a matrix is provided on an insulating substrate 2002 so as to surround the pixel array portion (pixel matrix portion) 2002a. An adhesive 2021 is disposed on the substrate, and a counter substrate 2006 such as glass is attached to form a display module. The transparent counter substrate 2006 may be provided with a color filter, a protective film, a light shielding film, and the like as necessary. For example, an FPC (flexible printed circuit) 2023 may be provided in the display module as a connector for inputting / outputting a signal or the like to / from the pixel array unit 2002a from the outside.

  The display device according to the present embodiment described above is input to various electronic devices shown in FIGS. 14 to 18 such as a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, and a video camera. The video signal generated or the video signal generated in the electronic device can be applied to a display device of an electronic device in any field for displaying as an image or a video. Below, an example of the electronic device to which this embodiment is applied is demonstrated.

  FIG. 14 is a perspective view showing a television to which the present embodiment is applied. The television according to this application example includes a video display screen unit 101 including a front panel 102, a filter glass 103, and the like, and is created by using the display device according to this embodiment as the video display screen unit 101.

  FIG. 15 is a perspective view showing a digital camera to which the present embodiment is applied. FIG. 15A is a perspective view seen from the front side, and FIG. 15B is a perspective view seen from the back side. The digital camera according to this application example includes a light emitting unit 111 for flash, a display unit 112, a menu switch 113, a shutter button 114, and the like, and is manufactured by using the display device according to the present embodiment as the display unit 112. .

  FIG. 16 is a perspective view showing a notebook personal computer to which the present embodiment is applied. A notebook personal computer according to this application example includes a main body 121 including a keyboard 122 that is operated when characters or the like are input, a display unit 123 that displays an image, and the like, and the display unit 123 includes a display device according to the present embodiment. It is produced by using.

  FIG. 17 is a perspective view showing a video camera to which the present embodiment is applied. The video camera according to this application example includes a main body 131, a subject shooting lens 132 on a side facing forward, a start / stop switch 133 at the time of shooting, a display unit 134, and the like. It is manufactured by using the display device according to the above.

  FIG. 18 is a diagram showing a mobile terminal device to which the present embodiment is applied, for example, a mobile phone, in which (A) is a front view in an opened state, (B) is a side view thereof, and (C) is closed. (D) is a left side view, (E) is a right side view, (F) is a top view, and (G) is a bottom view. The mobile phone according to this application example includes an upper housing 141, a lower housing 142, a connecting portion (here, a hinge portion) 143, a display 144, a sub display 145, a picture light 146, a camera 147, and the like. In addition, the display device according to this embodiment is used as the sub display 145.

<Application example: Display imaging device>
The display device according to the present embodiment is applicable to the following display imaging device. In addition, the display imaging device can be applied to the various electronic devices described above. FIG. 19 illustrates the overall configuration of the display imaging apparatus. The display imaging apparatus includes an I / O display panel 2000, a backlight 1500, a display drive circuit 1200, a light receiving drive circuit 1300, an image processing unit 1400, and an application program execution unit 1100.

  The I / O display panel 2000 is composed of a liquid crystal panel (LCD (Liquid Crystal Display)) in which a plurality of pixels are arranged in a matrix over the entire surface, and a predetermined figure or character based on display data while performing line sequential operation. As well as a function (imaging function) for imaging an object that is in contact with or close to the I / O display 2000 as will be described later. The backlight 1500 is a light source of the I / O display panel 2000 in which, for example, a plurality of light emitting diodes are arranged, and at a high speed at a predetermined timing synchronized with the operation timing of the I / O display 2000 as described later. An on / off operation is performed.

  The display drive circuit 1200 drives the I / O display panel 2000 (drives line-sequential operation) so that an image based on display data is displayed on the I / O display panel 2000 (so as to perform a display operation). Circuit).

  The light receiving drive circuit 1300 is a circuit that drives the I / O display panel 2000 (drives line-sequential operation) so that light reception data can be obtained in the I / O display panel 2000 (so as to image an object). It is. The light reception data at each pixel is accumulated in the frame memory 1300A, for example, in units of frames, and is output to the image processing unit 14 as a captured image.

  The image processing unit 1400 performs predetermined image processing (arithmetic processing) based on the captured image output from the light receiving drive circuit 1300, and information (position coordinate data, object of the object) that is in contact with or close to the I / O display 2000. Data on the shape and size, etc.) are detected and acquired. The details of the detection process will be described later.

  The application program execution unit 1100 executes processing according to predetermined application software based on the detection result of the image processing unit 1400. For example, the display data includes the position coordinates of the detected object, and the I / O What is displayed on the display panel 2000 is mentioned. The display data generated by the application program execution unit 1100 is supplied to the display drive circuit 1200.

  Next, a detailed configuration example of the I / O display panel 2000 will be described with reference to FIG. The I / O display panel 2000 includes a display area (sensor area) 2100, a display H driver 2200, a display V driver 2300, a sensor readout H driver 2500, and a sensor V driver 2400. Yes.

  A display area (sensor area) 2100 is a region that modulates light from the backlight 1500 to emit display light and images an object that is in contact with or close to this area, and is a light emitting element (display element). And light receiving elements (imaging elements) described later are arranged in a matrix.

  The display H driver 2200 line-sequentially drives the liquid crystal elements of each pixel in the display area 2100 together with the display V driver 2300 based on the display drive display signal and the control clock supplied from the display drive circuit 1200. It is.

  The sensor readout H driver 2500 drives the light receiving element of each pixel in the sensor area 2100 together with the sensor V driver 2400 to obtain a light reception signal.

  Next, a detailed configuration example of each pixel in the display area 2100 will be described with reference to FIG. A pixel 3100 shown in FIG. 21 includes a liquid crystal element as a display element and a light receiving element.

  Specifically, on the display element side, a switching element 3100a made of a thin film transistor (TFT) or the like is disposed at the intersection of a gate electrode 3100h extending in the horizontal direction and a drain electrode 3100i extending in the vertical direction. A pixel electrode 3100b including liquid crystal is disposed between the switching element 3100a and the counter electrode. Then, the switching element 3100a is turned on / off based on a drive signal supplied via the gate electrode 3100h, and the pixel voltage is applied to the pixel electrode 3100b based on a display signal supplied via the drain electrode 3100i in the on state. Is applied and the display state is set.

  On the other hand, on the side of the light receiving element adjacent to the display element, a light receiving sensor 3100c made of, for example, a photodiode or the like is disposed, and the power supply voltage VDD is supplied. Further, a reset switch 3100d and a capacitor 3100e are connected to the light receiving sensor 3100c, and charges corresponding to the amount of received light are accumulated in the capacitor 3100e while being reset by the reset switch 3100d. The accumulated charge is supplied to the signal output electrode 3100j via the buffer amplifier 3100f at the timing when the readout switch 3100g is turned on, and is output to the outside. The on / off operation of the reset switch 3100d is controlled by a signal supplied from the reset electrode 3100k, and the on / off operation of the readout switch 3100g is controlled by a signal supplied from the readout control electrode 3100k.

  Next, a connection relationship between each pixel in the display area 2100 and the sensor readout H driver 2500 will be described with reference to FIG. In this display area 2100, a red (R) pixel 3100, a green (G) pixel 3200, and a blue (B) pixel 3300 are arranged side by side.

  The charges accumulated in the capacitors connected to the light receiving sensors 3100c, 3200c, and 3300c of each pixel are amplified by the respective buffer amplifiers 3100f, 3200f, and 3300f, and the signals are output at the timing when the readout switches 3100g, 3200g, and 3300g are turned on. It is supplied to the sensor reading H driver 2500 via the output electrode. Each signal output electrode is connected to a constant current source 4100a, 4100b, 4100c, and a signal corresponding to the amount of received light is detected with high sensitivity by the sensor reading H driver 2500.

  Next, the operation of the display imaging device of the present embodiment will be described in detail.

  First, a basic operation of the display imaging apparatus, that is, an image display operation and an object imaging operation will be described.

  In this display imaging device, a display drive circuit 1200 generates a display drive signal based on display data supplied from the application program execution unit 1100, and the drive signal generates a line for the I / O display 2000. Sequential display drive is performed to display an image. At this time, the backlight 1500 is also driven by the display drive circuit 1200, and is turned on / off in synchronization with the I / O display 2000.

  Here, the relationship between the on / off state of the backlight 1500 and the display state of the I / O display panel 2000 will be described with reference to FIG.

  First, for example, when an image is displayed with a frame period of 1/60 seconds, the backlight 1500 is turned off (turned off) in the first half of each frame period (1/120 seconds), and display is not performed. On the other hand, in the second half of each frame period, the backlight 1500 is turned on (turned on), a display signal is supplied to each pixel, and an image in that frame period is displayed.

  Thus, the first half period of each frame period is a non-light period in which display light is not emitted from the I / O display panel 2000, while the display light is emitted from the I / O display panel 2000 in the second half period of each frame period. It has become a light period.

  Here, when there is an object (for example, a fingertip) in contact with or close to the I / O display panel 2000, the light receiving element of each pixel in the I / O display panel 2000 is driven by line sequential light receiving driving by the light receiving drive circuit 1300. The object is imaged, and a light receiving signal from each light receiving element is supplied to the light receiving drive circuit 1300. In the light receiving drive circuit 1300, the light receiving signals of the pixels for one frame are accumulated and output to the image processing unit 14 as a captured image.

  The image processing unit 1400 performs predetermined image processing (arithmetic processing) described below based on the captured image, and information (position coordinate data, object shape, and the like) related to an object in contact with or close to the I / O display 2000. Size data) is detected.

It is a block diagram which shows the structural example of the shift register circuit which concerns on this embodiment. It is a timing chart of input / output IN1 (1), IN2 (N), and OUT (1) to OUT (N) of input pulse ST, clock pulses CK1 and CK2, and registers 11-1 to 11-N. It is a figure explaining the structural example of the basic circuit of the shift register circuit which concerns on this embodiment. 4 is a timing chart for explaining the operation of the basic circuit shown in FIG. 3. It is a circuit diagram explaining the specific structural example of the basic circuit of the shift register circuit which concerns on this embodiment. 5 is a timing chart for explaining the operation of the basic circuit shown in FIG. 4. It is a schematic cross section explaining the structure of a capacitive asymmetric transistor applied in the shift register circuit of this embodiment. It is a model top view explaining the structure of a capacity asymmetric transistor. It is a figure explaining the circuit example of the inversion unit shown in FIG. It is a figure explaining the circuit example of the inverter shown in FIG. It is a figure explaining the active matrix type liquid crystal display device concerning the example of application of the present invention. It is a block diagram which shows an example of a specific structure of a vertical drive circuit. It is a schematic diagram which shows the example of a flat type module shape. It is a perspective view which shows the television with which this embodiment is applied. It is a perspective view which shows the digital camera to which this embodiment is applied. It is a perspective view which shows the notebook type personal computer to which this embodiment is applied. It is a perspective view which shows the video camera to which this embodiment is applied. It is a figure which shows the portable terminal device to which this embodiment is applied, for example, a mobile telephone. It is a block diagram showing the structure of the display imaging device which concerns on the 1st Embodiment of this invention. FIG. 2 is a block diagram illustrating a configuration example of an I / O display panel illustrated in FIG. 1. It is a circuit diagram showing the structural example of each pixel. It is a circuit diagram for demonstrating the connection relation of each pixel and the sensor reading H driver. It is a timing diagram for demonstrating the relationship between the ON / OFF state of a backlight, and a display state.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Basic circuit, 2 ... Control circuit, 3 ... Potential holding circuit, 211-1 to 11-N ... Register, 12 ... Transfer gate circuit, 13 ... Transfer gate circuit, C1 ... Capacitor, Tr1 ... First transistor, Tr2 ... Second transistor, Tr3 ... Third transistor, Tr4 ... Fourth transistor, Tr5 ... Fifth transistor

Claims (7)

In a shift register circuit including a transistor in which an input signal is given to a gate, a clock is inputted to a source, and an output line is connected to a drain,
A transistor having a larger gate-drain capacitance than a gate-source capacitance is used as the transistor. A transistor having an input signal applied to the gate, a clock input to the source, and an output line connected to the drain;
Means for setting the gate of the transistor to a floating state of ON potential by the output of the previous stage;
Means for resetting the gate of the transistor to a floating state of an OFF potential by a subsequent output;
A potential holding function that keeps the gate of the transistor at the OFF potential until the next previous stage output is input as a basic circuit,
A transistor having a larger gate-drain capacitance than a gate-source capacitance is used as the transistor. The shift register circuit according to claim 2, wherein the plurality of transistors constituting the basic circuit are formed of the same conductivity type. A pixel array unit in which a plurality of pixels are arranged;
In a display device including a shift register circuit that transfers a signal to be sent to each pixel of the pixel array unit, and a drive circuit that drives the pixel by the signal.
The shift register circuit includes:
An input signal is supplied to the gate, a clock is input to the source, and an output line is connected to the drain.
A transistor having a larger gate-drain capacitance than a gate-source capacitance is used as the transistor. A pixel array unit in which a plurality of pixels are arranged;
In a display device including a shift register circuit that transfers a signal to be sent to each pixel of the pixel array unit, and a drive circuit that drives the pixel by the signal.
The shift register circuit includes:
A transistor having an input signal applied to the gate, a clock input to the source, and an output line connected to the drain;
Means for setting the gate of the transistor to a floating state of ON potential by the output of the previous stage;
Means for resetting the gate of the transistor to a floating state of an OFF potential by a subsequent output;
A potential holding function that keeps the gate of the transistor at the OFF potential until the next previous stage output is input as a basic circuit,
A transistor having a larger gate-drain capacitance than a gate-source capacitance is used as the transistor. A display device including a shift register circuit that transfers a signal to be sent to each pixel of the pixel array unit, and a drive circuit that drives the pixel by the signal;
In an electronic device comprising a housing in which the display device is incorporated,
The shift register circuit includes:
An input signal is supplied to the gate, a clock is input to the source, and an output line is connected to the drain.
A transistor having a larger gate-drain capacitance than a gate-source capacitance is used as the transistor. A display device including a shift register circuit that transfers a signal to be sent to each pixel of the pixel array unit, and a drive circuit that drives the pixel by the signal;
In an electronic device comprising a housing in which the display device is incorporated,
The shift register circuit includes:
A transistor having an input signal applied to the gate, a clock input to the source, and an output line connected to the drain;
Means for setting the gate of the transistor to a floating state of ON potential by the output of the previous stage;
Means for resetting the gate of the transistor to a floating state of an OFF potential by a subsequent output;
A potential holding function that keeps the gate of the transistor at the OFF potential until the next previous stage output is input as a basic circuit,
A transistor having a larger gate-drain capacitance than a gate-source capacitance is used as the transistor.

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