JP2009201320A - Method for suppressing variation in series-connected capacitor and controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To occasionally suppress variation in degradation in each of cells, to retain self-convergency in a capacitance, and to enhance reliability for a long period of time, in a capacitor module with a plurality of capacitor cells connected in series to each other. <P>SOLUTION: A voltage V<SB>CT</SB>and its voltage difference range ΔV<SB>CT</SB>are detected at a predetermined timing in a capacitor module with a plurality of capacitor cells connected in series to each other (1). An average value per cell is obtained (2). A cell voltage V<SB>CC</SB>and its voltage difference range ΔV<SB>CC</SB>are detected in each cell of the capacitor module at the same timing (3). The voltage of the cell and its voltage difference range are compared with the average of the voltage per cell and the average of the voltage difference range; and a bypass circuit (6) provided with a switching function and connected in parallel to the cell is turned on for a constant period of time to flow the bypass current (4), to the cell in which both of the cell voltage and the voltage difference range are larger than the average of the voltage per cell and the average of the voltage difference range. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention suppresses variation in deterioration of each cell in a capacitor module in which a plurality of capacitor cells are connected in series by executing current bypass control of a bypass circuit with an open / close function connected in parallel to each cell at a predetermined interval. In addition, the present invention relates to a method for suppressing variation in series-connected capacitors and a control device that have self-convergence of capacitance.

  FIG. 6 is a diagram for explaining an example of setting levels for initializing the series-connected capacitors. As an indispensable condition for configuring a power storage device by combining a plurality of large-capacity capacitors, there is a problem of equalization of burden voltage that occurs when capacitors are connected in series. The present applicants have proposed a device for connecting and initializing a parallel monitor as a voltage monitoring control device to individual cells of capacitors connected in series (see, for example, Patent Documents 1 to 3).

  The parallel monitor detects that the voltage of the cell has reached a specific voltage and operates the bypass circuit, thereby suppressing the voltage of the cell from becoming higher. That is, in the parallel monitor, the voltage of each cell is compared with the reference voltage and monitored by the comparator CMP, and when the cell voltage exceeds the reference voltage, the bypass circuit (transistor) is turned on to bypass the charging current. With this operation, a reference voltage of a predetermined value is set as an initialization voltage, and the charging voltage is initialized (clamped) sequentially from the cell that has reached the reference voltage setting value. Solves the problem of non-uniformity.

The setting level of the reference voltage (initialization voltage) when the series connection capacitor is initialized is roughly classified into three. First, as shown in FIG. 6 (a), initialization is performed so that the voltages of the respective cells coincide with each other at the maximum charge voltage (full charge voltage). The second is initialization to make the voltages of the respective cells coincide with each other at the lowest voltage (voltage near zero) as shown in FIG. The third is initialization to make the voltage of each cell coincide with the intermediate voltage as shown in FIG.
Japanese Patent No. 3491875 Japanese Patent No. 3504871 Japanese Patent No. 3507384

  In the conventional initialization technique in which the voltages of all the cells of the series-connected capacitors are made to coincide with each other by using the parallel monitor as described above, for example, initialization is performed with a full charge voltage as shown in FIG. When the cell voltages are matched, if individual differences such as leakage current are ignored, the voltage of each cell again matches the maximum charge voltage regardless of any charge / discharge conditions after initialization. Therefore, it is possible to prevent overvoltage of the cell under normal use conditions.

  However, actually, the voltage of each cell matched with a specific voltage gradually shifts due to the influence of individual differences such as leakage current. Therefore, periodic initialization and similar operations are required. Moreover, in applications that operate continuously for a long time in an unspecified voltage range, it is difficult to perform initialization periodically, which is a problem.

  Incidentally, when the voltage of each cell of the series-connected capacitor is made to coincide with the maximum charging voltage by initialization, as shown in FIG. 6A, a cell Ca having a large capacitance, a cell Cb having a small capacitance, and a cell Cc having a smaller capacitance are obtained. When there is an individual difference in capacitance, the voltage of each cell becomes non-uniform in the voltage range below the maximum charging voltage. In this case, the voltage of the cell Ca having a large capacitance is always higher than the voltage of the cell Cc having a small capacitance.

  On the other hand, in the electric double layer capacitor, the voltage is a major deterioration factor, and the higher the voltage, the more accelerated the deterioration. Here, assuming that the other deterioration factors are equal, the cell Ca having a large capacitance has a higher voltage than the cell Cc having a small capacitance, and therefore the deterioration of the cell Ca having a large capacitance relatively proceeds. Capacitance is reduced. This is a change in the direction of reducing the initial individual difference of the electrostatic capacity, and therefore, the individual difference of the electrostatic capacity can be directed in the reducing direction by maintaining a state in which they are matched at the maximum charging voltage. That is, the electrostatic self-convergence can be provided.

  However, as described above, depending on the application, if it becomes difficult to maintain a state in which the maximum charging voltage is matched, the self-convergence of the capacitance cannot be expected. In addition, even if it is possible to maintain a matched state at the highest charging voltage, the voltage difference increases because the initialization is performed at the highest charging voltage, and the time until the matching becomes longer, the time until the initialization is completed. There is also a problem that power loss and heat generation increase.

  Also, as shown in FIG. 6B, when the cell voltage is matched by initializing at the lowest voltage, the cell Cc having a small capacitance is a cell having a large capacitance contrary to the initialization at the highest charging voltage. The voltage is higher than Ca. Therefore, the deterioration of the cell having a relatively small capacitance proceeds, the capacitance becomes further smaller, and the difference in capacitance expands (diverges). As shown in FIG. 6C, when the cell voltages are matched by initializing with an intermediate voltage, the capacitance difference is reduced or diffused depending on the relative magnitude relationship of the average value of the voltages.

  The present invention solves the above-described problem, and performs control of suppressing variation in deterioration of each cell of a series-connected capacitor as needed so as to have a self-convergence of capacitance and improve reliability over a long period of time. It is to make.

  For this purpose, according to the method for suppressing variation in series connected capacitors according to the present invention, in a capacitor module in which a plurality of capacitor cells are connected in series, the voltage of the capacitor module and the voltage fluctuation range are detected at a predetermined timing. The average value of the voltage per cell and the average value of the voltage fluctuation range are obtained, and the voltage and voltage fluctuation range of each cell in the capacitor module are detected at the predetermined timing, and the voltage and voltage fluctuation range of the cell are detected. Is compared with the average value of the voltage per cell and the average value of the voltage fluctuation range, and both the voltage and the voltage fluctuation range of the cell are larger than the average value of the voltage per cell and the average value of the voltage fluctuation range. With respect to a cell, a bypass circuit with an open / close function connected in parallel to the cell is turned on for a certain period of time to allow a bypass current to flow. By performing bypass control by the bypass circuit with an opening / closing function at a predetermined interval, the variation in deterioration of each cell in the capacitor module is suppressed, and the capacitance self-convergence is provided. Features.

  In addition, the series connected capacitor variation suppression control apparatus includes a control signal generating unit that periodically generates a control signal, and a voltage and voltage fluctuation of a capacitor module in which a plurality of capacitor cells are connected in series at a predetermined timing based on the control signal. Module voltage detecting means for detecting the width; computing means for obtaining an average value of the voltage per cell in the capacitor module and an average value of the voltage fluctuation width; and a predetermined timing based on the control signal. Cell voltage detection means for detecting the voltage and voltage fluctuation range of each cell, and the voltage per cell in the capacitor module obtained by the calculation means for the cell voltage and voltage fluctuation width detected by the cell voltage detection means The cell voltage and voltage fluctuation range are compared with the average value and voltage fluctuation range. A bypass control means for causing a bypass current to flow by turning on a bypass circuit with an open / close function connected in parallel to the cell for a certain period of time with respect to a cell whose deviation is greater than the average value of the voltage per cell and the average value of the voltage fluctuation range; And performing bypass control by the bypass circuit with an opening / closing function at a predetermined interval to suppress variation in deterioration of each cell in the capacitor module and to have self-convergence of capacitance. Features.

  According to the present invention, in a capacitor module in which a plurality of capacitor cells are connected in series, the cell voltage and the voltage fluctuation range are both the average value of the voltage per cell in the capacitor module and the voltage fluctuation range at a predetermined interval. For cells larger than the average value, the bypass circuit with open / close function connected in parallel to the cell is turned on for a certain period of time, so that the bypass current flows. Therefore, the voltage of the cell with a small capacitance is higher than the voltage of the cell with a large capacitance. It is possible to prevent the increase in size and to control the variation variation of each cell in the capacitor module as needed. In addition, since it is possible to repeatedly control the variation in cell deterioration regardless of the charge level from near zero voltage to near the maximum charge voltage, it is possible to increase the self-convergence of capacitance and improve reliability over a long period of time. it can.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram for explaining an embodiment of a variation suppression control device for series-connected capacitors according to the present invention, and FIG. 2 is a diagram for explaining a control signal Sg, voltage detection / control timing, and a control cycle. In FIG. 1, 1 is a module voltage detection unit, 2 is an arithmetic processing unit, 3 _{(1) to} 3 _(n) are cell voltage detection units, 4 ₍₁₎ to 4 _(n) are bypass control units, and 5 is a control signal. Generating unit, 6 _{(1) to} 6 _(n) is a bypass circuit with an opening / closing function, 100 is a capacitor module, 200 is a charging / discharging unit, 300 is a variation suppressing control device, C _{(1) to} C _(n) are cells, R _{(1) to} R _(n) are resistors, V _CC is a cell voltage, V _CT is a module voltage, ΔV _CC is a cell voltage fluctuation range, ΔV _CT is a module voltage fluctuation width, and n is the number of cells connected in series.

In FIG. 1, n (number of series connection ₎ cells C _{(1) to} C _(n) are connected in series and charged / discharged in an arbitrary voltage range from a charging / discharging unit 200 including a charging power source and a load. For example, a capacitor power storage device (unit, bank) composed of an electric double layer capacitor is configured. In each cell C _{(1) to} C _(n) , bypass circuits 4 _{(1) to} 6 _(n) with open / close functions for bypassing the bypass current are connected in parallel together with resistors R _{(1) to} R _(n). ing.

In the variation suppression control device 300, the module voltage detector 1 detects the voltage of the capacitor module 100 composed of the cells C _{(1) to} C _(n) , and the module voltage _VCT and the predetermined time at a predetermined timing. The module voltage fluctuation range ΔV _CT is output. The arithmetic processing unit 2 is a 1 / n value obtained by dividing the module voltage V _CT and the module voltage fluctuation range ΔV _CT output from the module voltage detection unit 1 by n, that is, an average value per cell in the capacitor module 100. Is calculated. The cell voltage detectors 3 _{(1) to} 3 _(n) detect the voltages of the cells C _{(1) to} C _(n) , and the cell voltage V _CC and the cell voltage at a predetermined time at a predetermined timing. The fluctuation range ΔV _CC is output. Here, the voltage fluctuation width is an absolute value including a voltage rise width during charging and a voltage drop width during discharge.

The bypass control units 4 ₍₁₎ to 4 _(n) are provided for each of the cells C _{(1) to} C _{(n) by n of} the module voltage V _CT and the module voltage fluctuation range ΔV _CT output from the arithmetic processing unit 2, respectively. 1 (average value per cell) and cell voltage V _CC output from cell voltage detectors 3 _{(1) to} 3 _(n) and cell voltage fluctuation width ΔV _CC The circuits 6 _{(1) to} 6 _(n) are on / off controlled. In the bypass control units 4 ₍₁₎ to 4 _(n) , the cell voltage V _CC is larger than 1 / n of the module voltage V _CT and the cell voltage fluctuation width ΔV _CC is n times the module voltage fluctuation width ΔV _CT . in the case of greater than a value of 1, to turn on the cell C ₍₁₎ -C with parallel-connected switching functional to _(n) bypass circuit 6 ₍₁₎ to 6 _(n). When the bypass circuit 6 _{(1) to} 6 _(n) with switching function is turned on, the terminals of the cells C _{(1) to} C _(n) are short-circuited through the resistors R _{(1) to} R _(n). Therefore, the current is bypassed depending on the cell voltage V _CC and the resistors R _{(1) to} R _(n) . By this bypass control, the charging voltage of the cells that have become larger than the average is selectively suppressed because the electrostatic capacity is small. As a result, equalization at the highest voltage is achieved, and variations in deterioration of each cell are suppressed, and electrostatic charges are suppressed. Capacitance self-convergence can be provided.

The control signal generator 5 generates a control signal Sg for operating the module voltage detector 1, the cell voltage detectors 3 _{(1) to} 3 _(n) , and the bypass controllers 4 ₍₁₎ to 4 _(n). Is. Based on the control signal Sg, timings t1, t2,... For detecting (sampling) the module voltage V _CT and the cell voltage V _CC , time widths for calculating the module voltage fluctuation width ΔV _CT and the cell voltage fluctuation width ΔV _CC , The time width for bypass control of the cells C _{(1) to} C _(n) is controlled.

The resistors R _{(1) to} R _(n) are impedance elements of the bypass circuit that define the magnitude of the current flowing through the bypass circuits 6 _{(1) to} 6 _(n) with switching functions. For example, the smaller the values of the resistors R _{(1) to} R _(n) , the smaller the values of the cells C _{(1) to} C _(n) when the bypass circuits 6 _{(1) to} 6 _(n) with switching functions are turned on. By bypassing the charging current, the current flowing through the open / close function bypass circuits 6 _{(1) to} 6 _(n) increases. Further, during discharge, the discharge current flowing from the cells C _{(1) to} C _(n) increases. As a result, the voltage rise is further suppressed during charging, and the voltage drop is further promoted during discharging. At the time of charging, if the values of the resistors R _{(1) to} R _(n) are zero, the entire charging current is bypassed, and the discharging currents from the cells C _{(1) to} C _(n) also flow.

Voltage drop due to the resistance R ₍₁₎ ~R _(n) through the current flowing through the opening and closing function with bypass circuit _{6 (1) ~6 (n)} , equal to the cell voltage of the C ₍₁₎ ~C _(n) at that time Become. That is, the bypass current at the time of constant current charging increases as the charging voltage of the cells C _{(1) to} C _(n) increases. On the other hand, at the time of discharging, the discharging current decreases as the charging voltage of the cells C _{(1) to} C _(n) decreases. That is, during charging, when the cell voltage is low, a part of the charging current flows by bypass, and when the cell voltage increases, the discharge current from the cell may flow. However, during discharge, a discharge current defined by the cell voltage and the resistance value flows from the cell.

In the present embodiment, for example, as shown in FIG. 2, the first voltage V _t1 is detected at the falling t1 of the control signal Sg, and then the second voltage V _t2 is detected at the rising t2 of the control signal Sg. In module voltage detection, the second voltage V _t2 is output as the module voltage V _CT and the difference obtained by subtracting the first voltage V _t1 from the second voltage V _t2 is output as the module voltage fluctuation width ΔV _CT. To do. Similarly, in the detection of the cell voltage, in each cell, the second voltage V _t2 is output as the cell voltage V _CC and the difference obtained by subtracting the first voltage V _t1 from the second voltage V _t2 is the cell voltage. Output as a fluctuation range ΔV _CC . Based on these outputs, in the bypass control, the cell voltage V _CC and the cell voltage fluctuation range ΔV _CC are respectively calculated as the average value of the module voltage V _CT per cell and the average value of the module voltage fluctuation range ΔV _CT per cell, that is, Compared with the value per cell divided by the number n of cells connected in series. Then, in the cell in which both the cell voltage V _CC and the cell voltage fluctuation range ΔV _CC are larger than the average value, the control signal Sg is set to the control period from t2 to t1 where the control signal Sg is High, and the charging current is charged during charging. By bypassing, the rise in charging voltage is suppressed. Further, at the time of discharging, the voltage is further lowered by passing a discharging current through the bypass circuit. As a result, the cells are equalized at the maximum voltage, the variation in deterioration of each cell is suppressed, and the self-convergence of the capacitance can be provided.

  FIG. 3 is a diagram for explaining an embodiment of a variation suppressing method during charging of the capacitor module according to the present invention, and FIG. 4 shows an example of a transition of voltage of each cell of the capacitor module in accordance with execution of the variation suppressing process. FIG.

For example, as shown in FIG. 3, the processing algorithm based on the variation suppression method during charging of the capacitor module 100 according to the present invention first starts timekeeping (step S11), and when timekeeping reaches t1 (step S12), the module voltage V _CTt1 and cell voltage V _CCt1 are measured and stored in the memory (step S13). t1 may be 0, that is, at the same time as the timing start, or may be a predetermined time from the timing start. Then, after waiting for the time t2 to _reach t2 (step S14), the module voltage V _CTt2 and the cell voltage V _CCt2 are measured and stored in the memory (step S15). Next, ΔV _CT = V _CTt2 −V _CTt1 and ΔV _CC = V _CCt2 −V _CCt1 are used to calculate fluctuation _ranges ΔV _CT and ΔV _CC of each voltage between t1 and t2, respectively (step S16).

_Whether the cell voltage V _CCt2 is larger than the average value per cell of the module voltage V _CTt2 (step S17) or whether the cell voltage fluctuation width ΔV _CC is larger than the average value per cell of the module voltage V _CT (step S18). judge. Cell voltage V _CCt2 is larger than the average value per cell of module voltage V _CTt2 (YES in step S17), and cell voltage fluctuation width ΔV _CC is larger than the average value per cell of module voltage V _CT (in step S18). If YES in the process, the bypass circuit with an opening / closing function of the cell is turned on (step S19). When at least one of the processes in steps S17 and S17 is NO, the bypass circuit with an opening / closing function of the cell remains off, and further waits for time t3 to reach t3 (step S20). The bypass circuit with open / close function turned on is turned off (step S21), the time count is reset (step S22), and the process returns to step S11.

The following description will be made assuming that the cell Ca has a relatively large capacitance, the cell Cb has a small capacitance, and the cell Cc has a small capacitance, and only the cell Ca is large in relation to the average value. FIG. 4A shows the transition of the voltage of each cell when the variation suppressing process of the present embodiment is executed by the example of the capacitor module. That is, since the cell voltage fluctuation range ΔV _CC is smaller than the average value in the cell Ca, the bypass circuit with an opening / closing function is not turned on. On the other hand, the cell Cc having the smallest capacitance has a cell voltage fluctuation range ΔV _CC larger than the average value, and the cell voltage V _CC soon becomes larger than the average value. The circuit is turned on (tc4-tc5, tc6-tc7, tc8-). In the cell Cb having an intermediate capacitance, the cell voltage fluctuation range ΔV _CC is larger than the average value, but the chance that the cell voltage V _CC becomes larger than the average value is reduced. The frequency decreases (tc2-tc3, tc6-tc7).

  As compared with the charge mode, in the discharge mode, as shown in FIGS. 4B and 4C, among the cells Cb and Cc having a small capacitance, a cell having a high voltage at the start of discharge is provided with an opening / closing function at an initial stage. It just turns on the bypass circuit. The example shown in FIG. 4B is a case where the voltage of the cell Cb is high at the start of discharge, and a low voltage level is obtained by turning on the bypass circuit with an opening / closing function between td2 and td3 by judging between td1 and td2. It is adjusted to. Similarly, the example shown in FIG. 4C is a case where the voltage of the cell Cc is high at the start of discharge, and is determined by turning on the bypass circuit with an opening / closing function between td6 and td7 as judged between td5 and td6. The voltage level is adjusted. As a result, the state in which the voltage of the cell having a small capacitance becomes higher than the voltage of the cell having a large capacitance is resolved early (thin broken line / dotted line → thick broken line / dotted line), and as a result, the highest voltage of each cell. The control close to that shown in FIG. 6A is realized, and the self-convergence of the capacitance is given.

  FIG. 5 is a diagram showing circuit configuration examples of the module voltage detection unit, the cell voltage detection unit, the bypass control unit, and the control signal generation unit. 11, 12, 21, and 22 are registers, 13 and 23 are subtraction circuits, Reference numeral 15 denotes a division circuit, 31 and 32 denote comparators, 33 denotes an AND circuit, 51 denotes a fall detection circuit, and 52 denotes a rise detection circuit.

In FIG. 5, the module voltage detection unit 1 measures the input module voltage by the register 11 storing the measurement data of the input module voltage by the falling signal S _gt1 of the control signal Sg and the rising signal S _gt2 of the control signal Sg. A register 12 for storing data and a subtracting circuit 13 for subtracting the output data of the register 11 from the output data of the register 12 are provided. The arithmetic processing unit 2 includes a division circuit 14 that divides the output data of the subtraction circuit 13 by n, and a division circuit 14 that divides the output data of the register 12 by n. The module voltage detecting unit 1, the average value [Delta] V _CT / n per cell from the division circuit 14 module voltage fluctuation width [Delta] V _CT is output, the average from the division circuit 14 per cell module voltage V _CT value V _CT / n Is output.

The cell voltage detector 2 is a register 21 for storing input cell voltage measurement data by the falling signal S _gt1 of the control signal Sg, and a register for storing input cell voltage measurement data by the rising signal S _gt2 of the control signal Sg. 22 and a subtracting circuit 23 for subtracting the output data of the register 21 from the output data of the register 22. The cell voltage detector 3 outputs the cell voltage fluctuation width ΔV _CC from the subtracting circuit 23 and the cell voltage V _CC from the register 22.

The bypass control unit 3 compares the cell voltage V _CC with the average value V _CT / n of the module voltage V _CT , the cell voltage fluctuation width ΔV _CC and the average value ΔV _CT / n of the module voltage fluctuation width ΔV _CT Are provided with an AND circuit 33 that AND-processes the output of the comparator 32, the output of the comparator 31, the output of the comparator 32, and the control signal Sg.

The control signal generator 5 detects a falling edge of the control signal Sg from High to Low and outputs a falling signal _Sgt1 , and detects a rising edge of the control signal Sg from Low to High. A rising _edge detection circuit 52 that outputs a rising _edge signal S _gt2 is provided.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, in the above embodiment, the bypass circuit with an opening / closing function is controlled both during charging and during discharging, and the controllable time is increased to quickly suppress the voltage. For example, when it is desired to effectively use the amount to the limit, the bypass circuit with an opening / closing function may be controlled only during charging. Although the present embodiment has been described with specific processing and circuit configuration examples, it goes without saying that the configuration of these processing and circuits and the like can be appropriately modified and changed as design matters for those skilled in the art. .

The figure explaining embodiment of the variation suppression control apparatus of the capacitor module which concerns on this invention. The figure explaining control signal Sg, voltage detection and control timing, and control cycle. The figure for demonstrating embodiment of the variation suppression method of the capacitor module which concerns on this invention. The figure which shows the example of transition of the voltage of each cell of a capacitor module accompanying execution of a variation suppression process. The figure which shows the circuit structural example of a module voltage detection part, a cell voltage detection part, a bypass control part, and a control signal generation part. The figure explaining the example of the setting level which initializes a capacitor module.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Module voltage detection part, 2 ... Arithmetic processing part, 3 ₍₁₎ -3 _{( n)} ... Cell voltage detection part, 4 ₍₁₎ -4 _(n) ... Bypass control part, 5 ... Control signal generation part, 6 _{(1) to} 6 _(n) ... bypass circuit with open / close function, 100 ... capacitor module, 200 ... charging / discharging unit, 300 ... variation control device, C _{(1) to} C _(n) ... cell, R ₍₁₎ to R _(n) ... resistance, V _CC ... cell voltage, V _CT ... module voltage, ΔV _CC ... cell voltage fluctuation range, ΔV _CT ... module voltage fluctuation range, n ... number of cells connected in series

Claims (2)

In a capacitor module in which a plurality of capacitor cells are connected in series,
Detecting the voltage and voltage fluctuation range of the capacitor module at a predetermined timing to obtain an average value of voltage per cell and an average value of voltage fluctuation range in the capacitor module;
The voltage and voltage fluctuation range of each cell in the capacitor module is detected at the predetermined timing, and the voltage and voltage fluctuation range of the cell are compared with the average value of the voltage per cell and the average value of the voltage fluctuation range. And
For a cell whose voltage and voltage fluctuation range are both greater than the average value of the voltage per cell and the average value of voltage fluctuation range, the bypass circuit with open / close function connected to the cell is turned on for a certain period of time. By passing a bypass current,
The bypass control by the bypass circuit with an opening / closing function is executed at a predetermined interval to suppress variation in deterioration of each cell in the capacitor module, and to have self-convergence of capacitance. A method for suppressing variation in series-connected capacitors. Control signal generating means for periodically generating a control signal;
Module voltage detecting means for detecting a voltage and a voltage fluctuation range of a capacitor module in which a plurality of capacitor cells are connected in series at a predetermined timing based on the control signal;
An arithmetic means for obtaining an average value of voltage and an average value of voltage fluctuation range per cell in the capacitor module;
Cell voltage detection means for detecting the voltage and voltage fluctuation range of each cell in the capacitor module at a predetermined timing based on the control signal;
The cell voltage and the voltage fluctuation range detected by the cell voltage detection means are compared with the average value of the voltage per cell in the capacitor module and the average value of the voltage fluctuation width obtained by the calculation means, For a cell whose voltage and voltage fluctuation range are both larger than the average value of the voltage per cell and the average value of voltage fluctuation range, a bypass circuit with an open / close function connected in parallel to the cell is turned on for a certain period of time and a bypass current And a bypass control means that performs bypass control by the bypass circuit with an opening / closing function at a predetermined interval to suppress variation in deterioration of each cell in the capacitor module, and to reduce the self-convergence of capacitance. An apparatus for suppressing variation in series-connected capacitors, characterized in that it is provided.

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