JP2009200371A - Thin film transistor, and display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor capable of suppressing leak current. <P>SOLUTION: This thin film transistor includes a semiconductor thin film 1 arranged on a substrate, a gate electrode G, and an insulation film 2 arranged between the semiconductor thin film 1 and the gate electrode G. The semiconductor thin film 1 is divided into an input-side region S and an output-side region D, and the thickness of the semiconductor thin film 1 located from a boundary 3 between both of them to the output-side region D is at least partially reduced as compared with that of the semiconductor thin film 1 located from the boundary 3 to the input-side region S. The gate electrode G is arranged to overlap the boundary 3, and a part of the semiconductor thin film 1 overlapping the gate electrode G is used for a channel region CH. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thin film transistor. The present invention also relates to an active matrix display device in which thin film transistors are integrated and formed as pixel driving transistors.

  The thin film transistor includes a semiconductor thin film formed on a substrate, a gate electrode, and a gate insulating film disposed between the semiconductor thin film and the gate electrode. The semiconductor thin film is divided into an input side region, an output side region, and a channel region therebetween. The channel region is a portion overlapping with the gate electrode through the gate insulating film. The thin film transistor is a three-terminal active element having a gate electrode as a control end and an input side region and an output side region as a pair of current ends.

A conventional thin film transistor basically has a structure in which an input side region and an output side region are symmetrical with a channel region in between. In some cases, a structure in which an input side region and an output side region are formed asymmetrically is known in order to obtain necessary characteristics according to the use of a thin film transistor. For example, the structure is disclosed in Patent Document 1 and Patent Document 2 below. .
JP 2001-298100 A JP 2004-047880 A

  By the way, when a thin film transistor is used as a pixel driving transistor of an active matrix display device, it is important to suppress a leakage current of each thin film transistor in order to ensure a display image quality at a practical level. However, although the conventional asymmetric thin film transistor contributes to the improvement of various characteristics, an asymmetric structure especially for the purpose of suppressing leakage current has not been proposed.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a thin film transistor capable of suppressing leakage current and a display device using the thin film transistor as a pixel driving transistor. In order to achieve this purpose, the following measures were taken. That is, a thin film transistor according to the present invention includes a semiconductor thin film disposed on a substrate, a gate electrode, and an insulating film disposed between the semiconductor thin film and the gate electrode. And the output side region, the thickness of the semiconductor thin film from the boundary to the output side region is at least partially thinner than the thickness of the semiconductor thin film from the boundary to the input side region, the gate electrode Are arranged so as to extend over the boundary, and a portion of the semiconductor thin film overlapping the gate electrode becomes a channel region.

  Preferably, the input side region of the semiconductor thin film is a conductive region into which impurities are implanted at a predetermined concentration, and a low concentration impurity between the conductive region and the channel region and having a lower impurity concentration than the conductive region. The output region of the semiconductor thin film is also divided into a conductive region and a low concentration impurity region, and the low concentration impurity region is formed in a portion where the thickness of the semiconductor thin film is reduced. . Further, the impurity concentration of the low concentration impurity region in the output side region is higher than that of the low concentration impurity region in the input side region.

  According to the present invention, a row-shaped scanning line, a column-shaped signal line, and a pixel located at the intersection of both are integrally formed on a substrate. The pixel includes an electro-optic element, the scanning line, In the display device including a thin film transistor connected to the signal line and driving the electro-optic element, the thin film transistor includes a semiconductor thin film, a gate electrode, and an insulating film disposed between the semiconductor thin film and the gate electrode The semiconductor thin film is divided into an input side region connected to the signal line and an output side region connected to the electro-optic element, and the boundary between the two is smaller than the thickness of the semiconductor thin film in the input side region. The thickness of the semiconductor thin film in the output side region is reduced, and the gate electrode is connected to the scanning line and is arranged so as to cover the boundary, and the portion of the semiconductor thin film overlapping the gate electrode is a channel Territory And wherein the made thing.

  According to the present invention, the semiconductor thin film in the output side region is thinner than the semiconductor thin film in the input side region. With this configuration, the impurity concentration in the output side region can be made higher than the impurity concentration in the input side region. By making the input side region and the output side region of the thin film transistor an asymmetric structure with respect to the thickness and impurity concentration of the semiconductor thin film, the leakage current can be reduced without reducing the on current of the thin film transistor. Such a thin film transistor that has a sufficient on-current supply capability and has a suppressed leakage current is suitable as a pixel driving transistor of an active matrix display device and has high practical value.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram illustrating a reference example of a thin film transistor. This reference example is a thin film transistor having a symmetrical structure. In order to clarify the background of the present invention, this symmetrical thin film transistor will be briefly described first. As shown in the figure, this thin film transistor comprises a semiconductor thin film 1 disposed on a substrate, a gate electrode G, and a gate insulating film disposed between the semiconductor thin film 1 and the gate electrode G. The semiconductor thin film 1 is divided into an input side region and an output side region with the gate electrode G in between. The portion of the semiconductor thin film 1 that overlaps the gate electrode G becomes the channel region CH. The input side region of the semiconductor thin film 1 is between the conductive region (source S) into which impurities are implanted at a predetermined concentration, and between the conductive region (source S) and the channel region CH, and has an impurity concentration lower than that of the source region S. It is separated from the low concentration impurity region LDD. The output side region of the semiconductor thin film 1 is also divided into a conductive region (drain D) and a low concentration impurity region LDD. For convenience of explanation, the conductive region in the input side region is set as the source S and the conductive region in the output side region is set as the drain D. However, depending on the polarity of the signal input to the thin film transistor in some cases, the source S and drain D Roles can be switched.

  In this thin film transistor, an LDD region is interposed between the source region S and the channel region CH, and an LDD region is also interposed between the channel region CH and the drain region D. This LDD region has a low impurity concentration, has a higher electric resistance than the source region S and the drain region D, and has an effect of suppressing leakage current. The graph on the left side of FIG. 1 is a graph showing the relationship between the impurity dose in the LDD region and the leakage current. The dose amount represents the impurity implantation amount per unit area. Curve A represents a leakage current from the source region S to the drain region D, and curve B represents a leakage current flowing from the drain region D to the source region S. In any case, the leakage current increases as the dose amount with respect to the LDD region increases (that is, as the electrical resistance of the LDD region decreases). Therefore, it is desirable that a general LDD-structured thin film transistor has a high electric resistance in the LDD region in order to suppress leakage current. However, when the dose amount is lowered, the leakage current increases conversely as shown in the graph. If the impurity dose with respect to the LDD region is excessively decreased in order to increase the electric resistance, the electric field at the drain end increases and the tunnel current component increases. As a result, as shown in the graph, a portion where the leakage current increases conversely occurs. Therefore, in order to set an appropriate LDD dose, it is necessary to consider the balance between the LDD resistance and the electric field concentration at the drain end.

  An energy band is represented below the schematic plan view of the thin film transistor of FIG. This energy band corresponds to the dose indicated by the circle in the graph shown in FIG. That is, since the LDD dose is excessively reduced, electric field concentration occurs at the end of the drain region D, and the energy band drops sharply. In the actual operation of the thin film transistor, the tunnel current where the energy band sharply drops cannot be ignored. When such a thin film transistor is used as a pixel driving transistor of an active matrix display device, image quality defects such as flicker and crosstalk occur due to leakage current. Therefore, when used for a pixel transistor, it is important to suppress leakage current including tunnel current as much as possible while securing on-current. In the thin film transistor having the LDD structure, it is basically desirable that the electric resistance of the LDD region is high. However, if the impurity dose with respect to the LDD region is excessively decreased in order to increase the resistance, the tunnel current component at the drain end increases. Therefore, it is necessary to determine the impurity concentration in consideration of the balance between the LDD resistance and the drain end electric field.

  FIG. 2 is a schematic plan view showing another reference example of the thin film transistor. This thin film transistor is formed as a pixel driving transistor of an active matrix display device. Unlike the reference example shown in FIG. 1, the layout of the thin film transistors is asymmetric in order to efficiently integrate high-density and fine pixels. In the illustrated reference example, the layout is asymmetric in the left region (input side region) and the right region (output side region) with the gate electrode G in between. In the case of the driving thin film transistor, the source S in the input side region is connected to the signal line, while the drain D in the output side region is connected to the pixel electrode. An LDD region for suppressing leakage current is interposed between the source region S and the channel region CH. An LDD region is also interposed between the channel region CH and the drain region D. In the case of this reference example, the wiring width of the LDD region on the drain D side is narrower than the LDD region on the source S side, particularly for the purpose of suppressing the light leakage current. In such a thin film transistor actually used for pixel switching, the layout on the source S side and the drain D side is asymmetrical, so the influence of the electric field received from the peripheral wiring is different, and the optimum impurity concentration is different in the left and right LDD regions. Different. At present, it is necessary to consider this balance.

  The graph on the left side of FIG. 2 represents the relationship between the LDD dose and the leakage current. A curve A represents a leakage current from the source S to the drain D. Curve B represents the leakage current from the drain D to the source S. As is clear from comparison between curve A and curve B, the amount of leakage current is different even if the dose is the same. Therefore, the optimum impurity concentration differs between the drain D side and the source S side. The conventional asymmetric thin film transistor does not take this point into consideration, and the impurity concentration of the LDD region is the same on the source side S and the drain side D. However, in an actual pixel switching transistor, the optimum impurity concentration differs in each input / output LDD region. It is important to realize an optimum impurity concentration for reducing the leakage current for each LDD of the input and output, which is a main object of the present invention.

  FIG. 3 is a schematic cross-sectional view showing the basic configuration of the thin film transistor according to the present invention. As shown in the figure, the thin film transistor according to the present invention includes a semiconductor thin film 1 disposed on a substrate, a gate electrode G, and an insulating film 2 disposed between the semiconductor thin film 1 and the gate electrode G. The gate insulating film 2 is made of, for example, a silicon dioxide film, a silicon nitride film, or a composite film thereof. The gate electrode G is made of a refractory metal film or a conductive polysilicon film. The semiconductor thin film 1 is a polysilicon film in this embodiment.

  The semiconductor thin film 1 made of polysilicon is divided into an input side region and an output side region, and the semiconductor thin film located from the boundary 3 to the output side region as compared to the thickness of the semiconductor thin film 1 from the boundary 3 to the input side region. The thickness of 1 is at least partially reduced. The gate electrode G is arranged so as to extend over the boundary 3, and a portion of the semiconductor thin film 1 overlapping the gate electrode G becomes a channel region CH.

  The input side region of the semiconductor thin film 1 is located between the conductive region (source region S) into which impurities are implanted at a predetermined concentration, and between the conductive region (source region S) and the channel region CH. S) is divided into a low concentration impurity region (LDD region) having a lower impurity concentration. The output side region of the semiconductor thin film 1 is also divided into a conductive region (drain region D) and a low concentration impurity region (LDD region), and the thickness of the semiconductor thin film 1 is reduced in this low concentration impurity region (LDD region). It is formed in the part. With this configuration, the impurity concentration of the low concentration impurity region (LDD region) in the output side region is higher than that of the low concentration impurity region (LDD region) in the input side region. That is, when an n-type impurity is implanted into the semiconductor thin film 1 to form LDD regions on both sides of the channel region CH, the concentration of the ions differs from side to side in a self-organized manner by controlling the acceleration voltage of the impurity ions. An LDD region can be formed. In general, n-type impurities are implanted into the semiconductor thin film 1 by ion implantation. In the ion implantation, impurity ions are accelerated and implanted into the semiconductor thin film 1 through the gate insulating film 2. At this time, the acceleration voltage of impurity ions is adjusted, and the profile is set so that, for example, the peak of the concentration profile matches the upper surface of the semiconductor thin film 1. In this manner, the impurity concentration in the LDD region on the source S side is relatively lowered due to the increase in thickness, while the LDD region on the drain region D side has a relatively high impurity concentration because the semiconductor thin film 1 is thin. . In this way, it is possible to make a difference in impurity concentration between the left and right LDD regions by one ion implantation process. That is, by reducing the thickness of the semiconductor thin film 1 in the output side region compared to the input side region and appropriately setting the acceleration voltage of impurity ions in ion implantation, the LDD concentration in the output side region is changed to the LDD concentration in the input side region. Compared to, it can be increased in a self-organizing manner (automatically).

  In this way, the semiconductor film thickness in the LDD region is made different in the input / output region, so that the impurity concentration in the LDD structure is formed asymmetrically. Leakage current can be reduced without reducing the on-current due to the asymmetry of the semiconductor film thickness and impurity concentration. However, the present invention is not necessarily limited to the thin film transistor having the LDD structure. Even in a thin film transistor that does not have an LDD structure, by reducing the thickness of the drain region compared to the source region, leakage current can be reduced due to the effect of thinning itself. Also, at this time, by controlling the acceleration voltage at the time of impurity implantation into the drain region, the thinned portion in the drain region is formed with a lower concentration than the portion remaining as it is in the thick film. Can have functions. Two or more steps on the output side thin film portion may be formed. By forming two or more steps, the concentration gradient in the LDD region or the drain region becomes gentler and the electric field concentration can be reduced.

  4 is a schematic plan view showing the layout of the pixel switching thin film transistor shown in FIG. As shown in the drawing, in the thin film transistor, a semiconductor thin film 1 serving as an element region is formed on a light shielding film 4 formed on a substrate. The semiconductor thin film 1 is patterned into a predetermined shape, and a gate electrode G is disposed thereon via a gate insulating film. An LDD region is interposed between the gate electrode G and the input side region (source S). An LDD region is also interposed between the output side region (drain D) and the gate electrode G. The source S on the input side is connected to a signal line (not shown), while the drain D on the output side is connected to the pixel electrode. The LDD region on the source S side and the LDD region on the drain D side are asymmetric. In the present invention, the polysilicon film thickness is created separately from the center of the channel, and at the same time, the concentration profile at the time of implantation of the n-type impurity into the LDD region is controlled, whereby the impurity concentration is separately created in each input / output LDD portion, and output The leakage current can be suppressed without reducing the on-current by reducing the polysilicon thickness on the side and optimizing the impurity concentration at the input / output LDD portions. By adopting the present invention, it becomes possible to optimize the impurity concentration of the input / output LDD portions of the pixel switching transistor, suppress the off current and eliminate the bright spot defect caused by the current leakage, and the image quality such as flicker. Defects can also be prevented. Further, by using the present invention, as an effect of making the polysilicon thin film on the output side of the pixel switching thin film transistor, the off current can be lowered without reducing the on current, and the bright spot defect and flicker caused by the current leakage are improved. It is possible.

  FIG. 5 is a graph showing the relationship between the polysilicon film thickness in the LDD region and the impurity concentration. The acceleration voltage of impurity ions is taken as a parameter. For example, when the acceleration voltage of impurity ions in impurity ion implantation (ion implantation) is 50 kev, the thinner the film thickness, the higher the impurity concentration in the LDD region. By selecting the optimum acceleration voltage in this way, it is possible to control the impurity concentration in the film and the film thickness to have negative linearity. Therefore, it is possible to make a difference in the impurity concentration of the LDD between the input side and the output side by one ion implantation process.

FIG. 6 is a graph showing the relationship between the LDD dose and the leakage current. A curve A represents a case of leakage current flowing from the output side region toward the input side region. Curve A is the case where there is no difference in LDD density between the input side and the output side. On the other hand, a curve A ′ is a case where the output side LDD concentration is made higher than the input side LDD concentration according to the present invention. The film thickness of the output side LDD region is reduced by 15 nm compared to the film thickness of the input side LDD region. As is clear from the curve A and the curve A ′, the leakage current can be suppressed by reducing the film thickness of the output side LDD and increasing the impurity concentration. When read on the graph, the effect of thinning the output side LDD corresponds to a change of 6 × 10 ¹² / cm ^{2 in} terms of the LDD dose. As a result, the leakage current can be reduced by about 20% by reducing the film thickness of the output side LDD region by 15 nm compared to the input side LDD region. On the other hand, as shown by curve B, there is no change in the leakage current from the input side region to the output side region.

FIG. 7 is a process diagram showing a method for manufacturing a display device according to the present invention. In this manufacturing method, the transistor in the pixel portion and the transistor in the peripheral circuit portion are formed simultaneously on the insulating substrate. In this embodiment, quartz is used as the insulating substrate. As a pretreatment, a back surface light shielding film is formed on the quartz substrate. In this embodiment, WSi is formed to a thickness of 200 nm to form a back light shielding film. Further, a SiO ₂ film having a thickness of 600 nm is formed on this backside light-shielding film by CVD as a base film.

  First, in step (1), a polycrystalline silicon film 1 is formed to a thickness of, for example, 75 nm on a substrate (not shown) prepared in advance. In this example, the polysilicon film 1 is formed by LP-CVD or epitaxy so that the channel region has a thickness of 75 nm. However, the present invention is not limited to this, and an amorphous silicon film may be used instead of the polysilicon film, and the film thickness is optimally about 10 nm to 50 nm. In some cases, a GaAs film or Ge film may be formed as the semiconductor thin film.

  Proceeding to step (2), the entire surface of the polysilicon film 1 is dummy oxidized to form an oxide film having a thickness of 60 nm, for example.

  Proceeding to step (3), a photoresist 51 is entirely formed on the dummy oxide film 50. The resist 51 is patterned by photolithography, and an opening is provided in a portion to be an element region of the pixel transistor.

  Proceeding to step (4), the oxide film 50 is wet-etched using the photoresist 51 as a mask, and removed from the portion corresponding to the element region of the pixel transistor. The etching process of the oxide film 50 may be either dry etching or wet etching, but in this embodiment, wet etching is used in consideration of the selection ratio. After the oxide film 50 is etched, the unnecessary photoresist is removed.

  Proceeding to the step (5), the second whole-surface dummy oxidation treatment is performed to oxidize the portion corresponding to the element region of the pixel transistor. As a result, the polysilicon film 1 in the element region is thinned. Note that the second dummy oxide film 52 is oxidized so as to have a thickness of 20 nm.

  Proceeding to step (6), the dummy oxide film 52 is removed by wet etching. Thereby, a predetermined portion of the polysilicon film 1 can be thinned. The thinned region becomes a channel region and an LDD region on the output side in a later process.

  Proceeding to step (7), the polysilicon film 1 is patterned into an island shape by photolithography. For the patterning of the polysilicon film 1, either wet etching or dry etching can be employed. However, in consideration of miniaturization of the pixel portion transistor, dry etching is employed in this example.

Proceeding to step (8), the island-patterned polysilicon film 1 is covered with a gate insulating film 2. In this example, SiO _{2 is formed} by the CVD method to form the gate insulating film 2.

  Proceeding to step (9), the gate electrode G is formed on the island-patterned polysilicon film 1 via the gate insulating film 2. In this case, on the pixel transistor side, a part of the gate electrode G covers a thinned portion formed in advance on the polysilicon film 1.

  Proceeding to step (10), an n-type impurity is implanted by ion implantation to form an LDD region. Here, the impurity P is implanted into the polysilicon film 1 using the gate electrode G as a mask. At this time, by utilizing the difference in film thickness between the LDD region on the output side and the LDD region on the input side with the gate electrode G in between, the impurity concentration between the output side LDD and the input side LDD is self-organized. To be different. Specifically, by controlling the ion implantation conditions (especially acceleration voltage) of impurities, the LDD impurity concentration on the output side can be increased and the impurity concentration on the input LDD can be decreased.

  Proceeding to the step (11), the photoresist 53 is patterned so as to cover the LDD region formed in the step (10) and the channel region immediately below the gate electrode G. Using this patterned photoresist as a mask, an n-type impurity is implanted at a high concentration to form a source region S and a drain region. In this example, P is used as an n-type impurity. In this manner, peripheral circuit transistors are formed at the same time as the pixel transistors are formed. Thereafter, although not shown in the drawing, a contact or the like is created to complete the transistor.

  FIG. 8 is a schematic perspective view showing the overall configuration of the display device created by the manufacturing method shown in FIG. As shown in the figure, the display device has a panel structure including a pair of insulating substrates 101 and 102 and a liquid crystal 103 held between the substrates. A pixel array unit 104 and a drive circuit unit are integrated on the lower insulating substrate 101. The drive circuit section is divided into a vertical drive circuit 105 and a horizontal drive circuit 106. Further, a terminal portion 107 for external connection is formed at the upper end of the peripheral portion of the insulating substrate 101. The terminal portion 107 is connected to the vertical drive circuit 105 and the horizontal drive circuit 106 through a wiring 108. In the pixel array portion 104, row-shaped gate wirings 109 and column-shaped signal wirings 110 are formed. A light-reflective pixel electrode 111 and a thin film transistor 112 that drives the pixel electrode 111 are formed at the intersection of both wirings. The thin film transistor 112 has a gate electrode connected to the corresponding gate wiring 109, a drain region connected to the corresponding pixel electrode 111, and a source region connected to the corresponding signal wiring 110. The gate wiring 109 is connected to the vertical driving circuit 105, while the signal wiring 110 is connected to the horizontal driving circuit 106.

  FIG. 9 is a configuration diagram showing an example of a reflective projector apparatus using the liquid crystal panel shown in FIG. 8 as an image display unit. The reflective projector apparatus illustrated in FIG. 7 has a lamp 201 that outputs white light, a collimator lens 202, and a fly-eye lens as a light source that provides three primary colors, that is, blue, green, and red. 203, 204, PS conversion means 205 that converts incident light, for example, P-polarized light into S-polarized light, a main condenser lens 206, a blue reflective dichroic mirror 207, and a green-red reflective dichroic mirror 208 And total reflection mirrors 209 and 210 and a green reflection dichroic mirror 211.

  The reflective projector device further includes a cross prism 224 and three polarization beam splitters (PBS) disposed around the cross prism 224, that is, a first polarization beam splitter (PBS) 218, a second PBS 219, 3 PBS 223. The reflection type projector device includes a projection lens 225 on the side facing the second PBS 219 with the cross prism 224 interposed therebetween. A condenser lens 212 is disposed on one surface side of the second PBS 219, and a green liquid crystal reflection panel 213 and a quarter wavelength plate 214 are disposed on the other surface. A condenser lens 215 is disposed on one surface side of the first PBS 218, and a red liquid crystal reflection panel 217 and a quarter-wave plate 216 are disposed on the other surface. A condenser lens 220 is disposed on one surface side of the third PBS 223, and a green liquid crystal reflection panel 222 and a quarter-wave plate 221 are disposed on the other surface.

  The light source outputs three primary color lights, that is, blue light, green light, and red light as follows. For the red light, white light output from the main condenser lens 206 is reflected by the green-red reflection dichroic mirror 208, reflected by the total reflection mirror 209, passes through the green reflection dichroic mirror 211, and enters the condenser lens 215. For the green light, the white light output from the main condenser lens 206 is reflected by the green-red reflection dichroic mirror 208, reflected by the total reflection mirror 209, reflected by the green reflection dichroic mirror 211, and enters the condenser lens 212. As for the blue light, white light output from the main condenser lens 206 is reflected by the blue reflection dichroic mirror 207, reflected by the total reflection mirror 210, and incident on the condenser lens 220.

  The green light incident on the condenser lens 212 is reflected by the second PBS 219, passes through the quarter-wave plate 214, enters the green liquid crystal reflecting panel 213, and, when modulated there, passes through the second PBS 219 and passes through the cross prism. The light is incident on 224 and projected from the projection lens 225 onto a screen (not shown) positioned in front of the projection lens 225. The red light incident on the condenser lens 215 is reflected by the first PBS 218, passes through the quarter-wave plate 216, enters the liquid crystal reflective panel 217 for red, and when modulated there, passes through the first PBS 218 and passes through the first prism 218. The light is incident on 224 and projected from the projection lens 225 onto a screen (not shown) positioned in front of the projection lens 225. The green light incident on the condenser lens 220 is reflected by the third PBS 223, passes through the quarter-wave plate 221 and enters the green liquid crystal reflection panel 222. When modulated there, the green light passes through the third PBS 223 and passes through the cross prism. The light is incident on 224 and projected from the projection lens 225 onto a screen (not shown) positioned in front of the projection lens 225.

It is a schematic diagram which shows the thin-film transistor concerning a reference example. It is a schematic diagram which shows the thin-film transistor concerning another reference example. It is typical sectional drawing which shows embodiment of the thin-film transistor concerning this invention. FIG. 3 is a schematic plan view of a thin film transistor according to the present invention. It is a graph which shows the relationship between a LDD film thickness and a LDD impurity concentration. It is a graph which shows the relationship between LDD dose amount and leak current. It is process drawing which shows the manufacturing method of the display apparatus concerning this invention. It is a perspective view which shows an example of the display apparatus concerning this invention. It is a schematic diagram which shows the projector incorporating the display apparatus concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor thin film, 2 ... Gate insulating film, 3 ... Boundary, G ... Gate electrode, S ... Source region, D ... Drain region, LDD ... Low concentration impurity region , CH ... channel region

Claims (4)

A semiconductor thin film disposed on a substrate, a gate electrode, and an insulating film disposed between the semiconductor thin film and the gate electrode,
The semiconductor thin film is divided into an input side region and an output side region, and the thickness of the semiconductor thin film from the boundary to the output side region is at least partially compared to the thickness of the semiconductor thin film from the boundary to the input side region. It ’s thinner,
The thin film transistor characterized in that the gate electrode is arranged so as to extend over the boundary, and a portion of the semiconductor thin film overlapping the gate electrode becomes a channel region. The input region of the semiconductor thin film includes a conductive region in which impurities are implanted at a predetermined concentration, and a low-concentration impurity region between the conductive region and the channel region and having a lower impurity concentration than the conductive region. Divided,
The output side region of the semiconductor thin film is also divided into a conductive region and a low concentration impurity region, and the low concentration impurity region is formed in a portion where the thickness of the semiconductor thin film is reduced. 1. The thin film transistor according to 1.   3. The thin film transistor according to claim 2, wherein the low concentration impurity region in the output side region has a higher impurity concentration than the low concentration impurity region in the input side region. Row-shaped scanning lines, column-shaped signal lines, and pixels located at the intersections of the two are integrated on the substrate,
In the display device, the pixel includes an electro-optical element, and a thin film transistor that is connected to the scanning line and the signal line to drive the electro-optical element.
The thin film transistor comprises a semiconductor thin film, a gate electrode, and an insulating film disposed between the semiconductor thin film and the gate electrode,
The semiconductor thin film is divided into an input side region connected to the signal line and an output side region connected to the electro-optic element, and the boundary from the boundary to the output side region compared to the thickness of the semiconductor thin film in the input side region The thickness of the semiconductor thin film in
The display device is characterized in that the gate electrode is connected to the scanning line and arranged so as to cover the boundary, and a portion of the semiconductor thin film overlapping the gate electrode becomes a channel region.

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