JP2009200233A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technique for achieving size reduction by constituting an MEMS structure such that pressure and a vibration signal from an outside space can be directly received, and mounting facedown a semiconductor chip where the MEMS structure and an integrated circuit are formed on a module substrate with bump electrodes. <P>SOLUTION: The integrated circuit is formed on one surface of a semiconductor substrate 1, and the MEMS structure is formed on the other surface of the semiconductor substrate 1. Then the bump electrodes BP formed on the integrated circuit are used for flip-chip connections with a mounting substrate. At this time, a transducer can be disposed facing the outside space. Consequently, the transducer never loses a function of interacting directly with the outside space, and a semiconductor device can be made compact. Here, the integrated circuit and MEMS structure are electrically connected through electrodes 20a and 20b penetrating the substrate 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device that forms a micro electro mechanical system (MEMS) and a large scale integrated circuit (LSI).

Japanese Patent Laying-Open No. 2004-271312 (Patent Document 1) describes a semiconductor device formed by stacking a sensor chip and a circuit chip, and reduces parasitic capacitance in electrical connection between the sensor chip and the circuit chip. A technique capable of improving the degree of design freedom is described. Specifically, the sensor chip is connected to the circuit chip face down, and the electrode pads of the sensor chip and the electrode pads of the circuit chip are connected by bump electrodes. In the state of the multichip module in which the sensor chip and the circuit chip are connected as described above, the circuit chip is connected to the package. The electrical connection between the circuit chip and the package is made by connecting the electrode pads of the circuit chip and the electrode leads of the package with bump electrodes.
JP 2004-271312 A

  There is a technique in which a cavity is formed on the surface of a semiconductor substrate (for example, Si substrate) or an SOI (Silicon On Insulator) substrate by using a semiconductor manufacturing process technique, and a diaphragm film is formed so as to cover the cavity. And what measures the mechanical deformation | transformation of the diaphragm film | membrane by an external force as an electrical signal is a pressure sensor, a vibration sensor, and a sound wave sensor (microphone).

  In recent years, such a microphone has been adopted as a microphone for a mobile phone or a personal computer, or the pressure sensor described above has begun to be applied to altitude measurement in a small portable device.

  The microphone and the pressure sensor used here are a MEMS structure composed of a diaphragm film formed so as to cover the cavity and the cavity (hereinafter referred to as the diaphragm structure together with the cavity and the diaphragm film) and a signal processing signal. It is composed of an integrated circuit (LSI).

  For example, according to the diaphragm structure, the diaphragm film is deformed by vibrations such as external pressure or sound waves from the outside, and the deformation of the diaphragm film can be regarded as a displacement of the strain sensor or the capacitive electrode. Then, by processing the change in resistance value in the strain sensor and the change in capacitance of the capacitive element with an integrated circuit, it is possible to output external pressure and sonic vibration as electrical signals. In this way, microphones and pressure sensors are composed of diaphragm structures and integrated circuits. In the future, however, these microphones and pressure sensors are considered to be miniaturized, and the integration of diaphragm structures and integrated circuits will be promoted. Required.

  For example, in the technique described in Patent Document 1, a technique for forming a MEMS structure and an integrated circuit on separate semiconductor chips is disclosed. According to this technique, the electrical connection between the sensor chip forming the MEMS structure and the circuit chip forming the integrated circuit, and the electrical connection between the circuit chip and the package are connected by wire bonding. Instead, they are connected by bump electrodes.

  However, since the MEMS structure and the integrated circuit are formed in separate semiconductor chips, the MEMS cannot be sufficiently thinned, and there is a limit to downsizing the MEMS. Furthermore, since it is necessary to connect the sensor chip on which the MEMS structure is formed to the circuit chip and to electrically connect the circuit chip to the package, the size of the circuit chip is necessarily larger than the size of the sensor chip. Therefore, it is necessary to increase the size of the MEMS.

  Therefore, in order to realize the miniaturization of MEMS, a diaphragm structure is formed on an integrated circuit (LSI) formed on a semiconductor substrate using a process compatible with the LSI wiring process, and is small and highly sensitive. There is a technique for forming a simple MEMS. By laminating a MEMS structure (diaphragm structure) on an integrated circuit (LSI) as in this technology, the integrated circuit and the MEMS structure are configured by separate semiconductor chips, or the integrated circuit is placed beside the MEMS structure. The mounting area and chip area of the entire MEMS can be reduced as compared with the arrangement.

  However, when a semiconductor chip having a MEMS structure formed on an integrated circuit is used as a bare chip, connection terminals (pad electrodes) from the semiconductor chip to the outside and the MEMS structure are disposed on the same surface. For this reason, when a semiconductor chip is mounted on a module substrate (mounting substrate, wiring substrate), the electrical connection between the pad electrode and the wiring on the module substrate needs to be connected with a wire. That is, when a bump electrode is provided on a pad electrode of a bare chip (semiconductor chip) and the semiconductor chip is mounted face-down on the module substrate using the bump electrode in order to reduce the size of the MEMS, it is formed on the same surface as the bump electrode. The MEMS structure formed is opposed to the module substrate. Therefore, the surface of the MEMS structure does not face the external space, and vibration signals such as pressure and sound waves in the external space cannot be directly received. For this reason, after placing the semiconductor chip on the module substrate with the MEMS structure facing up, it is necessary to connect the pad electrode formed on the same surface as the MEMS structure and the wiring on the module substrate with wires. There is a limit to downsizing the mounting area of MEMS. Furthermore, the semiconductor chip cannot be processed together with other surface mount components.

  An object of the present invention is to configure a MEMS structure such as a microphone or a pressure sensor so that a pressure or vibration signal from an external space can be directly received, and to bump a semiconductor chip on which the MEMS structure and an integrated circuit are formed. The object is to provide a technology capable of realizing downsizing by face-down mounting on a module substrate with electrodes.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a representative embodiment includes a semiconductor chip, the semiconductor chip comprising: (a) a semiconductor substrate; (b) a semiconductor element formed on a first surface of the semiconductor substrate; A multilayer wiring layer formed on the semiconductor element; (d) a pad formed on the uppermost layer of the multilayer wiring layer; and (e) a bump electrode formed on the pad. Then, the semiconductor chip is mounted on the mounting substrate by connecting the bump electrodes to terminals formed on the mounting substrate. At this time, a transducer for converting an electrical signal and a physical quantity is formed on the second surface of the semiconductor substrate opposite to the first surface. The transducer includes: (f1) a first insulating film formed on the second surface of the semiconductor substrate; (f2) a second insulating film formed on the first insulating film; A cavity formed in the second insulating film; and (f4) a diaphragm film formed so as to cover the cavity. The transducer has a function of converting mechanical deformation of the diaphragm film due to an external force into an electric signal, and the multilayer wiring layer and the transducer are electrically connected by a through electrode penetrating the semiconductor substrate. It is what.

  According to the semiconductor device according to the representative embodiment configured as described above, the MEMS structure (transducer) is configured to be able to directly receive pressure and vibration signals from the external space, and the MEMS structure. And a semiconductor chip on which an integrated circuit is formed can be face-down mounted on a module substrate with bump electrodes.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the MEMS structure (transducer) can be configured to directly receive pressure and vibration signals from the external space, and the MEMS structure and the integrated circuit are formed. The semiconductor chip can be mounted face-down on the module substrate with bump electrodes. In other words, since the integrated circuit (LSI) and the MEMS structure (transducer) are formed on both the front and back sides of the semiconductor chip, it is possible to reduce the size of the semiconductor chip and the mounting area by mounting the semiconductor chip face down on the module substrate This can be realized without impairing input signals (pressure, vibration signal, etc.) to the MEMS structure (transducer).

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
The semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. In FIG. 1, the semiconductor device according to the first embodiment has a configuration including an integrated circuit and a MEMS structure (transducer), and an integrated circuit is formed on one surface of the semiconductor substrate, and the other surface of the semiconductor substrate. One of the features is that a MEMS structure is formed on the substrate.

  First, the configuration of the integrated circuit formed on one surface of the semiconductor substrate will be described. As shown in FIG. 1, an element isolation region 2 is formed on one surface of the semiconductor substrate 1 (the lower surface of the semiconductor substrate 1), and an n-channel type is formed in an active region partitioned by the element isolation region. A MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qn and a p-channel type MISFET Qp are formed. An interlayer insulating film 11 is formed so as to cover the n-channel MISFET Qn and the p-channel MISFET Qp, and a multilayer wiring is formed on the interlayer insulating film 11. Specifically, a first layer wiring L1 electrically connected to the n channel MISFET Qn or p channel MISFET Qp via a plug is formed, and the first layer wiring is formed above the first layer wiring L1 via a plug. A second layer wiring L2 electrically connected to L1 is formed. Further, a third layer wiring L3 is formed above the second layer wiring L2. In the first embodiment, a multilayer wiring composed of three layers is shown as an example of the multilayer wiring. However, the three-layered multilayer wiring is merely an example, and even if the number of layers of the multilayer wiring is more than this, the number is less than this. There may be. A pad PD is formed in the same layer as the third layer wiring L3, and a bump electrode BP serving as an external connection terminal is formed on the pad PD. As described above, an integrated circuit is formed on one surface of the semiconductor substrate 1 by a circuit element composed of an n-channel type MISFET Qn, a p-channel type MISFET Qp, and the like, and a multilayer wiring formed on the circuit element. Yes. As will be described later, this integrated circuit has a function of performing signal processing of electrical signals detected by the MEMS structure (transducer).

  Next, the structure of the MEMS structure (transducer) formed on the other surface of the semiconductor substrate 1 will be described. In the first embodiment, a transducer is formed as the MEMS structure. A transducer is an element having a function of mutually converting a physical quantity and an electric signal. For example, in the first embodiment, a pressure sensor that converts pressure into an electric signal will be described. However, the transducer described in the first embodiment is not limited to the pressure sensor, and can be applied to a microphone, a vibration sensor, or the like that mutually converts sound waves and electrical signals.

  As shown in FIG. 1, a MEMS structure is formed on the surface of the semiconductor substrate 1 opposite to the integrated circuit formation surface. The configuration of this MEMS structure will be described. In FIG. 1, an insulating film 16 is formed on the surface of the semiconductor substrate 1 opposite to the integrated circuit formation surface, and a lower electrode 23 is formed on the insulating film 16. An insulating film 24 is formed on the lower electrode 23 so as to cover the lower electrode 23, and a cavity 28 is formed in the insulating film 24. The cavity 28 is disposed on the lower electrode 23. An upper electrode 26 is formed on the insulating film 24 in which the cavity 28 is formed. A structure in which the cavity 28 and the upper electrode 26 are combined is a diaphragm structure, and the upper electrode 26 is sometimes called a diaphragm film. An insulating film 29 is formed on the upper electrode 26, and a passivation film 30 is formed on the insulating film 29. The pressure sensor (MEMS structure) in the first embodiment is configured as described above, and the pressure sensor and the integrated circuit described above are electrically connected by a through electrode penetrating the semiconductor substrate 1. Specifically, the lower electrode 23 of the pressure sensor and the third layer wiring L3 constituting the integrated circuit are connected by the through electrode 20b, and the third layer wiring L3 constituting the integrated circuit and the upper electrode 26 of the pressure sensor are connected to each other. They are connected by through electrodes 20a. The through electrodes 20a and 20b are formed by embedding a conductive material in the holes. In order to insulate the side surfaces of the through electrodes 20a and 20b from the semiconductor substrate 1, an insulating film is formed on the side surfaces of the holes. Yes.

  The semiconductor device according to the first embodiment is configured as described above, and the operation thereof will be described below. First, when pressure is applied from the external space, the upper electrode (diaphragm film) 26 constituting the pressure sensor (MEMS structure) is mechanically deformed. That is, since the cavity 28 is formed in the lower part of the upper electrode 26, when pressure is applied from above the upper electrode 26, the upper electrode 26 is deformed so as to bite into the cavity 28. For this reason, the distance between the upper electrode 26 and the lower electrode 23 via the cavity 28 changes. In the pressure sensor, a capacitive element is formed by the upper electrode 26 and the lower electrode 23. Therefore, when the distance between the upper electrode 26 and the lower electrode 23 changes, the capacitance of the capacitive element changes. This change in capacitance is transmitted to the integrated circuit by the through electrode 20a connected to the upper electrode 26 and the through electrode 20b connected to the lower electrode 23. In the integrated circuit, the capacitance change of the capacitive element is electrically signal-processed. Thereafter, the electrical signal processed by the integrated circuit is output to the external circuit via the bump electrode BP which is an external connection terminal. In this way, the semiconductor device according to the first embodiment operates. In other words, by converting a physical quantity called pressure into a capacitance change with a pressure sensor (MEMS structure) and electrically processing this capacitance change with an integrated circuit, an electrical signal corresponding to the pressure can be generated. The pressure can be detected. Since the deformation of the upper electrode 26 changes depending on the magnitude of the pressure applied from the external space, the deformation of the upper electrode 26 changes according to the magnitude of the pressure. From this, the distance between the upper electrode 26 and the lower electrode 23 varies depending on the magnitude of the pressure, so that the capacitance of the capacitive element varies depending on the magnitude of the pressure. Therefore, it is possible to know the pressure in the external space by detecting how much the change in capacitance has changed. Specifically, when the pressure is high, the deformation of the upper electrode 26 also increases, and as a result, the capacitance change of the capacitive element constituted by the upper electrode 26 and the lower electrode 23 also increases. On the other hand, when the pressure is small, the deformation of the upper electrode 26 is small, and as a result, the capacitance change of the capacitive element is small. In an integrated circuit, for example, by converting a capacitance change as a voltage value, the magnitude of pressure can be output as the magnitude of the voltage value.

  Thus, a pressure sensor (transducer) formed on a semiconductor substrate requires a MEMS structure that detects pressure as a change in capacitance and an integrated circuit that electrically processes the change in capacitance. At this time, it is conceivable to form the MEMS structure and the integrated circuit on separate semiconductor chips. However, when the MEMS structure and the integrated circuit are formed on separate semiconductor chips, there is a problem that the size of the pressure sensor increases. In recent years, there is an increasing demand for miniaturization of the pressure sensor formed on the semiconductor substrate, and a device for realizing miniaturization of the pressure sensor is required.

  Therefore, it is conceivable to form the MEMS structure and the integrated circuit on the same semiconductor substrate. For example, a structure in which an integrated circuit is formed on a semiconductor substrate and a MEMS structure is formed on the integrated circuit has been studied. According to this structure, the size can be reduced as compared with the case where the MEMS structure and the integrated circuit are formed on separate semiconductor chips. However, there is a limit to the size reduction in this structure, and the pressure sensor is further reduced in size. Is required. That is, when the MEMS structure is formed on the integrated circuit, the bump structure cannot be used for the connection from the integrated circuit to the external circuit because the MEMS structure needs to be arranged toward the external space. It is necessary to make a connection. This is because the integrated circuit and the MEMS structure are formed on the same side of the semiconductor substrate, so that when the bump circuit is used when connecting the integrated circuit and the mounting substrate (interposer, wiring substrate), the integrated circuit of the semiconductor substrate This is because the formation surface adheres to the mounting substrate. That is, a MEMS structure is formed on the integrated circuit formation surface of the semiconductor substrate, and the MEMS structure is disposed so as to be sandwiched between the semiconductor substrate and the mounting substrate. Therefore, the MEMS structure is not arranged toward the external space, and the pressure from the external space cannot be detected by the MEMS structure. Therefore, in the structure in which the MEMS structure is formed on the integrated circuit, it is necessary to mount the semiconductor substrate on the mounting substrate with the integrated circuit formation surface (MEMS structure formation surface) of the semiconductor substrate facing upward. In this structure, the integrated circuit formed on the semiconductor substrate and the wiring of the mounting substrate are connected by wires.

  In this case, it is necessary to secure the space for the external connection terminals by making the planar size of the integrated circuit larger than the planar size of the MEMS structure. That is, by making the planar size of the integrated circuit larger than the planar size of the MEMS structure, the pad of the integrated circuit and the wiring of the mounting substrate are connected by a wire in a region outside the MEMS structure. It will be. For this reason, in this structure, the size of the integrated circuit must be larger than that of the MEMS structure. Therefore, even if the MEMS structure is downsized, the semiconductor device including the integrated circuit can be downsized as a whole. However, there is a limit, and further downsizing cannot be realized.

  Therefore, a structure as shown in FIG. 1 is proposed for the semiconductor device according to the first embodiment. That is, as shown in FIG. 1, an integrated circuit is formed on one surface of a semiconductor substrate 1, while a MEMS structure is formed on the other surface of the semiconductor substrate 1. In this manner, by forming the integrated circuit and the MEMS structure using both surfaces of the semiconductor substrate 1, it is possible to promote downsizing of the semiconductor device including the MEMS structure and the integrated circuit. The reason for this will be described. First, as shown in FIG. 1, a pad PD is formed on the uppermost layer (third layer) of the multilayer wiring constituting the integrated circuit, and a bump electrode BP is formed on the pad PD. In the first embodiment, the bump electrode BP is used to electrically connect the semiconductor substrate (semiconductor chip) 1 and the mounting substrate.

  FIG. 2 is a cross-sectional view showing a state where the semiconductor device shown in FIG. 1 is connected to a mounting substrate. As shown in FIG. 2, the wiring 35 formed on the mounting substrate 34 and the integrated circuit are electrically connected by the bump electrode BP formed on the integrated circuit. At this time, since the integrated circuit formed on the semiconductor substrate 1 is disposed so as to face the mounting substrate 34, the MEMS structure formed on the opposite side of the integrated circuit is disposed so as to face upward. That is, the MEMS structure is arranged toward the external space. Therefore, the MEMS structure can detect the pressure in the external space.

  As described above, in the first embodiment, the integrated circuit is formed on one surface of the semiconductor substrate 1 and the MEMS structure is formed on the other surface of the semiconductor substrate 1. When the circuit is face-down connected by the bump electrode BP, the MEMS structure is arranged toward the external space. That is, in the semiconductor device according to the first embodiment, even if the integrated circuit and the mounting substrate 34 are face-down connected by the bump electrode BP, the MEMS structure can be arranged facing the external space. This means that the size can be reduced as compared with the case where the integrated circuit is connected to the mounting substrate 34 with a wire. Specifically, in the structure shown in FIG. 1, it is not necessary to make the planar size of the integrated circuit larger than the planar size of the MEMS structure. For example, as described above, when the integrated circuit and the MEMS structure are formed on the same side of the semiconductor substrate and the MEMS structure is disposed on the integrated circuit, the planar size of the integrated circuit is set to It is necessary to make the size larger than the planar size and connect the pads on the integrated circuit and the wiring of the mounting board with wires. On the other hand, in the first embodiment, the integrated circuit is formed on one surface of the semiconductor substrate 1, while the MEMS structure is formed on the other surface of the semiconductor substrate 1, and the integrated circuit and the mounting substrate are formed. 34 is face-down connected by a bump electrode BP. That is, since the MEMS structure is not arranged on the same side as the integrated circuit, the integrated circuit can be formed regardless of the size of the MEMS structure. That is, it is not necessary to make the planar size of the integrated circuit larger than the planar size of the MEMS structure. Accordingly, the planar size of the integrated circuit can be made the same as or smaller than that of the MEMS structure, and thus the miniaturization of the semiconductor device including the integrated circuit and the MEMS structure can be promoted.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. First, as shown in FIG. 3, a MISFET is formed on the semiconductor substrate 1. In FIG. 3, the semiconductor substrate 1 is shown enlarged. A process of forming the MISFET shown in FIG. 3 will be described.

  The semiconductor substrate 1 is in a state of a semiconductor wafer having a substantially disk shape. Then, an element isolation region 2 for isolating elements is formed in the CMISFET formation region of the semiconductor substrate 1. The element isolation region 2 is provided in order to prevent the elements from interfering with each other. The element isolation region 2 can be formed using, for example, a LOCOS (local Oxidation of silicon) method or an STI (shallow trench isolation) method.

  Next, impurities are introduced into the active region isolated in the element isolation region 2 to form a well. For example, the p-type well 3 is formed in the n-channel MISFET formation region in the active region, and the n-type well 4 is formed in the p-channel MISFET formation region. The p-type well 3 is formed by introducing a p-type impurity such as boron into the semiconductor substrate 1 by ion implantation. Similarly, the n-type well 4 is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate 1 by ion implantation.

  Subsequently, channel forming semiconductor regions (not shown) are formed in the surface region of the p-type well 3 and the surface region of the n-type well 4. This channel forming semiconductor region is formed to adjust the threshold voltage for forming the channel.

  Next, a gate insulating film 5 is formed on the semiconductor substrate 1. The gate insulating film 5 is formed of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating film 5 is not limited to a silicon oxide film and can be variously changed. For example, the gate insulating film 5 is formed of a high dielectric constant film such as a silicon oxynitride film (SiON) or hafnium oxide. May be.

  Subsequently, a polysilicon film is formed on the gate insulating film 5. The polysilicon film can be formed using, for example, a CVD method. Then, n-type impurities such as phosphorus and arsenic are introduced into the polysilicon film formed in the n-channel type MISFET formation region by using a photolithography technique and an ion implantation method. Similarly, a p-type impurity such as boron is introduced into the polysilicon film formed in the p-channel MISFET formation region.

  Next, the polysilicon film is processed by etching using the patterned resist film as a mask to form the gate electrode 6a in the n-channel MISFET formation region and the gate electrode 6b in the p-channel MISFET formation region.

  Here, an n-type impurity is introduced into the polysilicon film in the gate electrode 6a in the n-channel type MISFET formation region. Therefore, the work function value of the gate electrode 6a can be set to a value in the vicinity of the conduction band of silicon (4.15 eV), so that the threshold voltage of the n-channel MISFET can be reduced. On the other hand, a p-type impurity is introduced into the polysilicon film in the gate electrode 6b in the p-channel type MISFET formation region. For this reason, since the work function value of the gate electrode 6b can be set to a value in the vicinity of the valence band of silicon (5.15 eV), the threshold voltage of the p-channel MISFET can be reduced. Thus, in the first embodiment, the threshold voltage can be reduced in both the n-channel MISFET and the p-channel MISFET (dual gate structure).

  Subsequently, by using a photolithography technique and an ion implantation method, a shallow n-type impurity diffusion region 7 aligned with the gate electrode 6a in the n-channel MISFET formation region is formed. The shallow n-type impurity diffusion region 7 is a semiconductor region. Similarly, a shallow p-type impurity diffusion region 8 is formed in the p-channel type MISFET formation region. The shallow p-type impurity diffusion region 8 is formed in alignment with the gate electrode 6b in the p-channel MISFET formation region. This shallow p-type impurity diffusion region 8 can be formed by using a photolithography technique and an ion implantation method.

  Next, a silicon oxide film is formed on the semiconductor substrate 1. The silicon oxide film can be formed using, for example, a CVD method. Then, the silicon oxide film is anisotropically etched to form side walls 9 on the side walls of the gate electrodes 6a and 6b. Although the sidewall 9 is formed from a single layer film of a silicon oxide film, the present invention is not limited to this. For example, a sidewall formed of a laminated film of a silicon nitride film and a silicon oxide film may be formed.

  Subsequently, a deep n-type impurity diffusion region 10a aligned with the sidewall 9 is formed in the n-channel MISFET formation region by using a photolithography technique and an ion implantation method. The deep n-type impurity diffusion region 10a is a semiconductor region. The deep n-type impurity diffusion region 10a and the shallow n-type impurity diffusion region 7 form a source region. Similarly, a drain region is formed by the deep n-type impurity diffusion region 10 a and the shallow n-type impurity diffusion region 7. Thus, by forming the source region and the drain region with the shallow n-type impurity diffusion region 7 and the deep n-type impurity diffusion region 10a, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  Similarly, a deep p-type impurity diffusion region 10b aligned with the sidewall 9 is formed in the p-channel MISFET formation region. The deep p-type impurity diffusion region 10b and the shallow p-type impurity diffusion region 8 form a source region and a drain region. Therefore, the source region and the drain region also have an LDD structure in the p-channel type MISFET.

  After forming the deep n-type impurity diffusion region 10a and the deep p-type impurity diffusion region 10b in this manner, a heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  In the first embodiment, the gate electrodes 6a and 6b are formed by using polysilicon and impurity regions in which the source and drain regions (diffusion regions) are formed in silicon. However, titanium, cobalt, and nickel films are deposited on the respective surfaces. The resistance of the gate electrodes 6a and 6b and the diffusion region can be reduced by silicidation by heat treatment. In this way, the n-channel MISFET Qn and the p-channel MISFET Qp shown in FIG. 3 can be formed on the semiconductor substrate 1.

  Next, as shown in FIG. 4, an interlayer insulating film 11 is formed so as to cover the n-channel MISFET Qn and the p-channel MISFET Qp. Then, the surface of the interlayer insulating film 11 is planarized by, for example, chemical mechanical polishing (CMP). The interlayer insulating film 11 is formed of, for example, a silicon oxide film, and can be formed by, for example, a CVD method (Chemical Vapor Deposition).

  Subsequently, as shown in FIG. 5, a plug PLG1 that penetrates the interlayer insulating film 11 and reaches the source region and drain region of the n-channel type MISFET Qn and the source region and drain region of the p-channel type MISFET Qp is formed. Although not shown in FIG. 5, a plug reaching the gate electrode of the n-channel MISFET Qn or the gate electrode of the p-channel MISFET Qp is also formed. Thereafter, a first layer wiring L1 is formed on the interlayer insulating film 11 on which the plug PLG1 is formed. The plug PLG1 is formed, for example, by embedding a tungsten film, and the first layer wiring L1 is formed from aluminum or a laminated film of aluminum, titanium, and titanium nitride.

  Next, as shown in FIG. 6, an interlayer insulating film 11 is formed so as to cover the first layer wiring L <b> 1, and a plug PLG <b> 2 is formed in the interlayer insulating film 11. The plug PLG2 is formed so as to be connected to the first layer wiring L1. Then, the second layer wiring L2 is formed on the interlayer insulating film 11 on which the plug PLG2 is formed, and the interlayer insulating film 11 is formed so as to cover the second layer wiring L2. Thereafter, the surface of the interlayer insulating film 11 is planarized by, for example, a CMP method. At this time, it is desirable that the surface of the interlayer insulating film 11 be a material having high CMP resistance such as a silicon nitride film or a film that suppresses copper diffusion in the subsequent process.

  Subsequently, as shown in FIG. 7, a plug PLG 3 is formed in the interlayer insulating film 11. The plug PLG3 is formed so as to be connected to the second layer wiring L2. Then, a resist film 12 is applied to the surface of the interlayer insulating film 11 on which the plug PLG3 is formed. Thereafter, the applied resist film 12 is subjected to patterning by exposure and development. The patterning of the resist film 12 is performed so that the opening 12a is formed in the through electrode formation region.

  Next, as shown in FIG. 8, the interlayer insulating film 11, the element isolation region 2, and a part of the semiconductor substrate 1 are etched using the resist film 12 having the opening 12 a as a mask. Thereby, the groove | channel 13 used as a through-hole can be formed. Thereafter, the patterned resist film 12 is removed, and the semiconductor substrate 1 is washed.

  Subsequently, as shown in FIG. 9, a silicon oxide film 14 is formed on the interlayer insulating film 11 including the inside of the trench 13. This silicon oxide film 14 can be formed by, for example, a plasma CVD method. Then, the silicon oxide film 14 is etched back. Thereby, the silicon oxide film 14 existing on the interlayer insulating film 11 and on the bottom of the trench 13 is removed, while the silicon oxide film 14 can be left only on the side surface of the trench 13. Thereafter, a metal film 15 that fills the inside of the groove 13 is formed. In the first embodiment, for example, as the metal film 15 for embedding the trench 13, first, a tantalum film (Ta film) and a copper film (Cu film) to be a seed layer are formed by sputtering and then plated. The copper film is embedded in the groove 13.

  Next, as shown in FIG. 10, the unnecessary metal film 15 formed on the interlayer insulating film 11 is removed. The unnecessary copper film constituting the metal film 15 is removed by a CMP method, and the tantalum film formed under the copper film is removed with a fluorine-based plasma gas. As a result, the metal film 15 formed on the interlayer insulating film 11 is removed, and the metal film 15 is buried only in the trench 13.

  Thereafter, as shown in FIG. 11, a third layer wiring L3 is formed. For example, for the third layer wiring L3, a titanium nitride film / aluminum film / titanium nitride film is formed as a laminated film on the interlayer insulating film 11 by sputtering, and a photolithography technique and an etching technique are used for this laminated film. Is formed. At this time, the pad PD is also formed in the same layer as the third layer wiring L3. Then, a passivation film is formed so as to cover the third layer wiring L3 and the pad PD. In FIG. 11, the passivation film is also described as the interlayer insulating film 11. A part of the third layer wiring L3 covers the upper part of the groove 13 in which the metal film 15 is embedded.

  In the first embodiment, as shown in FIG. 10, when the unnecessary metal film 15 formed on the interlayer insulating film 11 is removed, the copper film and the tantalum film formed under the copper film are also removed. However, from the formation of the third layer wiring L3 to the processing may be performed with the tantalum film formed in the lower layer of the copper film remaining.

  An integrated circuit can be formed on the semiconductor substrate 1 through the steps so far. The steps so far are obtained by adding a step of forming a through-electrode groove 13 and a step of embedding the metal film 15 in the groove 13 to a general integrated circuit manufacturing process.

  Next, a manufacturing process for forming the MEMS structure on the surface of the semiconductor substrate 1 opposite to the surface on which the integrated circuit is formed will be described with reference to the drawings.

  First, as shown in FIG. 12, the surface (back surface) opposite to the surface on which the integrated circuit is formed of the semiconductor substrate 1 is washed, and then the insulating film 16 is formed. The insulating film 16 can be formed from, for example, a silicon nitride film. In the first embodiment, the insulating film 16 is formed after the film formed on the back surface is removed by the process before the insulating film 16 is formed to expose the semiconductor substrate 1. At this time, a polishing process may be performed on the back surface of the semiconductor substrate 1.

  Next, as shown in FIG. 13, a patterned resist film (not shown) is formed using a photolithography technique. The patterning of the resist film is performed so as to open the through electrode formation region. Then, the insulating film 16 and a part of the semiconductor substrate 1 are etched using the patterned resist film as a mask. Thereby, a groove 17 connected to the groove 13 is formed.

  Then, as shown in FIG. 14, a silicon oxide film 18 is formed on the insulating film 16 including the inside of the trench 17. This silicon oxide film 18 can be formed by, for example, a plasma CVD method. Then, the silicon oxide film 18 is etched back. Thereby, the silicon oxide film 18 existing on the insulating film 16 and at the bottom of the groove 17 is removed, while the silicon oxide film 18 can be left only on the side surface of the groove 17. 13 to 14, the diameters of the groove 13 and the groove 17 are the same size. However, when the diameter of the groove 13 is changed to the diameter of the groove 17 to increase the alignment margin of photolithography, After the silicon oxide film 14 is formed, a silicon nitride film is stacked, the metal film 15 is embedded without etching back, and the metal film 15 is formed only inside the trench 13 by CMP, and then oxidized with the aforementioned silicon nitride film. It is preferable to remove the silicon film 14 so that the insulating film (silicon nitride film and silicon oxide film 14) remains at the bottom of the trench 13. Thereafter, after opening the diameter of the groove 17 smaller than the diameter of the groove 13, the insulating film (silicon nitride film and silicon oxide film 14) at the connection portion is removed, and the silicon oxide film 18 is formed on the sidewall of the groove 17. The surfaces of the grooves 13 and 17 can be covered with an insulating film with respect to the semiconductor substrate 1.

  Subsequently, as shown in FIG. 15, a metal film 19 filling the inside of the groove 17 is formed. In the first embodiment, for example, as the metal film 19 that fills the groove 17, first, a tantalum film (Ta film) and a copper film (Cu film) that becomes a seed layer are formed by sputtering and then plated. Thus, the copper film is embedded in the groove 17.

  Thereafter, as shown in FIG. 16, the unnecessary metal film 19 formed on the insulating film 16 is removed. The unnecessary copper film constituting the metal film 19 is removed by a CMP method, and the tantalum film formed under the copper film is removed by a fluorine-based plasma gas. As a result, the metal film 19 formed on the insulating film 16 is removed, and the metal film 19 is buried only in the trench 17. Through the above steps, the through electrodes 20a and 20b are formed. In the first embodiment, a part of the through electrode (groove 13) is formed in the integrated circuit forming process, and then a part of the through electrode (groove 17) is formed in the manufacturing process of the MEMS structure. All of the through electrodes 20a and 20b may be formed in the process of forming the integrated circuit, or all of the through electrodes 20a and 20b may be formed in the process of forming the MEMS structure.

  Next, as shown in FIG. 17, a conductor film 21 is formed on the insulating film 16 including the through electrodes 20a and 20b. The conductor film 21 can be formed from, for example, a tungsten (W) film. The conductor film 21 is a film that becomes the lower electrode of the MEMS structure, and is connected to the through electrode 20b, but is insulated from the through electrode 20a that is connected to the upper electrode in a subsequent process. Therefore, by patterning the conductor film 21, the conductor film 21 is connected to the through electrode 20b, while the conductor film 21 on the through electrode 20a is removed. At this time, in order to protect the surface of the through electrode 20a, as shown in FIG. 18, an insulating film 22 is formed on the insulating film 16 including the through electrodes 20a and 20b, and the insulating film 22 reaches the through electrode 20b. The conductor film 21 may be formed on the insulating film 22 after the opening is formed. More desirably, the surface of the through electrode 20a may be protected with a metal layer or the like. Thereby, when forming a lower electrode, the surface of the penetration electrode 20a can be protected. However, in this Embodiment 1, in order to simplify a process, it is set as the structure shown in FIG.

Subsequently, as shown in FIG. 19, the lower electrode 23 is formed by patterning the conductor film 21 by using a photolithography technique and an etching technique. The lower electrode 23 is patterned so as to be connected to the through electrode 20b. At this time, since the conductor film 21 formed on the through electrode 20a is removed by etching, care must be taken so that the surface of the through electrode 20a is not altered. Specifically, since the material in which the through electrode 20a is embedded is a copper film, the material of the conductor film 21 and the conductor film 21 are formed so that the surface of the copper film does not change in the formation process of the lower electrode 23. Care must be taken with the combination of etching gases used for dry etching. In the first embodiment, a tungsten film is used as the conductor film 21 so that the surface of the through electrode 20a formed of a copper film is not altered, and NF ₃ gas is used for processing the tungsten film.

In the first embodiment, the lower electrode 23 is formed only in the portion connected to the through electrode 20b, but at the same time, a conductive film electrically separated from the through electrode 20b is used to protect the surface of the through electrode 20a. It can also arrange so that penetration electrode 20a may be covered. In this case, since the surface of the through electrode 20a is not exposed to an etching atmosphere, to be able to use a gas that alter the copper like SF ₆ as an etching gas, the upper electrode and the through electrode of the MEMS in a step described later Although conduction with 20a is made, the reliability with respect to this conduction can be increased. On the other hand, since a step is generated by the conductor film covering the through electrode 20a, it is necessary to consider that over-etching is increased due to the step when the upper electrode is processed.

  Next, as shown in FIG. 20, an insulating film 24 is formed on the insulating film 16 including the lower electrode 23. The insulating film 24 is formed from, for example, a silicon oxide film. Then, as shown in FIG. 21, by using a photolithography technique and an etching technique, an opening reaching the through electrode 20a is formed in the insulating film 24, and then the conductor film 25 is formed on the insulating film 24 including the inside of the opening. Form. The conductor film 25 is electrically connected to the through electrode 20a existing in the opening. The conductor film 25 is formed from, for example, a tungsten silicide film. In the first embodiment, an upper electrode (diaphragm film) is formed by patterning the conductor film 25. When this conductor film 25 is formed, fluctuations in the impurity profile of the source region and drain region of the MISFET (n-channel type MISFET Qn, p-channel type MISFET Qp) formed in the previous integrated circuit formation step and alteration of the through electrodes 20a and 20b are caused. In order to suppress this, it is desirable to suppress the film forming temperature to 500 ° C. or lower. For this reason, it is desirable to use a sputtering method for forming the conductor film 25 made of a tungsten silicide film. In addition to the tungsten silicide film, a material such as tungsten, molybdenum (Mo), molybdenum silicide, or titanium silicide is desirable as the conductor film 25.

  Subsequently, as shown in FIG. 22, the upper electrode (diaphragm film) 26 is formed by patterning the conductor film 25. At this time, a plurality of etching holes 27 for forming a cavity are formed in the upper electrode 26. Then, as shown in FIG. 23, the cavity 28 is formed by removing the insulating film 24 between the upper electrode 26 and the lower electrode 23 by wet etching using the etching hole 27 formed in the upper electrode 26. To do. Thereby, the diaphragm structure in which the upper electrode 26 can be mechanically deformed can be formed. Although wet etching is used to form the cavity 28, the periphery of the upper electrode 26 is protected with a resist film in order to prevent the insulating film 24 in the periphery of the upper electrode 26 from being etched. is doing.

  Thereafter, as shown in FIG. 24, after removing the resist film, an insulating film 29 and a passivation film 30 are laminated and formed on the insulating film 24 including the upper electrode 26. As a result, the etching hole 27 formed in the upper electrode 26 is closed by the insulating film 29, and the cavity 28 is hermetically sealed. When forming the insulating film 29, the etching hole 27 is formed small so that the cavity 28 is not filled, and a gap (thickness of the insulating film 24) between the upper electrode 26 and the lower electrode 23 is set to a predetermined value. Design to be spaced. In the first embodiment, a TEOS (tetraethyl orthosilicate) film is isotropically formed as the insulating film 29. For this reason, the insulating film 29 wraps around inside the cavity 28, but the interior of the cavity 28 is designed not to be completely embedded. Further, by forming a silicon nitride film on the surface of the passivation film 30, it is possible to suppress the alteration of the TEOS film due to external humidity or the like. An organic film 31 is formed on the passivation film 30 in order to protect the surface of the MEMS structure. As described above, a MEMS structure including a capacitive element including the lower electrode 23 and the upper electrode 26 and a cavity portion 28 provided between the lower electrode 23 and the upper electrode 26 can be formed.

  Subsequently, a process of forming a bump electrode which is an external connection terminal on the integrated circuit will be described. As shown in FIG. 25, a photosensitive polyimide film 32 is formed on the interlayer insulating film 11 (here, a passivation film) on which the integrated circuit is formed. Then, an opening 32 a is formed in the photosensitive polyimide film 32 by using a photolithography technique. The opening 32a is formed in the upper part of the pad PD.

  Next, as shown in FIG. 26, an opening 33 is formed in the interlayer insulating film 11 (passivation film) exposed from the opening 32 a formed in the photosensitive polyimide film 32. The opening 33 exposes the surface of the pad PD. Then, as shown in FIG. 27, after applying flux on the pad PD, the bump electrode BP is disposed. Subsequently, after the semiconductor substrate 1 is subjected to a reflow process, the organic film 31 protecting the surface of the MEMS structure is peeled off to form the semiconductor device according to the first embodiment shown in FIG. can do.

  In the first embodiment, an integrated circuit is formed on one surface of the semiconductor substrate 1, while a MEMS structure is formed on the other surface of the semiconductor substrate 1, and the integrated circuit and the mounting substrate 34 are bumped. The electrode BP has a face-down connection structure. That is, since the MEMS structure is not arranged on the same side as the integrated circuit, the integrated circuit can be formed regardless of the size of the MEMS structure. In other words, the planar size of the integrated circuit does not need to be larger than the planar size of the MEMS structure, and the planar size of the integrated circuit can be the same as or smaller than that of the MEMS structure. Therefore, the semiconductor device including the integrated circuit and the MEMS structure can be downsized.

(Embodiment 2)
In the first embodiment, an example in which an integrated circuit is formed on one surface of a normal semiconductor substrate and a capacitance detection type MEMS structure (diaphragm structure) is formed on the other surface has been described. In the second embodiment, an example in which an integrated circuit is formed on one surface of an SOI (Silicon On Insulator) substrate and a resistance change type MEMS structure (diaphragm structure) is formed on the other surface will be described.

  FIG. 28 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. As shown in FIG. 28, an SOI substrate is used as the semiconductor substrate. Specifically, the SOI substrate includes a substrate layer 40, a buried insulating layer 41 formed on the substrate layer 40, and a silicon layer 42 formed on the buried insulating layer 41. Both the substrate layer 40 and the silicon layer 42 are layers mainly composed of silicon, but the thickness of the substrate layer 40 is sufficiently thicker than the thickness of the silicon layer 42. Normally, in an SOI substrate, an integrated circuit is formed on a thin silicon layer 42. However, in the second embodiment, since the thin silicon layer 42 is used to form the diaphragm film of the MEMS structure, An integrated circuit is formed on the thick substrate layer 40. That is, as shown in FIG. 28, an integrated circuit is formed on the substrate layer 40. This integrated circuit has the same structure as that of the first embodiment. Specifically, the element isolation region 2 is formed in the substrate layer 40, and the n-channel MISFET Qn and the p-channel MISFET Qp are formed in the active region isolated by the element isolation region 2. An interlayer insulating film 11 is formed so as to cover the n-channel type MISFET Qn and the p-channel type MISFET Qp, and a multilayer wiring is formed in the interlayer insulating film 11. Specifically, also in the second embodiment, three layers of multilayer wiring are formed. A third layer wiring L3 is formed as the uppermost layer wiring, and a pad PD is formed in the same layer as the third layer wiring L3. An opening is formed on the pad PD, and a bump electrode BP which is an external connection terminal is formed. The above is the configuration of the integrated circuit in Embodiment 2.

  Next, the configuration of the MEMS structure according to the second embodiment will be described. As shown in FIG. 28, the MEMS structure according to the second embodiment is formed in the silicon layer 42. That is, the thin silicon layer 42 is a diaphragm film, and a cavity 44 is formed below the film. That is, the cavity 44 is formed by removing the buried insulating layer 41. Here, impurities are introduced into the silicon layer 42 to form diffusion resistors (strain sensors) 43a and diffusion resistors 43b. The diffusion resistor 43a is electrically connected to the integrated circuit through the through electrode 20a, and the diffusion resistor 43b is electrically connected to the integrated circuit through the through electrode 20b. The silicon layer 42 is provided with an etching hole 45, and by performing wet etching from the etching hole 45, a cavity 44 can be formed in the buried insulating layer 41 formed under the silicon layer 42. ing. Finally, the etching hole 45 formed in the silicon layer 42 is sealed with a sealing film 46.

  At this time, the diffusion resistance (strain sensor) 43 a is arranged on the cavity 44, and the diffusion resistance 43 b is arranged on the buried insulating layer 41 that is not the cavity 44. ing. Here, the planar configuration of the MEMS structure will be described. FIG. 29 is a plan view seen from the MEMS structure side shown in FIG. A cross section taken along line AA in FIG. 29 corresponds to FIG. As shown in FIG. 29, an etching hole 45 is provided in the silicon layer 42, and a cavity 44 is formed below the etching hole 45. On the other hand, in the silicon layer 42, a diffusion resistor 43a, a diffusion resistor 43b, a diffusion resistor 43c, and a diffusion resistor 43d are formed. Of these diffused resistors, only the diffused resistor 43 a is formed on the cavity 44. Therefore, the diffusion resistor 43a is distorted toward the cavity 44 when subjected to vibrations such as pressure and sound waves. When subjected to such distortion, the resistance value of the diffused resistor 43a changes. On the other hand, the diffused resistors 43 b to 43 d are formed on the buried insulating layer and are not formed on the cavity 44. For this reason, even if an external force such as pressure or sound wave is applied, the diffusion resistors 43b to 43d are not distorted and the resistance value does not change. Therefore, by forming a Wheatstone bridge with these four diffusion resistors 43a to 43d, pressure and sound waves can be converted into electric signals. Hereinafter, this operation will be described.

First, in FIG. 29, it is assumed that pressure is applied from the upper side of the drawing. Then, the diffused resistor 43 a is distorted inward of the cavity 44 because the lower layer is the cavity 44. When the diaphragm film constituting the diffusion resistor 43a is distorted, the resistance value changes. On the other hand, the diffusion resistors 43b to 43d are not distorted even when subjected to pressure because the lower layer is not the hollow portion 44. Therefore, the resistance values of the diffusion resistors 43b to 43d do not change. For this reason, when the Wheatstone bridge is configured by the diffusion resistors 43a to 43d, the resistance value of one diffusion resistor 43a changes, so that a current caused by the resistance change flows. By reading out this change in resistance value with an integrated circuit constituting the Wheatstone bridge, an electrical signal due to pressure can be taken out. In particular, since the distortion of the diffused resistor 43a also changes depending on the magnitude of pressure, the change in resistance value also changes according to the magnitude of pressure. This indicates that the pressure can be detected as an electrical signal. By the above operation, it can be seen that the semiconductor device according to the second embodiment can detect pressure and sound waves.

  Also in the second embodiment, an integrated circuit is formed on one surface of the SOI substrate while a MEMS structure is formed on the other surface of the SOI substrate, and the integrated circuit and the mounting substrate are formed by bump electrodes BP. It is structured to be connected face down. That is, since the MEMS structure is not arranged on the same side as the integrated circuit, the integrated circuit can be formed regardless of the size of the MEMS structure. In other words, the planar size of the integrated circuit does not need to be larger than the planar size of the MEMS structure, and the planar size of the integrated circuit can be the same as or smaller than that of the MEMS structure. Therefore, the semiconductor device including the integrated circuit and the MEMS structure can be downsized.

  Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to the drawings. First, as shown in FIG. 30, an SOI substrate including a substrate layer 40, a buried insulating layer 41, and a silicon layer 42 is prepared. Then, an impurity is introduced into the silicon layer 42 using an ion implantation method, thereby forming a diffusion resistor 43a and a diffusion resistor 43b. At this time, after introducing impurities by ion implantation, heat treatment is performed to activate the impurities introduced into the silicon layer 42.

  Next, an integrated circuit is formed on the surface of the substrate layer 40. Specifically, after the n-channel MISFET Qn and the p-channel MISFET Qp are formed on the substrate layer 40, a multilayer wiring is formed on the n-channel MISFET Qn and the p-channel MISFET Qp. Through electrodes 20a and 20b are formed in the step of forming the multilayer wiring. Here, the heat treatment for the diffusion resistors 43a and 43b formed in the silicon layer 42 may be performed by the heat treatment for forming the source region and drain region of the n-channel type MISFET Qn and the source region and drain region of the p-channel type MISFET Qp. Good.

  In the first embodiment, the through electrodes 20a and 20b are formed by using both the integrated circuit formation process and the MEMS structure formation process. In the second embodiment, the substrate layer is formed in the integrated circuit formation process. Through-electrodes 20 a and 20 b are formed from 40. In FIG. 30, the through electrodes 20 a and 20 b connected to the third layer wiring L <b> 3 penetrate the substrate layer 40 and the buried insulating layer 41 and reach the silicon layer 42.

  Subsequently, as shown in FIG. 28, a plurality of etching holes 45 are formed in the silicon layer 42, and a part of the buried insulating layer 41 is removed by wet etching using the etching holes 45. As a result, the cavity 44 is formed in the buried insulating layer 41. Thereafter, a sealing film 46 is formed on the silicon layer 42 so as to close the etching hole 45. The etching hole 45 is closed by the sealing film 46, and the cavity 44 is hermetically sealed. As the sealing film 46, a TEOS film can be used as in the first embodiment. However, since the TEOS film easily changes in film quality due to moisture in the atmosphere, a silicon nitride film is formed on the TEOS film. May be laminated. Further, an organic film such as a polyimide film may be formed instead of the TEOS film.

  Thereafter, an opening for opening the pad PD formed on the substrate layer 40 is formed, and the bump electrode BP is disposed in the opening, whereby the semiconductor device according to the second embodiment can be manufactured.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  According to the embodiment, a transducer (for example, a pressure sensor or a microphone) using a surface micromachining technique or a bulk micromachining technique and an integrated circuit can be formed on both surfaces of one semiconductor chip, so that the size can be reduced. According to the semiconductor device in which the transducer and the integrated circuit are integrated, when the semiconductor device is mounted on the mounting substrate, the semiconductor device is flip-chip connected by the bump electrode formed on the integrated circuit side so that the transducer is brought into the external space. Can be placed in a facing state. For this reason, the semiconductor device can be reduced in size without impairing the function of the transducer directly interacting with the external space.

  In the first embodiment, the capacitance detection type transducer is described as an example of the MEMS structure. However, the case where the resistance change type transducer described in the second embodiment is formed as the MEMS structure may be applied. it can. That is, an integrated circuit can be formed on one surface of a normal semiconductor substrate, and a resistance variable transducer can be formed on the other surface of the semiconductor substrate. Similarly, in the second embodiment, an example in which an SOI substrate is used and a resistance change type transducer is formed as a MEMS structure using the silicon layer of the SOI substrate is described. However, the silicon layer of the SOI substrate is described. A capacitive detection type transducer can also be formed on top.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is sectional drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a mode that the semiconductor device shown in FIG. 1 is flip-chip connected to a mounting substrate by a bump electrode. It is sectional drawing which shows the structure of MISFET formed on a semiconductor substrate. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; It is sectional drawing which shows the modification of FIG. FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device in a second embodiment. FIG. 29 is a plan view corresponding to FIG. 28. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 P type well 4 N type well 5 Gate insulating film 6a Gate electrode 6b Gate electrode 7 Shallow n type impurity diffusion region 8 Shallow p type impurity diffusion region 9 Side wall 10a Deep n type impurity diffusion region 10b Deep p-type impurity diffusion region 11 Interlayer insulating film 12 Resist film 12a Opening 13 Groove 14 Silicon oxide film 15 Metal film 16 Insulating film 17 Groove 18 Silicon oxide film 19 Metal film 20a Through electrode 20b Through electrode 21 Conductor film 22 Insulating film 23 Lower electrode 24 Insulating film 25 Conductor film 26 Upper electrode 27 Etching hole 28 Cavity 29 Insulating film 30 Passivation film 31 Organic film 32 Photosensitive polyimide film 32a Opening 33 Opening 34 Mounting substrate 35 Wiring 40 Substrate layer 41 Embedded insulating layer 42 Silicon layer 43a Diffusion resistance 43b Diffusion resistance 43c Diffusion resistance 43d Diffusion resistance 44 Cavity 45 Etching hole 46 Sealing film BP Bump electrode L1 First layer wiring L2 Second layer wiring L3 Third layer wiring PD pad PLG1 plug PLG2 plug PLG3 plug Qn n channel Type MISFET
Qp p-channel MISFET

Claims (10)

With a semiconductor chip,
The semiconductor chip is
(A) a semiconductor substrate;
(B) a semiconductor element formed on the first surface of the semiconductor substrate;
(C) a multilayer wiring layer formed on the semiconductor element;
(D) a pad formed on the uppermost layer of the multilayer wiring layer;
(E) a bump electrode formed on the pad;
A semiconductor device for mounting the semiconductor chip on the mounting substrate by connecting the bump electrodes to terminals formed on the mounting substrate,
On the second surface opposite to the first surface of the semiconductor substrate, a transducer that converts electrical signals and physical quantities is formed,
The transducer is
(F1) a first insulating film formed on the second surface of the semiconductor substrate;
(F2) a second insulating film formed on the first insulating film;
(F3) a cavity formed in the second insulating film;
(F4) having a diaphragm film formed so as to cover the cavity,
The transducer has a function of converting mechanical deformation of the diaphragm film due to external force into an electrical signal,
The semiconductor device, wherein the multilayer wiring layer and the transducer are electrically connected by a through electrode penetrating the semiconductor substrate. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the transducer includes a strain sensor that converts strain of the diaphragm film due to mechanical deformation of the diaphragm film into an electric signal. The semiconductor device according to claim 2,
The strain sensor converts a strain of the diaphragm film due to an external force into an electric signal by utilizing a change in resistance value of the strain sensor due to a strain generated in the diaphragm film. The semiconductor device according to claim 1,
The transducer has a capacitive element;
The capacitive element is
A lower electrode formed between the first insulating film and the second insulating film;
An upper electrode formed from the diaphragm film,
The semiconductor device, wherein the cavity is formed between the lower electrode and the upper electrode. The semiconductor device according to claim 4,
Due to the mechanical deformation of the diaphragm film serving as the upper electrode, the distance between the upper electrode and the lower electrode through the cavity changes, and the distance between the upper electrode and the lower electrode changes. Thus, the semiconductor device is characterized in that the mechanical deformation of the diaphragm film due to an external force is converted into an electric signal by utilizing the change in the capacitance of the capacitor element. The semiconductor device according to claim 1,
The semiconductor device, wherein the transducer is a pressure sensor or a vibration sensor. With a semiconductor chip,
The semiconductor chip is
(A) a semiconductor substrate;
(B) a semiconductor element formed on the first surface of the semiconductor substrate;
(C) a multilayer wiring layer formed on the semiconductor element;
(D) a pad formed on the uppermost layer of the multilayer wiring layer;
(E) a bump electrode formed on the pad;
A semiconductor device for mounting the semiconductor chip on the mounting substrate by connecting the bump electrodes to terminals formed on the mounting substrate,
On the second surface opposite to the first surface of the semiconductor substrate, a transducer that converts electrical signals and physical quantities is formed,
The transducer is
(F1) a first insulating film formed on the second surface of the semiconductor substrate;
(F2) a lower electrode formed on the first insulating film;
(F3) a second insulating film formed on the lower electrode;
(F4) a cavity formed in the second insulating film and exposing the lower electrode;
(F5) having an upper electrode formed to cover the cavity,
The transducer has a function of converting mechanical deformation of the upper electrode due to an external force into an electric signal,
The semiconductor device, wherein the multilayer wiring layer and the transducer are electrically connected by a through electrode penetrating the semiconductor substrate. The semiconductor device according to claim 7,
Due to the mechanical deformation of the upper electrode, the distance between the upper electrode and the lower electrode through the cavity changes, and the distance between the upper electrode and the lower electrode changes, A semiconductor device characterized in that mechanical deformation of the upper electrode due to an external force is converted into an electric signal by utilizing a change in capacitance of a capacitive element including an upper electrode and the lower electrode. A semiconductor chip having an SOI substrate including a substrate layer, a buried insulating layer formed on the substrate layer, and a semiconductor layer formed on the buried insulating layer;
The semiconductor chip is
(A) a semiconductor element formed on the substrate layer of the SOI substrate;
(B) a multilayer wiring layer formed on the semiconductor element;
(C) a pad formed on the uppermost layer of the multilayer wiring layer;
(D) having a bump electrode formed on the pad;
A semiconductor device for mounting the semiconductor chip on the mounting substrate by connecting the bump electrodes to terminals formed on the mounting substrate,
In the semiconductor layer of the SOI substrate, a transducer for converting an electrical signal and a physical quantity is formed,
The transducer is
(E1) a cavity formed in the buried insulating layer;
(E2) a diaphragm film that covers the cavity and is composed of the semiconductor layer;
(E3) a strain sensor that converts strain of the diaphragm film due to external force into an electrical signal;
The semiconductor device, wherein the multilayer wiring layer and the transducer are electrically connected by a through electrode penetrating the SOI substrate. The semiconductor device according to claim 9,
The semiconductor device is characterized in that the substrate layer is formed thicker than the semiconductor layer.

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