JP2009194365A - Semiconductor light-emitting element and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element having an improved external emission efficiency and a method of manufacturing the same. <P>SOLUTION: The semiconductor light-emitting element including a substrate 10, a protection layer 18 disposed on the substrate 10, an n-type impurity-doped n-type semiconductor 12 disposed on the substrate 10 sandwiched by the protection layers 18 and disposed on the protection layer 18, an active layer 13 disposed on the n-type semiconductor 12, a p-type impurity-doped p-type semiconductor 14 disposed on the active layer 13 and a method of manufacturing the same is provided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a semiconductor light emitting device with improved external light emission efficiency and a method for manufacturing the same.

A semiconductor light emitting element made of a group III nitride semiconductor is used for a light emitting diode (LED) or the like. Examples of group III nitride semiconductors include aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). A typical group III nitride semiconductor is represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

  A semiconductor light emitting device using a group III nitride semiconductor includes, for example, an n-type group III nitride semiconductor layer (n-type semiconductor layer), an active layer (light-emitting layer), and a p-type group III nitride on a substrate. It has a structure in which a series semiconductor layer (p-type semiconductor layer) is laminated in this order. Then, light generated by recombination of holes supplied from the p-type semiconductor layer and electrons supplied from the n-type semiconductor layer in the active layer is output to the outside (see, for example, Patent Document 1). .

  As the active layer, a multi-quantum well (MQW) structure in which a plurality of well layers (well layers) are sandwiched between barrier layers (barrier layers) having a larger band gap than the well layers can be employed. (For example, refer to Patent Document 2).

In the metal organic vapor phase epitaxy (MOVPE) method, the dislocation density of GaN obtained using an AlN or GaN low-temperature buffer layer on a sapphire substrate is about 10 ⁸ to 10 ¹⁰ cm ^−2. . In producing a device such as a semiconductor laser, about 10 ⁶ cm ⁻² or less is required. The dislocations in question are threading dislocations that are inherited with crystal growth from the interface region with the sapphire substrate.

At present, a technique established as an effective method capable of reducing the dislocation density to about 10 ⁶ to 10 ⁷ cm ⁻² is an ELO (Epitaxial Lateral Overgrowth) technique utilizing the characteristics of selective lateral growth.

  Some ELO technologies applied to GaN are based on the HVPE (Hydride Vapor Phase Epitaxy) method and the MOVPE method. The HVPE method is characterized in that the growth rate can be increased to several tens to several hundreds μm / h.

A method based on the HVPE method is called FIELO (Facet-Initiated Epitaxial Lateral Overgrowth). In FIELO, for example, a SiO ₂ striped mask pattern formed by lithography on GaN having a thickness of 1 to 1.5 μm grown on the sapphire (0001) plane (c-plane) by the MOVPE method is used as a base. Used. That is, in the conventional semiconductor light emitting device, an n-type GaN layer is first epitaxially grown on the sapphire substrate by about several μm, and then a SiO ₂ film or SiN _x film is partially formed on the n-type GaN layer. An n-type semiconductor layer is formed by selective lateral epitaxial growth using an n-type GaN layer other than the SiO ₂ or SiN _x film as a seed crystal for selective lateral epitaxial growth (see, for example, Non-Patent Document 1).

However, an n-type GaN layer having a refractive index significantly different from the refractive index value of the sapphire substrate is disposed below the SiO ₂ film or SiN _x film having a refractive index close to that of the sapphire substrate. Then, light is reflected at the interface between the sapphire substrate and the n-type GaN layer, so that the light from the semiconductor light emitting device cannot be effectively extracted outside, and the external light emission efficiency is lowered.

  In the conventional structure, when a nitride-based semiconductor is manufactured by metal organic chemical vapor deposition (MOCVD), for example, a sapphire substrate is used as a growth substrate, and an organic metal compound gas is used as a reaction gas. The GaN epitaxial growth layer was formed on the sapphire substrate at a crystal growth temperature of about 900 ° C. to 1100 ° C. The surface morphology of the GaN semiconductor layer grown directly on the sapphire substrate using the MOCVD method is extremely poor. Therefore, a method of forming an AlN buffer layer on the sapphire substrate before the GaN semiconductor layer is grown is used. However, in the above method, the growth conditions of the buffer layer are strictly limited, and the film thickness needs to be strictly controlled within a very thin range of 100 to 500 mm (angstrom). In addition, when the GaN layer is grown on the AlN buffer layer, lattice constant mismatch is significant.

Further, when the p-type semiconductor layer is formed in a multilayer structure, it is necessary to grow at a low temperature in order to reduce the thermal damage to the active layer, and at the same time, the forward voltage (V _f ) is lowered and the luminous efficiency is improved. There is a need. Further, when a GaN layer is applied as the p-type semiconductor layer, there is a problem in terms of transparency with respect to the emission wavelength.

In the conventional structure, 4 to 5 pairs of MQWs are used. In this case, electrons supplied from the n-type semiconductor layer jump over the active layer and flow to the p-type semiconductor layer. At this time, holes supplied from the p-type semiconductor layer recombine with electrons before reaching the active layer, and the hole concentration reaching the active layer is reduced. Thereby, the brightness | luminance of LED will reduce. In order to prevent this, a structure in which a p-type AlGaN layer having a large band gap is inserted in front of the p-type semiconductor layer is used. However, when aluminum (Al) is introduced, it becomes difficult to form p-type, and the resistance value increases. On the other hand, when an InGaN layer is applied to the well layer of the active layer, there is a problem that it is vulnerable to thermal damage associated with a high temperature process in forming the p-type semiconductor layer.
Japanese Patent Laid-Open No. 10-284802 JP 2004-55719 A Akira Sakai, Akira Sakurai, “Reduction of dislocation density by lateral selection of GaN”, Applied Physics, Vol. 68, No. 7, pp.774-779 (1999)

  An object of the present invention is to provide a semiconductor light emitting device with improved external light emission efficiency and a method for manufacturing the same.

  Another object of the present invention is to add Al to the n-type semiconductor layer, the active layer, and the p-type semiconductor layer to reduce thermal damage, improve the transmittance with respect to the emission wavelength, and improve the external light emission efficiency. The object is to provide an element and a method of manufacturing the same.

  According to one embodiment of the present invention for achieving the above object, a substrate, a protective film disposed on the substrate, a substrate sandwiched between the protective films and the protective film, and doped with an n-type impurity There is provided a semiconductor light emitting device comprising: an n-type semiconductor layer; an active layer disposed on the n-type semiconductor layer; and a p-type semiconductor layer disposed on the active layer and doped with a p-type impurity.

  According to another aspect of the present invention, a substrate, a protective film disposed on the substrate, an AlN buffer layer disposed on the substrate sandwiched between the protective films, the AlN buffer layer, and the protection An n-type semiconductor layer disposed on the film and doped with n-type impurities, and a block layer disposed on the n-type semiconductor layer and doped with the n-type impurities at a lower concentration than the n-type semiconductor layer And an active layer comprising a multiple quantum well containing indium, wherein the active layer has a stacked structure in which barrier layers and well layers having a smaller band gap than the barrier layers are alternately arranged, and the active layer. A first nitride-based semiconductor layer including a p-type impurity, and a p-type impurity disposed on the first nitride-based semiconductor layer and having a lower concentration than the p-type impurity of the first nitride-based semiconductor layer. Second nitride system containing type impurities A semiconductor layer, a third nitride-based semiconductor layer disposed on the second nitride-based semiconductor layer and containing a p-type impurity at a concentration higher than that of the p-type impurity of the second nitride-based semiconductor layer; A fourth nitride-based semiconductor layer that is disposed on the three-nitride-based semiconductor layer and includes a p-type impurity at a concentration lower than that of the p-type impurity of the third nitride-based semiconductor layer; A semiconductor light emitting device is provided in which the film thickness of the final barrier layer is larger than the diffusion distance of the p-type impurity in the first nitride-based semiconductor layer.

  According to another aspect of the present invention, a substrate, a protective film disposed on the substrate, an AlN buffer layer disposed on the substrate sandwiched between the protective films, the AlN buffer layer, and the protection An n-type semiconductor layer disposed on the film and doped with n-type impurities, and a block layer disposed on the n-type semiconductor layer and doped with the n-type impurities at a lower concentration than the n-type semiconductor layer And an active layer comprising a multiple quantum well containing indium, wherein the active layer has a stacked structure in which barrier layers and well layers having a smaller band gap than the barrier layers are alternately arranged, and the active layer. A first nitride-based semiconductor layer including a p-type impurity, and a lower concentration than the p-type impurity of the first nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer. Second nitridation containing p-type impurities And a transparent electrode made of a transparent electrode disposed on the second nitride semiconductor layer, wherein the final barrier layer of the uppermost layer of the stacked structure has a film thickness of the first nitride system. A semiconductor light-emitting element thicker than the diffusion distance of the p-type impurity in the semiconductor layer is provided.

According to another aspect of the present invention, a substrate, an AlN buffer layer disposed on the substrate, and an Al _x Ga _1-x N layer disposed on the AlN buffer layer and doped with an n-type impurity. An n-type semiconductor layer composed of (0 <x <1), a barrier layer disposed on the n-type semiconductor layer and composed of an Al _x Ga _1-x N layer (0 <x <1), and a band formed from the barrier layer An active layer composed of a multiple quantum well having a stacked structure in which well layers composed of Al _x In _y Ga _1-xy N layers (0 <x ≦ y <1, 0 <x + y <1) having a small gap are alternately arranged; There is provided a semiconductor light emitting device including a p-type semiconductor layer disposed on the active layer and made of an Al _x Ga _1-x; N layer (0 ≦ x <1) doped with a p-type impurity.

  According to another aspect of the present invention, a step of forming a protective film on a substrate, a step of patterning the protective film and exposing the substrate, the substrate sandwiched and exposed by the protective film, and the Forming a n-type semiconductor layer doped with an n-type impurity on the protective film by lateral epitaxial growth; forming an active layer on the n-type semiconductor layer; and doping the p-type impurity on the active layer And a method of forming a p-type semiconductor layer.

According to another aspect of the present invention, an AlN buffer layer is formed on a substrate, and an Al _x Ga _1-x N layer doped with an n-type impurity (0 <x <) is doped on the AlN buffer layer. A step of forming an n-type semiconductor layer made of 1), a barrier layer made of an Al _x Ga _1-x N layer (0 <x <1) on the n-type semiconductor layer, and a band gap smaller than the barrier layer Forming an active layer made of a multiple quantum well having a stacked structure in which well layers made of Al _x In _y Ga _1-xy N layers (0 <x ≦ y <1, 0 <x + y <1) are alternately formed; And a step of forming a p-type semiconductor layer composed of an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity on the active layer. Provided.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device with improved external light emission efficiency and its manufacturing method can be provided.

  In addition, according to the present invention, Al is added to the n-type semiconductor layer, the active layer, and the p-type semiconductor layer to reduce thermal damage and improve the transmittance with respect to the emission wavelength, thereby improving the external light emission efficiency. A light-emitting element and a manufacturing method thereof can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following, the same reference numerals are assigned to the same blocks or elements to avoid duplication of explanation and simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. In the embodiments of the present invention, the arrangement of each component is as follows. Not specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

  In the semiconductor light emitting device according to the following embodiments of the present invention, “transparent” is defined as having a transmittance of about 50% or more. The term “transparent” is used to mean colorless and transparent with respect to visible light in the semiconductor light emitting device according to the embodiment of the present invention. Visible light corresponds to a wavelength of about 360 nm to 830 nm and an energy of about 3.4 eV to 1.5 eV, and is transparent unless absorption, reflection, or scattering occurs in this region.

Transparency is determined by the band gap E _g and the plasma frequency ω _p . When the band gap E _g is about 3.1 eV or more, the transition between electrons in the visible light does not occur, and therefore the visible light is transmitted without being absorbed. On the other hand, light having energy lower than the plasma frequency ω _p cannot enter the plasma and is reflected by carriers that can be regarded as plasma. The plasma frequency ω _p is expressed as ω _p = (nq ² / εm ^* ) ^1/2 where n is the carrier density, q is the charge, ε is the dielectric constant, and m ^* is the effective mass, and is a function of the carrier density. is there.

[First embodiment]
(Element structure)
As shown in FIGS. 1A and 1B, the semiconductor light emitting device according to the first embodiment of the present invention includes a substrate 10, a protective film 18 disposed on the substrate 10, and a protective film. N-type semiconductor layer 12 which is disposed on substrate 10 and protective film 18 sandwiched between 18 and doped with n-type impurities, active layer 13 disposed on n-type semiconductor layer 12, and active layer 13 And a p-type semiconductor layer 14 doped with a p-type impurity.

  Further, the buffer layer 16 may be further provided on the substrate 10 sandwiched between the protective films 18.

  In addition, as shown in FIGS. 1A and 1B, the semiconductor light emitting device according to the first embodiment includes a transparent electrode 15 disposed on the p-type semiconductor layer 14, a transparent electrode 15, An n-side electrode 200 disposed on the surface of the n-type semiconductor layer 12 obtained by removing a part of the p-type semiconductor layer 14, the active layer 13, and the n-type semiconductor layer 12, and a transparent electrode 15. a p-side electrode 100.

  The semiconductor light emitting device according to the first embodiment may further include a reflective laminated film 28 disposed on the transparent electrode 15 as shown in FIG.

  The protective film 18 is transparent with respect to the emission wavelength, and the refractive index of the protective film 18 is substantially equal to the refractive index of the substrate 10. For example, as the protective film 18, a film having a refractive index close to the refractive index of the substrate 10 that is sufficiently transparent with respect to the emission wavelength may be used.

When a sapphire substrate (n = 1.7 to 1.8) is used as the substrate 10, if a SiO ₂ film is used as the protective film 18, the refractive index of the SiO ₂ film is about n = 1.46. The refractive index n of the substrate is about the same as 1.7 to 1.8. If a SiN _x film is used as the protective film 18, the refractive index of the SiN _x film is about n = 2.05, which is about the same as the refractive index of the sapphire substrate. When a TiO _x film is used as the protective film 18, the refractive index of the TiO _x film is about n = 1.8, which is about the same as the refractive index of the sapphire substrate. Furthermore, as the protective film 18, the use of the Al ₂ O ₃ film, the refractive index of the Al ₂ O ₃ film is about n = on the order of 1.7 to 1.8 refractive index comparable to the sapphire substrate.

  Therefore, any of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a titanium oxide film, and an alumina film can be applied as the protective film 18.

  The transparent electrode 15 may be any one of ZnO, ITO, or ZnO containing indium.

Alternatively, as will be described later, the transparent electrode 15 is made of either ZnO doped with Ga or Al with an impurity concentration of 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ , ITO, or ZnO containing indium. There may be.

  The active layer 13 has a stacked structure in which barrier layers and well layers having a smaller band gap than the barrier layers are alternately arranged, and is formed of a multiple quantum well containing indium.

The barrier layer is made of GaN, the well layer is made of In _x Ga _1-x N (0 <x <1), and the number of pairs of multiple quantum wells is about 6 to 11, for example.

  Moreover, the thickness of a well layer is 2-3 nm, for example, and the thickness of a barrier layer is 15-18 nm, for example.

The substrate may be a c-plane (0001), 0.25 ° off sapphire (α-Al ₂ O ₃ ) substrate.

  The n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a nonpolar plane having a hexagonal crystal structure as a main surface for crystal growth, and the lateral growth plane of the n-type semiconductor layer 12 is the nonpolar plane. A vertical non-polar surface is desirable.

  Alternatively, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a hexagonal crystal m-plane as the main plane for crystal growth, and the lateral growth plane of the n-type semiconductor layer 12 is the m-plane. It is desirable that the a-plane be perpendicular to.

  Alternatively, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a hexagonal crystal a-plane as a main surface for crystal growth, and the lateral growth plane of the n-type semiconductor layer 12 is the a-plane. It is desirable that the m-plane be perpendicular to.

  Alternatively, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a semipolar plane of hexagonal crystal structure as a main plane for crystal growth, and the lateral growth plane of the n-type semiconductor layer 12 has An a-plane or m-plane perpendicular to the polar plane is desirable.

  Alternatively, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a hexagonal crystal polar surface as a main surface for crystal growth, and the lateral growth surface of the n-type semiconductor layer 12 has an m-plane or The a-plane is desirable.

(Structural example with a reflective laminated film)
In the structure of FIG. 1, by further disposing the reflective laminated film 28 on the transparent electrode 15, the light generated in the active layer 13 can be effectively reflected by the reflective laminated film 28 as shown in FIG. 9. .

  Further, in the structure of FIG. 9, the light generated in the active layer 13 can be effectively extracted to the substrate 10 side by the protective film 18 disposed on the substrate 10.

  A substrate in which a protective film 18 having a different refractive index is partially formed on a different substrate is prepared, and a nitride-based semiconductor is directly epitaxially grown on the above substrate to form a light emitting element, thereby forming an epitaxial growth layer-substrate interface. Irregularities can be formed, light scattering and diffraction occur, and light extraction efficiency is improved.

  Further, since processing of the substrate is unnecessary, there is little burden in terms of cost and process, and productivity is excellent.

  By performing epitaxial growth directly from the window portion of the protective film 18, the epitaxial growth process can be integrated at once.

  Since the lateral growth (ELO) is performed so as to cover the protective film 18, the threading dislocations of the crystal can be bent, and the crystallinity is also improved.

  On the other hand, in the semiconductor light emitting device according to the comparative example of the present invention compared with FIG. 9, as shown in FIG. Since the difference in rate is large, the angle of total reflection is large. This is because the refractive index of the sapphire substrate is about n = 1.7 to 1.8, whereas the refractive index of the GaN layer is about n = 2.5.

(Detailed structure example)
As shown in FIG. 11, the semiconductor light emitting device according to the first embodiment is disposed on the substrate 10, the protective film 18 disposed on the substrate 10, and the substrate 10 sandwiched between the protective films 18. Buffer layer 16, disposed on buffer layer 16 and protective film 18, n-type semiconductor layer 12 doped with n-type impurities, and disposed on n-type semiconductor layer 12, having a lower concentration than n-type semiconductor layer 12 The n-type impurity is added to the block layer 17, the active layer 13 disposed on the block layer 17, the p-type semiconductor layer 14 disposed on the active layer 13, and the p-type semiconductor layer 14. The transparent electrode 15 is provided.

  As shown in FIG. 11B, the active layer 13 has a laminated structure in which barrier layers 311 to 31n and 310 and well layers 321 to 32n having smaller band gaps than the barrier layers 311 to 31n and 310 are alternately arranged. Have. Hereinafter, the first barrier layer 311 to the n-th barrier layer 31n included in the active layer 13 are collectively referred to as “barrier layer 31”. Also, all well layers included in the active layer 13 are collectively referred to as “well layers 32”.

  The film thickness of the final barrier layer 310 in the uppermost layer of the stacked structure is larger than the thicknesses of the other barrier layers (the first barrier layer 311 to the nth barrier layer 31n) included in the stacked structure other than the final barrier layer 310. It may be formed.

  In the semiconductor light emitting device shown in FIG. 11, the concentration of the p-type dopant in the final barrier layer 310 extends from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 14 along the film thickness direction of the final barrier layer 310. There is no p-type dopant on the second main surface that gradually decreases and faces the first main surface.

  As the substrate 10, for example, a c-plane (0001), 0.25 ° off sapphire substrate or the like can be used. The n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 are each made of a group III nitride semiconductor. After forming the protective film 18 on the substrate 10, the buffer layer 16, the n-type semiconductor layer 12, and the block layer 17. The active layer 13 and the p-type semiconductor layer 14 are sequentially stacked.

(Protective film)
The protective film 18 is transparent to the emission wavelength, and the refractive index of the protective film 18 needs to be a material substantially equal to the refractive index of the substrate 10. For example, the protective film is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a titanium oxide film, an alumina film, or the like.

In the case of a sapphire substrate (n = 1.7 to 1.8), the protective film 18 includes SiO ₂ (n = 1.46), SiN _x (n = 2.05), TiO _x (n = 1.8). ), Al ₂ O ₃ (n = 1.7 to 1.8) or the like can be applied.

  As the size of the protective film 18, for example, the maximum width is about 10 μm, and the thickness is preferably about 100 nm or more and about 1 μm, for example. The shape of the protective film 18 is preferably a pattern shape that does not inhibit selective lateral epitaxial growth (ELO), such as a triangle, a rhombus, a hexagon, a circle, and a stripe. In particular, in order to perform ELO, the direction of the pattern is selected in consideration of the a-plane and m-plane which are lateral growth planes.

  When light is extracted from the back surface of the substrate 10 or the upper surface of the epitaxial growth layer, irregularities are generated at the interface between the protective film 18 and the epitaxial growth layer, so that the light is scattered or diffracted and totally reflected by the difference in refractive index between the epitaxial growth layer and the heterogeneous substrate interface. The light that has been emitted is efficiently extracted outside.

(AlN buffer layer)
The buffer layer 16 is formed of, for example, an AlN layer having a thickness of about 10 to 50 angstroms. When the AlN buffer layer 16 is crystal-grown, for example, it is grown at a high temperature in the temperature range of about 900 ° C. to 950 ° C.

By supplying trimethylaluminum (TMA) and ammonia (NH ₃ ) to the reaction chamber using H ₂ gas as a carrier, a thin AlN buffer layer 16 having a thickness of about 10 to 50 Å can be grown at a high speed. And can be formed while maintaining good crystallinity.

  According to the semiconductor light emitting device according to the first embodiment, the crystallinity and surface morphology of the group III nitride semiconductor formed on the high temperature AlN buffer layer 16 and the protective film 18 can be improved.

(Block layer)
The block layer 17 disposed between the n-type semiconductor layer 12 and the active layer 13 is a group III nitride semiconductor having a thickness of about 200 nm doped with Si as an n-type impurity at a ^{concentration of} less than 1 × 10 ¹⁷ cm ^−3. For example, a GaN layer can be employed.

In the semiconductor light emitting device shown in FIG. 11, for example, when Si is doped with about 3 × 10 ¹⁸ cm ^{−3 in the} n-type semiconductor layer 12, Si is doped with about 8 × 10 ¹⁶ cm ^−3. By disposing the layer 17 between the n-type semiconductor layer 12 and the active layer 13, the diffusion of Si from the n-type semiconductor layer 12 to the active layer 13 in the process of forming the active layer 13 and the manufacturing process after that process can be prevented. .

  That is, Si does not diffuse into the active layer 13, and a decrease in luminance of light generated in the active layer 13 is prevented. Further, when a bias is applied between the n-type semiconductor layer 12 and the p-type semiconductor layer 14 to cause the active layer 13 to emit light, electrons supplied from the n-type semiconductor layer 12 to the active layer 13 cause the active layer 13 to An overflow that passes through and reaches the p-type semiconductor layer 14 can be prevented, and a decrease in luminance of light output from the semiconductor light emitting element can be prevented.

The Si concentration of the block layer 17 is less than 1 × 10 ¹⁷ cm ⁻³ . This is because, when the Si concentration of the block layer 17 is too high, electrons supplied from the n-type semiconductor layer 12 overflow the active layer 13 and reach the p-type semiconductor layer 14. This is because recombination occurs, the recombination rate in the active layer 13 decreases, and the luminance of light generated in the active layer 13 decreases. On the other hand, when the Si concentration of the block layer 17 is too low, the carrier density of electrons injected from the n-type semiconductor layer 12 into the active layer 13 cannot be increased. Therefore, the Si concentration of the block layer 17 is preferably about 5 × 10 ¹⁶ to less than 1 × 10 ¹⁷ cm ⁻³ .

  As described above, in the semiconductor light emitting device according to the first embodiment, the block layer 17 is disposed between the n-type semiconductor layer 12 and the active layer 13, thereby allowing the n-type semiconductor layer 12 during the manufacturing process. Diffusion of Si from the active layer 13 to the active layer 13 and overflow of electrons from the n-type semiconductor layer 12 to the p-type semiconductor layer 14 during light emission can be prevented, and the luminance of light output from the semiconductor light-emitting element can be reduced. Can be prevented. As a result, deterioration of the quality of the semiconductor light emitting element shown in FIG. 11 can be prevented.

(N-type semiconductor layer)
The n-type semiconductor layer 12 supplies electrons to the active layer 13, and the p-type semiconductor layer 14 supplies holes (holes) to the active layer 13. Light is generated by the recombination of the supplied electrons and holes in the active layer 13.

  The n-type semiconductor layer 12 may be a group III nitride semiconductor having a thickness of about 1 to 6 μm doped with an n-type impurity such as silicon (Si), such as a GaN layer.

  The n-type semiconductor layer 12 made of a nitride semiconductor is directly epitaxially grown on the heterogeneous substrate 10 through the protective film 18. In order to fill the protective film 18, the condition is changed from the middle to a condition that promotes lateral growth. In order to promote the lateral growth, for example, the pressure of the gas system during crystal growth may be changed. As a first step, for example, after growth of about 1 μm at about 1050 ° C. and about 100 Torr, for example, about 1.5 μm can be grown at about 1050 ° C. and about 200 Torr, for example. By forming the n-type semiconductor layer 12 in this way, lateral growth can be promoted together with the effect of reducing threading dislocation density by lateral growth (ELO).

  Since the lateral growth (ELO) is performed so as to cover the protective film 18, the threading dislocations of the crystal can be bent, and the crystallinity is also improved.

  Furthermore, the pressure and growth temperature conditions for forming the n-type semiconductor layer 12 can be changed to divide into several steps. For example, as shown in FIG. 12 (121, 122, 123, 124) can also be formed. By doing so, the surface morphology of the n-type semiconductor layer 12 is improved, and the crystallinity can be improved.

(P-type semiconductor layer)
The p-type semiconductor layer 14 may be a group III nitride semiconductor having a thickness of about 0.05 to 1 μm doped with p-type impurities, such as a GaN layer. As the p-type impurity, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like can be used.

  A configuration example of the p-type semiconductor layer 14 is as follows in more detail. That is, as shown in FIG. 11A, the p-type semiconductor layer 14 is disposed on the active layer 13, and includes a first nitride-based semiconductor layer 41 including a p-type impurity, and a first nitride-based semiconductor layer. 41, a second nitride-based semiconductor layer 42 containing a p-type impurity at a lower concentration than the p-type impurity of the first nitride-based semiconductor layer 41, and a second nitride-based semiconductor layer 42. , A third nitride-based semiconductor layer 43 containing a p-type impurity having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer 42, and the third nitride-based semiconductor layer 43 disposed on the third nitride-based semiconductor layer 43. And a fourth nitride semiconductor layer 44 containing a p-type impurity having a lower concentration than the p-type impurity of the system semiconductor layer 43.

  The thickness of the second nitride-based semiconductor layer 42 is formed to be greater than the thickness of the first nitride-based semiconductor layer 41 or the third nitride-based semiconductor layer 43 to the fourth nitride-based semiconductor layer 44.

Here, the material and thickness of each layer will be specifically described. The first nitride semiconductor layer 41 containing p-type impurities disposed on the active layer 13 is, for example, a p-type GaN layer of about 2 × 10 ²⁰ cm ⁻³ and about 50 nm thick doped with Mg. Formed with.

The second nitride semiconductor layer 42 disposed on the first nitride semiconductor layer 41 and containing a p-type impurity having a lower concentration than the p-type impurity of the first nitride semiconductor layer 41 is doped with, for example, Mg. The p-type GaN layer is about 4 × 10 ¹⁹ cm ⁻³ and about 100 nm thick.

The third nitride-based semiconductor layer 43 disposed on the second nitride-based semiconductor layer 42 and containing a p-type impurity having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer 42 is doped with, for example, Mg. The p-type GaN layer is about 1 × 10 ²⁰ cm ⁻³ and about 40 nm thick.

The fourth nitride semiconductor layer 44 disposed on the third nitride semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 43 is doped with, for example, Mg. The p-type GaN layer is about 8 × 10 ¹⁹ cm ⁻³ and about 10 nm thick.

  In the semiconductor light emitting device according to the first embodiment, the p-type semiconductor layer 14 formed on the active layer 13 made of a multiple quantum well containing indium has a four-layer structure with different Mg concentrations as described above. It consists of a p-type GaN layer and is doped at the above concentration. The p-type GaN layer is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 13.

  The first nitride semiconductor layer 41 closest to the active layer 13 has a higher emission intensity as the Mg concentration is higher. Therefore, the higher the Mg concentration, the better.

The second nitride-based semiconductor layer 42 has a Mg concentration of about 10 ¹⁹ cm ⁻³ because the crystal defects due to Mg increase and the resistance of the film increases when Mg is excessively doped. It is desirable.

  The third nitride-based semiconductor layer 43 is a layer that determines the amount of holes injected into the active layer 13, and is therefore preferably set to a slightly higher Mg concentration than the second nitride-based semiconductor layer 42.

The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for making ohmic contact with the transparent electrode 15 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al is used as the transparent electrode 15, Mg when the forward voltage V _f of the semiconductor light emitting element is lowered most is used. Mg is added to the fourth nitride-based semiconductor layer 44 so as to have a concentration.

When four p-type GaN layers are grown, the third nitride semiconductor layer 43 and the fourth nitride semiconductor layer 44 close to the p-side electrode 100 need to increase the hole concentration in the film. Increase the amount of H ₂ gas in the carrier gas. Further, the first nitride semiconductor layer 41 and the second nitride semiconductor layer 42 close to the active layer 13 do not need to increase the amount of H ₂ gas in the carrier gas, and the active layer 13 is made of N ₂ carrier gas. The crystal is grown by the extension of the growth. When these p-type GaN layers are grown, a film having a lower resistance can be grown by increasing the V / III ratio as much as possible, and the forward voltage (V _f ) of the light emitting element can be lowered.

According to the semiconductor light emitting device according to the first embodiment, the p-type semiconductor layer is formed at a low temperature to reduce the thermal damage to the active layer, to reduce the forward voltage (V _f ), and to improve the luminous efficiency. Can be improved.

(Active layer)
As shown in FIG. 11B, the active layer 13 includes a first well layer 321 to an nth well layer 32n sandwiched between a first barrier layer 311 to an nth barrier layer 31n and a final barrier layer 310, respectively. It is a quantum well (MQW) structure (n: natural number). That is, the active layer 13 has a quantum well structure in which a well layer 32 is sandwiched between barrier layers 31 having a larger band gap than the well layer 32 in a unit pair structure, and this unit pair structure is stacked n times. Have

  Specifically, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer 322 is disposed between the second barrier layer 312 and the third barrier layer 313. The The nth well layer 32n is disposed between the nth barrier layer 31n and the final barrier layer 310. The first barrier layer 311 of the active layer 13 is disposed on the n-type semiconductor layer 12 via the block layer 17, and the p-type semiconductor layer 14 (41 to 44) is disposed on the final barrier layer 310 of the active layer 13. Is done.

The well layers 321 to 32n are formed by, for example, In _x Ga _1-x N (0 <x <1) layers, and the barrier layers 311 to 31n and 310 are formed by, for example, GaN layers. The number of pairs of the multiple quantum well layers is, for example, 6 to 11. The indium (In) ratio {x / (1-x)} of the well layers 321 to 32n is appropriately set according to the wavelength of light to be generated.

  Further, the thickness of the well layers 321 to 32n is, for example, about 2 to 3 nm, preferably about 2.8 nm, and the thickness of the barrier layers 311 to 31n is about 7 to 18 nm, preferably about It is about 16.5 nm.

  In the semiconductor light emitting device according to the first embodiment, the active layer for efficiently recombining the electrons supplied from the n-type semiconductor layer 12 and the holes supplied from the p-type semiconductor layer 14 in the active layer 13. The number of MQW pairs in 13 can be optimized.

(Final barrier layer)
The final barrier layer 310 is formed thicker than the Mg diffusion distance from the p-type semiconductor layer 14 to the active layer 13.

  In the example of the semiconductor light emitting device shown in FIG. 11, the concentration of the p-type impurity in the final barrier layer 310 is from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 14 in the film thickness direction of the final barrier layer 310. The p-type impurity is substantially absent in the second main surface that gradually decreases along the second main surface and faces the first main surface.

The film thickness d ₀ of the final barrier layer 310 of the semiconductor light emitting device shown in FIG. 11 is such that the p-type impurity diffused from the p-type semiconductor layer 14 to the active layer 13 after the step of forming the p-type semiconductor layer 14 It is set so as not to reach the well layer 32 of the active layer 13. That is, the p-type impurity diffused from the p-type semiconductor layer 14 to the final barrier layer 310 is a second main surface (the final barrier layer 310 is a well) facing the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 14. The film thickness d ₀ is set to a thickness that does not reach the surface) that contacts the layer 32n.

The Mg concentration on the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 14 is, for example, about 2 × 10 ²⁰ cm ⁻³ , and the second concentration of the final barrier layer 310 facing the first main surface is about 2 × 10 ²⁰ cm ⁻³ . The Mg concentration gradually decreases toward the main surface, and the Mg concentration does not have an influence of less than about 10 ¹⁶ cm ^{−3 at a} distance of about 7 to 8 nm from the first main surface, and is below the detection lower limit in the analysis. Become.

That is, by setting the film thickness d ₀ of the final barrier layer 310 to about 10 nm, Mg does not diffuse to the second main surface of the final barrier layer 310, and therefore, the first barrier layer 310 in contact with the active layer 13 is not diffused. 2 Mg does not exist on the main surface. That is, Mg does not diffuse into the n-th well layer 32n, and a reduction in the luminance of light generated in the active layer 13 is prevented.

The film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n may be the same. However, the thicknesses d1 to dn are such that holes injected from the n-type semiconductor layer 12 into the active layer 13 reach the n-th well layer 32n, and light is emitted by recombination of electrons and holes in the n-th well layer 32n. It is necessary to set a thickness that can be generated. This is because if the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are too thick, the movement of holes in the active layer 13 is hindered and the light emission efficiency is lowered. For example, the film thickness d ₀ of the final barrier layer 310 is about 10 nm, the film thicknesses d ₁ to dn of the first barrier layer 311 to the n-th barrier layer 31 n are about 7 to 18 nm, and the first well layers 321 to 321 The film thickness of the n-th well layer 32n is about 2 to 3 nm.

As described above, in the semiconductor light emitting device according to the first embodiment, the film thickness d ₀ of the final barrier layer 310 in contact with the p-type semiconductor layer 14 diffuses from the p-type semiconductor layer 14 to the active layer 13. The thickness is set such that the p-type impurity does not reach the well layer 32 of the active layer 13. In other words, according to the semiconductor light emitting device shown in FIG. 11, by setting the film thickness d ₀ of the final barrier layer 310 to be greater than the Mg diffusion distance, the increase in the film thickness of the entire active layer 13 is suppressed, while p. The diffusion of p-type impurities from the type semiconductor layer 14 to the well layer 32 of the active layer 13 can be prevented. As a result, it is possible to manufacture a semiconductor light emitting device in which the light luminance is not lowered due to the diffusion of the p-type impurity into the well layer 32 and the deterioration of the quality of the semiconductor light emitting device is suppressed.

(Modification)
FIG. 12A is a schematic cross-sectional structure diagram of a semiconductor light-emitting element according to a modification of the first embodiment, and is a schematic cross-sectional structure diagram of the semiconductor light-emitting element part, and FIG. The schematic cross-sectional structure figure by which the part was expanded is shown.

  As shown in FIG. 12, the semiconductor light emitting device according to the modified example of the first embodiment is formed on a substrate 10, a protective film 18 disposed on the substrate 10, and a substrate 10 sandwiched between the protective films 18. The n-type semiconductor layer 12 disposed on the buffer layer 16, the buffer layer 16 and the protective film 18, doped with an n-type impurity, and the n-type semiconductor layer 12. Block layer 17 doped with n-type impurities at a lower concentration, active layer 13 disposed on block layer 17, p-type semiconductor layer 14 disposed on active layer 13, and p-type semiconductor layer 14 And a transparent electrode 15 disposed on the top.

  The semiconductor light emitting device according to the modification of the first embodiment is disposed on the third nitride semiconductor layer 43 including the p-type impurity disposed on the active layer 13 and the third nitride semiconductor layer. A fourth nitride-based semiconductor layer containing a p-type impurity at a lower concentration than the p-type impurity of the third nitride-based semiconductor layer, and a transparent electrode 15 disposed on the fourth nitride-based semiconductor layer. .

The transparent electrode 15 includes any one of ZnO doped with impurities of Ga or Al up to about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ , ITO, or ZnO containing indium.

  The semiconductor light emitting device according to the modification of the first embodiment has a third structure in which the p-type semiconductor layer 14 is directly disposed on the active layer 13 due to the structure of the semiconductor light emitting device according to the first embodiment. Nitride-based semiconductor layer 43 and a fourth nitride-based semiconductor layer that is disposed on third nitride-based semiconductor layer 43 and contains a p-type impurity at a lower concentration than the p-type impurity of third nitride-based semiconductor layer 43 A two-layer structure consisting of 44 is formed.

The third nitride semiconductor layer 43 disposed directly on the active layer 13 is formed of, for example, a p-type GaN layer of about 1 × 10 ²⁰ cm ⁻³ doped with Mg and having a thickness of about 40 nm. .

The fourth nitride semiconductor layer 44 disposed on the third nitride semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 43 is doped with, for example, Mg. The p-type GaN layer is about 8 × 10 ¹⁹ cm ⁻³ and about 10 nm thick.

  In the semiconductor light emitting device according to the modification of the first embodiment, the p-type semiconductor layer 14 formed on the active layer 13 made of a multiple quantum well containing indium has two different Mg concentrations as described above. It consists of a p-type GaN layer with a layer structure and is doped at the above-mentioned concentration. The p-type GaN layer is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 13.

  Since the third nitride semiconductor layer 43 closest to the active layer 13 is a layer that determines the amount of holes injected into the active layer 13, the higher the Mg concentration, the higher the emission intensity. For this reason, the higher the Mg concentration, the better.

The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for making ohmic contact with the transparent electrode 15 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al is used as the transparent electrode 15, Mg when the forward voltage V _f of the semiconductor light emitting element is lowered most is used. Mg is added to the fourth nitride-based semiconductor layer 44 so as to have a concentration.

When growing two p-type GaN layers, the third nitride-based semiconductor layer 43 and the fourth nitride-based semiconductor layer 44 close to the p-side electrode 100 need to increase the hole concentration in the film. Increase the amount of H ₂ gas in the carrier gas. Alternatively, the third nitride-based semiconductor layer 43 close to the active layer 13 does not need to increase the amount of H ₂ gas in the carrier gas, and the active layer 13 is grown by the N ₂ carrier gas, so that the third nitride semiconductor layer 43 is crystallized. It may be grown.

  Also in the semiconductor light emitting device according to the modification of the first embodiment, the protective film 18 disposed on the substrate 10, the buffer layer 16 disposed on the substrate 10 sandwiched between the protective films 18, the buffer layer 16, and The n-type semiconductor layer 12, the block layer 17, the active layer 13, the p-type semiconductor layer 14, the final barrier layer 310, the reflective laminated film 28, and the electrode structure which are disposed on the protective film 18 and doped with n-type impurities are Since it is the same as that of the semiconductor light emitting element according to the first embodiment of the invention, the description thereof is omitted.

  According to the semiconductor light emitting device according to the first embodiment and the modification thereof, the crystallinity and surface morphology of the group III nitride semiconductor formed on the high temperature AlN buffer layer 16 and the protective film 18 can be improved. it can.

In addition, the p-type semiconductor layer 14 can be formed at a low temperature to reduce thermal damage to the active layer 13 and to reduce the forward voltage V _f to improve the light emission efficiency.

  Further, the number of MQW pairs in the active layer 13 for efficiently recombining the electrons supplied from the n-type semiconductor layer 12 and the holes supplied from the p-type semiconductor layer 14 in the active layer 13 is optimized, and the light emission efficiency is improved. Can be improved.

  Further, the diffusion of p-type impurities from the p-type semiconductor layer 14 to the well layer can be suppressed, and the light emission efficiency can be improved. The overflow of electrons from the n-type semiconductor layer 12 to the p-type semiconductor layer 14 and the n-type The diffusion of n-type impurities from the semiconductor layer 12 to the active layer 13 can be suppressed, and the light emission efficiency can be improved.

  In addition, it is possible to provide a semiconductor light-emitting device that does not require an annealing step for removing hydrogen atoms from the p-type semiconductor layer 14, and to provide a semiconductor light-emitting device with improved external light emission efficiency by a reflective laminated film.

  A flip chip structure that is a path for extracting light from the GaN layer side to the outside through the sapphire substrate 10 is particularly effective in that the external light emission efficiency can be improved. From the simulation results, when the taper angle of 40 ° to 60 ° is set in the circular or lattice-like protective film 18 having a diameter of 5 μm, the light extraction efficiency is improved 1.5 times.

  A substrate in which a protective film 18 having a partially different refractive index is formed on a different substrate 10 is prepared, and a nitride-based semiconductor is directly epitaxially grown on the substrate to form a light emitting element. Unevenness can be formed at the substrate interface, light scattering / diffraction occurs, and not only the light extraction efficiency is improved, but also the quality of the epitaxial growth layer is improved.

(Crystal growth plane orientation)
FIG. 13 is a schematic diagram for explaining a crystal plane of a group III nitride semiconductor applied to the semiconductor light emitting device according to the first embodiment and its modification, and FIG. FIG. 13B is a schematic diagram for explaining the semipolar plane {10-11}, and FIG. 13C is a schematic diagram showing the c-plane, a-plane, and m-plane of the crystal structure of the group nitride semiconductor. FIG. 13D is a schematic diagram for explaining the semipolar plane {10-13}, and FIG. 13D is a schematic diagram showing a bond between a group III atom and a nitrogen atom.

  As shown in FIGS. 13A to 13D, the crystal structure of a group III nitride semiconductor can be approximated by a hexagonal system, and four nitrogen atoms are included in one group III atom. Are connected. The four nitrogen atoms are located at the four vertices of a regular tetrahedron with a group III atom arranged in the center. Of these four nitrogen atoms, one nitrogen atom is located in the + c axis direction with respect to the group III atom, and the other three nitrogen atoms are located on the −c axis side with respect to the group III atom. Due to such a structure, in the group III nitride semiconductor, the polarization direction is along the c-axis.

  The c-axis is along the axial direction of the hexagonal column, and the plane (the top surface of the hexagonal column) having the c-axis as a normal is the c-plane {0001}. When a group III nitride semiconductor crystal is cleaved by two planes parallel to the c plane, the + c axis side plane (+ c plane) becomes a crystal plane in which group III atoms are arranged, and the −c axis side plane (−c plane) ) Is a crystal plane with nitrogen atoms. For this reason, the c-plane is called a polar plane because it exhibits different properties on the + c-axis side and the −c-axis side.

  Since the + c plane and the −c plane are different crystal planes, different physical properties are exhibited accordingly. Specifically, it is known that the + c surface has high durability against chemical reactions such as resistance to alkali, and conversely, the −c surface is chemically weak and is soluble in alkali, for example.

  On the other hand, the side surfaces of the hexagonal columns are m-planes {10-10}, respectively, and the planes passing through a pair of ridge lines that are not adjacent to each other are a-planes {11-20}. Since these are crystal planes perpendicular to the c-plane and orthogonal to the polarization direction, they are nonpolar planes, that is, nonpolar planes. Furthermore, as shown in FIGS. 13B and 13C, crystal planes {10-11} and {10-13} that are inclined with respect to the c-plane (not parallel nor perpendicular) are Since it crosses diagonally with respect to the polarization direction, it is a slightly polar plane, that is, a semipolar plane. Specific examples of other semipolar planes are planes such as {10-1-1} plane, {10-1-3} plane, {11-22} plane.

  For example, a GaN single crystal substrate having an m-plane as a main surface can be produced by cutting from a GaN single crystal having a c-plane as a main surface. The m-plane of the cut substrate is polished by, for example, a chemical mechanical polishing process, and the orientation error with respect to both the [0001] direction and the [11-20] direction is within ± 1 ° (preferably ± 0.3 °). Within). In this way, a GaN single crystal substrate having an m-plane as a main surface is obtained.

  The semiconductor light emitting device according to the first embodiment can use each surface of the hexagonal crystal structure as a crystal main surface, and can form a semiconductor light emitting device by MOCVD or the like.

  In the semiconductor light emitting device according to the first embodiment and its modification, for example, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a non-polar plane with a hexagonal crystal structure as the main crystal growth. The pattern shape of the protective film 18 is preferably selected so that the lateral growth surface of the n-type semiconductor layer 12 is a nonpolar surface perpendicular to the nonpolar surface.

  Alternatively, in the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14, the m-plane of the hexagonal crystal structure is a main surface for crystal growth, and the lateral growth surface of the n-type semiconductor layer 12 is the above m-plane. The pattern shape of the protective film 18 may be selected so as to be an a-plane perpendicular to the plane.

  Alternatively, in the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14, the a-plane of the hexagonal crystal structure is a main surface for crystal growth, and the lateral growth surface of the n-type semiconductor layer 12 is the above-described a The pattern shape of the protective film 18 may be selected so that the m-plane is perpendicular to the plane.

  Alternatively, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a hexapolar structure semipolar plane as the main plane for crystal growth, and the lateral growth plane of the n-type semiconductor layer 12 is The pattern shape of the protective film 18 may be selected so as to be an a-plane or m-plane perpendicular to the semipolar plane.

  Alternatively, the n-type semiconductor layer 12, the active layer 13, and the p-type semiconductor layer 14 have a hexagonal crystal polar surface as a main surface for crystal growth, and the lateral growth surface of the n-type semiconductor layer 12 has an m-plane or The pattern shape of the protective film 18 may be selected so as to be the a-plane.

(Electrode structure)
As shown in FIG. 14, the semiconductor light emitting device according to the first embodiment includes n-side electrodes 200 and 300 that apply a voltage to the n-type semiconductor layer 12 and a p-side that applies a voltage to the p-type semiconductor layer 14. An electrode 100 is further provided. As shown in FIG. 14, the p-type semiconductor layer 14, the active layer 13, the block layer 17, and a partial region of the n-type semiconductor layer 12 are exposed on the n-type semiconductor layer 12 by mesa etching. An electrode 200 is disposed.

  The p-side electrode 100 is disposed on the p-type semiconductor layer 14 via the transparent electrode 15. Alternatively, the p-side electrode 100 may be disposed directly on the p-type semiconductor layer 14. The transparent electrode 15 disposed on the fourth nitride-based semiconductor layer 44 includes, for example, any of ZnO, ITO, or ZnO containing indium.

  The n-side electrodes 200 and 300 are, for example, an aluminum (Al) film, a multilayer film of Ti / Ni / Au or Al / Ti / Au, Al / Ni / Au, Al / Ti / Ni / Au, or Au—Sn from the upper layer. The p-side electrode 100 is made of, for example, an Al film, a palladium (Pd) -gold (Au) alloy film, a Ni / Ti / Au multilayer film, or an Au- It consists of a multilayer film of Sn / Ti / Au. The n-side electrodes 200 and 300 are ohmically connected to the n-type semiconductor layer 12, and the p-side electrode 100 is ohmically connected to the p-type semiconductor layer 14 via the transparent electrode 15.

  FIG. 15 shows that the height of the surface of the p-side electrode 100 and the surface of the n-side electrode 300 measured from the substrate 10 is substantially the same in order to mount the semiconductor light emitting device according to the first embodiment on the flip chip structure. It is formed to be high.

  The structure of FIG. 15 includes a structure in which a transparent conductive film ZnO is formed as the transparent electrode 15 and this ZnO is covered with a reflective laminated film 28 that reflects the wavelength λ of the emitted light.

The reflective laminated film 28 has a laminated structure of λ / 4n ₁ and λ / 4n ₂ (n ₁ and n ₂ are the refractive indices of the laminated layers). As a material used for the laminated structure, for example, a laminated structure made of ZrO ₂ (n = 2.12) and SiO ₂ (n = 1.46) can be used for blue light with λ = 450 nm. In this case, the thickness of each layer is, for example, about 53 nm for ZrO ₂ and about 77 nm for SiO ₂ . As another material for forming the laminated structure, TiO ₂ , Al ₂ O ₃ or the like can be used.

  According to the semiconductor light emitting device according to the first embodiment, the light emitted in the active layer 13 by the reflective laminated film 28 can be extracted outside from the substrate 10 side without being absorbed by the p-side electrode 100. Therefore, the external luminous efficiency can be improved.

  As described above, the flip chip structure that is a path for extracting light from the GaN layer side to the outside through the sapphire substrate 10 is particularly effective in that the external light emission efficiency can be improved. A substrate in which a protective film 18 having a partially different refractive index is formed on a different substrate 10 is prepared, and a nitride-based semiconductor is directly epitaxially grown on the substrate to form a light emitting element. Unevenness can be formed on the substrate interface, light scattering and diffraction occur, and light extraction efficiency is improved.

(Production method)
As shown in FIGS. 2 to 8, the method for manufacturing a semiconductor light emitting device according to the first embodiment includes a step of preparing a substrate 10, a step of forming a protective film 18 on the substrate 10, and a protective film 18. And exposing the substrate 10 and forming the n-type semiconductor layer 12 doped with n-type impurities on the exposed substrate 10 and the protective film 18 by lateral epitaxial growth. And a step of forming an active layer 13 on the n-type semiconductor layer 12 and a step of forming a p-type semiconductor layer 14 doped with a p-type impurity on the active layer 13.

  Further, after the step of exposing the substrate 10, the method further includes a step of forming the buffer layer 16 on the exposed substrate 10 sandwiched between the protective films 18.

  The step of forming the n-type semiconductor layer 12 by lateral epitaxial growth includes the step of forming at a first pressure and the step of forming at a second pressure higher than the first pressure during the lateral epitaxial growth. And have.

  Hereinafter, with reference to FIGS. 2 to 8, a method for manufacturing the semiconductor light emitting device according to the first embodiment will be described. The manufacturing method of the semiconductor light emitting element described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification. Here, an example in which a sapphire substrate is applied to the substrate 10 will be described.

(A) First, as shown in FIG. 2, a sapphire substrate 10 is prepared, a protective film 18 is formed on the sapphire substrate 10, and then patterned to expose the surface of the substrate 10.

  The protective film 18 is transparent to the emission wavelength, and the refractive index of the protective film 18 is a material that is substantially equal to the refractive index of the substrate 10, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, A titanium oxide film, an alumina film, or the like is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) such as sputtering.

  As the pattern size of the protective film 18, for example, the maximum width is about 10 μm, and the thickness is preferably about 100 nm or more and about 1 μm, for example. The shape of the protective film 18 is preferably a pattern shape that does not hinder lateral selective epitaxial growth (ELOG), such as a triangle, a rhombus, a hexagon, a circle, and a stripe. In particular, in order to perform ELOG, the direction of the pattern is selected in consideration of the a-plane and m-plane which are lateral growth planes. When light is extracted from the back surface of the substrate 10 or the upper surface of the epitaxial growth layer, irregularities are generated at the interface between the protective film 18 and the epitaxial growth layer, so that the light is scattered or diffracted and totally reflected by the refractive index difference between the epitaxial growth layer and the heterogeneous substrate interface. The light that has been emitted is efficiently extracted outside.

(B) Next, as shown in FIG. 3, an AlN buffer layer 16 is grown on the sapphire substrate 10 exposed by a well-known metal organic chemical vapor deposition (MOCVD) method or the like. For example, by supplying trimethylaluminum (TMA) and ammonia (NH ₃ ) to the reaction chamber using H ₂ gas as a carrier at a high temperature of about 900 ° C. to 950 ° C., the thickness is about 10 to 50 Å. A thin AlN buffer layer 16 is grown in a short time.

(C) Next, as shown in FIG. 4, a GaN layer to be the n-type semiconductor layer 12 is grown on the AlN buffer layer 16 by MOCVD or the like. For example, after the substrate 10 on which the AlN buffer layer 16 is formed is thermally cleaned, the substrate temperature is set to about 1000 ° C., and the n-type semiconductor layer 12 doped with n-type impurities on the AlN buffer layer 16 is set to 1 Grow about ~ 5 μm. As the n-type semiconductor layer 12, for example, a GaN film doped with Si as an n-type impurity at a concentration of about 3 × 10 ¹⁸ cm ⁻³ can be used. When adding Si as an impurity, trimethylgallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) are supplied as source gases to form the n-type semiconductor layer 12. As shown in FIG. 4, threading dislocations 20 are generated in the GaN layer that becomes the n-type semiconductor layer 12.

(D) Next, as shown in FIG. 5, the n-type semiconductor layer 12 is formed by lateral selective epitaxial growth (ELO). A lateral selective epitaxial growth layer is formed on the m-plane or a-plane which is the lateral selective epitaxial growth surface, and the n-type semiconductor layer 12 is selectively epitaxially grown in the lateral direction in the vectors LA and LB in FIG. As a result, the threading dislocations 20 are also bent, and the selective epitaxial growth surfaces from the left and right are merged in the vicinity of the central portion LO of the protective film 18, and the threading dislocations 20 are also connected at the same time.

  In order to fill the protective film 18, the epitaxial growth condition may be changed from the middle to a condition that promotes lateral growth. In order to promote the lateral growth, for example, the pressure of the gas system during crystal growth may be changed. As a first step, for example, after growth of about 1 μm at about 1050 ° C. and about 100 Torr, for example, about 1.5 μm can be grown at about 1050 ° C. and about 200 Torr, for example. By forming the n-type semiconductor layer 12 in this way, lateral growth can be promoted together with the effect of reducing threading dislocation density by ELO.

  Since the lateral growth (ELO) is performed so as to cover the protective film 18, the threading dislocations of the crystal can be bent, and the crystallinity is also improved.

  Furthermore, the pressure and growth temperature conditions for forming the n-type semiconductor layer 12 can be changed to divide into several steps. For example, as shown in FIG. 12 (121, 122, 123, 124) can also be formed. By doing so, the surface morphology of the n-type semiconductor layer 12 is improved, and the crystallinity can be improved.

For example, when the pattern of the protective film 18 is formed in a stripe shape, the stripe is in the <11-20> or <1-100> direction, the width of the protective film 18 is about 1 to 4 μm, and the repetition period is about, for example, about The thickness is about 7 μm. On top of this, GaN to be the n-type semiconductor layer 12 is grown at 1000 ° C. by HVPE. In the HVPE method, GaCl and NH ₃ are reacted to grow GaN. In the case where the stripe direction is <11-20>, the growth of GaN is first faceted in the opening of the protective film 18 by the {1-101} plane inclined with respect to the substrate surface by the growth in the first (0001) direction. A triangular cross-sectional shape is generated. Next, while maintaining the facet, the lateral growth on the protective film 18 proceeds until adjacent growth portions merge. After the coalescence, the growth proceeds so that the surface is further flattened, and a completely flat growth layer having a (0001) plane is obtained. In the pattern in which the stripe is in the <1-100> direction, the {11-22} plane is faceted, but a similar growth layer is obtained.

  The above example is an example, and other patterns and pattern directions are also applicable. In addition, in the above example, the example of the polar plane is described as the main plane of crystal growth, but a nonpolar plane or a semipolar plane can also be applied.

(E) Next, as the block layer 17 on the n-type semiconductor layer 12, a GaN film doped with Si at a concentration of less than 1 × 10 ¹⁷ cm ⁻³ , for example, about 8 × 10 ¹⁶ cm ⁻³ , for example, Grow about 200 nm. At this time, the same source gas as in the case of forming the n-type semiconductor layer 12 can be applied.

(F) Next, as shown in FIG. 7, the active layer 13 is formed on the n-type semiconductor layer 12. For example, the active layer 13 is formed by alternately laminating barrier layers 31 made of GaN films and well layers 32 made of InGaN films. Specifically, the barrier layer 31 and the well layer 32 are alternately and continuously grown while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 13, and the barrier layer 31 and the well layer 32 are laminated. An active layer 13 is formed. That is, the step of laminating the well layer 32 and the barrier layer 31 having a larger band gap than the well layer 32 by adjusting the substrate temperature and the flow rate of the source gas is defined as a unit step, and this unit step is repeated n times, for example, about 8 times. Thus, a stacked structure in which the barrier layers 31 and the well layers 32 are alternately stacked is obtained.

In the case of forming the barrier layer 31, for example, TMG gas and NH ₃ gas are supplied to the processing apparatus for film formation as source gases. On the other hand, when forming the well layer 32, for example, TMG gas, trimethylindium (TMI) gas, and NH ₃ gas are supplied to the processing apparatus as source gases. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, and NH ₃ gas is supplied as nitrogen atom source gas.

On the formed laminated structure, a non-doped GaN film of about 10 nm is formed as the final barrier layer 310 to form the active layer 13 shown in FIG. 1 or FIG. As already described, the film thickness d ₀ of the final barrier layer 310 is set to such a thickness that the p-type dopant diffused from the p-type semiconductor layer 14 to the active layer 13 does not reach the well layer 32 of the active layer 13.

(G) Next, as shown in FIG. 8, the substrate temperature is set to about 800 ° C. to 900 ° C., and the p-type semiconductor layer 14 doped with p-type impurities on the final barrier layer 310 is about 0.05 to 1 μm. Form.

The p-type semiconductor layer 14 is formed, for example, in a four-layer structure in which Mg is added as a p-type impurity. The first nitride-based semiconductor layer 41 disposed on the active layer 13 is formed of a p-type GaN layer having a thickness of about 2 × 10 ²⁰ cm ⁻³ and a thickness of about 50 nm, and the second nitride-based semiconductor layer 42 is formed. Is formed of a p-type GaN layer having a thickness of about 4 × 10 ¹⁹ cm ⁻³ and a thickness of about 100 nm. The third nitride semiconductor layer 43 has a thickness of about 1 × 10 ²⁰ cm ⁻³ and a thickness of about 40 nm, for example. The fourth nitride semiconductor layer 44 is formed of a p-type GaN layer having a thickness of about 8 × 10 ¹⁹ cm ⁻³ and a thickness of about 10 nm.

When Mg is added as an impurity, TMG gas, NH ₃ gas and biscyclopentadienyl magnesium (Cp ₂ Mg) gas are supplied as source gases to form the p-type semiconductor layers 14 (41 to 44). Mg is diffused from the p-type semiconductor layer 14 (41 to 44) to the active layer 13 during the formation of the p-type semiconductor layer 14 (41 to 44), but the final barrier layer 310 causes Mg to enter the well layer 32 of the active layer 13. It is prevented from spreading.

(H) Next, the transparent electrode 15 is formed on the p-type semiconductor layer 14 by vapor deposition, sputtering technique, or the like. As the transparent electrode 15, for example, any one of ZnO, ITO, or ZnO containing indium can be used. Further, an n-type impurity such as Ga or Al may be added at a high concentration up to about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ .

(I) Next, as shown in FIG. 9, after patterning the transparent electrode 15, a reflective laminated film 28 that reflects the wavelength λ of the emitted light is formed so as to cover the transparent electrode 15 by vapor deposition, sputtering technique, or the like. To do.

(J) Next, the reflective laminated film 28 and the middle of the p-type semiconductor layer 14 to the n-type semiconductor layer 12 are removed by mesa etching using an etching technique such as reactive ion etching (RIE). Then, the surface of the n-type semiconductor layer 12 is exposed.

(K) Next, n-side electrodes 200 and 300 are formed on the exposed surface of the n-type semiconductor layer 12 by vapor deposition, sputtering technique, or the like. Also on the transparent electrode 15 on the p-type semiconductor layer 14, the p-side electrode 100 is formed by vapor deposition or sputtering after pattern formation, and the semiconductor light emitting device shown in FIG. 9, FIG. 14 or FIG. 15 is completed. .

  According to the first embodiment, it is possible to provide a semiconductor light emitting device with improved external light emission efficiency and a method for manufacturing the same.

[Second Embodiment]
(Element structure)
As shown in FIG. 16A, the semiconductor light emitting device according to the second embodiment of the present invention is disposed on the substrate 10, the AlN buffer layer 16 disposed on the substrate 10, and the AlN buffer layer 16. And an n-type semiconductor layer 25 composed of an Al _x Ga _1-x N layer (0 <x <1) doped with an n-type impurity, and disposed on the n-type semiconductor layer 25, and Al _x Ga _1-x A barrier layer composed of an N layer (0 <x <1) and a well layer composed of an Al _x In _y Ga _1-xy N layer (0 <x ≦ y <1, 0 <x + y <1) having a smaller band gap than the barrier layer Active layer 60 having a multi-quantum well having a laminated structure in which Al is alternately arranged, and an Al _x Ga _1-x N layer (0 ≦ x <1) arranged on active layer 60 and doped with p-type impurities. And a p-type semiconductor layer 80.

As shown in FIG. 16B, the active layer 60 has a band gap formed by barrier layers 611 to 61n and 610 made of Al _x Ga _1-x N layers (0 <x <1) and barrier layers 611 to 61n and 610. Has a stacked structure in which well layers 621 to 62n composed of Al _x In _y Ga _1-xy N layers (0 <x ≦ y <1, 0 <x + y <1) are alternately arranged. Hereinafter, the first barrier layer 611 to the nth barrier layer 61n included in the active layer 60 are collectively referred to as “barrier layer 61”. Also, all well layers included in the active layer 60 are collectively referred to as “well layers 62”.

  The film thickness of the final barrier layer 610 as the uppermost layer in the stacked structure is thicker than the thicknesses of the other barrier layers (the first barrier layer 611 to the nth barrier layer 61n) included in the stacked structure other than the final barrier layer 610. It may be formed.

  In the semiconductor light emitting device shown in FIG. 16, the concentration of the p-type dopant in the final barrier layer 610 extends from the first main surface of the final barrier layer 610 in contact with the p-type semiconductor layer 80 along the film thickness direction of the final barrier layer 610. There is no p-type dopant on the second main surface that gradually decreases and faces the first main surface.

  As the substrate 10, for example, a c-plane (0001), 0.25 ° off sapphire substrate or the like can be used. The n-type semiconductor layer 25, the active layer 60, and the p-type semiconductor layer 80 are each made of an AlGaN layer, and the buffer layer 16, the n-type nitride semiconductor layer 2, the n-type contact layer 19, the active layer 60 and the p-type are formed on the substrate 10. The type semiconductor layers 80 are sequentially stacked.

(AlN buffer layer)
The buffer layer 16 is formed of, for example, an AlN layer having a thickness of about 10 to 50 angstroms. When the AlN buffer layer 16 is crystal-grown, for example, it is grown at a high temperature in the temperature range of about 900 ° C. to 950 ° C.

By supplying trimethylaluminum (TMA) and ammonia (NH ₃ ) to the reaction chamber using H ₂ gas as a carrier, a thin AlN buffer layer 16 having a thickness of about 10 to 50 Å can be grown at a high speed. And can be formed while maintaining good crystallinity.

(N-type semiconductor layer)
As shown in FIG. 16A, the n-type semiconductor layer 25 is disposed on the AlN buffer layer 16 and is formed from an Al _x Ga _1-x N layer (0 <x <1) doped with an n-type impurity. N-type nitride-based semiconductor layer 2 and n-type nitride-based semiconductor layer 2 and an Al _x Ga _1-x N layer (0 <x <1) doped with n-type impurities. A mold contact layer 19.

  The n-type nitride semiconductor layer 2 is doped with an n-type impurity such as silicon (Si), and the film thickness is, for example, about 1 to 6 μm.

  The n-type nitride semiconductor layer 2 supplies electrons to the active layer 60, and the p-type semiconductor layer 80 supplies holes (holes) to the active layer 60. Light is generated by the recombination of the supplied electrons and holes in the active layer 60.

According to the semiconductor light emitting device according to the second embodiment, the Al _x Ga _1-x N layer (0 <x <1) having the lattice constant relatively close to the AlN layer is formed on the high temperature AlN buffer layer 16. Thus, the crystallinity and surface morphology of the n-type semiconductor layer 25 can be improved, and the transparency to the emission wavelength can be improved.

(Active layer)
As shown in FIG. 16B, the active layer 60 includes a first barrier layer 611 to an nth barrier layer 61 n and a final barrier layer 610 each made of an Al _x Ga _1-x N layer (0 <x <1). Multiple quantum well (MQW) structure having a first well layer 621 to an n-th well layer 62n composed of sandwiched Al _x In _y Ga _1-xy N layers (0 <x ≦ y <1, 0 <x + y <1) (N: natural number). In other words, the active layer _{60, Al x In y Ga 1-} xy N layer (0 <x ≦ y <1 , 0 <x + y <1) well layer 62 made of a band gap than the well layer 62 large Al _x Ga _A quantum well structure sandwiched between barrier layers 61 composed of _1-x N layers (0 <x <1) is used as a unit pair structure, and this unit pair structure is stacked n times.

  Specifically, the first well layer 621 is disposed between the first barrier layer 611 and the second barrier layer 612, and the second well layer 622 is disposed between the second barrier layer 612 and the third barrier layer 613. The The nth well layer 62n is disposed between the nth barrier layer 61n and the final barrier layer 610. The first barrier layer 611 of the active layer 60 is disposed on the n-type nitride-based semiconductor layer 2 via the n-type contact layer 19, and the p-type semiconductor layer 80 (21 on the final barrier layer 610 of the active layer 60). , 22, 81-84) are arranged.

In addition, the first barrier layer 611 to the nth barrier layer 61n made of an Al _x Ga _1-x N layer (0 <x <1), the first barrier layer 611 to the nth barrier layer 61n, and the final barrier layer 610, respectively. Each of the first well layer 621 to the n-th well layer 62n composed of sandwiched Al _x In _y Ga _1-xy N layers (0 <x ≦ y <1, 0 <x + y <1) contains n-type impurities. Impurities may be added. For example, Si atoms may be added as n-type impurities, for example, about 5 × 10 ¹⁶ impurities.

  In addition, the number of pairs of multiple quantum well layers is, for example, 2 to 8. The indium (In) ratio {y / (1-xy)} of the well layers 621 to 62n is appropriately set according to the wavelength of light to be generated.

  For example, the In composition ratio y is about 0.15, and the Al composition ratio is about 0.01 to 0.1, for example.

  The thickness of the well layers 621 to 62n is, for example, about 2-3 nm, preferably about 2.8 nm, and the thickness of the barrier layers 611-61n is about 7-18 nm, preferably about It is about 16.5 nm.

  In the semiconductor light emitting device according to the second embodiment, the active layer for efficiently recombining the electrons supplied from the n-type semiconductor layer 25 and the holes supplied from the p-type semiconductor layer 80 in the active layer 60. The number of MQW pairs in 60 can be optimized.

In the semiconductor light emitting device according to the second embodiment, the active layer 60 includes a well layer 62 made of an Al _x In _y Ga _1-xy N layer (0 <x ≦ y <1, 0 <x + y <1). A barrier comprising an Al _x Ga _1-x N layer (0 <x <1) having a larger band gap than the Al _x In _y Ga _1-xy N layer (0 <x ≦ y <1, 0 <x + y <1) Since the layer 61 is provided, it is possible to improve the transparency with respect to the emission wavelength and to improve the resistance against thermal damage to the subsequent high-temperature process.

(Final barrier layer)
The final barrier layer 610 is formed thicker than the Mg diffusion distance from the p-type semiconductor layer 80 to the active layer 60.

  In the semiconductor light emitting device shown in FIG. 16, the concentration of the p-type impurity in the final barrier layer 610 extends from the first main surface of the final barrier layer 610 in contact with the p-type semiconductor layer 80 along the film thickness direction of the final barrier layer 610. The p-type impurity is substantially absent in the second main surface that gradually decreases and faces the first main surface.

The film thickness d ₀ of the final barrier layer 610 of the semiconductor light emitting device shown in FIG. 16 is such that the p-type impurity diffused from the p-type semiconductor layer 80 to the active layer 60 in the step of forming the p-type semiconductor layer 80 and the subsequent steps is It is set so as not to reach the well layer 62 of the active layer 60. That is, the p-type impurity diffused from the p-type semiconductor layer 80 to the final barrier layer 610 is a second main surface (the final barrier layer 610 is a well) facing the first main surface of the final barrier layer 610 in contact with the p-type semiconductor layer 80. The film thickness d ₀ is set to a thickness that does not reach the surface contacting the layer 62n.

The Mg concentration on the first main surface of the final barrier layer 610 in contact with the p-type semiconductor layer 80 is, for example, about 2 × 10 ²⁰ cm ⁻³ , and the second concentration of the final barrier layer 610 facing the first main surface is about 2 × 10 ²⁰ cm ⁻³ . The Mg concentration gradually decreases toward the main surface, and the Mg concentration does not have an influence of less than about 10 ¹⁶ cm ^{−3 at a} distance of about 7 to 8 nm from the first main surface, and is below the detection lower limit in the analysis. Become.

That is, by setting the film thickness d ₀ of the final barrier layer 610 to about 10 nm, Mg does not diffuse to the second main surface of the final barrier layer 610, and therefore the first barrier layer 610 in contact with the active layer 60 is not diffused. 2 Mg does not exist on the main surface. That is, Mg does not diffuse into the n-th well layer 62n, and a reduction in the luminance of light generated in the active layer 60 is prevented.

The film thicknesses d1 to dn of the first barrier layer 611 to the nth barrier layer 61n may be the same. However, the thicknesses d1 to dn are such that holes injected from the n-type semiconductor layer 25 into the active layer 60 reach the n-th well layer 62n, and light is emitted by recombination of electrons and holes in the n-th well layer 62n. It is necessary to set a thickness that can be generated. This is because if the film thicknesses d1 to dn of the first barrier layer 611 to the nth barrier layer 61n are too thick, the movement of holes in the active layer 60 is hindered and the light emission efficiency is lowered. For example, the film thickness d ₀ of the final barrier layer 610 is about 10 nm, the film thicknesses d ₁ to dn of the first barrier layer 611 to the n-th barrier layer 61 n are about 7 to 18 nm, and the first well layers 621 to 621 The film thickness of the nth well layer 62n is about 2 to 3 nm.

As described above, in the semiconductor light emitting device according to the second embodiment, the film thickness d ₀ of the final barrier layer 610 in contact with the p-type semiconductor layer 80 diffuses from the p-type semiconductor layer 80 to the active layer 60. The thickness is set such that the p-type impurity does not reach the well layer 62 of the active layer 60. That is, according to the semiconductor light emitting device shown in FIG. 16, by setting the film thickness d ₀ of the final barrier layer 610 to be larger than the Mg diffusion distance, the increase in the film thickness of the entire active layer 60 is suppressed, while p. The diffusion of p-type impurities from the type semiconductor layer 80 to the well layer 62 of the active layer 60 can be prevented. As a result, it is possible to manufacture a semiconductor light emitting device in which the light luminance is not lowered due to the diffusion of the p-type impurity into the well layer 62 and the deterioration of the quality of the semiconductor light emitting device is suppressed.

(P-type semiconductor layer)
The p-type semiconductor layer 80 is formed of an Al _x Ga _1-x N layer (0 ≦ x <1) having a thickness of about 0.05 to ₁ μm doped with p-type impurities. As the p-type impurity, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like can be used.

A configuration example of the p-type semiconductor layer 80 is as follows in more detail. That is, as shown in FIG. 16A, the p-type semiconductor layer 80 is disposed on the active layer 60 and is an Al _x Ga _1-x N layer (0 ≦ x <1) doped with p-type impurities. ), An electron cap layer 22 formed on the electron barrier layer 21 and made of an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity, A first nitride-based semiconductor layer 81 which is disposed on the cap layer 22 and includes an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity; and a first nitride-based semiconductor layer A second layer comprising an Al _x Ga _1-x N layer (0 ≦ x <1), which is disposed on 81 and doped with a p-type impurity having a lower concentration than the p-type impurity of the first nitride-based semiconductor layer 81. The nitride-based semiconductor layer 82 and the second nitride-based semiconductor layer 82 are disposed on the second nitride-based semiconductor layer 82. A third nitride-based semiconductor layer 83 made of an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a higher concentration of p-type impurities, and a third nitride-based semiconductor layer 83 A fourth nitride system comprising an Al _x Ga _1-x N layer (0 ≦ x <1) disposed and doped with a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 83 And a semiconductor layer 84.

  The second nitride-based semiconductor layer 82 is formed to be thicker than the first nitride-based semiconductor layer 81 or the third nitride-based semiconductor layer 83 to the fourth nitride-based semiconductor layer 84.

Here, the material and thickness of each layer will be specifically described. The first nitride-based semiconductor layer 81 containing p-type impurities disposed on the active layer 60 is, for example, p-type having a thickness of about 1.3 × 10 ²⁰ cm ⁻³ and a thickness of about 40 nm doped with Mg. An Al _x Ga _1-x N layer (0 ≦ x <1) is formed.

The second nitride-based semiconductor layer 82 disposed on the first nitride-based semiconductor layer 81 and containing a p-type impurity having a lower concentration than the p-type impurity of the first nitride-based semiconductor layer 81 is doped with, for example, Mg. The p-type Al _x Ga _1-x N layer (0 ≦ x <1) having a thickness of about 2.7 × 10 ¹⁹ cm ⁻³ and a thickness of about 90 nm is formed.

The third nitride semiconductor layer 83 disposed on the second nitride semiconductor layer 82 and containing a p-type impurity at a higher concentration than the p-type impurity of the second nitride semiconductor layer 82 is doped with, for example, Mg. The p-type Al _x Ga _1-x N layer (0 ≦ x <1) having a thickness of about 1.2 × 10 ²⁰ cm ⁻³ and a thickness of about 20 nm is formed.

The fourth nitride semiconductor layer 84 disposed on the third nitride semiconductor layer 83 and containing a p-type impurity at a lower concentration than the p-type impurity of the third nitride semiconductor layer 83 is doped with, for example, Mg. The p-type Al _x Ga _1-x N layer (0 ≦ x <1) having a thickness of less than about 5 × 10 ¹⁹ cm ⁻³ and a thickness of about 5 nm is formed. The fourth nitride semiconductor layer 84 functions as a p-type contact layer.

In the semiconductor light emitting device according to the second embodiment, the p-type semiconductor layer 80 formed on the active layer 60 has a p-type Al _x Ga _{1-x having a} four-layer structure with different Mg concentrations as described above. It consists of N layers (0 ≦ x <1) and is doped at the above concentrations. The p-type Al _x Ga _1-x N layer (0 ≦ x <1) is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 60.

  The first nitride-based semiconductor layer 81 closest to the active layer 60 has a higher emission intensity as the Mg concentration is higher. Therefore, the higher the Mg concentration, the better.

The second nitride semiconductor layer 82 has a Mg concentration of about 10 ¹⁹ cm ⁻³ , since crystal defects due to Mg increase and the resistance of the film increases when Mg is excessively doped. It is desirable.

  Since the third nitride semiconductor layer 83 is a layer that determines the amount of holes injected into the active layer 60, it is desirable that the third nitride semiconductor layer 83 have a slightly higher Mg concentration than the second nitride semiconductor layer 82.

As shown in FIG. 17, the fourth nitride semiconductor layer 84 is a p-type AlGaN layer for making ohmic contact with the transparent electrode 15, and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al is used as the transparent electrode 15, Mg when the forward voltage V _f of the semiconductor light emitting element is lowered most is used. Mg is added to the fourth nitride-based semiconductor layer 84 so as to have a concentration.

When the p-type Al _x Ga _1-x N layer (0 ≦ x <1) is grown, the third nitride-based semiconductor layer 83 and the fourth nitride-based semiconductor layer 84 close to the p-side electrode 100 are formed in the film. Since the hole concentration needs to be increased, the amount of H ₂ gas in the carrier gas is increased. The first nitride semiconductor layer 81 and the second nitride semiconductor layer 82 close to the active layer 60 do not need to increase the amount of H ₂ gas in the carrier gas, and the active layer 60 is made of N ₂ carrier gas. The crystal is grown by the extension of the growth. When these p-type Al _x Ga _1-x N layers (0 ≦ x <1) are grown, a film having lower resistance can be grown by increasing the V / III ratio as much as possible. The forward voltage (V _f ) can be lowered.

According to the semiconductor light emitting device according to the second embodiment, a low temperature to form a p-type semiconductor layer to reduce the thermal damage to the active layer, the wider the p-type semiconductor layer having a band gap than the GaN layer Al _x By forming the Ga _1-x N layer (0 ≦ x <1), it is possible to improve the transparency with respect to the emission wavelength, reduce the forward voltage (V _f ), and improve the luminous efficiency.

(Electrode structure)
As shown in FIGS. 17 and 18, the semiconductor light emitting device according to the second embodiment includes an n-side electrode 200 that applies a voltage to the n-type semiconductor layer 25, and a p that applies a voltage to the p-type semiconductor layer 80. A side electrode 100 is further provided. As shown in FIG. 17, the n-side electrode 200 is disposed on the surface of the n-type contact layer 19 exposed by mesa etching of the p-type semiconductor layer 80, the active layer 60, and a partial region of the n-type contact layer 19. Is done.

  The p-side electrode 100 is disposed on the p-type semiconductor layer 80 via the transparent electrode 15. Alternatively, the p-side electrode 100 may be disposed directly on the p-type semiconductor layer 80. Alternatively, the p-side electrode 100 may be disposed on an opening that is opened with respect to the transparent electrode 15.

  The transparent electrode 15 disposed on the fourth nitride semiconductor layer 84 includes, for example, any of ZnO, ITO, or ZnO containing indium.

  The n-side electrode 200 includes, for example, an Al film, Ti / Au / Ni film, Al / Ti / Au film, Al / Ni / Au film, Al / Ti / Ni / Au film, Al / Ni / Ti / Au film, Al / Ni / Ti / Ni / Au film or a multilayer film of Au-Sn / Au / Ti / Ni / Al film and Au-Sn / Au / Ni / Ti / Ni / Al film from the upper layer.

  The p-side electrode 100 is, for example, an Al film, a palladium (Pd) -gold (Au) alloy film, a Ni / Ti / Au film, a Ti / Au / Ti / Au film, a Ti / Au / Ni / Ti / Ni / Au film. , A multilayer film of Ti / Ni / Au / Ti / Ni / Au film, or from the upper layer, Au-Sn / Ti / Au film, Au-Sn / Au film, Au-Sn / Au / Ti / Au / Ti film, Au -It consists of a multilayer film of Sn / Au / Ni / Ti / Ni / Au / Ti film and Au-Sn / Au / Ni / Ti / Au / Ni / Ti film. The n-side electrode 200 is ohmically connected to the n-type semiconductor layer 25, and the p-side electrode 100 is ohmically connected to the p-type semiconductor layer 80 via the transparent electrode 15.

  FIG. 19 shows that the n-side electrode 300 is further formed on the n-side electrode 200 in order to mount the semiconductor light emitting device according to the second embodiment on the flip chip structure, and the surface of the p-side electrode 100 and the n-side are formed. The surface of the electrode 300 is formed so that the height measured from the substrate 10 is substantially the same.

  The structure of FIG. 19 includes a structure in which a transparent conductive film ZnO is formed as the transparent electrode 15 and this ZnO is covered with a reflective laminated film 28 that reflects the wavelength λ of the emitted light.

  Further, the transparent electrode 15 may be covered with an insulating film and further covered with a reflective laminated film 28 that reflects the wavelength λ of light emitted from the insulating film.

The reflective laminated film 28 has a laminated structure of λ / 4n ₁ and λ / 4n ₂ (n ₁ and n ₂ are the refractive indices of the laminated layers). As a material used for the laminated structure, for example, a laminated structure made of ZrO ₂ (n = 2.12) and SiO ₂ (n = 1.46) can be used for blue light with λ = 450 nm. In this case, the thickness of each layer is, for example, about 53 nm for ZrO ₂ and about 77 nm for SiO ₂ . As another material for forming the laminated structure, TiO ₂ , Al ₂ O ₃ or the like can be used.

  According to the semiconductor light emitting device according to the second embodiment, the light emitted in the active layer 30 by the reflective laminated film 28 can be extracted outside from the substrate 10 side without being absorbed by the p-side electrode 100. Therefore, the external luminous efficiency can be improved.

  A flip chip structure that provides a path for extracting light from the AlGaN layer side to the outside through the sapphire substrate 10 is particularly effective in that the external light emission efficiency can be improved. A substrate on which a protective film having a different refractive index is partially formed on a different substrate 10 is prepared, and an AlGaN layer is epitaxially grown on the substrate 10 on the substrate 10 to form a light emitting element, thereby forming an epitaxial growth layer-substrate interface. Unevenness can be formed, light scattering / diffraction occurs, and light extraction efficiency can be improved.

  According to the semiconductor light emitting device according to the second embodiment, Al is added to the n-type semiconductor layer 25, the active layer 60, and the p-type semiconductor layer 80 to reduce thermal damage and improve the transmittance with respect to the emission wavelength. In addition, since the light emitted in the active layer 60 by the reflective laminated film 28 can be extracted outside without being absorbed by the p-side electrode 100, the external light emission efficiency can be improved.

(Production method)
Hereinafter, an example of a method for manufacturing the semiconductor light emitting device according to the second embodiment shown in FIG. 16 will be described. In addition, the manufacturing method of the semiconductor light emitting element described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification. Here, an example in which a sapphire substrate is applied to the substrate 10 will be described.

(A) First, an AlN buffer layer 16 is grown on the sapphire substrate 10 exposed by a well-known metal organic chemical vapor deposition (MOCVD) method or the like. For example, by supplying trimethylaluminum (TMA) and ammonia (NH ₃ ) to the reaction chamber using H ₂ gas as a carrier at a high temperature of about 900 ° C. to 950 ° C., the thickness is about 10 to 50 Å. A thin AlN buffer layer 16 is grown in a short time.

(B) Next, the n-type nitride semiconductor layer 2 doped with n-type impurities is grown on the AlN buffer layer 16 by MOCVD or the like. For example, after thermally cleaning the substrate 10 on which the AlN buffer layer 16 is formed, the substrate temperature is set to about 1000 ° C., and an Al _x Ga _1-x N doped with an n-type impurity on the AlN buffer layer 16. An n-type nitride semiconductor layer 2 composed of layers (0 <x <1) is grown to about 1 to 5 μm. The n-type nitride semiconductor layer 2 is doped with, for example, Si as an n-type impurity at a concentration of about 3 × 10 ¹⁸ cm ⁻³ . When Si is added as an impurity, trimethylgallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) are supplied as source gases to form an n-type Al _x Ga _1-x N layer (0 <x <1). Form.

(C) Next, an n-type contact layer 19 is formed on the n-type nitride semiconductor layer 2 to a thickness of, for example, about 1550 nm. The n-type contact layer 19 is doped with, for example, Si as an n-type impurity at a concentration of about 3 × 10 ¹⁸ cm ⁻³ .

(D) Next, the active layer 60 is formed on the n-type semiconductor layer 25 (2, 19). For example, a barrier layer 61 composed of an Al _x Ga _1-x N layer (0 <x <1) and an Al _x In _y Ga _1-xy N layer (0 <x ≦ y <1, 0 <x + y <1). The active layers 60 are formed by alternately stacking the well layers 62. Specifically, the barrier layer 61 and the well layer 62 are alternately grown continuously while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 60, and the barrier layer 61 and the well layer 62 are laminated. Thus, an active layer 60 is formed. That is, the step of laminating the well layer 62 and the barrier layer 61 having a larger band gap than the well layer 62 by adjusting the substrate temperature and the flow rate of the source gas is defined as a unit step, and this unit step is repeated n times, for example, about 8 times. Thus, a laminated structure in which the barrier layers 61 and the well layers 62 are alternately laminated is obtained.

When the barrier layer 61 is formed, for example, TMG gas, TMA gas, and NH ₃ gas are supplied as source gases to the film forming processing apparatus. On the other hand, when forming the well layer 62, for example, TMG gas, TMA gas, trimethylindium (TMI) gas, and NH ₃ gas are supplied to the processing apparatus as source gases. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, TMA gas is supplied as Al atom source gas, and NH ₃ gas is supplied as nitrogen atom source gas.

On the formed laminated structure, a non-doped Al _x Ga _1-x N layer (0 <x <1) is formed as a final barrier layer 610 to a thickness of about 10 nm, and the active layer 60 shown in FIG. 16 or FIG. 17 is formed. Is done. As already described, the film thickness d ₀ of the final barrier layer 610 is set to such a thickness that the p-type dopant diffused from the p-type semiconductor layer 80 to the active layer 60 does not reach the well layer 62 of the active layer 60.

(E) Next, the substrate temperature is set to about 800 ° C. to 900 ° C., and a p-type semiconductor layer 80 doped with p-type impurities is formed on the final barrier layer 610 by about 0.05 to 1 μm.

When adding Mg as a p-type impurity, TMG gas, TMA gas, NH ₃ gas and biscyclopentadienylmagnesium (Cp ₂ Mg) gas are supplied as source gases, and the p-type semiconductor layer 80 (21 , 22, 81-84). Mg is diffused from the p-type semiconductor layer 80 to the active layer 60 when the p-type semiconductor layer 80 is formed, but the final barrier layer 610 prevents Mg from diffusing into the well layer 62 of the active layer 60.

(F) Next, the transparent electrode 15 is formed on the p-type semiconductor layer 80 by vapor deposition, sputtering technique, or the like. As the transparent electrode 15, for example, any one of ZnO, ITO, or ZnO containing indium can be used. Further, an n-type impurity such as Ga or Al may be added at a high concentration up to about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ .

(G) Next, after patterning the transparent electrode 15, a reflective laminated film 28 that reflects the wavelength λ of the emitted light is formed so as to cover the transparent electrode 15 by vapor deposition, sputtering technique, or the like.

(H) Next, the reflective laminated film 28 and the middle of the p-type semiconductor layer 80 to the n-type semiconductor layer 25 are removed by mesa etching using an etching technique such as reactive ion etching (RIE). Then, the surface of the n-type contact layer 19 is exposed.

(I) Next, n-side electrodes 200 and 300 are formed on the exposed surface of the n-type contact layer 19 by vapor deposition, sputtering technique, or the like. Also on the transparent electrode 15 on the p-type semiconductor layer 80, the p-side electrode 100 is formed by vapor deposition, sputtering technique or the like after pattern formation, and the semiconductor light emitting device shown in FIG. 17 or FIG. 19 is completed.

(Modification)
As a modification of the second embodiment, as a p-type semiconductor layer 80 disposed above the active layer 60, Al _x Ga ₁₋ doped with a p-type impurity is disposed above the active layer 60. _An electron barrier layer 21 composed of an xN layer (0 ≦ x <1), and an Al _x Ga _1-x N layer (0 ≦ x <1) disposed on the electron barrier layer 21 and doped with a p-type impurity An electron cap layer 22, a third nitride semiconductor layer 83 disposed on the electron cap layer 22 and containing p-type impurities, and a third nitride semiconductor disposed on the third nitride semiconductor layer 83. A structure including the fourth nitride semiconductor layer 84 containing a p-type impurity having a lower concentration than the p-type impurity of the layer 83 may be provided.

The third nitride semiconductor layer 83 is a p-type Al _x Ga _1-x N layer (0 ≦ x <1) doped with Mg, for example, having an impurity content of about 1.2 × 10 ²⁰ cm ⁻³ and a thickness of about 20 nm. ).

The fourth nitride semiconductor layer 84 disposed on the third nitride semiconductor layer 83 and containing a p-type impurity at a lower concentration than the p-type impurity of the third nitride semiconductor layer 83 is doped with, for example, Mg. The p-type Al _x Ga _1-x N layer (0 ≦ x <1) having a thickness of less than about 5 × 10 ¹⁹ cm ⁻³ and a thickness of about 5 nm is formed.

In the semiconductor light emitting device according to the modification of the second embodiment, the p-type semiconductor layer 80 formed on the active layer 60 has a p-type Al _x Ga ₁₋ structure with a different Mg concentration as described above. _It consists of _xN layers (0 ≦ x <1) and is doped at the above concentrations. The p-type Al _x Ga _1-x N layer (0 ≦ x <1) is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 60.

  Since the third nitride semiconductor layer 83 is a layer that determines the amount of holes injected into the active layer 60, the higher the Mg concentration, the higher the emission intensity. For this reason, the higher the Mg concentration, the better.

The fourth nitride-based semiconductor layer 84 is a p-type Al _x Ga _1-x N layer (0 ≦ x <1) for making ohmic contact with the transparent electrode 15 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al is used as the transparent electrode 15, Mg when the forward voltage V _f of the semiconductor light emitting element is lowered most is used. Mg is added to the fourth nitride-based semiconductor layer 84 so as to have a concentration.

  Also in the semiconductor light emitting device according to the modification of the second embodiment, the AlN buffer layer 16, the n-type semiconductor layer 25, the active layer 60, the p-type semiconductor layer 80 (20, 21, 83, 84), and the final barrier layer 610. Since the reflective laminated film 28 and the electrode structure are the same as those of the semiconductor light emitting device according to the second embodiment, description thereof will be omitted.

  According to the semiconductor light emitting device according to the second embodiment and its modification, Al is added to all layers of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer to reduce thermal damage and to reduce the emission wavelength. Therefore, it is possible to provide a semiconductor light emitting device with improved external light emission efficiency and a method for manufacturing the same.

[Third embodiment]
(Element structure)
As shown in FIG. 20A, the semiconductor light emitting device according to the third embodiment of the present invention includes a substrate 10, a protective film 18 disposed on the substrate 10, and a substrate sandwiched between the protective films 18. 10 and an AlN buffer layer 16 disposed on the AlN buffer layer 16 and the protective film 18, and an Al _x Ga _1-x N layer (0 <x <1) doped with an n-type impurity. An n-type semiconductor layer 25, and a barrier layer made of an Al _x Ga _1-x N layer (0 <x <1) and Al _x In _y Ga having a smaller band gap than the barrier layer. An active layer 60 composed of multiple quantum wells having a stacked structure in which well layers composed of _1-xy N layers (0 <x ≦ y <1, 0 <x + y <1) are alternately disposed, and disposed on the active layer 60 is, Al _x Ga _1-x N layer p-type impurity is added impurity (0 ≦ x <1) made of p-type half And a body layer 80.

As shown in FIG. 20B, the active layer 60 has a band gap formed by barrier layers 611 to 61n and 610 composed of Al _x Ga _1-x N layers (0 <x <1) and barrier layers 611 to 61n and 610. Has a stacked structure in which well layers 621 to 62n composed of Al _x In _y Ga _1-xy N layers (0 <x ≦ y <1, 0 <x + y <1) are alternately arranged.

(Electrode structure)
As shown in FIG. 21, the semiconductor light emitting device according to the third embodiment includes an n-side electrode 200 that applies a voltage to the n-type semiconductor layer 25 and a p-side electrode 100 that applies a voltage to the p-type semiconductor layer 80. Is further provided. As shown in FIG. 21, the n-side electrode 200 is disposed on the surface of the n-type contact layer 19 exposed by mesa etching of the p-type semiconductor layer 80, the active layer 60, and a partial region of the n-type contact layer 19. Is done.

  FIG. 22 shows that the n-side electrode 300 is further formed on the n-side electrode 200 in order to mount the semiconductor light emitting device according to the third embodiment in a flip chip structure, and the surface of the p-side electrode 100 and the n-side are formed. The surface of the electrode 300 is formed so that the height measured from the substrate 10 is substantially the same.

  The structure of FIG. 22 includes a structure in which a transparent conductive film ZnO is formed as the transparent electrode 15 and this ZnO is covered with a reflective laminated film 28 that reflects the wavelength λ of the emitted light.

  Further, the transparent electrode 15 may be covered with an insulating film and further covered with a reflective laminated film 28 that reflects the wavelength λ of light emitted from the insulating film.

(Production method)
A method of manufacturing a semiconductor light emitting device according to a third embodiment includes a step of forming a protective film on a substrate, a step of forming an AlN buffer layer on the substrate sandwiched between the protective films, and an AlN buffer layer A step of forming an n-type semiconductor layer made of an Al _x Ga _1-x N layer doped with an n-type impurity (0 <x <1) on the protective film; _A barrier layer composed of _x Ga _1-x N layer (0 <x <1) and an Al _x In _y Ga _1-xy N layer (0 <x ≦ y <1, 0 <x + y <) whose band gap is smaller than that of the barrier layer 1) a step of forming an active layer composed of multiple quantum wells having a laminated structure in which well layers composed of 1) are alternately formed, and an Al _x Ga _1-x N layer doped with a p-type impurity on the active layer Forming a p-type semiconductor layer made of (0 ≦ x <1).

  According to the semiconductor light emitting device according to the third embodiment, Al is added to all layers of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer to reduce thermal damage and to have transparency to the emission wavelength. Thus, it is possible to provide a semiconductor light emitting device with improved external light emission efficiency and a method for manufacturing the same.

[Other embodiments]
As described above, the present invention has been described with reference to the first to third embodiments and the modifications thereof. However, the discussion and the drawings that form a part of this disclosure are exemplary and limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

In the description of the embodiment already described, the barrier layer 31 composed of the Al _x Ga _1-x N layer (0 <x <1) and the Al _x In _y Ga _1-xy N having a smaller band gap than the barrier layer 31. Although an example of the active layer 30 composed of multiple quantum wells having a stacked structure in which the well layers 32 composed of layers (0 <x ≦ y <1, 0 <x + y <1) are alternately arranged is shown, One well layer 32 composed of an Al _x In _y Ga _1-xy N layer (0 <x ≦ y <1, 0 <x + y <1) is included, and is disposed between the well layer 32 and the p-type semiconductor layer 40. The final barrier layer 310 may have a structure in which the film thickness d ₀ is thicker than the Mg diffusion distance.

  As described above, the present invention includes various embodiments that are not described herein.

  The semiconductor light emitting device of the present invention can be used for all nitride semiconductor devices such as LED devices and LD devices having a quantum well structure.

BRIEF DESCRIPTION OF THE DRAWINGS It is a semiconductor light-emitting device concerning the 1st Embodiment of this invention, Comprising: (a) Typical sectional structure drawing of semiconductor light-emitting device, (b) Typical plane pattern block diagram. FIG. 3 is a schematic cross-sectional structure diagram for explaining one step of the method for manufacturing the semiconductor light emitting element according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining one step of the method for manufacturing the semiconductor light emitting element according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining one step of the method for manufacturing the semiconductor light emitting element according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining one step of the method for manufacturing the semiconductor light emitting element according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining one step of the method for manufacturing the semiconductor light emitting element according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining one step of the method for manufacturing the semiconductor light emitting element according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram for explaining one step of the method for manufacturing the semiconductor light emitting element according to the first embodiment of the present invention. 1 is a schematic cross-sectional structure diagram of a semiconductor light emitting element according to a first embodiment of the present invention, and is a structural example including a reflective laminated film. FIG. 10 is a schematic cross-sectional structure diagram of a semiconductor light emitting element according to a comparative example of the present invention compared with FIG. 9. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a detailed schematic cross-sectional structure diagram of a semiconductor light-emitting device according to a first embodiment of the present invention, where (a) a schematic cross-sectional structure diagram of a semiconductor light-emitting device portion and (b) an enlarged active layer portion. FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor light-emitting device according to a modification of the first embodiment of the present invention; (a) a schematic cross-sectional structure diagram of a semiconductor light-emitting device portion; and (b) an enlarged active layer portion. FIG. It is a schematic diagram for demonstrating the crystal plane of the group III nitride semiconductor applied to the semiconductor light-emitting device which concerns on the 1st Embodiment of this invention, and its modification, Comprising: (a) III group nitride semiconductor Schematic diagram showing c-plane, a-plane and m-plane of crystal structure, (b) schematic diagram for explaining semipolar plane {10-11}, (c) for explaining semipolar plane {10-13} (D) The schematic diagram which shows the coupling | bonding of a group III atom and a nitrogen atom. FIG. 12 is a schematic cross-sectional structure diagram formed up to a p-side electrode and an n-side electrode in the semiconductor light emitting device according to the first embodiment of the present invention shown in FIG. 11. 1 is a schematic cross-sectional structure diagram of a semiconductor light emitting element according to a first embodiment of the present invention in which a flip chip structure is formed. FIG. 4 is a schematic cross-sectional structure diagram of a semiconductor light-emitting device according to a second embodiment of the present invention, where (a) a schematic cross-sectional structure diagram of a semiconductor light-emitting device portion, and (b) an enlarged schematic view of an active layer portion. FIG. The typical cross-section figure formed to the p side electrode and n side electrode of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention. FIG. 18 is a schematic planar pattern configuration diagram corresponding to FIG. 17 in the semiconductor light emitting device according to the second embodiment of the present invention. FIG. 6 is a schematic cross-sectional structure diagram of a flip chip configuration in a semiconductor light emitting device according to a second embodiment of the present invention. FIG. 4 is a schematic cross-sectional structure diagram of a semiconductor light-emitting device according to a third embodiment of the present invention, where (a) a schematic cross-sectional structure diagram of a semiconductor light-emitting device portion, and (b) an enlarged schematic view of an active layer portion. FIG. The typical cross-section figure formed to the p side electrode and n side electrode of the semiconductor light-emitting device concerning the 3rd Embodiment of this invention. FIG. 10 is a schematic cross-sectional structure diagram of a flip chip configuration in a semiconductor light emitting device according to a third embodiment of the present invention.

Explanation of symbols

2 ... n-type nitride semiconductor layer 10 ... substrate (insulating substrate)
12 ... n-type semiconductor layer 13 ... active layer 14 ... p-type semiconductor layer 15 ... transparent electrode 16 ... buffer layer 17 ... block layer 18 ... protective film 19 ... n-type contact layer 20 ... threading dislocation 21 ... electronic barrier layer 22 ... cap Layer 25... N-type semiconductor layer 28... Reflection laminated film 30, 60... Active layer 31, 311 to 31 n.
32, 321-32n ... well layer (InGaN layer)
61,611-61n ... barrier layer (AlGaN layer)
62,621-62n ... well layer (AlInGaN layer)
40, 80 ... p-type semiconductor layers 41, 81 ... first nitride semiconductor layers 42, 82 ... second nitride semiconductor layers 43, 83 ... third nitride semiconductor layers 44, 84 ... fourth nitride systems Semiconductor layer (p-type contact layer)
100 ... p-side electrode 121 ... first n-type semiconductor layer 122 ... second n-type semiconductor layer 123 ... third n-type semiconductor layer 124 ... fourth n-type semiconductor layer 200, 300 ... n-side electrode 310 ... Final barrier layer LO... Center portion LA, LB of protective film 18.

Claims (20)

A substrate,
A protective film disposed on the substrate;
An n-type semiconductor layer disposed on the substrate and the protective film sandwiched between the protective films and doped with an n-type impurity;
An active layer disposed on the n-type semiconductor layer;
A semiconductor light emitting device comprising: a p-type semiconductor layer disposed on the active layer and doped with a p-type impurity.   The semiconductor light emitting device according to claim 1, further comprising a buffer layer disposed on the substrate sandwiched between the protective films. A transparent electrode disposed on the p-type semiconductor layer;
An n-side electrode disposed on the n-type semiconductor layer surface obtained by removing a part of the transparent electrode, the p-type semiconductor layer, the active layer and the n-type semiconductor layer;
The semiconductor light-emitting element according to claim 1, further comprising: a p-side electrode disposed on the transparent electrode.   The semiconductor light emitting element according to claim 3, further comprising a reflective laminated film disposed on the transparent electrode.   The semiconductor according to claim 1, wherein the protective film is transparent with respect to an emission wavelength, and a refractive index of the protective film is substantially equal to a refractive index of the substrate. Light emitting element.   6. The semiconductor light emitting device according to claim 1, wherein the protective film is any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a titanium oxide film, and an alumina film. . A substrate,
A protective film disposed on the substrate;
An AlN buffer layer disposed on the substrate sandwiched between the protective films;
An n-type semiconductor layer disposed on the AlN buffer layer and the protective film and doped with an n-type impurity;
A block layer disposed on the n-type semiconductor layer and doped with the n-type impurity at a lower concentration than the n-type semiconductor layer;
An active layer made of multiple quantum wells containing indium, having a stacked structure in which a barrier layer and well layers having a smaller band gap than the barrier layer are alternately arranged, arranged on the block layer;
A first nitride-based semiconductor layer disposed on the active layer and including a p-type impurity;
A second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and including a p-type impurity at a concentration lower than that of the p-type impurity of the first nitride-based semiconductor layer;
A third nitride-based semiconductor layer disposed on the second nitride-based semiconductor layer and including a p-type impurity having a concentration higher than that of the p-type impurity of the second nitride-based semiconductor layer;
A fourth nitride-based semiconductor layer that is disposed on the third nitride-based semiconductor layer and includes a p-type impurity at a concentration lower than that of the p-type impurity of the third nitride-based semiconductor layer. The semiconductor light emitting device, wherein the film thickness of the uppermost final barrier layer is thicker than the p-type impurity diffusion distance of the first nitride-based semiconductor layer. A substrate,
A protective film disposed on the substrate;
An AlN buffer layer disposed on the substrate sandwiched between the protective films;
An n-type semiconductor layer disposed on the AlN buffer layer and the protective film and doped with an n-type impurity;
A block layer disposed on the n-type semiconductor layer and doped with the n-type impurity at a lower concentration than the n-type semiconductor layer;
An active layer made of multiple quantum wells containing indium, having a stacked structure in which a barrier layer and well layers having a smaller band gap than the barrier layer are alternately arranged, arranged on the block layer;
A first nitride-based semiconductor layer disposed on the active layer and including a p-type impurity;
A second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and including a p-type impurity at a concentration lower than that of the p-type impurity of the first nitride-based semiconductor layer;
A transparent electrode made of a transparent electrode and disposed on the second nitride-based semiconductor layer, wherein the final barrier layer of the uppermost layer of the stacked structure has a p-type impurity in the first nitride-based semiconductor layer A semiconductor light emitting device characterized in that it is thicker than the diffusion distance.   The semiconductor light-emitting element according to claim 7, further comprising a reflective laminated film on the transparent electrode.   The semiconductor light emitting element according to claim 7, wherein the protective film is transparent to an emission wavelength, and a refractive index of the protective film is substantially equal to a refractive index of the substrate.   11. The semiconductor light emitting device according to claim 9, wherein the semiconductor light emitting device has a flip chip structure, and light reflected by the reflective laminated film is extracted from the substrate side. A substrate,
An AlN buffer layer disposed on the substrate;
An n-type semiconductor layer formed on the AlN buffer layer and comprising an Al _x Ga _1-x N layer (0 <x <1) doped with an n-type impurity;
A barrier layer made of an Al _x Ga _1-x N layer (0 <x <1) and an Al _x In _y Ga _1-xy N layer (0) having a smaller band gap than the barrier layer is disposed on the n-type semiconductor layer. <X ≦ y <1, 0 <x + y <1) active layers composed of multiple quantum wells having a stacked structure in which well layers are alternately arranged;
And a p-type semiconductor layer comprising an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity and disposed on the active layer. Further comprising a protective film disposed on the substrate;
13. The semiconductor light emitting device according to claim 12, wherein the AlN buffer layer is disposed on the substrate sandwiched between the protective films, and the n-type semiconductor layer is also disposed on the protective film. . The p-type semiconductor layer is
An electron barrier layer disposed on the active layer and comprising an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity;
An electron cap layer that is disposed on the electron barrier layer and includes an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity;
A first nitride-based semiconductor layer that is disposed on the electron cap layer and includes an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity;
An Al _x Ga _1-x N layer (0 ≦ x) disposed on the first nitride-based semiconductor layer and doped with a p-type impurity having a lower concentration than the p-type impurity of the first nitride-based semiconductor layer. A second nitride-based semiconductor layer comprising <1);
An Al _x Ga _1-x N layer (0 ≦ x) disposed on the second nitride semiconductor layer and doped with a p-type impurity having a higher concentration than the p-type impurity of the second nitride semiconductor layer. A third nitride semiconductor layer comprising <1);
An Al _x Ga _1-x N layer (0 ≦ x) disposed on the third nitride semiconductor layer and doped with a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer. The semiconductor light-emitting device according to claim 12, further comprising: a fourth nitride-based semiconductor layer made of <1). Forming a protective film on the substrate;
Patterning the protective film and exposing the substrate;
Forming an n-type semiconductor layer doped with n-type impurities on the exposed substrate and the protective film sandwiched between the protective films by lateral epitaxial growth;
Forming an active layer on the n-type semiconductor layer;
And a step of forming a p-type semiconductor layer doped with a p-type impurity on the active layer.   16. The method of manufacturing a semiconductor light emitting device according to claim 15, further comprising a step of forming a buffer layer on the exposed substrate sandwiched between the protective films after the step of exposing the substrate.   The step of forming the n-type semiconductor layer by lateral epitaxial growth includes a step of forming at a first pressure and a step of forming at a second pressure higher than the first pressure at the time of lateral epitaxial growth. The method of manufacturing a semiconductor light-emitting element according to claim 15 or 16, wherein: Forming an AlN buffer layer on the substrate;
Forming an n-type semiconductor layer comprising an Al _x Ga _1-x N layer doped with an n-type impurity (0 <x <1) on the AlN buffer layer;
On the n-type semiconductor layer, a barrier layer composed of an Al _x Ga _1-x N layer (0 <x <1) and an Al _x In _y Ga _1-xy N layer (0 <x <1) having a smaller band gap than the barrier layer. Forming an active layer composed of multiple quantum wells having a stacked structure in which well layers composed of ≦ y <1, 0 <x + y <1) are alternately formed;
Forming a p-type semiconductor layer made of an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity on the active layer. Manufacturing method.   A step of forming a protective film on the substrate, wherein the AlN buffer layer is also formed on the substrate sandwiched between the protective films, and the n-type semiconductor layer is also formed on the protective film. The method of manufacturing a semiconductor light emitting element according to claim 18. The step of forming the p-type semiconductor layer includes:
Forming an electron barrier layer composed of an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity on the active layer;
Forming an electron cap layer comprising an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity on the electron barrier layer;
Forming a first nitride-based semiconductor layer composed of an Al _x Ga _1-x N layer (0 ≦ x <1) doped with a p-type impurity on the electron cap layer;
The first nitride semiconductor layer, the first nitride semiconductor layer Al _x Ga _1-x N layer low-concentration p-type impurity is added impurities than the p-type impurity (0 ≦ x <1 Forming a second nitride-based semiconductor layer comprising:
The second nitride semiconductor layer, the second nitride semiconductor layer Al _x Ga _1-x N layer than the p-type impurity high concentration p-type impurity of the impurity doping (0 ≦ x <1 Forming a third nitride-based semiconductor layer comprising:
The third nitride semiconductor layer, the third nitride semiconductor layer Al _x Ga _1-x N layer low-concentration p-type impurity is added impurities than the p-type impurity (0 ≦ x <1 The method of manufacturing a semiconductor light-emitting device according to claim 18, further comprising: forming a fourth nitride-based semiconductor layer comprising:

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