JP2009194344A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with an integrally structured gate electrode. <P>SOLUTION: The method of manufacturing the semiconductor device has: a step of forming a multilayer film 18 including a charge accumulating layer 14 on a semiconductor substrate 10; a step of forming a first spacer layer 36 on the sidewall of a mask layer 20 formed so as to extend onto the multilayer film; a step of removing the multilayer film while using the mask layer and the first spacer layer as masks, thereby forming a first opening 38; a step of forming a gate oxide film 22 on the first opening after removing the first spacer layer; a step of forming a gate electrode 28 on the multilayer film and on the gate oxide film, between the masks; a step of removing the multilayer film using the gate electrode as a mask after the mask layer, thereby forming a second opening 40; and a step of forming bit lines 30 defined in the second opening and extending through the inside of the semiconductor substrate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a separated charge storage layer.

  Nonvolatile memories, which are semiconductor devices that can rewrite data and retain stored data even when the power is turned off, are widely used. In a flash memory that is a typical nonvolatile memory, a transistor that forms a memory cell has a floating gate or an insulating film called a charge storage layer. Data is stored by accumulating charges in the charge accumulation layer. As a flash memory using an insulating film as a charge storage layer, there is a flash memory having a SONOS (silicon oxide nitride oxide silicon) type structure in which charges are stored in a charge storage layer in an ONO (oxide nitride oxide) film. One type of SONOS type flash memory is a flash memory having virtual ground type memory cells that operate symmetrically by switching the source and drain. According to this, 2-bit data can be stored in one memory cell.

  In recent years, there has been a great demand for miniaturization and high integration of memory cells, and in order to realize this demand, it is necessary to shorten the channel length. However, when the channel length is shortened, the influence of interference accumulated in two charge accumulation regions called CBD (Complementary bit disturb) increases. As a method for solving this problem, a technique for separating the charge storage layer in the channel direction has been proposed.

For example, Patent Document 1 and Patent Document 2 disclose a method for manufacturing a semiconductor device having an ONO film separated in a channel direction. For example, Patent Document 3 and Patent Document 4 disclose a technique regarding a manufacturing method in which a part of a thin film made of an insulating film or the like is removed to separate the thin film.
JP 2003-258128 A Japanese Patent Laid-Open No. 2004-80022 Japanese Patent Laid-Open No. 3-180034 Special table 2003-533848 gazette

  In a semiconductor device having a charge storage layer separated by a gate insulating film, for example, the following problems exist. The gate electrode formed on the gate insulating film and the charge storage layer includes a first conductive layer formed on the gate insulating film and a side wall of the first conductive layer and formed on the charge storage layer. And two conductive layers. Since the first conductive layer and the second conductive layer are formed in separate steps, an insulating film such as a natural oxide film is formed between the first conductive layer and the second conductive layer, and the gate electrode is electrically There may be cases where they are not united.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device having a gate electrode having an integral structure.

  The present invention includes a step of forming a laminated film including a charge storage layer on a semiconductor substrate, a step of forming a first spacer layer on a side wall of a mask layer formed by extending on the laminated film, and the mask layer And using the first spacer layer as a mask, the stacked film is removed to form a first opening, and after removing the first spacer layer, a gate oxide film is formed in the first opening. A step of forming a gate electrode between the mask layers on the stacked film and the gate oxide film, and after removing the mask layer, the stacked film is formed using the gate electrode as a mask. And a step of forming a second opening and a step of forming a bit line defined by the second opening and extending in the semiconductor substrate. It is. According to the present invention, a gate electrode having an integral structure can be formed. Thereby, an electrically integrated gate electrode can be obtained.

  In the above structure, the step of forming the gate electrode may be a step of forming the gate electrode by depositing the conductive film once.

  In the above structure, a step of forming a first insulating film so as to be embedded in the second opening, and a word line extending across the bit line are formed on the gate electrode and the first insulating film. And a forming step.

  In the above structure, the first spacer layer may be formed of a material that can be removed with high selectivity with respect to the stacked film and the mask layer. Moreover, the said structure WHEREIN: A said 1st spacer layer can be set as the structure which consists of polymer films.

  In the above configuration, the step of forming the gate oxide film may include a step of forming the gate oxide film so that an end portion of the charge storage layer is oxidized. According to this configuration, contact between the charge storage layer and the gate electrode can be suppressed, and the charge retention characteristics of the charge storage layer can be improved.

  In the above configuration, the step of forming the gate oxide film is a step of forming the gate oxide film so that the thickness of the gate oxide film is the same as the equivalent oxide thickness of the stacked film. It can be. According to this configuration, it is possible to efficiently remove charges from the charge storage layer.

  In the above configuration, the method includes a step of forming a second spacer layer on a sidewall of the gate electrode, and the step of forming the second opening includes the second electrode using the gate electrode and the second spacer layer as a mask. It can be set as the structure including the process of forming an opening part. According to this configuration, the region of the charge storage layer can be enlarged, and the amount of charge that can be stored can be increased.

  In the above structure, the second spacer layer may be formed of a material that can be removed with high selectivity with respect to the stacked film and the gate electrode.

  According to the present invention, a gate electrode having an integral structure can be formed. Thereby, an electrically integrated gate electrode can be obtained.

  First, a method for manufacturing a flash memory according to Comparative Example 1 will be described using FIGS. 1A to 3 to clarify the problem. With reference to FIG. 1A, a laminated film 18 including a tunnel insulating film 12, a charge storage layer 14, and a top insulating film 16 is formed on a semiconductor substrate 10. Using the mask layer 20 formed by stretching on the laminated film 18 as a mask, the laminated film 18 is removed to form a third opening 21.

  Referring to FIG. 1B, a gate oxide film 22 is formed on the semiconductor substrate 10 in the third opening 21. Referring to FIG. 1C, the first conductive layer 24 is formed so as to be embedded in the third opening 21. That is, the first conductive layer 24 is formed on the gate oxide film 22.

  Referring to FIG. 2A, the mask layer 20 is removed. Referring to FIG. 2B, a second conductive layer 26 is formed on the laminated film 18 so as to cover the first conductive layer 24, and then the second conductive layer 26 is etched back. As a result, the spacer-like second conductive layer 26 remains on the laminated film 18 on the side wall of the first conductive layer 24. A gate electrode 28 is formed from the first conductive layer 24 and the second conductive layer 26. Referring to FIG. 2C, the top insulating film 16 and the charge storage layer 14 are removed using the gate electrode 28 as a mask. Thereafter, the bit line 30 is formed in the semiconductor substrate 10 using the gate electrode 28 as a mask. Referring to FIG. 3, a first insulating film 32 is formed so as to be embedded on the tunnel insulating film 12 between the gate electrodes 28. A polysilicon film is formed on the gate electrode 28 and the first insulating film 32. After a mask layer (not shown) extending across the bit line 30 is formed on the polysilicon film, the polysilicon film and the gate electrode 28 are removed using the mask layer as a mask. As a result, a word line 34 made of a polysilicon film and extending across the bit line 30 is formed. The gate electrode 28 is formed under the word line 34.

  According to the comparative example 1, the first conductive layer 24 is formed on the gate oxide film 22 as shown in FIG. 1C, and then the sidewall of the first conductive layer 24 is used as shown in FIG. Therefore, the second conductive layer 26 is formed on the laminated film 18. Then, a gate electrode 28 is formed from the first conductive layer 24 and the second conductive layer 26. Thus, the gate electrode 28 is composed of two layers, the first conductive layer 24 and the second conductive layer 26, and the first conductive layer 24 and the second conductive layer 26 are formed in separate steps. Therefore, an insulating film such as a natural oxide film is formed between the first conductive layer 24 and the second conductive layer 26, and the gate electrode 28 may not be electrically integrated.

  When the gate electrode 28 is not electrically integrated, for example, there are the following problems. As shown in FIG. 3, the area of the contact portion 35 between the second conductive layer 26 and the word line 34 is very small. For this reason, the resistance between the second conductive layer 26 and the word line 34 becomes very large. Therefore, when the gate electrode 28 is not electrically integrated, there arises a problem that an electric field having a sufficient magnitude cannot be applied to the laminated film 18 in writing and erasing data.

  Further, as shown in FIG. 3, the first insulating film 32 has a shape in which the upper width W1 is wider than the lower width W2. For this reason, when removing the polysilicon film and the gate electrode 28 in the step of forming the word line 34, the second conductive layer 26 is difficult to remove and may remain between the adjacent word lines 34. As a result, adjacent word lines 34 may be short-circuited by the second conductive layer 26.

  Therefore, in order to solve the above problems, an embodiment of the present invention having a gate electrode having an integral structure will be described below.

  4A is a cross-sectional view of the flash memory according to the first embodiment, and FIG. 4B is an enlarged view of a region A in FIG. 4A. In FIG. 4B, the gate electrode 28 and the first insulating film 32 are not shown. Referring to FIGS. 4A and 4B, a bit line 30 serving as a source and a drain is provided in the semiconductor substrate 10 so as to extend. Between the bit lines 30 is a channel. A gate oxide film 22 is formed on the center between the bit lines 30. A laminated film 18 composed of the tunnel insulating film 12, the charge storage layer 14, and the top insulating film 16 is formed so as to sandwich the gate oxide film 22 in the channel direction. An end portion of the charge storage layer 14 on the gate oxide film 22 side is oxidized to form a silicon oxide film 42. A first insulating film 32 is formed on the bit line 30. A gate electrode 28 having an integral structure is formed between the first insulating films 32 and on the gate oxide film 22 and the laminated film 18. That is, the gate electrode 28 is electrically integrated. A word line 34 extending across the bit line 30 is formed on the gate electrode 28 and the first insulating film 32.

  Next, the basic operation of the flash memory according to the first embodiment will be described. First, a method for accumulating charges in the charge accumulation layer 14 which is a data write operation will be described. As a method for accumulating charges in the charge accumulation layer 14, for example, there is a method using a hot electron effect. In this method, for example, a positive voltage is applied to the word line 34 (gate electrode 28). A positive voltage is applied to the bit line 30 (drain), and the bit line 30 (source) is set to the ground potential. As a result, a high electric field is generated between the bit lines 30 (between the source and the drain), and an electron flow serving as a channel current is generated. The electrons become hot electrons in the vicinity of the bit line 30 (drain), jump over the barrier of the tunnel insulating film 12, are taken into the charge storage layer 14, and are stored as charges.

  Next, a method for removing charges from the charge storage layer 14 as a data erasing operation will be described. As a method for removing charges from the charge storage layer 14, for example, there is a method using an FN (Fowler Nordheim) tunnel effect. In this method, for example, the word line 34 is set to the ground potential, and a positive voltage is applied to the semiconductor substrate 10. As a result, a high electric field is generated between the word line 34 (gate electrode 28) and the semiconductor substrate 10, and the charge can be removed from the charge storage layer 14.

  Next, the manufacturing method of the flash memory according to the first embodiment will be described with reference to FIGS. 5A, on a p-type silicon semiconductor substrate 10, a tunnel insulating film 12 made of, for example, a silicon oxide film, a charge storage layer 14 made of, for example, a silicon nitride film, and a top insulation made of, for example, a silicon oxide film. A film 16 is sequentially formed. Thereby, the laminated film 18 is formed. A mask layer 20 made of, for example, a silicon nitride film is formed on the laminated film 18 so as to extend. A polymer film is formed on the laminated film 18 so as to cover the mask layer 20. The polymer film is formed using an etching gas in a dry etching apparatus. The polymer film is formed of C, F, H, O, or the like. The polymer film is anisotropically etched. Thereby, the first spacer layer 36 made of the polymer film is formed on the side wall of the mask layer 20. The width of the first spacer layer 36 is, for example, 20 nm.

  Referring to FIG. 5B, the laminated film 18 is removed by using, for example, RIE (reactive ion etching) with the mask layer 20 and the first spacer layer 36 as a mask. Thereby, the laminated film 18 is separated, and a first opening 38 is formed in the region where the laminated film 18 is removed. Referring to FIG. 5C, the first spacer layer 36 is removed.

  Referring to FIG. 6A, the semiconductor substrate 10 is oxidized using, for example, a thermal oxidation method. As a result, the gate oxide film 22 made of a silicon oxide film is formed in the first opening 38. At this time, the end portion of the charge storage layer 14 is also oxidized to form a silicon oxide film 42.

  With reference to FIG. 6B, a polysilicon film is formed on the gate oxide film 22 and the laminated film 18 by using, for example, a CVD (chemical vapor deposition) method so as to cover the mask layer 20. Thereafter, the polysilicon film is polished using, for example, a CMP (Chemical Mechanical Polishing) method until the surface of the mask layer 20 is exposed. As a result, a gate electrode 28 made of a polysilicon film is formed on the gate oxide film 22 and the laminated film 18. Referring to FIG. 6C, the mask layer 20 is removed.

  Referring to FIG. 7A, using the gate electrode 28 as a mask, the stacked film 18 is removed using, for example, the RIE method. Thereby, the second opening 40 defined by the gate electrode 28 is formed. Arsenic ions, for example, are implanted into the semiconductor substrate 10 from the second opening 40. As a result, the inside of the semiconductor substrate 10 is extended, and the bit line 30 that is an n-type diffusion region defined by the second opening 40 is formed.

  Referring to FIG. 7B, a silicon oxide film is formed using, for example, a high-density plasma CVD method so as to be embedded in the second opening 40. The silicon oxide film is polished using, for example, a CMP method so that the surface of the gate electrode 28 is exposed. Thereby, the first insulating film 32 made of the silicon oxide film is formed in the second opening 40. A polysilicon film is deposited on the gate electrode 28 and the first insulating film 32 by using, for example, a CVD method. Thereafter, the polysilicon film and the gate electrode 28 are removed using a mask layer (not shown) formed on the polysilicon film so as to extend across the bit line 30 as a mask. As a result, a word line 34 made of a polysilicon film extending across the bit line 30 is formed. The gate electrode 28 is formed under the word line 34.

  According to the first embodiment, as shown in FIG. 5A, the laminated film 18 is formed on the semiconductor substrate 10, the mask layer 20 extending on the laminated film 18, and the first spacer layer 36 on the sidewall of the mask layer 20. And form. As shown in FIG. 5B, the laminated film 18 is removed using the mask layer 20 and the first spacer layer 36 as a mask to form a first opening 38. As shown in FIG. 5C, the first spacer layer 36 is removed. Thereby, the width W4 of the laminated film 18 becomes larger than the width W3 of the mask layer 20. In other words, the distance L1 between the mask layers 20 is larger than the distance L2 between the stacked films 18.

  As shown in FIG. 6A, the gate oxide film 22 is formed in the first opening 38. As shown in FIG. 6B, a polysilicon film is deposited on the entire surface, and a gate electrode 28 is formed between the mask layer 20 and on the laminated film 18 and the gate oxide film 22. At this time, since the distance L1 between the mask layers 20 is larger than the distance L2 between the laminated films 18, the gate electrode 28 can be formed on the laminated film 18 and the gate oxide film 22 by one deposition of the polysilicon film. it can. That is, the gate electrode 28 having an integral structure can be formed on the stacked film 18 and the gate oxide film 22. Therefore, an electrically integrated gate electrode 28 can be obtained.

  Further, after removing the mask layer 20 as shown in FIG. 6C, the laminated film 18 is removed using the gate electrode 28 as a mask to form the second opening 40 as shown in FIG. 7A. Then, the bit line 30 defined by the second opening 40 is formed in the semiconductor substrate 10. Thereby, the gate electrode 28, the bit line 30, and the laminated film 18 can be formed in a self-aligned manner.

  Further, as shown in FIG. 7B, the first insulating film 32 is formed in the second opening 40. As a result, the first insulating film 32 has the same upper and lower widths. That is, the side surface of the gate electrode 28 is vertical. Therefore, when removing the polysilicon film and the gate electrode 28 in the step of forming the word line 34, the gate electrode 28 formed between the adjacent word lines 34 can be easily removed. Therefore, it is possible to suppress the gate electrode 28 from remaining between the adjacent word lines 34, and to suppress the adjacent word lines 34 from being short-circuited.

  Further, as shown in FIGS. 5B and 5C, the laminated film 18 protrudes from the mask layer 20 by the width of the first spacer layer 36. As shown in FIG. 6B, the gate electrode 28 is formed on the laminated film 18 protruding from the mask layer 20. Therefore, the width of the laminated film 18 under the gate electrode 28 is the same as the width of the first spacer layer 36. Therefore, as shown in FIG. 7A, when the laminated film 18 is removed using the gate electrode 28 as a mask, the laminated film 18 having the same size as the width of the first spacer layer 36 remains under the gate electrode 28. From the above, by controlling the width of the first spacer layer 36, the size of the region of the charge storage layer 14 remaining under the gate electrode 28 can be controlled.

  Further, as shown in FIG. 6A, in the step of forming the gate oxide film 22 using the thermal oxidation method, it is preferable that the end portion of the charge storage layer 14 is also oxidized to form the silicon oxide film 42. Thereby, the silicon oxide film 42 can be interposed between the charge storage layer 14 and the gate electrode 28, and the contact between the charge storage layer 14 and the gate electrode 28 can be suppressed. Thereby, the charge accumulated in the charge accumulation layer 14 can be suppressed from moving to the gate electrode 28, and the charge retention characteristics of the charge accumulation layer 14 can be improved.

  Further, as shown in FIG. 6A, when the gate oxide film 22 is formed, the thickness of the gate oxide film 22 is the same as the equivalent oxide thickness (hereinafter referred to as EOT) of the stacked film 18. Thus, it is preferable to form the gate oxide film 22. Note that EOT is a film thickness in consideration of the dielectric constant, and is a value obtained by dividing the product of the actual thickness of a certain film and the dielectric constant of the silicon oxide film by the dielectric constant of the film. Here, for example, when erasing data using the FN tunnel effect, if the thickness of the gate oxide film 22 is smaller than the EOT of the stacked film 18, the current flowing from the gate electrode 28 to the semiconductor substrate 10 is most of the current. Passes through the gate oxide film 22. For this reason, it is difficult to apply a sufficiently large electric field to the laminated film 18, and it is difficult to efficiently remove electrons from the charge storage layer 14. On the other hand, when the thickness of the gate oxide film 22 is the same as the EOT of the stacked film 18, the current flowing from the gate electrode 28 to the semiconductor substrate 10 flows uniformly through the gate oxide film 22 and the stacked film 18. For this reason, a sufficiently large electric field can be applied to the laminated film 18, and electrons can be efficiently removed from the charge storage layer 14.

  In the first embodiment, the first spacer layer 36 is made of a polymer film. However, the present invention is not limited to this. As long as the material can be removed with high selectivity with respect to the laminated film 18 and the mask layer 20, the material may be made of other materials. Furthermore, the first spacer layer 36 is preferably made of a material that can be removed without damaging the surface of the semiconductor substrate 10 exposed at the first opening 38. This is because the gate oxide film 22 is formed in a later step on the semiconductor substrate 10 in the first opening 38. Further, the mask layer 20 is made of a silicon nitride film as an example. However, the present invention is not limited to this. It may be the case.

  Moreover, although the case where the charge storage layer 14 is made of a silicon nitride film has been described as an example, the present invention is not limited to this, and the charge storage layer 14 may be made of other materials as long as the material can store charges, such as a polysilicon film. . Further, as shown in FIG. 6A, the gate oxide film 22 is formed using a thermal oxidation method, but the present invention is not limited thereto. For example, other oxidation methods such as a radical oxidation method and a plasma oxidation method may be used.

  A method for manufacturing the flash memory according to the second embodiment will be described with reference to FIGS. 8A to 8C. First, the manufacturing steps shown in FIGS. 5A to 6C shown in the first embodiment are performed. Next, referring to FIG. 8A, a polymer film is formed so as to cover the gate electrode 28. Thereafter, anisotropic etching is performed. Thereby, the second spacer layer 44 made of the polymer film is formed on the side wall of the gate electrode 28. The width of the second spacer layer 44 is, for example, 10 nm.

  Referring to FIG. 8B, the stacked film 18 is removed using the gate electrode 28 and the second spacer layer 44 as a mask. Thereby, the 2nd opening part 40 is formed. A bit line 30 defined by the second opening 40 and extending in the semiconductor substrate 10 is formed. Referring to FIG. 8C, the first insulating film 32 is formed so as to be embedded in the second opening 40. A polysilicon film is deposited on the gate electrode 28 and the first insulating film 32. Thereafter, the polysilicon film and the gate electrode 28 are removed using a mask layer formed on the polysilicon film so as to extend across the bit line 30 as a mask. As a result, a word line 34 made of a polysilicon film extending across the bit line 30 is formed. The gate electrode 28 is formed under the word line 34.

  According to the second embodiment, the second spacer layer 44 is formed on the side wall of the gate electrode 28 as shown in FIG. As illustrated in FIG. 8B, the stacked film 18 is removed using the gate electrode 28 and the second spacer layer 44 as a mask to form the second opening 40. Thereby, the width | variety of the 2nd opening part 40 can be made small compared with Example 1. FIG. In other words, the width of the remaining laminated film 18 can be increased as compared with the first embodiment.

  As shown in FIG. 6A, when the gate oxide film 22 is formed using a thermal oxidation method or the like, the end portion of the charge storage layer 14 is also oxidized to form a silicon oxide film 42. At this time, the region of the silicon oxide film 42 may be too large, and the region of the charge storage layer 14 may be small. As the region of the charge storage layer 14 becomes smaller, the amount of charge that can be stored also decreases. However, by using the manufacturing method of Example 2, the width of the remaining laminated film 18 can be made larger than that of Example 1. Therefore, according to the second embodiment, the area of the charge storage layer 14 can be made larger than in the first embodiment, and more charges can be stored.

  In the second embodiment, the case where the second spacer layer 44 is made of a polymer film is shown as an example, but the present invention is not limited to this. As long as the material can be removed with high selectivity with respect to the laminated film 18 and the gate electrode 28, it may be made of other materials.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

FIG. 1A to FIG. 1C are cross-sectional views (part 1) showing a method for manufacturing a flash memory according to Comparative Example 1. FIG. 2A to FIG. 2C are cross-sectional views (part 2) showing the manufacturing method of the flash memory according to Comparative Example 1. FIG. 3 is a sectional view (No. 3) showing the method for manufacturing the flash memory according to the first comparative example. 4A is a cross-sectional view of the flash memory according to the first embodiment, and FIG. 4B is an enlarged view of a region A in FIG. 4A. FIG. 5A to FIG. 5C are cross-sectional views (part 1) showing the manufacturing method of the flash memory according to the first embodiment. 6A to 6C are cross-sectional views (part 2) illustrating the method for manufacturing the flash memory according to the first embodiment. 7A and 7B are cross-sectional views (part 3) illustrating the method for manufacturing the flash memory according to the first embodiment. FIG. 8A to FIG. 8C are cross-sectional views illustrating a method for manufacturing a flash memory according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Tunnel insulating film 14 Charge storage layer 16 Top insulating film 18 Laminated | multilayer film 20 Mask layer 21 3rd opening part 22 Gate oxide film 24 1st conductive layer 26 2nd conductive layer 28 Gate electrode 30 Bit line 32 1st insulation Film 34 Word line 35 Contact part 36 First spacer layer 38 First opening 40 Second opening 42 Silicon oxide film 44 Second spacer layer

Claims (9)

Forming a stacked film including a charge storage layer on a semiconductor substrate;
Forming a first spacer layer on a side wall of a mask layer formed by stretching on the laminated film;
Removing the laminated film using the mask layer and the first spacer layer as a mask to form a first opening;
Forming a gate oxide film in the first opening after removing the first spacer layer;
Forming a gate electrode between the mask layers and on the stacked film and the gate oxide film;
Removing the mask layer, then removing the stacked film using the gate electrode as a mask, and forming a second opening;
Forming a bit line defined by the second opening and extending in the semiconductor substrate.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the gate electrode is a step of forming the gate electrode by depositing the conductive film once. Forming a first insulating film so as to be embedded in the second opening;
3. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a word line extending across the bit line on the gate electrode and the first insulating film. .   4. The semiconductor device according to claim 1, wherein the first spacer layer is made of a material that can be removed with high selectivity with respect to the stacked film and the mask layer. 5. Manufacturing method.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the first spacer layer is made of a polymer film.   6. The step of forming the gate oxide film includes a step of forming the gate oxide film so that an end portion of the charge storage layer is oxidized. Semiconductor device manufacturing method.   The step of forming the gate oxide film includes the step of forming the gate oxide film so that the thickness of the gate oxide film is the same as the equivalent oxide thickness of the stacked film. A method for manufacturing a semiconductor device according to claim 1. Forming a second spacer layer on the side wall of the gate electrode;
The step of forming the second opening includes a step of forming the second opening by removing the stacked film using the gate electrode and the second spacer layer as a mask. The manufacturing method of the semiconductor device as described in any one of 1 to 7.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the second spacer layer is made of a material that can be removed with high selectivity with respect to the stacked film and the gate electrode.

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