JP2009192893A - Electrooptical apparatus and method of driving the same, drive circuit for electrooptical apparatus, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce display unevenness due to change in data voltage, and display a high-quality image in an electrooptical apparatus. <P>SOLUTION: The electrooptical apparatus is provided with a switching means 41H for periodically switching an electrical connection of output circuits 41f1-41fi to a data line X so as to shift the data line X between the output circuits 41f1-41f2 in an output circuit group 41F1 among the output circuit groups 41F1-41Fi. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal display device and a driving method thereof, a driving circuit for an electro-optical device for driving the electro-optical device, and an electronic apparatus such as a liquid crystal projector.

  As this type of electro-optical device, for example, a flexible mounted with an electro-optical panel that performs an electro-optical operation such as a display operation in a pixel region, and a driving integrated circuit that bears at least a part of a driving circuit for driving the electro-optical panel. There is an electro-optical device composed of a substrate. In the electro-optical device configured as described above, a part of the control circuit is separated from the electro-optical panel, thereby making it possible to reduce the size of the electro-optical panel, expand the pixel area with respect to the size of the electro-optical panel, or the like.

  For example, Patent Document 1 discloses a technique in which an integrated circuit for driving an electro-optical panel is provided on a flexible substrate by a mounting technique such as COF (Chip On Film), and data voltages are sequentially output to the electro-optical panel. .

Japanese Patent Laid-Open No. 2005-43417

  However, when the electro-optical panel is driven by the data voltage output from the driving integrated circuit as in the above-described technique, the output amplifier is set to the data voltage output from the plurality of output amplifiers included in the driving integrated circuit. Variations occur every time. Such a variation in data voltage may cause, for example, vertical luminance unevenness in a displayed image. Such luminance unevenness can also occur when the output amplifier is provided in a built-in circuit in the electro-optical device outside the driving integrated circuit. Therefore, the above-described technique has a technical problem that the image quality may be deteriorated due to the variation in the data voltage.

  The present invention has been made in view of the above-described problems, for example, an electro-optical device that can reduce display unevenness due to variations in data voltage and display a high-quality image, a driving method thereof, and the electro-optical device. It is an object of the present invention to provide an electro-optical device driving circuit and an electronic device for driving the electronic device.

  In order to solve the above problems, an electro-optical device of the present invention includes a substrate, a plurality of pixel portions arranged on the substrate along a first direction and a second direction that intersects the first direction, and the substrate. A plurality of data lines provided along the first direction, a plurality of output circuits for outputting data voltages to the plurality of pixel portions via the plurality of data lines, and a plurality of output circuits. Each of the output circuits belonging to the output circuit group so that the data lines corresponding to each other in each of the output circuits belonging to the output circuit group are switched for each output circuit group including two or more output circuits. Switching means for periodically switching electrical connection to each of the data lines corresponding to the output circuit group.

  According to the electro-optical device of the present invention, during the operation, first, a data voltage is output from the output circuit via the plurality of data lines. The “data voltage” means a voltage having data for displaying an image. That is, the data voltage here can also be called an image signal. The output circuit is an amplifier circuit such as an operational amplifier, for example, and outputs the data voltage while amplifying it. The output circuit is typically formed as a part of an integrated circuit, and is disposed on a flexible substrate that is electrically connected to the substrate on which the pixel portion is arranged. In addition, you may arrange | position on the board | substrate with which a pixel part is arranged.

  Data voltages output to the plurality of data lines are supplied to a plurality of pixel portions arranged on the substrate. For example, the data voltage is supplied to the plurality of pixel portions in response to a scanning signal supplied from a scanning line (wiring along the second direction) that crosses the data line and is wired on the same substrate. Thereby, image display by a so-called active matrix method is performed. The pixel portion includes a transparent electrode made of a transparent conductive material such as ITO (Indium Tin Oxide), for example, and is arranged along a first direction along the data line and a second direction intersecting the first direction. ing. That is, the plurality of pixel portions are arranged in a matrix on the substrate.

  In the electro-optical device of the present invention, switching means for switching the electrical connection to each data line of the plurality of output circuits on the substrate is provided. According to the switching means, the electrical connection of each of the plurality of output circuits to the corresponding data line is switched for each output circuit group. More specifically, the switching means switches the electrical connection of each output circuit to the data line so that the data lines corresponding to each other are periodically switched in each of the output circuits belonging to the output circuit group. Accordingly, the data voltage is periodically supplied from different output circuits to each of the data lines corresponding to the output circuit group.

  Here, the data voltages output from the plurality of output circuits may vary due to, for example, a slight difference in amplification factor between the output circuits. Therefore, for example, even when the same data voltage is output, the data voltages output from different output circuits may be shifted from each other. Here, if a data voltage is supplied to only one pixel column with only one output circuit, the data voltage supplied to each pixel column varies. That is, a luminance difference is generated for each pixel column. Therefore, the display image has a line-like display unevenness extending in the data line direction.

  In the electro-optical device of the present invention, data output from one output circuit is switched periodically by switching the corresponding data line in each output circuit belonging to the output circuit group, for example, every horizontal period or every frame period. The voltage can be distributed to each of the data lines corresponding to the output circuit group. As a result, each output (data voltage) of the output circuit in the output circuit group is distributed to the pixel portions corresponding to these data lines. For example, when the electrical connection is switched by the switching means every horizontal period, the output of the output circuit in the output circuit group in each pixel unit in the pixel column composed of the pixel units arranged along each data line Is distributed. Alternatively, for example, when the electrical connection is switched by the switching means every frame period, the output of the output circuit in the output circuit group is distributed to each pixel column.

  Therefore, even if the data voltage varies among the output circuits in the output circuit group, the line-shaped display unevenness based on the luminance difference between the data lines is noticeable on the display screen by the plurality of pixel portions. Can be suppressed. Therefore, according to the electro-optical device of the present invention, it is possible to reduce display unevenness due to variation in data voltage. Therefore, it is possible to display a high quality image.

  In one aspect of the electro-optical device of the present invention, the switching unit switches the electrical connection every horizontal period.

  According to this aspect, the data lines corresponding to each other are exchanged for each horizontal period in each of the output circuits belonging to the output circuit group by switching of the electrical connection by the switching means. Therefore, in each of the data lines corresponding to the output circuit group, the corresponding output circuit is replaced every horizontal period, and in each of the pixel columns corresponding to these data lines, each pixel portion has an output circuit group in the output circuit group. Output (data voltage) is distributed. Therefore, due to the variation in the data voltage of each output circuit in the output circuit group, the line-shaped display unevenness along the data line extending direction (first direction) is noticeable on the display screen. Can be suppressed.

  In another aspect of the electro-optical device of the present invention, the switching unit switches the electrical connection every frame period.

  According to this aspect, the data lines corresponding to each other are exchanged every one frame period in each of the output circuits belonging to the output circuit group by switching of the electrical connection by the switching means. Therefore, in each of the data lines corresponding to the output circuit group, the corresponding output circuit is replaced every frame period, and the output of the output circuit in the output circuit group (ie, the pixel line corresponding to these data lines) Data voltage) is distributed. Therefore, due to the variation in the data voltage of each output circuit in the output circuit group, the line-shaped display unevenness along the data line extending direction (that is, the first direction) is noticeable on the display screen. Can be suppressed.

  In another aspect of the electro-optical device of the present invention, the switching means is provided for each output circuit by the number of output circuits belonging to the output circuit group, and each of the switching means is electrically connected to a different output circuit in the output circuit group. And a plurality of changeover signals for selecting one of the changeover switches in the changeover switch group. The changeover switch group includes a changeover switch group that is connected to the same data line and electrically connected to the same data line. Are input to the changeover switch group, and the output circuits different from each other are alternately electrically connected to the data line by the changeover switch according to the different changeover signals, and the changeover switch corresponding to the output circuit group In each of the switch groups, the different output circuits are selected by the changeover switch based on the same changeover signal.

  According to this aspect, the switching means has the changeover switch group provided for each output circuit of the output circuit group. The changeover switch group includes changeover switches provided for the number of output circuits belonging to the output circuit group for one output circuit. The changeover switches belonging to the changeover switch group are electrically connected to different output circuits of the output circuit group.

  A plurality of changeover signals are input to the changeover switch group, and one changeover switch is selected according to one changeover signal. Accordingly, different changeover switches in the changeover switch group are selected based on different changeover signals, and different output circuits in the output circuit group are alternately electrically connected to the data lines. Here, each of the changeover switches belonging to the same changeover switch group is electrically connected to the same data line. Therefore, in the data line corresponding to the changeover switch group, the data voltage is periodically supplied from different output circuits based on the changeover signal in the output circuit group corresponding thereto.

  Further, in this aspect, different output circuits in the output circuit group are selected from each other in the switch group corresponding to the output circuit group by the same switching signal. Therefore, in the supply period of the same switching signal, different output circuits are electrically connected to different data lines. As a result, in this aspect, based on different switching signals, the output lines belonging to the output circuit group can mutually exchange corresponding data lines by the changeover switch group.

  That is, in this aspect, by periodically supplying each of the plurality of switching signals, the corresponding data line can be easily replaced by the switching switch belonging to the switching switch group for each output circuit in the output circuit group. It becomes possible. In addition, the change-over switch can be composed of, for example, a P-channel or N-channel single-channel TFT or a complementary TFT, and the structure of the switching means can be simplified. The effect of being easily miniaturized and miniaturized can be expected.

  In another aspect of the electro-optical device according to the aspect of the invention, the data voltage is driven for each data line group including two or more data lines among the plurality of data lines as the data voltage via the output circuit. A time-series voltage is supplied, the time-series data voltage is time-divisioned, and the data voltage defining the gray level of the pixel portion obtained by the time-division is represented by the data line group A time division circuit that distributes the data line to any one of the data lines, wherein the time division circuit periodically and alternately outputs the data voltage from the different output circuits of the output circuit group via the switching means. Are supplied, and each of the time division circuits corresponding to the output circuit group is electrically connected to the different output circuits via the switching means.

  According to this aspect, the time-series data voltage supplied via the output circuit by the time division circuit is time-divided and distributed to the plurality of data lines for each data line group. Therefore, each data line belonging to the data line group is sequentially driven based on the data voltage time-divided by the time-division circuit, and the data voltage is supplied to the corresponding pixel portion.

  In this embodiment, each time division circuit is supplied with a data voltage periodically and alternately from the different output circuits in the output circuit group via the switching means. Therefore, the data voltage periodically and alternately output from the different output circuits in the output circuit group is supplied to each of the data lines belonging to the data line group.

  On the other hand, in each of the time division circuits corresponding to the output circuit group, data voltages are supplied from different output circuits through the switching means among the output circuits belonging to the output circuit group. That is, when viewed from the output circuit of the output circuit group, different output circuits are electrically connected to different time division circuits and electrically connected to different data line groups.

  Therefore, in this aspect, it is possible to replace the data line groups corresponding to each other in each of the output circuits belonging to the output circuit group. Therefore, the data voltage output from each output circuit can be distributed to the data line group corresponding to the output circuit group.

  In another aspect of the electro-optical device of the present invention, the data voltage is sequentially supplied to each data line group including two or more data lines among the plurality of data lines as the data voltage via each of the plurality of output circuits. In order to drive the plurality of image signal lines, a plurality of data voltages corresponding to each of the data lines belonging to the data line group are supplied to the plurality of image signal lines and a plurality of image signal lines respectively supplied as time-series voltages. The plurality of time-series data voltages are each time-divided, and a plurality of the data voltages defining each gradation of the pixel portion corresponding to the data line group obtained by the time-division are obtained. A sampling circuit for supplying data lines to the data lines belonging to the data line group at the same time, and the plurality of image signal lines are periodically alternated from different output circuits in the output circuit group via the switching means. On the day With a voltage is supplied, each of the image signal lines corresponding to the output circuits are electrically connected different said output circuit and each other through the switching means.

  According to this aspect, a time-series data voltage is supplied to the plurality of image signal lines via the output circuit in order to sequentially drive each data line group. The sampling circuit time-divides the time-series data voltage supplied to each of the plurality of image signal lines, and sequentially distributes and supplies the data voltage obtained by time-division to each data line group. In each data line group, a data voltage is simultaneously supplied from the sampling circuit to each of the data lines belonging to the data line group, and is written in the corresponding pixel portion.

  In this aspect, a data voltage is supplied to the plurality of image signal lines from the different output circuits in the output circuit group alternately and periodically via the switching means. Therefore, in each data line group, the data lines belonging to the data line group are supplied with data voltages periodically and alternately output from different output circuits in the output circuit group via the sampling circuit.

  On the other hand, each of the image signal lines corresponding to the output circuit group is supplied with a data voltage from different output circuits via the switching means. That is, when viewed from the output circuit of the output circuit group, different output circuits are electrically connected to different image signal lines, and in each data line group, they are electrically connected to different data lines via sampling circuits. The

  Therefore, in this aspect, each of the output circuits belonging to the output circuit group can exchange the corresponding data line among the data lines belonging to the data line group for each data line group. Therefore, in each data line group, the data voltage output from each output circuit in the output circuit group can be distributed to each corresponding data line belonging to the data line group.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the above-described electro-optical device according to the present invention is provided, display unevenness due to data voltage variation can be reduced. Therefore, a projection display device, television, mobile phone, electronic notebook, word processor, viewfinder type or monitor direct-view type video tape recorder, workstation, videophone, POS terminal, touch panel capable of high-quality display Various electronic devices such as can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  In order to solve the above problems, a driving method for an electro-optical device according to an aspect of the invention includes a substrate and a plurality of pixel portions arranged on the substrate along a first direction and a second direction intersecting the first direction, An electro-optic comprising: a plurality of data lines provided on the substrate along the first direction; and a plurality of output circuits for outputting data voltages to the plurality of pixel portions via the plurality of data lines. In the driving method of the apparatus, for each output circuit group including two or more output circuits among the plurality of output circuits, the data lines corresponding to each other in each of the output circuits belonging to the output circuit group are A step of periodically switching the electrical connection of each of the output circuits belonging to the output circuit group to each of the data lines corresponding to the output circuit group so as to be interchanged.

  According to the driving method of the electro-optical device of the present invention, similarly to the electro-optical device of the present invention described above, in the electro-optical device, it is possible to reduce display unevenness due to data voltage variation.

  Note that the driving method of the electro-optical device of the present invention can also employ various aspects similar to the various aspects of the electro-optical device of the present invention described above.

  In order to solve the above problems, a drive circuit for an electro-optical device according to the present invention includes a substrate and a plurality of pixel portions arranged on the substrate along a first direction and a second direction intersecting the first direction, A drive circuit for driving an electro-optical device comprising a plurality of data lines provided along the first direction on the substrate, the plurality of data lines being connected to the plurality of pixel portions. A plurality of output circuits for outputting the data voltage and an output circuit group including two or more output circuits among the plurality of output circuits as a group, the output circuits belonging to the output circuit group correspond to each other. And switching means for periodically switching the electrical connection of the output circuits belonging to the output circuit group to each of the data lines corresponding to the output circuit group so that the data lines are switched.

  According to the drive circuit for an electro-optical device of the present invention, it is possible to reduce display unevenness due to data voltage variation in the electro-optical device, similarly to the electro-optical device of the present invention described above.

  The electro-optical device drive circuit of the present invention can also adopt various aspects similar to the various aspects of the electro-optical device of the present invention described above.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, the electro-optical device according to the first embodiment will be described with reference to the drawings. In the following, a drive circuit built-in type TFT (Thin Film Transistor) active matrix drive type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

  First, the configuration of the electro-optical panel in the electro-optical device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the electro-optical panel in the electro-optical device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line HH ′ of FIG.

  1 and 2, in the electro-optical panel according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. The TFT array substrate 10 is an example of the “substrate” in the present invention, and is, for example, a transparent substrate such as a quartz substrate or a glass substrate, a silicon substrate, or the like. The counter substrate 20 is a transparent substrate such as a quartz substrate or a glass substrate. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20. The TFT array substrate 10 and the counter substrate 20 are bonded to each other by a sealing material 52 provided in a sealing region located around the image display region 10a provided with a plurality of pixel electrodes.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material 56 such as glass fiber or glass bead for dispersing the distance between the TFT array substrate 10 and the counter substrate 20 (that is, the inter-substrate gap) to a predetermined value is dispersed.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  A time division circuit 42 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the seal region where the seal material 52 is disposed in the peripheral region. The scanning line driving circuit 104 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display area 10 a in this way, a plurality of the pixel lines are covered along the remaining side of the TFT array substrate 10 and covered with the frame light shielding film 53. Wiring 105 is provided.

  On the TFT array substrate 10, vertical conduction terminals 106 for electrically connecting the two substrates with a vertical conduction material are disposed in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 2, a pixel electrode 9a (shown as a pixel electrode 22a in FIG. 5) after a pixel switching TFT, a scanning line, a data line, and the like are formed on the TFT array substrate 10 is shown. An alignment film 16 is formed thereon. The pixel electrode 9a is made of a transparent conductive film such as an ITO film, and the alignment film 16 is made of an organic film such as a polyimide film. On the other hand, on the counter substrate 20, after forming a lattice-shaped or stripe-shaped light shielding film 23, a counter electrode 21 is provided over the entire surface, and further, an alignment film 22 is formed in the uppermost layer portion. ing. The counter electrode 21 is made of a transparent conductive film such as an ITO film, and the alignment film 22 is made of an organic film such as a polyimide film. A liquid crystal layer 50 is formed between the TFT array substrate 10 and the counter substrate 20 that are configured as described above and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  1 and FIG. 2, on the TFT array substrate 10, in addition to the drive circuits such as the time division circuit 42 and the scanning line drive circuit 104, the image signal on the image signal line is sampled to obtain the data line. A sampling circuit that supplies a precharge signal at a predetermined voltage level to a plurality of data lines in advance of an image signal, and inspects the quality, defects, etc. of the electro-optical device during manufacture or at the time of shipment An inspection circuit or the like may be formed.

  Next, the configuration of the electro-optical device according to the present embodiment will be schematically described with reference to FIGS. 3 to 6. FIG. 3 is a perspective view schematically showing the overall configuration of the electro-optical device, and FIG. 4 is a circuit diagram showing a specific configuration of the electro-optical device according to the present embodiment. FIG. 5 is a circuit diagram showing the configuration of the pixel portion, and FIG. 6 is a block diagram showing the configuration of the driver IC.

  3, the electro-optical device according to the present embodiment includes the electro-optical panel described with reference to FIGS. 1 and 2, a flexible substrate 200, and a driver IC 41.

  The flexible substrate 200 is electrically connected to the electro-optical panel via the external circuit connection terminal 102. In addition, the end portion on the side not connected to the electro-optical panel is electrically connected to a circuit board (not shown) or the like. That is, the image signal is supplied from the circuit board or the like to the electro-optical panel via the flexible board 200.

  The driver IC 41 is provided on the flexible substrate 200 outside the electro-optical panel, and is constructed as an image signal supply device or circuit for the electro-optical panel. In addition, the driver IC 41 may be configured to execute correction processing such as gamma correction and serial-parallel conversion. The driver IC 41 may be constructed as a circuit or device built in the electro-optical panel. In such a case, the driver IC 41 may be constructed including the time division circuit 42, the scanning line driving circuit 104, etc. described above. Good. In this case, output circuits 41f1 to 41fi (see FIG. 6) of the driver IC 41 and switching means 41H (see FIG. 6), which are main components of the present embodiment to be described later, are built-in on the TFT array substrate 10. It will be built in the circuit. A more detailed configuration of the driver IC 41 will be described later.

  As shown in FIG. 4, the electro-optical panel is an active matrix display panel in which a liquid crystal element is driven by a switching element such as a TFT. In the image display area 10a of the electro-optical panel, m dots × n lines of pixel portions 2 are arranged in a matrix (two-dimensional plane). In the image display area 10a, n scanning lines Y1 to Yn each extending in the row direction (that is, the X direction) and each extending in the column direction (that is, the Y direction). M data lines X1 to Xm are provided, and the pixel portion 2 is arranged corresponding to these intersections. In the following description, when a certain pixel portion 2 in the image display area 10a is specified, the subscripts 1 to m of the data line X and the subscripts 1 to n of the scanning line Y are used, and these intersections (1 to m , 1-n). For example, the upper left pixel 2 is (1, 1), and the lower right pixel 2 is (m, n).

  FIG. 5 shows an example of the configuration of one pixel unit 2. The pixel unit 2 includes a TFT 21 that is a switching element, a liquid crystal capacitor 22, and a storage capacitor 23. The source of the TFT 21 is connected to one data line X, and its gate is connected to one scanning line Y. Regarding the pixel portions 2 arranged in the same column, the sources of the respective TFTs 21 are connected to the same data line X. For the pixels 2 arranged in the same row, the gates of the respective TFTs 21 are connected to the same scanning line Y. The drain of the TFT 21 is commonly connected to a liquid crystal capacitor 22 and a storage capacitor 23 that are electrically parallel to each other. The liquid crystal capacitor 22 includes a pixel electrode 22a, a counter electrode 22b, and a liquid crystal layer sandwiched between these electrodes 22a and 22b. The storage capacitor 23 is formed between the pixel electrode 22a and a common capacitor electrode (not shown), and is supplied with the voltage Vcs. The storage capacitor 23 suppresses the influence of leakage of charges accumulated in the liquid crystal. On the other hand, a data voltage or the like is applied to the pixel electrode 22a side via the TFT 21, and the liquid crystal capacitor 22 and the storage capacitor 23 are charged / discharged according to the applied voltage level. Thereby, the transmittance of the liquid crystal layer is set according to the potential difference between the pixel electrode 22a and the counter electrode 22b (that is, the applied voltage of the liquid crystal), and the gradation of the pixel unit 2 is set.

  Returning to FIG. 4, the driving of the pixel unit 2 is preferably performed by AC driving in which the voltage polarity is inverted every predetermined period in order to extend the life of the liquid crystal. The voltage polarity is defined based on the direction of the electric field acting on the liquid crystal layer, in other words, based on the forward and reverse of the voltage applied to the liquid crystal layer. In the present embodiment, typically, common DC driving, which is one type of alternating drive, that is, the voltage Vlcom applied to the counter electrode 22b and the voltage Vcs applied to the common capacitor electrode are kept constant, and the pixel A driving method in which the polarity on the electrode 22a side is reversed is adopted.

  The control circuit 5 is based on external signals such as a vertical synchronization signal Vs, a horizontal synchronization signal Hs, and a dot clock signal DCLK that are input from a host device (not shown). Are controlled synchronously. Under this synchronous control, the scanning line driving circuit 104 and the data line driving circuit 101 cooperate with each other to perform display control in the image display region 10a. In this embodiment, in order to suppress the occurrence of flicker by high-speed display, a double speed drive in which the refresh rate (that is, the vertical synchronization frequency) is set to 120 [Hz] corresponding to twice the normal speed is adopted. . In this case, one frame (that is, 1/60 [Sec]) defined by the vertical synchronization signal Vs is composed of two fields, and two line sequential scans are performed in one frame.

  The scanning line driving circuit 104 is mainly configured by a shift register, an output circuit, and the like, and outputs a scanning signal SEL to each of the scanning lines Y1 to Yn (see FIG. 8 to be described later). The scanning lines Y1 to Yn are sequentially selected every one horizontal scanning period (hereinafter referred to as “1H”) corresponding to the period in which is selected. The scanning signal SEL (see FIG. 8) takes a binary level of a high potential level (hereinafter referred to as “H level”) or a low potential level (hereinafter referred to as “L level”), and is a pixel to which data is to be written. The scanning line Y corresponding to the row is set to the H level, and the other scanning lines Y are set to the L level. By this scanning signal SEL, pixel rows to which data is to be written are sequentially selected, and data written in the pixel portion 2 is held over one field.

  The frame memory 6 has at least an m × n-bit memory space corresponding to the resolution in the image display area 10a, and stores and holds display data input from the host device in units of frames. Writing of data to the frame memory 6 and reading of data from the frame memory 6 are controlled by the control circuit 5. Here, the display data D defining the gradation of the pixel unit 2 is, for example, 64 gradation data composed of 6 bits D0 to D5. The display data D read from the frame memory 6 is serially transferred to the data line driving circuit 101 via a 6-bit bus.

  Here, the control circuit 5 and the frame memory 6 are provided together with the driver IC 41 on the flexible board 200 shown in FIG. 3 or are built in a circuit board electrically connected to the electro-optical panel via the flexible board 200. You may be made to do. Alternatively, at least a part of the control circuit 5 and the frame memory 6 may be built in the electro-optical panel.

  The data line driving circuit 101 provided in the subsequent stage of the frame memory 6 outputs data to be supplied for each pixel row to which data is to be written to the data lines X1 to Xm in cooperation with the scanning line driving circuit 104. To do. The data line driving circuit 101 includes a driver IC 41 provided outside the electro-optical panel as shown in FIG. 3, and a time division circuit 42 built in the TFT array substrate 10 as shown in FIG. 1 or FIG. ing. Output lines DO1 to DOi are electrically connected to i output pins PIN1 to PINi of the driver IC 41. The time division circuit 42 is integrally formed on the display panel by polysilicon TFTs or the like in order to reduce manufacturing costs. Although the detailed configuration is shown in a simplified manner in FIG. 4, the i output pins PIN1 to PINi of the driver IC 41 are external circuit connection terminals 102 (FIG. 1 or FIG. 1) of the corresponding electro-optical panel. It is typically assumed that the output lines DO1 to DOi wired on the TFT array substrate 10 are electrically connected to each other via the reference (FIG. 2).

  The driver IC 41 simultaneously outputs data for the pixel row to which data is written this time and performs dot sequential latching (ie, holding) of data relating to the pixel row to which data is to be written next time, as well as time-series voltages (typical Is configured to output a data voltage). Hereinafter, the configuration and operation of the driver IC 41 will be described in detail.

  In FIG. 6, the driver IC 41 includes main circuits such as an X shift register 41a, a first latch circuit 41b, a second latch circuit 41c, a changeover switch group 41d, and a D / A conversion circuit 41e. The X shift register 41a transfers the start signal ST supplied first at 1H according to the clock signal CLX, and sets any one of the latch signals S1, S2, S3,. To do. The first latch circuit 41b sequentially latches m pieces of 6-bit data D supplied as serial data when the latch signals S1, S2, S3,. The second latch circuit 41c simultaneously latches the data D latched by the first latch circuit 41b when the latch pulse LP falls. The latched m pieces of data D are output in parallel from the second latch circuit 41c as data signals d1 to dm which are digital data in the next 1H.

  For example, the data signals d1 to dm are grouped as time-series data for four pixels by m / 4 (= i) changeover switch groups 41d provided in units of four data lines. . Here, the single changeover switch group 41d is illustrated as a set of five switches, but actually has five systems of 6-bit switch groups. Since six switches in the same system always operate in the same manner, the following description will be made assuming that the six switches are one switch. The same applies to the selection switches (one selection switch is one system) constituting the time division circuit 42 corresponding to the changeover switch group 41d.

  In addition to the data signals (for example, d1 to d4) for four pixels output from the second latch circuit 41c, the correction data damd is also input to each changeover switch group 41d. The correction data damd is digital data that defines a voltage level of a correction voltage Vamd described later. The five switches constituting the changeover switch group 41d are conduction-controlled by any of the five control signals CNT1 to CNT5, and are sequentially turned on alternately at the offset timing. Thereby, in 1H, the set of the correction data damd and the data signals d1 to d4 for four pixels is time-series in this order (in order of damd, d1, d2, d3, and d4). Output in time series.

  The digital data arranged in time series output in this way is D / A converted by a D / A (Digital to Analog) conversion circuit 41e, and each is outputted as analog data arranged in time series. . Here, in FIG. 6, four pixels of each of the data signals d1 to dm are grouped as one group, and each group from the D / A conversion circuit 41e is divided into data voltages Vg1, Vg2, Vg3, Vg4,. 1, converted to Vgi and output. The correction data damd is analogized and output as a correction voltage Vamd shown in FIG.

  In FIG. 6, in the driver IC 41, the data voltages Vg1, Vg2, Vg3, Vg4,..., Vgi-1, Vgi output from the D / A conversion circuit 41e are output circuits 41f1, 41f2, 41f3, 41f4, respectively. ... amplified at each of 41fi-1 and 41fi and output from the output pins PIN1 to PINi via the switching means 41H.

  As shown in FIG. 4, any of output lines DO1 to DOi is connected to the output pins PIN1 to PINi of the driver IC 41. One output line DO is associated with a data line group including a group of four adjacent data lines X, and a time division circuit 42 is provided between the output line DO and the data line group. It is provided for each output line. Each time division circuit 42 has four selection switches corresponding to the number of data lines X in the data line group, and each selection switch is one of the selection signals SS1 to SS4 from the control circuit 5. The conduction is controlled by. The selection signals SS1 to SS4 define the ON period of the selection switch in the same group and are synchronized with the time-series signal output from the driver IC 41. The i time division circuits 42 have the same configuration, and all of them operate simultaneously.

  Although the detailed operation of each time division circuit 42 will be described later, based on the selection signals SS1 to SS4, switching means from each of the output circuits 41f1, 41f2, 41f3, 41f4,..., 41fi-1, 41fi. When the correction voltage Vamd (see FIG. 8) is supplied for the correction voltage Vamd and the data voltages Vg1, Vg2, Vg3, Vg4,..., Vgi-1, Vgi supplied via 41H, it is preferable for the data line group. Are simultaneously supplied, and the data voltages Vg1, Vg2, Vg3, Vg4,..., Vgi-1, and Vgi are time-divided and distributed to the respective data lines X of the data line group.

  Here, with reference to FIG. 7 in addition to FIG. 6, the detailed configuration and operation of the switching means 41H in the driver IC 41 will be described.

  The switching unit 41H switches the electrical connection of each of the output circuits 41f1 to 41fi to the data line X by switching the electrical connection of each of the output circuits 41f1 to 41fi to the data line X. It is configured to be interchangeable. According to the switching means 41H, among the plurality of output circuits 41f1 to 41fi, for example, as shown in FIG. 6, an output circuit group including two adjacent output circuits (for example, 41f1 and 41f2 or 41f3 and 41f4) as a group. For each of 41F1 to 41Fj, the electrical connection to each of the corresponding data lines X is periodically switched.

  More specifically, the switching means 41H has a selector switch group 41h provided for each of the output circuits 41f1 to 41fi. These changeover switch groups 41h preferably have the same configuration. If attention is paid to the two changeover switch groups 41h corresponding to one output circuit group 41F1 in FIG. Includes as many output switches 41ha and 41hb as the number of output circuits 41f1 and 41f2 belonging to the output circuit group 41F1. The changeover switches 41ha and 41hb can each be constituted by, for example, a P-channel type or N-channel type single-channel TFT or a complementary TFT. Therefore, in the present embodiment, effects such as simplifying the configuration of the switching means 41H, easily miniaturizing the driver IC 41, and downsizing can be expected.

  For each changeover switch group 41h corresponding to one output circuit group 41F1, the two changeover switches 41ha and 41hb belonging thereto are electrically connected to the different output circuits 41f1 and 41f2 of the output circuit group 41F1, respectively. . In the same selector switch group 41h, the two selector switches 41ha and 41hb are electrically connected to the same output pin PIN1 or PIN2.

  A number corresponding to the two changeover switches 41ha and 41hb belonging to the changeover switch group 41h, that is, two changeover signals Sa and Sb are input from the control circuit 5 shown in FIG. The two changeover signals Sa and Sb are periodically input alternately from the control circuit 5, one changeover switch 41ha is selected according to one changeover signal Sa, and another changeover switch 41hb according to the other changeover signal Sb. Is selected. That is, the different selector switches 41ha and 41hb in the selector switch group 41h are periodically selected based on the different selector signals Sa and Sb, and the different output circuits 41f1 and 41f2 in the output circuit group F1 are the same output pin PIN1 or PIN2. Are electrically connected to the time division circuit 42 via the corresponding output lines DO1 or DO2.

  Therefore, in FIG. 4, the data voltage Vg1 or Vg2 is periodically and alternately supplied from the output circuits 41f1 and 41f2 to the two time division circuits 42 corresponding thereto from the output circuit group F1. Therefore, the data lines X1 to X4 and X5 to X8 belonging to the data line group corresponding to the two time division circuits 42 are periodically and alternately output from the different output circuits 41f1 and 41f2 in the output circuit group F1. The data voltage Vg1 or Vg2 is supplied.

  On the other hand, in FIG. 6, in the changeover switch group 41h corresponding to the output circuit group F1, output circuits 41f1 and 41f2 different from each other in the output circuit group F1 are selected in accordance with the one changeover signal Sa or Sb. Therefore, in FIG. 4, in the two time division circuits 42 corresponding to the output circuit group F1, the data voltages Vg1 and Vg2 are supplied from the output circuits 41f1 and 41f2 that are different from each other in the output circuit group F1, respectively. Accordingly, when viewed from the output circuit group F1, the different output circuits 41f1 and 41f2 are electrically connected to different time division circuits 42 and electrically connected to different data line groups.

  As a result, in this embodiment, in each of the output circuits 41f1 and 41f2 belonging to the output circuit group F1, the data line groups corresponding to each other periodically are changed by the changeover switch group 41h based on the different changeover signals Sa and Sb. The corresponding data lines X can be interchanged with each other. Therefore, by periodically supplying different switching signals Sa and Sb to the changeover switch group 41h, the corresponding data lines are respectively generated in the output circuits 41f1 and 41f2 in the output circuit group F1 by the changeover switches 41ha and 41hb. X can be easily replaced.

  Next, the operation of the switching means 41H will be described with reference to FIG. FIG. 7 is a timing chart for explaining the operation of the switching means according to this embodiment. As described above, the selector switch groups 41h of the switching means 41H preferably have the same configuration and perform the same operation. Therefore, in FIG. 7, the operation of each of the output circuit group 41F1 and the other output circuit group 41F2 adjacent to the output circuit group 41F1 will be described by focusing on the corresponding changeover switch group 41h.

  Here, in FIG. 7, as described with reference to FIG. 4, the output circuit group 41F1 adjacent to each other shown in FIG. Two changeover signals Sa and Sb are alternately supplied from the control circuit 5 to each changeover switch group 41h corresponding to 41F2.

  In FIG. 7, when one switching signal Sa of the two switching signals Sa and Sb becomes H level, one corresponding switching switch 41ha is selected from each switching switch group 41h. Thus, for the output circuits 41f1 and 41f2 belonging to one output circuit group 41F1, the data voltage Vg1 output from one output circuit 41f1 is output from the output pin PIN1 to the corresponding output line DO1 via the changeover switch 41ha. The data voltage Vg2 output from the other output circuit 41f2 is output from the output pin PIN2 to the corresponding output line DO2 via the changeover switch 41ha. Accordingly, the data voltages Vg1 and Vg2 output from the output lines DO1 and DO2 are respectively supplied from the time division circuit 42 to the data line group, and the data voltage Vg1 is time-divided and distributed to each of the data lines X1 to X4. The data voltage Vg2 is distributed in time division to each of the data lines X5 to X8.

  On the other hand, similarly for the other output circuit group 41F2, for the output circuits 41f3 and 41f4 belonging thereto, the data voltage Vg3 is output from one output circuit 41f3 to the output line DO3 from the other output circuit PIN3, and from the other output circuit 41f4. The output data voltage Vg4 is output from the output pin PIN4 to the output line DO4. Accordingly, the data voltages Vg3 and Vg4 output from the output lines DO3 and DO4 are respectively supplied from the time division circuit 42 to the data line group in the same manner as the data voltages Vg1 and Vg2.

  In FIG. 7, when the other switching signal Sb of the two switching signals Sa and Sb becomes H level, the corresponding other switching switch 41hb is selected from each switching switch group 41h. As a result, when one selector switch 41ha is selected, the output circuits 41f1 and 41f2 belonging to the one output circuit group 41F1 are interchanged with the corresponding output lines DO1 and DO2, respectively. Correspondences with each of the data lines X1 to X4 and X5 to X8 are also switched. Specifically, the data voltage Vg1 output from one output circuit 41f1 is output from the output pin PIN2 to the corresponding output line DO2 via the changeover switch 41hb, and the data voltage Vg2 output from the other output circuit 41f2 is output. The signal is output from the output pin PIN1 to the corresponding output line DO1 via the changeover switch 41hb. Therefore, the data voltages Vg1 and Vg2 output from the output lines DO1 and DO2 are respectively supplied from the time division circuit 42 to the data line group, and the data voltage Vg1 is time-divided and distributed to each of the data lines X5 to X8. The data voltage Vg2 is distributed in time division to each of the data lines X1 to X4.

  On the other hand, similarly for the other output circuit group 41F2, for the output circuits 41f3 and 41f4 belonging thereto, the data voltage Vg3 is output from one output circuit 41f3 to the output line DO4 from the other output circuit PIN4, and from the other output circuit 41f4. The output data voltage Vg4 is output from the output pin PIN3 to the output line DO3. Accordingly, the data voltages Vg3 and Vg4 output from the output lines DO3 and DO4 are respectively supplied from the time division circuit 42 to the data line group in the same manner as the data voltages Vg1 and Vg2.

  Therefore, according to the operation shown in FIG. 7, the switching means 41H causes the output circuits belonging to each of the output circuit groups 41F1 to 41Fj (for example, each of the output circuits 41f1 and 41f2 of the output circuit group 41F1) to cross each other for every 1H. The electrical connection of each output circuit to the data line is switched so that the data lines corresponding to (for example, the data lines X1 to X4 or X5 to X8) are switched.

  Here, the operation of the time division circuit 42 shown in FIG. 4 will be specifically described with reference to FIG. FIG. 8 is a timing chart of time division driving in the data line driving circuit according to the present embodiment.

  As described above, in FIG. 4, the i time division circuits 42 have the same configuration, and all operate in parallel. Therefore, in the following description, the data voltage Vg1 or Vg2 is Description will be made by paying attention only to the system of the output line DO1 to be output. That is, the process of the system of the output line DO1 described below is similarly performed in parallel for each system from the output line DO2 to the output line DOi.

  In FIG. 4, the leftmost time division circuit 42 connected to the output line DO1 uses the four data lines X1 to X4 of the corresponding line group to output the correction voltage Vamd output to the output line DO1 as four data. The lines X1 to X4 are supplied simultaneously. The time division circuit 42 time-divides one of the supplied data voltages Vg1 and Vg2 in which four time-sequential pixels are grouped into one group, and obtains the individual data voltages thus obtained from the data lines X1 to X1. Sort to any of X4.

  Specifically, in FIG. 8, in the first 1H in one field, the scanning signal SEL1 becomes H level, and the uppermost scanning line Y1 shown in FIG. 4 is selected. In 1H, the correction voltage Vamd is first output to the output line DO1, and subsequently, the data voltage Vg1 or Vg2 for four pixels corresponding to each intersection of the data lines X1 to X4 and the scanning line Y1 is applied. V (1,1), V (2,1), V (3,1), V (4,1) are sequentially output.

  In a state where the correction voltage Vamd is output to the output line DO1, the selection signals SS1 to SS4 simultaneously become H level, and the four switches constituting the time division circuit 42 are turned on all at once. As a result, the correction voltage Vamd output to the output line DO1 is simultaneously supplied to the data lines X1 to X4.

  Next, in a state where V (1,1) is output to the output line DO1, only the selection signal SS1 becomes H level, and among the switches constituting the time division circuit 42, the switch corresponding to the data line X1. Only turn on. As a result, the data voltage V (1, 1) output to the output line DO1 is supplied to the data line X1, and data is written to the pixel (1, 1) according to the data voltage V (1, 1). Done. While the data voltage V (1,1) is being output to the output line DO1, the switches corresponding to the data lines X2, X3, and X4 remain off, so the voltages on the data lines X2, X3, and X4 are corrected. The voltage Vamd is maintained (precisely, the voltage level decreases with time due to leakage).

  Subsequently, in a state where the data voltage V (2, 1) is output to the output line DO1, only the selection signal SS2 becomes H level, and only the switch corresponding to the data line X2 in the time division circuit 42 is turned on. . Thereby, data is written to the pixel (2, 1) via the data line X2 based on the data voltage V (2, 1). Similar to the output state of the data voltage V (1,1) described above, at this time, the data line X1 is maintained at the data voltage V (1,1), and the data lines X3 and X4 are maintained at the correction voltage Vamd.

  Similarly, in a state where the data voltage V (3, 1) is output to the output line DO1, only the selection signal SS3 becomes H level, and only the switch corresponding to the data line X3 in the time division circuit 42 is turned on. . Thus, data is written to the pixel (3, 1) via the data line X3 based on the data voltage V (3, 1). At this time, the data line X1 is maintained at the data voltage V (1, 1), the data line X2 is maintained at the data voltage V (2, 1), and the data line X4 is maintained at the correction voltage Vamd.

  Finally, in a state where the data voltage V (4, 1) is output to the output line DO1, only the selection signal SS4 becomes H level and corresponds to the data line X4 among the switches constituting the time division circuit 42. Only the switch to turn on. As a result, data is written to the pixel (4, 1) via the data line X4 based on the data voltage V (4, 1). At this time, the data line X1 is maintained at the data voltage V (1, 1), the data line X2 is maintained at the data voltage V (2, 1), and the data line X3 is maintained at the data voltage V (3, 1).

  In the next 1H, the scanning signal SEL2 becomes H level, and the second scanning line Y2 from the top is selected. In 1H, the correction voltage Vamd is first output to the output line DO1, and subsequently, as the other of the supplied data voltages Vg1 and Vg2, at each intersection of the data lines X1 to X4 and the scanning line Y2. Data voltages V (1,2), V (2,2), V (3,2), V (4,2) for the corresponding four pixels are sequentially output. The process at 1H is the same as that at 1H except that the polarity of the voltage output to the output line DO1 is inverted, and the supply of the correction voltage Vamd and the time-series data voltage V (1 , 2), V (2, 2), and V (3, 2) are distributed. The same applies to the subsequent steps. While the polarity is inverted every 1H until the lowest scanning line Yn is selected, the supply of the correction voltage Vamd to each pixel row and the subsequent distribution of the data voltage are performed. It is performed line-sequentially. 4 shows an example in which the polarity of the voltage output to the output line DO1 is inverted every 1H period, the same applies to the case where the polarity is inverted every field or every frame. Operate.

  Therefore, in the present embodiment described above, according to the switching means 41H described with reference to FIG. 6 or FIG. 7, in each of the output circuits belonging to each of the output circuit groups 41F1 to 41Fj, periodically every 1H, For example, in one output circuit group 41F1, the output lines 41f1 and 41f2 which are different from each other replace the corresponding data lines X, and outputs (data voltages Vg1 and Vg2) of the respective output circuits (for example, the output circuits 41f and 41f2). Can be distributed to each of the data lines (each of the data lines X1 to X8) for each corresponding data line group.

  As a result, for example, the outputs (data voltages Vg1 and Vg2) of the output circuits 41f and 41f2 in the output circuit group 41F1 are distributed to the pixel unit 2 corresponding to each of the data lines X1 to X8. According to the operation of the switching means 41H shown in FIG. 7, in each of the data lines X1 to X8 corresponding to the output circuit group 41F1, the correspondence relationship with each of the output circuits 41f and 41f2 is set for each data line group every 1H. Instead, in each of the pixel columns corresponding to these data lines X1 to X8, each output (data voltages Vg1 and Vg2) of the output circuits 41f and 41f2 in the output circuit group 41F1 is distributed to each pixel unit 2. For the other output circuit groups 41F2 to 41Fj, the output of each output circuit can be distributed to the pixel unit 2 as in the output circuit group 41F1.

  Therefore, in the present embodiment, data is output due to variations in the data voltage output from each output circuit (for example, each of the output circuits 41f and 41f2) in each output circuit group 41F1 to 41Fj (for example, the output circuit group 41F1). It is possible to prevent the display unevenness in the line shape from being noticeable on the display screen along the extending direction of the line X. Accordingly, it is possible to reduce display unevenness due to data voltage variations in the electro-optical device, and it is possible to display a high-quality image.

  Further, in FIG. 7 described above, the case where the two switching signals Sa and Sb are alternately supplied from the control circuit 5 every 1H has been described. However, the present embodiment is not limited to this, and two switching signals Sa and Sb are supplied. For example, the signals Sa and Sb may be alternately supplied every frame. In this case, each of the output circuits belonging to each of the output circuit groups 41F1 to 41Fj (for example, the output circuits 41f1 and 41f2 of the output circuit group 41F1) based on the switching signals Sa and Sb by the changeover switch group 41h of the switching means 41H. ), The electrical connection of each output circuit to the data line is switched so that the corresponding data lines (for example, the data lines X1 to X4 or X5 to X8) are switched every frame period.

  Accordingly, each of the output circuit groups 41F1 to 41Fj (for example, the output circuit group 41F1) has a corresponding relationship with each of the output circuits (for example, the output circuits 41f1 and 41f2) belonging to the corresponding data line group for each frame period. In each of the pixel columns corresponding to the data lines belonging to the data line group (for example, the data lines X1 to X4 or X5 to X8), each output circuit (for example, each of the output circuits 41f1 and 41f2) is replaced. Outputs (eg, data voltages Vg1 and Vg2) are distributed. Therefore, even in this case, the line-shaped display unevenness is caused by the variation in the data voltage of each output circuit (for example, each output circuit 41f1 and 41f2) in each output circuit group 41F1 to 41Fj (for example, output circuit group 41F1). Remarkably visible on the display screen can be suppressed.

  In the first embodiment described above, for each output circuit group 41F that includes two output circuits 41f adjacent to each other as a group, the two output circuits 41f belonging to the output circuit group 41F are electrically connected to the data line X. However, the cycle for switching the electrical connection is not limited to 1H, and may be a period that is an integral multiple of one horizontal scanning period, such as 2H, 3H, and 4H. A period that is an integral multiple of one frame period, such as a frame period, three frame periods, or four frame periods, may be used. Further, the output circuit group 41F is not limited to the one constituted by the two output circuits 41f adjacent to each other, and for example, every other output circuit 41f arranged corresponding to the data line X, or Alternatively, two output circuits 41f that are separated from each other (that is, output circuits 41f belonging to another output circuit group 41F are disposed between them), such as every other two, may be used. Further, the output circuit group 41F is not limited to the one constituted by the two output circuits 41f, and may be constituted by three or more output circuits 41f. In this case, since the electrical connection between the three or more output circuits 41f and the corresponding three or more data lines X can be switched periodically, the display is based on variations in the data voltage output from the output circuit 41f. Unevenness can be further reduced.

Second Embodiment
Next, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment will be described with reference to the drawings centering on differences from the first embodiment, and the same configurations as those of the first embodiment will be denoted by the same reference numerals in FIGS. 9 to 11. In some cases, duplicate descriptions are omitted.

  FIG. 9 schematically shows the configuration of the external circuit according to the second embodiment, and FIG. 10 is a circuit diagram showing the specific configuration of the electro-optical panel according to the second embodiment. The second embodiment includes an electro-optical panel having the configuration shown in FIG. 10 and an external circuit shown in FIG. 9 provided outside the electro-optical panel. Note that at least a part of the external circuit (for example, the switching unit 41H or the output circuits 41f1 to 41f4) in FIG. 10 may be built in the electro-optical panel.

  In FIG. 9, the control circuit 5 includes a frame memory 6 and a scanning line driving circuit 104 which is a built-in circuit shown in FIG. 10 based on external signals such as a vertical synchronizing signal Vs, a horizontal synchronizing signal Hs, and a dot clock signal DCLK. The data line driving circuit 101 is synchronously controlled. The control circuit 5 writes and reads data for the display data stored / held in the frame memory 6. The control circuit 5 performs serial-parallel expansion (that is, phase expansion) of the read display data D into, for example, four phases, and generates data voltages Vd1 to Vd4.

  Each of the data voltages Vd1 to Vd4 is amplified by the four output circuits 41f1 to 41f4, and is output from the output pins PIN1 to PIN4 via the switching means 41H.

  In FIG. 10, in the electro-optical panel, the data line driving circuit 101 and the scanning line driving circuit 104 cooperate with each other to perform active matrix driving on the pixel portion 2 for m dots × n lines in the image display region 10a. That is, the scanning lines Y1 to Yn are sequentially selected by the scanning line driving circuit 104, and the data line driving circuit 101 synchronizes with each of the scanning lines Y1 to Yn, and sets the data lines X1 to Xm to the pixel rows corresponding to the selected scanning line Y. A signal is generated so that data is supplied through the network. In the second embodiment, the data line driving circuit 101 is typically arranged on the TFT array substrate 10 together with the sampling circuit 107 in the electro-optical panel shown in FIG. 1 or 2 instead of the time division circuit 42, for example. Is done.

  10, output pins PIN1 to PIN4 of the external circuit shown in FIG. 9 are electrically connected to, for example, four image signal lines Vi1 to Vi4 wired on the TFT array substrate 10 in the electro-optical panel. In more detail, for example, the output pins PIN1 to PIN4 are electrically connected to the four image signal lines Vi1 to Vi4 via the external circuit connection terminals 102 on the TFT array substrate 10. For this configuration, Illustration is omitted.

  From the data line driving circuit 101, sampling circuit driving signals S1 to Si are sequentially output. The sampling circuit 107 samples the data voltages Vd1 to Vd4 supplied to the image signal lines Vi1 to Vi4 according to the sampling circuit drive signals S1 to Si, and supplies them to the data line X. For example, as shown in FIG. 10, the sampling circuit 107 includes a sampling switch 71 formed of a P-channel or N-channel single-channel TFT or a complementary TFT.

  In the sampling circuit 107, four sampling switches 71 correspond to the image signal lines Vi1 to Vi4 as a group, and each sampling switch 71 belonging to the group samples the data voltages Vd1 to Vd4 according to the same sampling signal S all at once. Then, the data is supplied to the corresponding data line X. Accordingly, each of the data lines X1 to Xm is driven for each data line group including four lines, and data is written to the pixel row to be written.

  That is, each of the image signal lines Vi1 to Vi4 is electrically connected to one of the data lines X belonging to each data line group via the sampling switch 71 of the sampling circuit 107. Therefore, each of the data voltages Vd1 to Vd4 supplied to the image signal lines Vi1 to Vi4 is a time-series voltage in which the data of the corresponding data line X among the data line groups is one group. In the sampling circuit 107, each of the data voltages Vd1 to Vd4 supplied from the image signal lines Vi1 to Vi4 is time-divided and distributed to each data line group.

  Next, in addition to FIGS. 9 and 10, the switching means 41H in the external circuit will be described with reference to FIG.

  In FIG. 9, the configuration of the switching means 41H is the same as that of the first embodiment. However, when attention is focused on one output circuit group 41F1, each of the corresponding switch groups 41h has a corresponding output pin PIN1 or It is electrically connected to the image signal line Vi1 or Vi2 in FIG. 10 via PIN2. In each changeover switch group 41h, different changeover switches 41ha and 41hb are periodically selected in accordance with one of the two changeover signals Sa and Sb, and the image signal line Vi1 or Vi2 is output via the output pin PIN1 or PIN2. Is electrically connected. Therefore, the data voltages Vd1 and Vd2 are periodically and alternately supplied from the different output circuits 41f1 and 41f2 to the corresponding two image signal lines Vi1 and Vi2 from the output circuit group 41F1. Therefore, in each data line group, the output circuit group F1 is different for each of the data lines (for example, the data lines X1 and X2 or the data lines X5 and X6) corresponding to the two image signal lines Vi1 and Vi2. Data voltages Vd1 and Vd2 output alternately and periodically from the output circuits 41f1 and 41f2 are supplied.

  On the other hand, in FIG. 9, in the changeover switch group 41h corresponding to the output circuit group F1, output circuits 41f1 and 41f2 different from each other in the output circuit group F1 are selected in accordance with one switching signal Sa or Sb. Therefore, in FIG. 10, the data voltages Vd1 and Vd2 are supplied from the different output circuits 41f1 and 41f2 of the output circuit group F1 to the two image signal lines Vi1 and Vi2 corresponding to the output circuit group F1, respectively. Therefore, when viewed from the output circuit group F1, the different output circuits 41f1 and 41f2 are electrically connected to the different image signal lines Vi1 and Vi2, and different data lines (for example, the data lines X1 and X1) in each data line group. X2 or data lines X5 and X6).

  As a result, in this embodiment, each of the output circuits 41f1 and 41f2 belonging to the output circuit group F1 is periodically connected to each other by the changeover switch group 41h based on the different changeover signals Sa and Sb. Corresponding data lines (for example, data lines X1 and X2 or data lines X5 and X6) can be exchanged. Therefore, by periodically supplying different switching signals Sa and Sb to the changeover switch group 41h, the corresponding data lines are respectively generated in the output circuits 41f1 and 41f2 in the output circuit group F1 by the changeover switches 41ha and 41hb. X can be easily replaced.

  Next, the operation of the switching means 41H will be described with reference to FIG. FIG. 11 is a timing chart for explaining the operation of the switching means according to the second embodiment. In FIG. 11, the operation of each of the output circuit group 41F1 and the other output circuit group 41F2 adjacent to the output circuit group 41F1 will be described by focusing on the corresponding changeover switch group 41h.

  In FIG. 11, two switch signals Sa and Sb are alternately supplied from the control circuit 5 to each switch group 41 h corresponding to the adjacent output circuit groups 41 F 1 and 41 F 2 shown in FIG. When one switching signal Sa of the two switching signals Sa and Sb becomes H level, one corresponding switching switch 41ha is selected from each switching switch group 41h. Accordingly, in one output circuit group 41F1, the data voltage Vd1 is output from the one output circuit 41f1 to the image signal line Vi1, and the data voltage Vd2 is output from the other output circuit 41f2 to the image signal line Vi2. Similarly, in the other output circuit group 41F2, the data voltage Vd3 is output from the one output circuit 41f3 to the image signal line Vi3, and the data voltage Vd4 is output from the other output circuit 41f4 to the image signal line Vi4.

  In FIG. 10, the data voltages Vd1 to Vd4 output from the image signal lines Vi1 to Vi4 are respectively distributed from the sampling circuit 107 to the data line groups, and the data lines belonging to the data line group (for example, the data lines X1 to X4, or Data lines X5 to X8) are supplied all at once. At this time, the data voltage Vd1 output to the image signal line Vi1 is the first data line (for example, the data line X1 or the data line X5) in each data line group, and the data voltage Vd2 output to the image signal line Vi2 is The data voltage Vd3 output to the second data line (for example, the data line X2 or the data line X6) and the image signal line Vi3 in each data line group is the third data line (for example, the data line X3 or the data line X3). The data voltage Vd4 output to the data line X7) and the image signal line Vi4 is supplied to the fourth data line (for example, the data line X4 or the data line X8) in each data line group.

  In FIG. 11, when the other switching signal Sb of the two switching signals Sa and Sb becomes H level, the corresponding other switching switch 41hb is selected from each switching switch group 41h. As a result, when one changeover switch 41ha is selected, the corresponding relationship with each of the image signal lines Vi1 and Vi2 is switched in each of the output circuits 41f1 and 41f2 belonging to the one output circuit group 41F1. The correspondence with the line X is also exchanged. Specifically, the data voltage Vd1 is output from one output circuit 41f1 to the image signal line Vi2, and the data voltage Vd2 is output from the other output circuit 41f2 to the image signal line Vi1.

  Similarly, for the other output circuit group 41F2, the data voltage Vd3 is output from the one output circuit 41f3 to the image signal line Vi4, and the data voltage Vd4 is output from the other output circuit 41f4 to the image signal line Vi3.

  In this case, for the data voltages Vd1 to Vd4 distributed from the image signal lines Vi1 to Vi4 to each data line group via the sampling circuit 107, the data voltage Vd1 is the second data in each data line group from the image signal line Vi2. Line (for example, data line X2 or data line X6), data voltage Vd2 is the first data line (for example, data line X1 or data line X5) in each data line group from image signal line Vi1, and data voltage Vd3 is the image signal. The fourth data line (for example, the data line X4 or the data line X8) from the line Vi4 to each data line group and the data voltage Vd4 are transmitted from the image signal line Vi3 to the third data line (for example, the data line X3 or the like). Is supplied to each of the data lines X7).

  Therefore, according to the switching means 41H shown in FIG. 9, different output circuits 41f1 and 41f2 or 41f3 and 41f4 are different in each of the output circuits 41f1 to 41f4 belonging to the output circuit groups 41F1 and 41F2 periodically every 1H. Thus, the corresponding data lines X1 and X2 or X3 and X4 in each data line group are interchanged, and the outputs of the output circuits 41f1 and 41f2, or 41f3 and 41f4 (data voltages Vd1 and Vd2, or Vd3 and Vd4). Can be distributed to the corresponding data lines X1 and X2 or X3 and X4 in each data line group.

  Therefore, also in the second embodiment as described above, similarly to the first embodiment, it is possible to reduce display unevenness due to data voltage variation in the electro-optical device.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described. FIG. 12 is a plan view showing a configuration example of the projector. Hereinafter, a projector using the liquid crystal device as a light valve will be described.

  As shown in FIG. 12, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  In addition to the electronic device described with reference to FIG. 12, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal devices described in the above embodiments, the present invention can be applied to a reflective liquid crystal device (LCOS) or the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. The driving method, the driving circuit for the electro-optical device, and the electronic apparatus are also included in the technical scope of the present invention.

It is a schematic plan view of an electro-optical panel. It is the H-H 'sectional view taken on the line of FIG. 1 is a perspective view schematically showing an overall configuration of an electro-optical device. FIG. 3 is a circuit diagram illustrating a specific configuration of the electro-optical device according to the first embodiment. It is a circuit diagram which shows the structure of a pixel part. It is a block diagram which shows the structure of driver IC. It is a timing chart for demonstrating operation | movement of the switching means which concerns on 1st Embodiment. 3 is a timing chart of time division driving in the data line driving circuit according to the first embodiment. It is a figure which shows schematically the structure of the external circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the specific structure of the electro-optical panel which concerns on 2nd Embodiment. It is a timing chart for demonstrating operation | movement of the switching means which concerns on 2nd Embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which a liquid crystal device is applied.

Explanation of symbols

  X ... data line, 2 ... pixel unit, 10 ... TFT array substrate, 10a ... image display area, 41H ... switching means, 41f ... output circuit, 41F ... output circuit group

Claims (9)

A substrate,
A plurality of pixel portions arranged along a first direction and a second direction intersecting the first direction on the substrate;
A plurality of data lines provided along the first direction on the substrate;
A plurality of output circuits for outputting data voltages to the plurality of pixel portions via the plurality of data lines;
The output circuit group so that the data lines corresponding to each other in each of the output circuits belonging to the output circuit group are switched for each output circuit group including two or more output circuits as a group among the plurality of output circuits. An electro-optical device comprising: switching means for periodically switching the electrical connection of each of the output circuits belonging to each of the data lines corresponding to the output circuit group.   The electro-optical device according to claim 1, wherein the switching unit switches the electrical connection every horizontal period.   The electro-optical device according to claim 1, wherein the switching unit switches the electrical connection every frame period. The switching means is provided for each of the output circuits by the number of output circuits belonging to the output circuit group, and each of the switching means is electrically connected to different output circuits in the output circuit group and electrically connected to the same data line. A group of changeover switches including a group of changeover switches connected to each other,
A plurality of changeover signals for selecting any changeover switch in the changeover switch group are input to the changeover switch group, and the output circuits different from each other by the changeover switch alternately according to the different changeover signals. Electrically connected to the wire,
4. In each of the changeover switch groups corresponding to the output circuit group, the different output circuits are selected by the changeover switch based on the same changeover signal. The electro-optical device according to Item. Through the output circuit, a time-series voltage for driving each data line group including two or more data lines among the plurality of data lines as a group is supplied as the data voltage. Time-division that time-divides a time-series data voltage and distributes the data voltage that defines the gradation of the pixel portion obtained by the time-division to any of the data lines that form the data line group With a circuit,
The time division circuit is supplied with the data voltage periodically and alternately from the different output circuits of the output circuit group via the switching means, and the time division circuit corresponds to the output circuit group. 5. The electro-optical device according to claim 1, wherein each of the circuits is electrically connected to the different output circuits via the switching unit. The data belonging to the data line group is sequentially driven for each data line group including two or more data lines among the plurality of data lines as the data voltage via each of the plurality of output circuits. A plurality of image signal lines to which a plurality of data voltages corresponding to each of the lines are respectively supplied as time-series voltages;
Each of the plurality of time-series data voltages supplied to the plurality of image signal lines is time-divided, and each gradation of the pixel portion corresponding to the data line group obtained by the time-division is obtained. A sampling circuit for simultaneously supplying a plurality of data voltages to be defined to the data lines belonging to the data line group;
Each of the plurality of image signal lines is supplied with the data voltage periodically and alternately from the different output circuits of the output circuit group via the switching means, and the image corresponding to the output circuit group. 5. The electro-optical device according to claim 1, wherein each of the signal lines is electrically connected to the different output circuits via the switching unit.   An electronic apparatus comprising the electro-optical device according to claim 1. A substrate, a plurality of pixel portions arranged along a first direction on the substrate and a second direction intersecting the first direction, and a plurality of data lines provided along the first direction on the substrate And a driving method of an electro-optical device comprising a plurality of output circuits that output data voltages to the plurality of pixel portions via the plurality of data lines,
The output circuit group is configured such that, for each output circuit group including two or more output circuits among the plurality of output circuits, the data lines corresponding to each other in each of the output circuits belonging to the output circuit group are switched. A method for driving an electro-optical device, comprising: periodically switching electrical connection of each of the output circuits belonging to 1 to each of the data lines corresponding to the output circuit group. A substrate, a plurality of pixel portions arranged along a first direction on the substrate and a second direction intersecting the first direction, and a plurality of data lines provided along the first direction on the substrate A driving circuit for driving an electro-optical device comprising:
A plurality of output circuits for outputting data voltages to the plurality of pixel portions via the plurality of data lines;
The output circuit group so that the data lines corresponding to each other in each of the output circuits belonging to the output circuit group are switched for each output circuit group including two or more output circuits as a group among the plurality of output circuits. And a switching means for periodically switching the electrical connection of the output circuit belonging to each of the data lines corresponding to the output circuit group.

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