JP2009189708A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine contrived so as not to turn off a player immoderately. <P>SOLUTION: A performance control part 51 for executing a performance operation on the basis of a control command CMD received from a main control part 50 is constituted to have main processing to be started when a CPU is reset and power interruption processing to be activated on the basis of abnormality signals received prior to the interruption of a power supply voltage, for preserving the data of a work area specifying a performance operation in progress. In the power interruption processing, when the processing is completed, prescribed end data are added and preserved. In the main processing, when the prescribed end data are not detected, regular processing is started without clearing the work area. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic game machine such as a ball game machine or a revolving game machine with a built-in computer device, and particularly suitably applied to a revolving game machine in which a game is started every time on the condition that a game medium is inserted. Is done.

  In a spinning machine such as a slot machine, when a player inserts a medal into the medal slot and operates a start lever, the rotation of the three rotating reels is started accordingly. When the player presses the stop button to stop the rotating reel, when the symbols are aligned on the stop line, a payout medal corresponding to the symbol is paid out.

  In such a slot machine, the highest game value is the big bonus (BB) symbol, and the regular bonus (RB) symbol is equivalent to this. If this BB symbol or RB symbol can be aligned on the stop line, then a bonus game is started and a game state with a high winning probability is continuously maintained, so that there are much more dividend medals than before. Numbers can be expected.

  In such a slot machine, in order to prevent the player from getting bored even in a normal game other than the bonus game, a video effect and a lamp effect are executed in accordance with the sound effect on the liquid crystal display and the LED lamp. The production operation is usually realized by a dedicated processor corresponding to the production type, but these dedicated processors are not controlled by a single CPU, but a plurality of CPUs distributed on a plurality of circuit boards cooperate. By doing so, it is possible to smoothly realize a complex and advanced production.

  However, the power consumption of each gaming machine increases as the performance contents of the gaming machine become more sophisticated, and there are many gaming machines arranged in the gaming hall. When the countermeasures are insufficient, the CPU realizing the rendering operation may be in a runaway state. When the CPU is in a runaway state, the CPU is reset based on a watchdog timer function or the like, and thus the game operation that has been excited is initialized, and the player may be whitened.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a gaming machine that is devised so as not to make the player unnecessarily white.

  In order to achieve the above object, the present invention has a first storage unit that maintains stored contents even after the power supply voltage is shut off, and a main control unit that controls the game operation in an integrated manner, and also after the power supply voltage is shut off. An effect control unit that has a second storage unit that maintains stored contents and that performs an effect operation based on a control command received from the main control unit, The control unit is activated based on a main process that is started when the CPU is reset and an abnormal signal received before the power supply voltage is cut off, and the work area data that specifies the ongoing production operation is Power interruption interrupt processing to be stored in the second storage unit, and in the power interruption interrupt processing, upon completion of the processing, a predetermined end data is added to the second storage unit and stored, In the main process, start a steady process. If the predetermined end data is detected, the stored data of the second storage unit is stored in the work area. On the other hand, if the predetermined end data is not detected, the work area is cleared. The steady process is started without doing this.

  The main processing of the present invention is started when the power is reset or when the CPU is reset by the watchdog timer. In the main process, when the predetermined end data is detected from the second storage unit, the stored data of the second storage unit is stored in the work area and the steady process is started. Is not initialized, for example, even after the CPU has runaway, the player will not be whitened.

  Also, in the main process, even if the predetermined end data is not detected from the second storage unit, the routine process is started without clearing the work area, so that a slight irrationality may occur. Even if there is, it will not let the player be whitened fatally.

  The present invention further includes a second effect control unit that executes an effect operation based on an effect command output by the effect control unit, and the effect control unit and the second effect control unit are synchronized with each other. It is preferable that an effect display operation, an audio effect, and a lamp effect are executed. In this case, the second effect control unit may be a control unit that executes an audio effect and / or a lamp effect, but preferably, an image control unit in charge of the effect display operation should be provided.

  This is because the player usually progresses the game by paying attention to the effect display operation in the image control unit, so even if some irrational voice production or lamp production occurs, the effect display in the image control unit This is because it is not as noticeable as the irrational behavior. In the case of a noisy game hall or a game hall in which the same kind of gaming machines are densely packed, there is no concern about the unreasonableness of sound production and lamp production.

  In the power interruption interrupt process, prior to storing the end data, general data calculated based on the data stored in the second storage unit is stored in the second storage unit. In the main process, the predetermined end data is stored. Is detected, the summary data is calculated by the same processing as in the power interruption interrupt processing before starting the routine processing, and the calculated value matches the summary data stored in the second storage unit. Even if not, the process is shifted to a steady process without clearing the work area. This is because, as long as predetermined end data is detected from the second storage unit, it is understood that even if a slight irrationality occurs, it is more preferable than letting the player be fatally whitened.

  The effect control unit further includes a reception interrupt process with the highest priority that is activated when the control command CPU is transmitted from the main control unit. It is preferable to set a high priority following the processing. In this case, since the control command is not missed even when the power is interrupted, the rendering operation can be resumed normally based on the data stored in the second storage unit even during a power failure.

  The power interruption interrupt process of the production control unit is configured as a maskable interrupt process, while the main control unit is configured to activate a non-maskable power interruption interrupt process based on an abnormal signal. Is preferred. In this case, since the power-off process of the main control unit precedes the power-off process of the effect control unit, the control command is not transmitted when the power-off process of the effect control unit is started.

  According to the present invention described above, in any case, the production operation does not suddenly return to the initial state, so that the player is not unnecessarily turned white.

  Hereinafter, embodiments of the present invention will be described in detail. 1 to 4 illustrate a slot machine SL according to the embodiment. In this slot machine SL, a rectangular box-shaped main body case 1 and a front panel 2 fitted with various game members are connected via a hinge 3 so that the front panel 2 can be opened and closed with respect to the main body case 1. (FIG. 2). 1 is a front view of the front panel 2, FIG. 2 is a right side view (a) and a plan view (b) of the slot machine SL, FIG. 3 is a rear view of the front panel 2, and FIG. A front view is shown.

  As shown in FIG. 4, a symbol rotating unit 4 including three rotating reels 4 a to 4 c is disposed in the approximate center of the main body case 1, and a medal payout device 5 is disposed below the symbol rotating unit 4. On each of the rotating reels 4a to 4c, a BB symbol, an RB symbol, various fruit symbols, a replay symbol, and the like are drawn. The medal payout device 5 is provided with a medal hopper 5a for storing medals, a payout motor M, a medal payout control board 55, a payout relay board 63, a payout sensor (not shown), and the like. Here, the medal is derived from the payout opening 5b toward the front of the drawing based on the rotation of the payout motor M. Note that medals stored exceeding the limit amount are configured to fall into the auxiliary tank 6 through the overflow portion 5c.

  A power supply board 62 is arranged adjacent to the medal payout device 5, a main control board 50 is arranged above the symbol rotation unit 4, and a rotating drum setting board 54 is arranged adjacent to the main control board 50. ing. In addition, inside the symbol rotating unit 4, a rotating LED relay substrate 58 and a rotating relay substrate 57 are provided, and an external concentrated terminal plate 56 is disposed adjacent to the symbol rotating unit 4.

  As shown in FIG. 1, a liquid crystal display unit 7 is disposed on the upper portion of the front panel 2, and display windows 8a to 8c corresponding to the respective rotating reels 4a to 4c are disposed on the lower portion thereof. Through the display windows 8a to 8c, about 3 symbols can be seen in the rotational direction of each of the rotating reels 4a to 4c, and a total of 9 symbols in the horizontal direction and 2 in the diagonal direction. Becomes a virtual stop line. On the left side of the display window 8a, an LED group 9 indicating a gaming state is provided. Below that, a payout display unit 10 for displaying the number of medals to be paid out as a gaming result, and the number of medals in a credit state are displayed. The storage number display part 11 to display is provided.

  In the center of the front panel 2 in the vertical direction, a medal insertion slot 12 for inserting medals is provided, and adjacent thereto, a return button 13 for returning medals filled in the medal insertion slot 12 is provided. Also, a credit check button 14 for paying out a credit medal, an insertion button 15 for artificially inserting one credit medal in place of inserting a medal into the medal slot 12, and a credit medal in a pseudo manner A maximum loading button 16 for loading three sheets is provided.

  Below these gaming members, a start lever 17 for starting the rotation of the rotating reels 4a to 4c, stop buttons 18a to 18c for stopping the rotating reels 4a to 4c, and the liquid crystal display unit 7 An inquiry switch 19 is provided which is operated when displaying the history. The inquiry switch 19 includes an up contact with an upward arrow, a down contact with a downward arrow, and a determination contact provided therebetween. These inquiry switches 19 can be operated only when a medal is inserted into the medal insertion slot 12 after each game is completed, or until the next game is started after the insertion buttons 15 and 16 are turned ON. It has become.

  In addition, below the front panel 2, a horizontally long tray 20 that stores medals and a medal outlet 21 that communicates with the payout port 5 b of the payout device 5 are provided. Speakers SP are arranged on the left and right sides of the medal outlet 21. The speaker SP is also arranged at the upper part of the gaming machine, but does not appear in FIG.

  As shown in FIG. 3, on the back side of the front panel 2, a medal sorting device 22 that sorts medals inserted into the medal insertion port 12, and a medal that has been determined to be inappropriate by the medal sorting device 22 A return passage 23 that guides the vehicle 21 is provided. A substrate case 24 that houses the effect control board 51, the effect interface board 52, the liquid crystal control board 61, and the like is disposed on the upper back side of the front panel 2. A game relay board 53 that relays signals between the various game members shown in FIG. 1 and the main control board 50 is provided on the medal sorting device 22.

  FIG. 5 is a block diagram illustrating a circuit configuration of the slot machine SL according to the embodiment. As shown in the figure, the slot machine SL is unified based on a main control board 50 that comprehensively controls operations of various game members including the rotating reels 4a to 4c, and a control command CMD received from the main control board 50. Control command from the effect control unit 51 via the effect interface board 52, the effect interface board 52 located between the main control board 50 and the effect control board 51 A liquid crystal control board 61 that receives the CMD ′ and drives the liquid crystal display unit 7 and a power supply board 62 that converts the AC input voltage (24V) into a DC voltage (5V, 12V, 24V) and supplies the converted voltage to each unit. It is configured.

  A computer circuit having a one-chip microcomputer is mounted on the main control board 50, the effect control board 51, and the liquid crystal control board 61. Accordingly, the hardware configuration and software functions of the computer circuit may be collectively referred to as a main control unit 50, an effect control unit 51, and a liquid crystal control unit 61 in the following description. The production interface board 52 and the production control unit 51 are integrated by being closely coupled by a connector.

  The power supply board 62 monitors the voltage level 24V of the AC input voltage. If a voltage abnormality is detected, the abnormality signal ABN is sent to the non-maskable NMI (non maskable interrupt) terminal of the main control unit 50. The effect control unit 51 is configured to supply to a maskable interrupt (INT) terminal. Then, each control unit 50 that receives the abnormal signal ABN starts a power interruption interrupt process, and executes a backup process for storing necessary data in the RAM. Corresponding to this backup processing, the power supply board 62 supplies DC5V stored in the large-capacity capacitor to the main control unit 50 as the backup power supply BU. Therefore, the storage content of the RAM saved by the backup process of the main control unit 50 is maintained as it is for several days.

  On the other hand, the DC 5V backup power generated by the power supply board 62 is not supplied to the effect control unit 51, and another backup power BU generated by the effect interface board 52 is supplied. The one-chip microcomputer that can be used in the main control unit 50 is legally restricted to adopt such a complicated configuration. For example, it is preferable to use a built-in RAM that functions by DC5V. This is because the production control unit 51 without such legal restrictions sets the voltage value of the backup power supply BU low and increases the storage capacity of the RAM in order to realize a more appropriate backup operation. Specifically, the production control unit 51 stores necessary data in a RAM of about 32 Kbytes functioning at 3.3V. The contents stored in the RAM are maintained as they are for several days or more by a large-capacitance capacitor provided on the effect interface board 52 regardless of the storage volume.

  Incidentally, the main control unit 50 shown in FIG. 5 transmits a control command CMD to the effect control unit 51 via the effect interface board 52. On the other hand, the effect control unit 51 executes an effect lottery based on the received control command CMD to produce an audio effect by the speaker SP, a lamp effect by an LED lamp or a cold cathode ray tube discharge tube, and an image effect by the liquid crystal display unit 7. The contents of the production have been decided.

  Here, the sound effect, the lamp effect, and the video effect are executed in synchronization with each other, but the sound effect and the lamp effect are executed in the effect control unit 51 in order to smoothly execute the complicated and advanced effect operation. On the other hand, the video effect is executed by the liquid crystal control unit 61. Then, the effect command CMD ′ for specifying the effect content is transmitted from the effect control unit 51 to the liquid crystal control unit 61. The control command CMD 'transmitted from the effect control unit 51 to the liquid crystal control board 61 includes an error notification command for transferring the control command CMD received from the main control board 50 by the effect control unit 51 as it is.

  On the other hand, the liquid crystal control unit 61 executes a video effect process in the liquid crystal display unit 7 based on the effect command CMD ′ received from the effect control unit 51. When an error notification command is transferred from the effect control unit 51, a corresponding notification process is executed.

  In this embodiment, the effect command CMD ′ transmitted from the effect control unit 51 to the liquid crystal control unit 61 is (a) the effect command of the group A to be started by interrupting the effect operation being executed in the liquid crystal control unit 61. And (b) a group B production command for chain reproduction, which should be executed after the production operation being executed is completed.

  All the production commands are composed of 2 bytes, but each byte is transmitted by parallel communication. The effect command is configured such that the most significant bit (bit 7) of the first byte (upper byte) is “1” and the most significant bit of the second byte (lower byte) is “0”. Further, it is specified by the high-order byte bit 6 (chain bit) whether the command is for group A or group B. In this embodiment, when bit 6 = 1, group B that is chain-reproduced If bit6 = 0, this indicates that the command is for group A that is not chain-reproduced.

  The production commands for group A are, for example, production commands that start in response to medal insertion operations, production commands that specify production that starts in response to start lever operations, etc. It is included in the production command of group A. On the other hand, the group B effect command is an effect command for executing and completing a series of video effects without difficulty.

  In order to specifically explain the significance of the group B effect command, the medal is started from the second stop switch operation among the three stop switch operations, and after the third stop switch operation, Assume a series of effects that continue until the payout. In such a series of effects, as shown in FIG. 11, an effect command at the time of the second switch operation, an effect command at the time of the third stop switch operation, and an effect command at the time of medal payout command, It is transmitted from the effect control unit 51 to the liquid crystal control unit 61. Then, by setting the effect command at the time of the third final stop switch operation and the effect command at the time of medal payout command to the control command for chain reproduction of the B group, the operation timing of the final stop switch by the player is set. Whether it is early or late, a series of video productions will be completed without interruption without interruption.

  Subsequently, the remaining part will be described with reference to FIG. The main control unit 50 is connected to various game members of the slot machine through the game relay board 53. Specifically, the start switch of the start lever 17, the stop switch of the stop buttons 18a to 18c, the input switch of the input buttons 15 and 16, the liquidation switch of the checkout button 14, and the photointerrupters PH1 and PH2 constituting the input number determination unit 21d The blocker solenoid 31 constituting the inserted medal return unit 21c and the various LED elements 9 to 11 are connected.

  Further, the main control unit 50 is connected to the three stepping motors for rotating the rotating reels 4a to 4c and the index sensor for detecting the reference position of the rotating reels 4a to 4c via the rotating relay board 57. Has been. Then, by rotating or stopping the stepping motor, the rotating operation of the rotating reels 4a to 4c and the stopping operation at the target position are realized.

  The main controller 50 is also connected to the medal payout device 5 through the payout relay board 63. The medal payout device 5 is provided with a medal payout control board 55, a medal payout sensor, and a payout motor M. The medal payout control board 55 is based on a control command from the main control unit 50. Is rotated to pay out a predetermined amount of medals.

  In addition, the main control unit 50 is also connected to the external concentration terminal board 56 and the rotary setting board 54. The external concentrated terminal board 56 is connected to the hall computer HC, for example, and the main control unit 50 outputs the number of inserted medals, the number of paid out medals, etc. through the external concentrated terminal board 56. Further, the rotating setting board 54 outputs a setting key signal indicating the rank setting value of the probabilistic medal payout number set by the staff.

  FIG. 6 illustrates the mutual connection relationship of the effect control board 51, the effect interface board 52, and the liquid crystal control board 61 together with the internal circuit.

  As shown in FIG. 6, the production control board 51 receives a series of audio signals based on a control command CMD received from the main control unit 50 and a ROM 66 that stores a control program executed by the one-chip microcomputer 65. The sound reproduction IC 67 output in accordance with the control of the one-chip microcomputer 65, the sound ROM 68 for storing the sound information to be output by the sound reproduction IC 67 in a compressed state, and the 3.3V generated by the effect interface board 52 And an external RAM 69 that retains stored contents even after the power supply is cut off.

  Here, the one-chip microcomputer 65 of the production control unit 51 includes a CPU, a ROM and RAM memory circuit STG, a watchdog timer circuit WDT, a parallel input port INP1, a parallel output port OUT, an input terminal RXD, and an output. And a serial communication circuit having a terminal RTS.

  The one-chip microcomputer 65 is provided with two interrupt terminals INT1 and INT2 for receiving maskable interrupt signals. The strobe signal STB is supplied to the interrupt terminal INT1, and the abnormality signal ABN output from the power supply board 62 is supplied to the interrupt terminal INT2.

  As shown in FIG. 6, the one-chip microcomputer 65 receives the control command CMD and the strobe signal STB output from the main control unit 50 via the effect interface board 52 at the input port INP1. As described above, the strobe signal STB is also supplied to the interrupt terminal INT1 of the one-chip microcomputer 65, and the control command CMD is acquired by the interrupt processing program according to the level change of the strobe signal STB.

  The one-chip microcomputer 65 outputs a control command CMD ′ and a strobe signal STB ′ from the output port OUT toward the effect interface board 52. Furthermore, the one-chip microcomputer 65 receives serial data SD at the serial input terminal RXD and outputs a control signal RTS (request to send) from the serial output terminal RTS.

  On the other hand, the effect interface board 52 has an RC filter 70A for smoothing the control command CMD and strobe signal STB output from the main control unit 50, and a bus buffer 70B for transferring the output of the RC filter 70A to the effect control unit 51. The bus buffer 71 that transfers the control command CMD ′ and the strobe signal STB ′ output from the effect control unit 51 to the liquid crystal control unit 61 and the serial data SD output from the liquid crystal control unit 61 are waveform-shaped to control the effect. A Schmitt trigger 72A that is transferred to the unit 51, a Schmitt trigger 72B that shapes the control signal RTS output from the effect control unit 51 and transfers it to the liquid crystal control unit 61, and a two-channel stereo output from the audio reproduction IC 67. Class D amplifiers 73A and 73B for class D amplifying the audio signals AOL and AOR It has been mounting.

  The liquid crystal control board 61 includes a one-chip microcomputer 74, an RC filter 75A for smoothing the control command CMD ′ and the strobe signal STB ′ transferred from the effect interface board 52, and the output of the RC filter 75A. The bus buffer 75B for transferring to the LCD, the driving IC 76 for the liquid crystal display unit 7, and the ROM 77 are mounted.

  Here, the one-chip microcomputer 74 of the liquid crystal controller 61 includes a CPU, a memory circuit STG of ROM and RAM, a watchdog timer circuit WDT, a parallel input port INP2, a serial having an output terminal TXD and an input terminal CTS. The communication circuit is built in. The one-chip microcomputer 74 receives the control command CMD ′ at the input port INP2, and the control command CMD ′ is acquired by the interrupt processing program according to the level change of the strobe signal STB ′ supplied to the interrupt terminal INT3. It has become. Then, the one-chip microcomputer 74 displays a screen corresponding to the acquired control command CMD ′ on the liquid crystal display unit 7 by controlling the LCD driving IC 76.

  The serial communication circuit of the one-chip microcomputer 74 (liquid crystal control unit 61) is configured to correspond to the serial communication circuit of the one-chip microcomputer 65 (production control unit 51), and realizes asynchronous serial communication (UART mode). is doing. Specifically, 9600 bps serial communication is realized using a total of 10 bits of 1 bit of start bit + serial data SD of 8 bit length + 1 bit of stop bit as a communication unit.

  In addition, the serial communication circuits of the liquid crystal control unit 61 and the effect control unit 51 are set so that handshake processing flow control by RTS (Request to Send) and CTS (Clear to Send) is performed. The liquid crystal controller 61 is configured such that a transmission completion interrupt process is started each time the serial communication circuit finishes transmitting 8-bit serial data SD. In the case of this embodiment, the serial data SD is specifically an effect command CMD 'having a length of 2 bytes received from the effect control unit 51, and this is returned in two portions every 8 bits.

  On the other hand, the effect control unit 51 is configured such that the reception interrupt process is activated every time the serial communication circuit receives the 1-byte length of the serial data SD (= effect command CMD ′). The control signal RTS is set to return to the active level every time the one-byte microcomputer 65 acquires 1-byte serial data SD.

  As described above, the slot machine of FIG. 1 has been described with a focus on the circuit configuration. Next, the control operation realized by the main control unit 50 will be briefly described. The control program of the main control unit 50 includes an infinite loop main process (FIG. 7) that is started when the power is turned on, a timer interrupt process (not shown) that is started by a scheduled interrupt of the built-in counter of the one-chip microcomputer, It has a power interruption interrupt process (not shown) which is an NMI (non maskable interrupt) process activated by an abnormal signal ABN received from the power supply board 62 at the time of interruption.

  As shown in FIG. 7, when the power is turned on, the work area of the RAM is cleared (SS2) after the initial processing (SS1). Further, the CPU that is set to the interrupt disabled state in the initial process (SS1) is set to the interrupt enabled state (SS2).

  When the process of step SS2 is completed, the medal insertion process for the medal actually inserted from the medal insertion slot 12 and the medal that is artificially inserted by pressing the insertion buttons 15 and 16 is performed (SS3). . Next, for example, a random number extraction process (SS4) is executed in accordance with the pressing timing of the start lever 17. In the random number extraction process, the value of the random number counter that is a software counter is acquired in the variable RND. Note that the value of the random number counter is periodically updated in a timer interrupt process (not shown).

  Thereafter, a symbol lottery process is executed based on the random number value RND extracted in the random number extraction process (SS4) (SS5). The winning combination determined by the symbol lottery process includes per BB (big bonus), RB (regular bonus), and other small combinations. Per small role includes per fruit symbol (small role 1 to small role 3) from which about 2 to 15 payout medals are paid out and per replay game (small role 4) where a re-game is possible.

  In this embodiment, per RB (regular bonus) means a winning combination in which a high-value game called a jack game or the like can be executed within a predetermined number of times within a range of a maximum of 133 payouts. The jack game is, for example, a game in which about 15 medals are paid out when one medal is inserted. On the other hand, per BB (big bonus) is a winning combination in which the state per RB is repeatedly realized. For example, this big bonus game is continued until 346 medals are paid out.

  However, even if such a high-value bonus game (RB / BB) is in a winning state in the lottery process inside the device (referred to as a bonus internal winning state), the corresponding symbols on the rotating reels 4a to 4c are set to a predetermined state. Execution will not start unless it is aligned with the stop line. Moreover, since it is not easy to immediately align the corresponding symbol with the predetermined stop line in a game that has been in the bonus internal winning state, the bonus internal winning state is continuously maintained until it is activated. It has become.

  When the symbol lottery process (SS5) as described above is completed, the preparatory work for rotating the rotating reels 4a to 4c is performed, and the rotating reels 4a to 4c can be rotated by a timer interruption (SS6), and then the stop button. When 18a to 18c are pressed, a rotating cylinder stop process for stopping the corresponding rotating reels 4a to 4c is performed (SS7).

  Here, stop control is executed so as to follow the result of the symbol lottery process (SS5). That is, as a result of the symbol lottery process (SS5), if there is any internal winning state, the symbols of the rotating reels 4a to 4c are aligned so as to match the winning result on condition that the player performs an appropriate stop operation. However, if the timing at which the player presses the stop button is inappropriate, the player is stopped with the symbol in the detached state. As a result, the small winning combination at the corner is wasted, but the bonus winning is carried over after the next game.

  When all the rotating reels 4a to 4c are stopped in this way, it is determined whether or not the winning symbols are aligned on the effective stop line (SS8), and the required number of medals are paid out (SS9). Then, it is determined whether or not the replay symbols are aligned (SS10). If the replay symbols are aligned, the re-game operation start process (SS11) is executed, and then the process proceeds to step SS2. If the replay symbols are not aligned, it is determined whether or not the RB symbols are aligned. If the RB symbols are aligned, the regular bonus start process (SS13) is executed, and then the process proceeds to step SS2. Further, it is determined whether or not the present is in the regular bonus game (SS14), and if it is in the regular bonus game, necessary processing (SS15) is executed, and then the process proceeds to step SS2.

  On the other hand, if the determination in step SS14 is NO, it is determined whether or not the BB symbols are aligned (SS16). If the BB symbols are aligned, the big bonus start process (SS17) is executed. The process proceeds to step SS2. Further, it is determined whether or not the big bonus game is currently being played (SS18). If NO, nothing is done and the process proceeds to step SS2. On the other hand, if it is during the big bonus game, after executing the processing necessary for the big bonus game (SS19), it is determined whether or not the end condition of the big bonus game is satisfied (SS20). If the determination result is NO, nothing is done and the process proceeds to step SS2. If the determination result is YES, the work area including the RAM area used during the BB game is cleared and the process proceeds to step SS3. Transition.

  By the way, at an appropriate timing of the series of game control operations described above, the main control unit 50 outputs a control command CMD in a timer interrupt process (not shown). As described above, the control command CMD is transmitted to the effect control unit 51 via the effect interface board 52 together with the strobe signal STB. The control command CMD is all configured with a 2-byte length, and is transmitted twice for each byte. The most significant bit of the first byte (upper byte) of the control command CMD is set to “1”, and the most significant bit of the second byte (lower byte) is set to “0”. This is the same as the production command.

  The transmission timing of the control command CMD is not particularly limited, but, for example, during a normal game that is not a bonus game, for example, (1) when a medal is inserted, (2) when the start lever is pressed, and (3) when rotation of the rotating reel starts , (4) at the first stop by the stop button operation, (5) at the second stop by the subsequent stop button operation, (6) at the final stop ON by the last stop button operation, (7) at the end of the stop operation This includes when the stop is OFF, (8) when a medal is paid out, and (9) when the demo state is entered. It should be noted that if a medal is not accepted for a predetermined time (for example, 5 minutes) or longer, a demo state is entered.

  By the control command CMD transmitted at each timing described above, for example, (1) medal insertion information, (2) winning / failing state and winning symbol (winning role), (3) rotation start timing information, ( The effect control unit 51 is notified of 4) to (6) stop position information, (7) stop timing information, (8) winning information such as the number of payouts, and (9) demo start timing information (FIG. 6). (See (b)). Then, in the production control unit 51, for example, based on the control command CMD transmitted when the start lever is pressed, the success / failure result and the winning symbol of this game are grasped, and the production is performed so that various production operations corresponding to these are executed. A lottery will be executed (ST81 in FIG. 9).

  Next, the operation content of the effect control unit 51 will be described with reference to FIGS. The operation of the effect control unit 51 includes a main process (FIG. 8 (a)) that is executed when the CPU is reset, such as after power-on, and a power interruption interrupt process (based on an abnormal signal ABN at the time of power interruption) 8 (c)), timer interrupt processing activated every 2 mS (FIG. 9 (a)), and reception interrupt processing of the control command CMD activated due to the strobe signal STB (FIG. 9 (b)). And a reception interrupt process (FIG. 9 (c)) for an effect command CMD ′ that is activated when the 8-bit serial data SD is received from the liquid crystal controller 61, and a timer interrupt process (not illustrated) that is activated every 16 ms. It has been realized. In the 16 mS timer interrupt, the lamp effect progress process is executed.

  In this embodiment, non-maskable NMI interrupts are not used, and all interrupt processes can be masked. The priority level is (1) [control command CMD reception interrupt (FIG. 9B)] → ( 2) [Power interruption interrupt (FIG. 8 (c))] → (3) [Reception interrupt of production command SD (FIG. 9 (c))] → (4) [2mS timer interrupt (FIG. 9 (a))] → (5) The order is [16 mS timer interrupt (not shown)]. In this embodiment, when a multiple interrupt request is generated, in principle, only an interrupt request having a higher priority level than the interrupt being executed is permitted. If a plurality of interrupt requests exist at the same timing, naturally, an interrupt request with a high priority level is accepted.

  As described above, in the present embodiment, the reception process of the control command CMD is prioritized over the interruption interruption of power when the power is cut off, so that the acquisition process of the control command CMD acquired in units of 1 byte is interrupted in the middle. And the reading of the control command CMD is prevented.

  By the way, in the present embodiment, with respect to the 2 mS timer interrupt (FIG. 9A), the interrupt request is configured to be accepted in an exceptional manner. Therefore, when the allocated time (2 mS) is used up during the process of FIG. 9A, the timer interrupt process being executed is interrupted and the same 2 mS timer interrupt process is executed again from the beginning. In this embodiment, since such a configuration is adopted, for example, (1) when the main control unit 50 needs to transmit a large number of control commands to the effect control unit 51 in a short time, or ( 2) Even when the effect control unit 51 executes a complicated response process related to the received control command, no trouble occurs. However, in this embodiment, a unique configuration corresponding to the above-described overlapping interrupt is adopted.

  Based on the above, the power interruption interrupt process shown in FIG. When receiving the abnormality signal ABN from the power supply board 62, the CPU of the effect control unit 51 disables all interruptions (ST10). As described above, the power interruption interrupt is started only when the control command CMD is not being received, but once the power interruption interrupt is started, the reception of the control command CMD must be started. The process of step ST10 is provided so that there is no. The power interruption interrupt process is also started by the main control unit 50 based on the same abnormality signal ABN. However, the main control 50 uses the highest priority interrupt process that cannot be masked, and the electric power interruption process is performed before the effect control unit 51. The disconnection process is started. Therefore, the control command CMD is not transmitted from the main control unit 50 to the effect control unit 51 after the start of the power interruption process of FIG.

  When the process of step ST10 is completed, the effect data existing in the work area of the built-in memory of the one-chip microcomputer 65 is transferred to the external memory 69 (ST11). During this transfer, a 16-bit addition operation is performed on the transfer data in accordance with the transfer process, and the addition result is stored in the external memory 69 as a checksum value (ST12). Since the backup process is completed by the above process, an appropriate BK (backup) keyword is stored in the external memory 69 and the process is terminated (ST13).

  Thus, in the power interruption process of the effect control unit 51, the value of the general-purpose register of the CPU, the value of the stack pointer, and the stored value of the stack area are not transferred. Disappear. Therefore, in the effect control unit 51, after the power is restored, the process at the time of power-off cannot be resumed accurately, and the game operation is resumed retroactively. On the other hand, in the main control unit 50, the value of the general-purpose register of the CPU and the value of the stack pointer at the time of power interruption are stored in the built-in RAM of the one-chip microcomputer, and the contents stored in the built-in RAM including the stack area Are all retained by the backup power supply BU, so that the power-off process can be accurately resumed after the power is restored.

  In this embodiment, the presentation data is about 100 bytes, but the external RAM 69 has a storage area of 32 Kbytes. The game results are constantly accumulated and stored during the game operation. Although the game results to be stored are not particularly limited, for example, the occurrence of a bonus game is specified from the control command CMD received from the main control unit 50, and this is stored in order. In addition, by adding appropriate time stamp information at the time of the power interruption process, daily game results are separated and stored.

  These game results are read from the external RAM 69 by the CPU of the effect control unit 51 when the inquiry switch 19 is pressed, and transmitted to the liquid crystal control unit 61 together with an appropriate effect command CMD ′. It is displayed on the liquid crystal display unit 7 as a game record. The up contact, the down contact, and the determination contact provided in the inquiry switch 19 are used for selecting a menu screen or the like that appears on the liquid crystal display unit 7.

  Next, the CPU reset process (main process) shown in FIG. This main process is executed when the power is reset by turning on the power. However, the main process is also executed when the CPU is abnormally reset due to the watchdog timer circuit WDT being up due to a program runaway or the like.

  In any case, first, the one-chip microcomputer is initialized (ST1), and the stack area and the system work area of the built-in memory are initialized. As described above, in the effect control unit 51, the contents of the stack area disappears when the power is turned off, and thus are cleared to zero by the process of step ST2.

  Subsequently, it is determined whether or not the backup process is correctly completed (ST3). The specific processing content is as shown in FIG. 8B. First, it is determined whether or not the BK keyword is valid (ST20). The BK keyword to be determined is a value stored in the external RAM 69 in the process of step ST13 of the power interruption process, and is cleared to zero after the state return process (ST7) by the backup data. Therefore, when a valid value is not maintained, it can be assumed that this timing is the time of CPU abnormality reset by the watchdog timer.

  Therefore, in such a case, the random number seed of the random number generation calculation used for the effect lottery is set to an appropriate value (ST25). Therefore, the production data of the built-in memory at this stage is a reset start that is maintained as it is. Note that the random number seed is determined based on the value of a management timer that manages the progress of the lamp effect in, for example, 16 mS timer interruption processing.

  If the determination in step ST20 is YES, the timing is assumed to be when the CPU power is reset when the power is turned on. Next, the value of the effect data storage area of the external RAM 69 is added by 16 bits. The checksum value is calculated (ST21). Then, the 16-bit sum value calculated in step ST21 is compared with the checksum value stored in the external RAM 69 (ST22). Here, when both do not correspond, it is made to transfer to step ST25. This is because it is unreasonable to transfer and use the production data stored in the external RAM 69 to the built-in memory as long as the validity of the production data is questionable.

  On the other hand, if the calculated sum value matches the sum value of the external RAM 69, the effect data in the external RAM is copied to the internal memory (ST23), and the check sum value at this stage is used as a random number generation process. Is set as a random number seed (ST24). Then, a random number generation operation is executed using the set random number seed to set a random number initial value (ST27).

  As described above, in this embodiment, even if the BK keyword does not maintain a normal value or the checksum values do not match, the effect data stored in the built-in memory is used as it is. Become. Accordingly, there is a concern that the subsequent operation cannot be executed normally at the time of an abnormality in which the power supply is shut down without completing the power interruption process or at the time of an abnormality in which the contents of the internal memory are rewritten due to a program runaway.

  However, (1) the processing speed of the CPU of the production control unit 51 is fast, (2) the interruption interruption process is simple, (3) the interruption interruption priority is high, and (4) the AC input voltage. It has been experimentally confirmed that the power supply is practically not shut down without the power interruption process being completed normally because an abnormal signal is generated by detecting a drop in the power.

  On the other hand, the possibility that the contents of the built-in memory are fatally destroyed is extremely low, but it cannot be denied. However, considering this extremely low possibility, it is actually considered irrational to clear the work area to zero and completely return to the initial state (demonstration state after power-on). 8 (b) is adopted.

  The reason will be further described. (1) The effect control unit 51 executes an effect operation synchronized with the liquid crystal control unit 61 based on the control command CMD received from the main control unit 50, but the effect control unit 51 The main control unit 50 and the liquid crystal control unit 61 continue to function normally except in exceptional cases. (2) Therefore, in the unlikely event that a part of the built-in memory is Even if it is destroyed, there is a slight inconsistency in the effects relating to the lamp effect and the sound effect. Therefore, a series of video effects on the liquid crystal display unit 7 are uniformly interrupted to return the effect control to the initial state. This is because it is considered to be irrational.

  When the backup check process (ST3) described above is completed, the communication data queue for transmission is initialized (ST4). As described above, in the production control unit 51, unlike the main control unit 50, the operation is not faithfully resumed from the processing before the interruption even at the normal return from the power-off time. Therefore, even if there is an untransmitted effect command, deleting it will not cause any problem.

  Next, initial setting is performed for the interrupt, and the priority of maskable interrupts is set as described above (ST5). Also, the audio reproduction IC 67 is initialized (ST6). Finally, the rendering operation restarts based on the rendering data in the built-in RAM. However, even when the backup process is perfect, the rendering operation is resumed retroactively to the break point of the rendering operation. The point that the production operation is resumed retroactively to the break point of the production operation is the same in the case of the reset start via the process of step ST25, and in any case, the BK keyword is cleared to zero.

  When the above processing is completed, the CPU waits for an interrupt request while repeating infinite loop processing that does nothing. In this embodiment, an infinite loop process that does not execute anything is adopted, and therefore it is not necessary to save the CPU register in the 16 mS timer interrupt process with the lowest priority level. However, in other interrupt processing, the CPU register is first saved in the stack area, and finally, the saved value is returned to the register. However, these processes are not described in each flowchart for convenience.

  When the main process is in the above-described standby state, (1) [Reception interrupt of control command CMD (FIG. 9B)] → (2) [Power interruption interrupt (FIG. 8C)] → (3) [Reception interrupt of production command SD (FIG. 9 (c))] → (4) [2mS timer interrupt (FIG. 9 (a))] → (5) [16mS timer interrupt (not shown)] Is accepted. In addition, the 2 mS timer interrupt (FIG. 9A) may be activated twice.

  Therefore, next, the interrupt processing of the highest priority level will be described based on the flowchart of FIG. When there is a reception interrupt request, the input port INP1 is accessed to determine whether or not the strobe signal STB is at the interrupt level (ST40). This considers the possibility of erroneously accepting an interrupt request due to the influence of noise or the like. If the strobe signal STB is not at the interrupt level, the processing is terminated without doing anything.

  On the other hand, if the strobe signal STB is at the interrupt level, it is determined whether or not the acquired most significant bit of 1 byte is “1” (ST41). As described above, the control commands CMD are all 2 bytes long, and the most significant bit of the upper byte is set to “1”. Therefore, if it is confirmed that the current received data is the upper byte, it is stored in the corresponding area of the reception queue (the upper byte area of the 16-bit storage area), and the process ends.

  On the other hand, if the most significant bit is “0”, it is determined whether the upper byte of the control command is received at the previous reception interrupt (ST43). If the upper byte is not received, it means that the lower byte has been received continuously, so that it is determined as a malfunction and the process is terminated. Conversely, if the upper byte has been acquired, the lower byte received this time is stored in the corresponding area of the reception queue (lower byte area of the 16-bit storage area) (ST44). Then, the pointer indicating the storage area of the reception queue is advanced, and the process ends (ST45).

  In the reception process of the control command CMD described above, the interrupt level is set to the highest priority. Therefore, unless the power interruption process (FIG. 8C) is started, even if there is another interrupt process being executed, the reception process is executed by interrupting the process, There is virtually no possibility of missing control commands.

  FIG. 9C is a flowchart for explaining the reception interruption of the effect command SD with the priority 3. Since this interrupt request has priority 3, the interrupt request is executed even if other interrupt processes are interrupted except for the control command CMD reception process (FIG. 9B) and the power interruption process (FIG. 8C). Is started.

  As shown in step ST <b> 73 of FIG. 10C, when the liquid crystal control unit 61 starts to execute the group B production command CMD ′ received from the production control unit 51, the production command CMD ′ is serialized. The data SD is returned to the effect control unit 51. The effect command CMD ′ to be returned is 2 bytes long, but every time the serial communication circuit of the effect control unit 51 finishes receiving 1 byte data, an interrupt request is generated. As a result, the processing of FIG. Is started. Note that only the group B production command CMD 'for chain reproduction is returned, and the group A production command CMD' is not returned.

  The processing content for obtaining the effect command CMD ′ shown in FIG. 9C is almost the same as that in the control command CMD reception processing in FIG. 9B, and the received data is based on the most significant bit of 1-byte data. Is the upper byte or lower byte (ST51, ST53), and only the data received in the correct order is stored in the corresponding area of the reception queue (ST52, ST54).

  By the way, the reception interrupt of the effect command CMD 'has the priority of No. 3. If there is a reception interrupt request of the control command CMD, the process of FIG. 9C is postponed. However, each serial communication circuit of the liquid crystal control unit 61 and the effect control unit 51 is set to execute a handshake process by RTS (request to send) and CTS (clear to send), and the CPU of the effect control unit 51 Unless the received data is acquired, the control signal RTS does not return to the active level, so that no communication trouble occurs. That is, in the serial communication circuit of the liquid crystal control unit 61, the control signal RTS is received at the CTS terminal, and unless the control signal RTS returns to the active level, the next transmission process is not performed. There is no possibility that the serial communication circuit will lose the received data received earlier.

  FIG. 9A is a flowchart for explaining timer interrupt processing (priority order 4) activated every 2 mS. In this 2 mS timer interrupt processing, substantially all the effect control processing is realized.

  In the 2 mS timer interrupt process, first, a clear process of the watchdog timer circuit WDT is executed, and a time measuring process including an update process of a management timer for managing sound effects and lamp effects is executed (ST30). In addition, in the timing process of step ST30, the effect command that has reached the timing to be transmitted to the liquid crystal control unit 61 among the series of effect commands CMD ′ stored in the buffer area is transferred from the buffer area to the transmission queue. . As described above, in the present embodiment, the 2 mS timer interrupt process is configured to be activated in duplicate. Therefore, even if an interrupt request of the 2 mS timer is awaited, it is not skipped, so the timing process in step ST30 is executed approximately every 2 mS, and its significance is not lost.

  Next, the random number value is updated based on the random number generation calculation (ST32). As the random number generation calculation, a simple algorithm such as a mixed congruential method or a squaring method is used, but the random number seed is set when the CPU is reset (ST24, ST25).

  Subsequently, it is determined based on the value of the processing flag WK whether or not the control command corresponding processing in step ST34 is currently being performed (ST32). The control command handling process (ST34) is a process for specifically specifying the subsequent operation content based on the control command CMD acquired in the reception interrupt process (FIG. 9B).

  Here, the value of the in-process flag WK is determined in order to appropriately cope with the case where the 2 mS timer interrupt process is started in duplicate. For example, since the time interval from the ON operation of the start lever 17 to the start of rotation of the rotating reels 8a to 8c is very short, a plurality of control commands CMD are continuously transmitted from the main control unit 50 in a short time. The production control unit 51 gives the highest priority to this reception process (FIG. 9B), so the 2mS timer interrupt process (FIG. 9A) is completed before the first response to the received control command. In some cases, the processing time (= 2 mS) is used up. In such a case, the interrupt process being executed is interrupted, and the 2 mS timer interrupt process is executed again from the beginning.

  However, in the present embodiment, when the 2 mS timer interrupt processing is activated twice, the processing content interrupted by the interrupt request is evaluated, and if the control command corresponding processing (ST34) is interrupted, In the 2 mS timer interrupt process, the control command response process (ST34) is skipped. Therefore, the current 2 mS timer interrupt process is completed quickly with the minimum processing time T, and the remaining time (2 mS-T) is used to execute the control command response process (ST34) in the remaining state. Is done.

  On the other hand, if it is determined in step ST32 that there is no unprocessed control command handling process (ST34) at the time of the current 2mS timer interrupt request, whether or not the reception queue of the control command CMD is empty is determined next. Is determined (ST33). If the control command CMD exists in the reception queue, the processing flag WK is set, and processing corresponding to the received control command CMD (that is, control command response processing) is executed (ST34). The processing flag WK is reset when the control command handling process (ST34) is completed.

  As shown in FIG. 6B, there are various types of control commands. For example, at the timing of receiving a control command indicating that the start lever has been pressed (ST80), the process of step ST31 is performed. An effect lottery process is executed based on the updated random number value (ST81). As described above, since the winning / notifying state and the winning combination are specified by the control command when the start lever is pressed, an effect corresponding to the specified winning combination is determined by lottery.

  Through this lottery process (ST81), a series of audio effects, lamp effects, and video effects synchronized with each other are specified. Here, the audio effect and the lamp effect are realized by the control of the effect control unit 51, while the video effect is realized by the control of the liquid crystal control unit 61. Therefore, a plurality of effect commands CMD 'specifying a series of video effects are selected and stored in the buffer area (ST82). However, the effect command to be transmitted immediately is stored in the transmission queue without being stored in the buffer area.

  Here, as the effect command CMD ′ for specifying the image effect, for example, the effect command (A) at the start shown in FIG. 11 is stored in the transmission queue, the effect command (B) at the second stop, and the third It is assumed that the stop effect command (C) and the payout effect command (D) are stored in the buffer area.

  The effect command CMD ′ is a chain reproduction that should be started after the effect display operation being executed is completed and the effect command of the group A that should be started by interrupting the effect display operation being executed on the liquid crystal display unit 7. However, here, only the effect command (C) and the effect command (D) belong to the B group.

  When the above processing is completed, it is then determined whether or not there is an effect command CMD ′ to be transmitted at this timing in the transmission queue (ST35). If there is an effect command CMD ′, it is determined. It is transmitted to the liquid crystal control unit 61 by parallel communication (ST36). In this description, since the present time is when the start lever is pressed, the start production command (A) is transmitted (FIG. 11).

  Subsequently, after determining whether or not the effect command CMD ′ returned by the liquid crystal control unit 61 is stored in the reception queue, if it is received, an audio effect and a lamp effect corresponding to the effect command CMD ′ are displayed. Start (ST37). Then, the sound effect and the lamp effect including the effect being executed are advanced based on the management timer, and the interruption process is finished (ST38, ST39).

  FIGS. 10A and 10C are flowcharts showing, in particular, the portion related to the effect command CMD ′ in the processing contents of the liquid crystal controller 61. Both are subroutines during timer interrupt processing, and are repeatedly executed at predetermined time intervals. First, FIG. 10A shows an acquisition process of the effect command CMD ′ received from the effect control unit 51. Each time the liquid crystal control unit 61 receives the strobe signal STB ′ from the production control unit 51, the reception interrupt process is activated to receive the production command CMD ′, and this is sequentially stored in the reception queue (FIG. 10B). ing. Note that the reception queue employs a FIFO (First In First Out), as with other transmission queues and chain reproduction queues.

  FIG. 10C shows a video reproduction process executed based on the effect command. FIG. 10D shows a chain reproduction queue in which only the group B effect commands to be chain-reproduced among the received effect commands CMD 'are stored. As described above, the execution command of the group A is started immediately after receiving from the effect control unit 51 (normal playback), but the effect command of the group B is chained after the video effect being executed is completed. Then, execution starts (chain playback).

  Based on the above, description will be made from the flowchart of FIG. In the effect command acquisition process, first, it is determined whether or not the reception queue (FIG. 10B) is empty (ST60). If it is not empty, the chain bit of the oldest received data is determined (ST61). As described above, the chain bit is bit 6 of the upper byte of the production command having a length of 2 bytes, and bit 6 = 1 in the case of the command of the B group.

  Therefore, when the effect command of group A whose chain bit is OFF (bit 6 = 0) is stored in the reception queue, a playback reservation area (not shown) is used to start the effect on the oldest effect command. The effect command is transferred to, and the chain reproduction queue shown in FIG. 10D is initialized by zero clear (ST64, ST65).

  On the other hand, when the production command of group B whose chain bit is ON (bit6 = 1) is received, the production command is stored in the chain reproduction queue (ST62), and the oldest corresponding one is received from the reception queue. The production command is deleted and the process is terminated (ST63).

  Next, the video reproduction process will be described with reference to FIG. Here, first, it is determined whether or not the video playback process has been completed for the effect command in the playback reservation area (not shown) (ST70). Then, when the video reproduction is finished, it is determined whether or not the chain reproduction queue is empty (ST71). Here, if the effect command (group B) is stored in the chain reproduction queue, it is copied to the reproduction reservation area (ST72).

  When the group B effect command has been copied to the playback reservation area, a video effect corresponding to this effect command is started by the processing of step ST76 thereafter. Therefore, in order to notify the effect control unit 51 that chain reproduction by the group B effect command is started, the corresponding effect command CMD 'is transmitted as serial data SD (ST73). Then, the effect command CMD 'is deleted from the chain reproduction queue (ST74).

  By the way, the effect control unit 51 obtains an effect command CMD ′ for each byte by handshake processing by RTS control (ST37 in FIG. 9). In addition, since the effect control unit 51 starts the lamp effect and the sound effect corresponding to the acquired effect command CMD ′ (ST38 to ST39 in FIG. 9), the video effect, the lamp effect, and the sound effect are correctly synchronized. It will be.

  Continuing the description of the processing in the liquid crystal control unit 61, is the chain reproduction queue empty (ST71), or is the production command stored in the reproduction reserved area when the chain reproduction queue is organized (ST74)? It is determined whether or not (ST75), and if it exists, the video effect is started for the effect command, and the effect command is deleted from the reproduction reserved area (ST76). As described above, both the group A effect command stored in the playback reservation area in the process of step ST65 and the group B effect command stored in the playback reservation area in the process of step ST72 are performed at the timing of step ST76. Will be started.

  The production commands for group A are activated immediately after reception, whereas the production commands for group B are temporarily stored in the chain reproduction queue and are activated in the order of the FIFO method. Therefore, by appropriately using the group A and group B effect commands, it is possible to arbitrarily realize an effect that does not cause a sense of incongruity even when suddenly interrupted, and an effect that should be completed without being interrupted during execution.

  FIG. 11 shows a control command transmitted from the main control unit 50 to the effect control unit 51, an effect command (A group + B group) transmitted from the effect control unit 51 to the liquid crystal control unit 61, and an effect from the liquid crystal control unit 61. It is drawing which shows the relationship with the production command (B group) returned to the control part 51, and the vertical axis | shaft direction has shown progress of time.

  In this example, in accordance with the reception timing of the control command CMD, the production control command 51 from the production control unit 51 to the liquid crystal control unit 61, the production command (B) at the second stop, 3. The effect command (C) at the time of stop and the effect command (D) at the time of payout are transmitted.

  Among the effect commands to be transmitted, the effect command (C) and the effect command (D) belong to the group B that is chain-reproduced, so the liquid crystal control unit that has received the effect command (C) and the effect command (D) In 61, the video effect is not started just by storing this in the chain reproduction queue (see ST62). Therefore, the video production by the production command (B) is completed without interruption.

  When the video production by the production command (B) is completed (YES in ST70), the production command (C) is read from the chain reproduction queue and reserved for reproduction (ST72), and the production command (C) is produced by the production control. Returned to unit 51 (ST73). Then, the effect control unit 51 that has received the effect command (C), together with the liquid crystal control unit 61, starts the effect operation related to the effect command (C) in synchronization.

  Thereafter, the same applies to the case where the video production by the production command (C) is completed (ST70 is YES), and the production control unit 51 starts the production operation related to the production command (D) in synchronization with the liquid crystal control unit 61. .

  And if the production command related to the production command (D) is completed before the production command at the time of medal insertion is received, since the received production command belongs to the A group, Starts video production related to medal insertion. At this stage, even if the production commands remain in the chain reproduction queue, they are all erased and are not activated. Then, as long as the production operation is not started by the liquid crystal control unit 61 and the production command is not returned (see ST73), the production command erased by the liquid crystal control unit 61 is not activated by the production control unit 51. . In addition, there is an advantage that the control load on the effect control unit 51 does not increase in such effect cancellation processing.

  As mentioned above, although the Example of this invention was described in detail, the concrete description content does not specifically limit this invention, Various modifications are possible without deviating from the meaning of this invention.

  For example, it is not necessary to fix whether the first group production command or the second group production command is set, and it is variably determined according to the progress of the game so far. Is preferred. When such a variable configuration is adopted, the same video effect can be used separately for the case where the chain is reproduced and the case where the chain is not reproduced, and the continuous effect by the chain reproduction can be realized more effectively.

  For example, (1) Assuming an effect command that specifies an image effect α corresponding to an effect when a medal is inserted in the next game, when a highly anticipated effect (video effect β) is performed at the end of the previous game, The chain reproduction bit of the production command is turned ON, and the video production α is started after the video production β is finished. On the other hand, when an effect with a low expectation (video effect γ) is performed at the end of the previous game, the chain effect bit is turned OFF, the video effect γ is interrupted, and the video effect α is started.

  In addition, (2) during playback of the start video effect X, when playing the video effect Y at the first stop, the chain playback bit of the effect command specifying the video effect Y is turned ON, and the start video effect X is finished. After that, video production Y is started. On the other hand, when starting the video effect Y at the third stop, the chain reproduction bit is turned OFF. This is because it is not necessary to play back the chain because the video effect X has ended at the time of the third stop.

  The above operation is realized by changing the chain bit in real time. FIG. 12 exemplifies the configuration. In this example, an effect command that may instruct chain playback is initially set to bit 6 = 0 so as to belong to the A group.

  First, after selecting an effect command by the effect lottery process (ST81), based on the game history up to this time, it is determined whether or not the image effect by the effect command is to be chained (ST811). Then, only in the case of chain playback, it is only necessary to set Bit 6 of the selected effect command to 1 and change it to the effect command of group B (ST813).

It is a front view of the slot machine which concerns on an Example. FIG. 2 is a right side view (a) and a plan view (b) of the slot machine of FIG. 1. It is the figure which illustrated the front panel of the slot machine from the back. It is an internal front view of the main body case of the slot machine. FIG. 2 is a block diagram showing a circuit configuration of the slot machine of FIG. 1. It is a block diagram showing a connection relationship among the production interface board, the production control unit, and the liquid crystal control unit. It is a flowchart explaining the main process in a main control part. It is drawing explaining the main process and power interruption process in an effect control part. It is a flowchart explaining a timer interruption process and a command reception process in the effect control unit. It is a flowchart explaining operation | movement of a liquid-crystal control part. It is a time chart which shows the operation content of a main control part, an effect control part, and a liquid-crystal control part. It is a flowchart explaining a modification.

Explanation of symbols

50 Main Control Unit 51 Production Control Unit 61 Image Control Unit CMD Control Command CMD ′ Production Command

Claims (6)

It has a first storage unit that maintains the stored contents even after the power supply voltage is cut off, and has a main control unit that controls the game operation in an integrated manner, and a second storage unit that maintains the stored contents even after the supply voltage is cut off. An effect control unit that executes an effect operation based on a control command received from the main control unit, and a gaming machine configured to include:
The production control unit is activated based on a main process that is started when the CPU is reset and an abnormal signal that is received before the power supply voltage is cut off, and data in a work area that identifies an ongoing production operation. Power interruption interruption processing to save the second storage unit,
In the power interruption interrupt process, upon completion of the process, a predetermined end data is added and stored in the second storage unit,
In the main process, when the predetermined end data is detected prior to starting the steady process, the stored data of the second storage unit is stored in the work area, while the predetermined end data is If not detected, the gaming machine is configured to start a steady process without clearing the work area. A second production control unit that executes production operation based on the production command output by the production control unit;
The gaming machine according to claim 1, wherein an effect display operation, a sound effect, and a lamp effect synchronized with each other are executed in the effect control unit and the second effect control unit. In the power interruption interrupt process, prior to storing the end data, the overall data calculated based on the data stored in the second storage unit is stored in the second storage unit,
In the main process, when the predetermined end data is detected, the general data is calculated by the same process as that in the power interruption interrupt process before starting the steady process, and the calculated value is the first value. The gaming machine according to claim 1 or 2, wherein a steady process is started without clearing the work area even when the total data stored in the two storage units does not match. The production control unit is configured to further include a reception interrupt process with the highest priority, which is activated when the control command is transmitted from the main control unit,
The gaming machine according to any one of claims 1 to 3, wherein the power interruption interrupt process is set to a higher priority following the reception interrupt process.   The power interruption interrupt process of the effect control unit is configured as a maskable interrupt process, while the main control unit is not maskable based on an abnormal signal received before the power supply voltage is cut off. The gaming machine according to any one of claims 1 to 4, wherein an interrupt process is activated. The first storage unit is arranged inside a one-chip microcomputer mounted on the main control unit, and its backup power is supplied from the power supply unit,
The said 2nd memory | storage part is arrange | positioned outside the one-chip microcomputer mounted in the said presentation control part, The backup power supply is ensured by the path | route different from the power supply of said 1st memory | storage part. A gaming machine according to any one of the above.

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