JP2009188818A - Ask demodulating circuit, and receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ASK demodulating circuit for improving the DUTY ratio of an output signal without depending on the waveform of an input signal while suppressing increase in a circuit area. <P>SOLUTION: This ASK demodulating circuit is equipped with a detector 1 to logarithmically detect a received signal, a first integrator 2 to output a first signal voltage V1 as an analog signal in response to the output of the detector 1, a second integrator 3 to output a second signal voltage V2 in response to the output of the detector 1 while having a time constant larger than that of the first integrator 2, a modulation factor detecting circuit 6 to detect the modulation factor of the first signal voltage V1, a reference voltage control circuit 5 to output a third signal voltage V3 obtained by changing the second signal voltage V2 in accordance with the modulation factor of the first signal voltage detected by the modulation detecting circuit 6, and a first comparator 4 to binarize the first signal voltage V1 on the basis of the third signal voltage. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a demodulation circuit used for receiving a signal modulated by an ASK (Amplitude Shift Keying) method.

  FIG. 16 is a diagram showing a configuration of an ASK demodulation circuit according to the first conventional example described in Patent Document 1. In FIG.

  This conventional ASK demodulating circuit includes a detector 101 for logarithmically detecting a received signal, a first voltage generating circuit for generating a first voltage in response to an output signal of the detector 101, and an output signal of the detector 101. A comparator 107 having a second voltage generation circuit that receives and generates a second voltage, a first input terminal to which the second voltage is input, and a second input terminal to which the first voltage is input; And a control circuit 109 that relatively changes the reference level of the comparator 107 in accordance with the second voltage. The first voltage generation circuit includes a first resistance element 103 a that receives the output signal of the detector 101 and a capacitive element 105 a, and the second voltage generation circuit receives a second output signal of the detector 101. The resistor element 103b and the capacitor element 105b. The comparator 107 binarizes (converts into a digital signal) the first voltage, which is an analog signal, using the second voltage controlled by the control circuit as a reference, and outputs it.

  As another conventional example, an ASK demodulation circuit described in Patent Document 2 is known. FIG. 17 is a block diagram showing an ASK demodulator circuit according to a second conventional example.

In the ASK demodulating circuit according to the second conventional example, the ASK-detected signal is amplified, the local maximum value and the local minimum value of the amplified signal at a plurality of predetermined times are detected, and the local maximum value and the local minimum value are averaged. Further, the result of the moving average is averaged, and the amplified signal is binarized using the value as the reference voltage of the comparator.
Japanese Patent Laying-Open No. 2005-341239 (FIG. 1) Japanese Patent Laid-Open No. 2000-78211 (FIG. 3)

  However, in the ASK demodulation circuit according to the first conventional example, the voltage difference between the maximum value and the minimum value of the analog detection signal output from the detector 101 via the first voltage generation circuit (hereinafter referred to as “modulation degree”). The reference voltage of the comparator 107 fluctuates in accordance with (referred to as “call”), so that the DUTY ratio of the output waveform fluctuates.

  FIG. 18 is a diagram illustrating a case where the DUTY ratio of the output waveform varies in the ASK demodulation circuit according to the first conventional example. Since the modulation degree of the detection signal is larger in the right diagram of the figure than in the left diagram, the reference voltage V2 of the comparator, which is the average value of the minimum value and the maximum value of the detection signal, is the same as in the right diagram and the left diagram. It varies depending on the case of the figure. For this reason, the DUTY ratio is larger in the example in the right diagram than in the example in the left diagram. The DUTY ratio is preferably 50%. If the DUTY ratio varies depending on the intensity of the received signal, a malfunction may occur in the processing of the received signal.

  In the ASK demodulating circuit according to the second conventional example, the local maximum value and the local minimum value of the detection signal are detected, the moving average of the local maximum value and the local minimum value is taken, and the average value of these moving averages is used as a reference voltage. Convert to value. That is, in the ASK demodulator circuit according to the second conventional example, as in the ASK demodulator circuit according to the first conventional example, the reference voltage of the comparator that binarizes according to the modulation degree of the detection signal greatly fluctuates. There is a problem that the DUTY ratio of the output waveform of the demodulation circuit varies depending on the received signal. It is also possible to correct the output signal DUTY ratio to about 50% by increasing the number of bits of the A / D converter and calculating the output signal of the ASK demodulator circuit by a DSP (Digital Signal Processor). However, the area of the A / D converter and the DSP increases as the reception accuracy is improved, and the manufacturing cost of the ASK receiver increases.

  The present invention is intended to solve the above-described problems of the conventional example, and provides an ASK demodulating circuit that can improve the DUTY ratio of an output signal while suppressing an increase in circuit area without depending on the waveform of an input signal. For the purpose.

  In order to achieve the above object, an ASK demodulation circuit according to the present invention includes a detector for logarithmically detecting a received signal, and a first integration for receiving a first signal voltage which is an analog signal in response to the output of the detector. And a second signal voltage output from the detector, a second integrator having a larger time constant than the first integrator, and a degree of modulation of the first signal voltage is detected. A modulation degree detection circuit that receives the second signal voltage and increases or decreases the second signal voltage according to the modulation degree of the first signal voltage detected by the modulation degree detection circuit. A reference voltage control circuit that outputs a signal voltage; and a first comparator that binarizes the first signal voltage with reference to the third signal voltage.

  According to this configuration, the modulation degree of the first signal voltage indicating the detection signal can be detected, and the second signal voltage can be increased or decreased according to the modulation degree. Therefore, the reference voltage (first voltage) of the first comparator can be increased or decreased. 3 signal voltage) can be adjusted to an appropriate value. Therefore, depending on the input signal by setting the third signal voltage so that the pulse width of the output of the first comparator, which is the demodulated signal, is set to an appropriate value (for example, 50%) of the DUTY ratio. In other words, the DUTY ratio of the output signal can be brought close to the ideal value. Therefore, if the ASK demodulator circuit of the present invention is used, the received signal can be demodulated more accurately than before. Further, since the DUTY ratio is adjusted when the received signal is an analog signal, the circuit area required for demodulation can be reduced as compared with the case where the DUTY ratio is adjusted by a DSP circuit or the like using the demodulated signal.

  The receiver according to the present invention includes an antenna for capturing a received signal, a detector for logarithmically detecting the received signal converted to an intermediate frequency signal, and an analog signal received from the detector. A first integrator that outputs a signal voltage; a second integrator that receives the output of the detector and outputs a second signal voltage; and has a larger time constant than the first integrator; A modulation degree detection circuit for detecting a modulation degree of the first signal voltage; and the second signal according to the modulation degree of the first signal voltage detected by the modulation degree detection circuit upon receiving the second signal voltage. A reference voltage control circuit for outputting a third signal voltage obtained by increasing or decreasing the voltage; and an ASK demodulating circuit having a comparator for binarizing the first signal voltage with reference to the third signal voltage. ing.

  With this configuration, the reference voltage of the comparator in the ASK demodulator circuit can be adjusted to a value that makes the DUTY ratio of the demodulated signal appropriate, so that the modulation degree of the received signal input to the ASK demodulator circuit can be adjusted. Regardless of this, the received signal can be accurately demodulated.

  According to the ASK demodulating circuit and the receiver of the present invention, the modulation degree of the first signal voltage indicating the detection signal is detected, and the reference voltage of the first comparator is appropriately set according to the modulation degree of the first signal voltage. It can be adjusted to a value (for example, a constant value). Since the pulse width of the output signal of the first comparator is adjusted by this reference voltage, by appropriately adjusting the third signal voltage as the reference voltage, the output signal can be output without depending on the waveform of the input signal. The DUTY ratio can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a receiver including an ASK demodulation circuit according to the first embodiment of the present invention. This ASK receiver is applied to, for example, an ETC (Electronic Toll Collection System) vehicle-mounted device, and receives a modulated signal transmitted from a road device in the ETC system.

  The receiver of this embodiment includes an antenna 7 that captures transmission radio waves from a road device, a low noise amplifier (LNA) 8 that amplifies a received signal supplied from the antenna 7, and an output of the LNA 8 that is a local oscillator 10. Is provided with a mixer 9 that mixes with a local signal generated by the signal and converts the signal into an intermediate frequency (IF) signal of 40 MHz, for example, and an ASK demodulator 60.

  The ASK demodulation circuit 60 of the present embodiment includes an RSSI detector 1, a first integrator 2, a second integrator 3, a reference voltage control circuit 5, a modulation degree detection circuit 6, and a comparator 4. Have. These circuits constituting the ASK demodulation circuit 60 can be integrated on a single semiconductor substrate. It is also possible to integrate the entire constituent circuits of the receiver on one semiconductor substrate.

  FIG. 2 is a block diagram showing a detailed configuration of the ASK demodulation circuit of the present embodiment. As shown in the figure, the first integrator 2 includes a first resistor 11 connected to the output of the RSSI detector 1, one electrode grounded, and the other electrode connected to the first resistor 11. The first capacitor 12 is connected. The second integrator 3 includes a second resistor 13 connected to the output portion of the RSSI detector 1 and a second capacitor in which one electrode is grounded and the other electrode is connected to the second resistor 13. 14.

  The ASK demodulation circuit 60 receives the IF signal output from the mixer 9 and demodulates the received signal by logarithmically detecting the envelope using, for example, an RSSI (Receive Signal Strength Indicator) detector 1.

  The output signal of the RSSI detector 1 is input to the comparator 4 through two signal paths described below. That is, the output signal of the RSSI detector 1 is supplied to the non-inverting input terminal of the comparator 4 through the first integrator 2 as the signal voltage V1. On the other hand, the output signal of the RSSI detector 1 is also supplied to the reference voltage control circuit 5 connected to the inverting input terminal of the comparator 4 via the second integrator 3. Here, the signal voltage input to the reference voltage control circuit 16 is V2.

  The CR product (time constant) of the first integrator 2 is set sufficiently smaller than the CR product (time constant) of the second integrator 3. For example, if the resistance value of the first resistor 11 is about 10 kΩ and the resistance value of the second resistor 13 is about 10 kΩ, the capacitance value of the first capacitor 12 is about 22 pF and the capacitance value of the second capacitor 14 is 220 pF. It will be about.

  By setting in this way, a predetermined potential difference can be generated between the two signals input to the comparator 4 along different paths. The comparator 4 outputs a “High” signal when the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, and outputs a “Low” signal when the potential of the non-inverting input terminal is lower than the potential of the inverting input terminal. Is output.

  The reference voltage control circuit 5 includes a buffer circuit 16 and a resistor 15, and an output terminal of the reference voltage control circuit 5 is connected to the inverting input terminal of the comparator 4 and the modulation degree detection circuit 6. Here, the signal voltage output from the reference voltage control circuit 5 to the inverting input terminal of the comparator 4 is V3.

  The modulation degree detection circuit 6 includes a peak hold circuit 19 that holds the maximum value of the signal voltage V1, a bottom hold circuit 20 that holds the minimum value of the signal voltage V1, and a variable current source 21 of the voltage control system. . The output signal of the RSSI detector 1 is input to the peak hold circuit 19 and the bottom hold circuit 20 via the first integrator 2. The control terminal of the variable current source 21 is connected to the peak hold circuit 19 and the bottom hold circuit 20. The variable current source 21 can be set to either a sink or a source.

  Next, the operation in the ASK demodulation circuit 60 of this embodiment will be described. FIG. 3 is a flowchart showing the receiving operation in the ASK demodulator circuit of this embodiment.

  Since the RSSI detector 1 performs logarithmic weighting on the input IF signal, the signal voltage V1 (detection signal) detected by the RSSI detector 1 is an envelope as shown in the upper diagram of FIG. The waveform is such that the positive half cycle in the waveform is compressed in the vertical direction, and the negative cycle is limited. Accordingly, the signal voltage V1 has a vertically asymmetrically distorted waveform.

  As shown in FIG. 3, first, a signal received by the antenna 7 is input to the RSSI detector 1 of the ASK demodulation circuit 60 via the LNA 8 and the mixer 9 (step S1).

  Next, the RSSI detector 1 performs a detection operation at a predetermined interval. When a signal is input, the RSSI detector 1 outputs a signal voltage corresponding to the electric field strength (step S2).

  Next, the output of the RSSI detector 1 is input to the first integrator 2 and input to the non-inverting output terminal of the comparator 4 and the modulation degree detection circuit 6 as the signal voltage V1. At the same time, the output of the RSSI detector 1 is also input to the second integrator 3, and is input to the reference voltage control circuit 5 as the signal voltage V2 (step S3). Since the CR product of the second integrator 3 is larger than the CR product of the first integrator 2, the signal voltage V1 is an AC signal, and the signal voltage V2 is a DC signal containing a little AC component. Yes. Note that the CR product of the second integrator 3 is set to be approximately the average value V2 of the output voltage of the RSSI detector 1. Even if the received signal strength is the same, the second output voltage V2 of the RSSI detector 1 is higher as the modulation degree is lower, and is lower as the modulation degree is higher. Note that the “modulation degree” here is the maximum value and the minimum value of the signal voltage V1 that is an analog detection signal output from the RSSI detector 1 via the first integrator 2 as defined above. It shall mean the voltage difference.

  Next, the modulation degree detection circuit 6 detects the modulation degree using the maximum value and the minimum value of the signal voltage V1, and outputs the detection result to the reference voltage control circuit 5 (step S4). Then, the reference voltage control circuit 5 changes the signal voltage V2 in accordance with the detected modulation degree, and outputs the signal voltage V3 to the inverting input terminal of the comparator 4 (step S5).

  4A is a diagram showing a relationship between the current I flowing through the variable current source 21 and the modulation degree of the signal voltage V1, and FIG. 4B is a modulation degree of the signal voltages V2, V3 and the signal voltage V1. It is a figure which shows the relationship. In FIG. 4A, the vertical axis is a current I having a positive direction from the variable current source 21 toward the ground.

  In steps S4 and S5, the modulation degree detection circuit 6 can change the current value flowing through the resistor 15 by changing the current value flowing through the variable current source 21 in accordance with the modulation degree of the detection signal. Specifically, as shown in FIG. 4A, the value of the current flowing through the variable current source 21 has a current value when the modulation degree of the signal voltage V1 is large (that is, the modulation degree of the output of the RSSI detector 1 is large). Is small, and the current value increases when the modulation degree is small. However, the relationship between the modulation factor and the current flowing through the variable current source 21 is not limited to the relationship shown in FIG. 4A in which the current is expressed by a primary expression of the modulation factor.

  Further, in the reference voltage control circuit 5, when the modulation degree of the signal voltage V1 is small (that is, the modulation degree of the output of the RSSI detector 1 is small), the current I flowing through the variable current source 21 increases, and the reference voltage control circuit 5 The current flowing through the resistor 15 in 5 increases. That is, the voltage drop due to the resistor 15 increases. As a result, the output voltage V3 of the reference voltage control circuit 5 is lower than the output voltage V2. When the modulation degree of the signal voltage V1 is large (that is, the modulation degree of the output of the RSSI detector 1 is large), the current value flowing through the variable current source 21 becomes small, so that the current flowing through the resistor 15 decreases, and the voltage generated by the resistor 15 The drop is reduced or the current I flowing through the variable current source 21 flows into the reference voltage control circuit 5 conversely, and the output voltage V3 increases due to the voltage rise by the resistor 15 in the reference voltage control circuit 5. Therefore, the output voltage V3 of the reference voltage control circuit 5 is a constant voltage regardless of the modulation degree of the output of the RSSI detector 1, as shown in FIG.

  Next, the comparator 4 binarizes the signal voltage V1 using the signal voltage V3 as a reference, and outputs a demodulated signal Vout (step S6 in FIG. 3).

  FIG. 6A is a waveform diagram showing signal voltages V1, V2, and V3 in the ASK demodulating circuit of this embodiment, and FIG. 6B is a waveform showing the current I flowing from the variable current source 21 to the ground. (C) is a waveform diagram showing a command signal (RX data) included in a received signal, and (d) is a waveform diagram showing a demodulated signal Vout.

  As shown in FIGS. 6A to 6D, when the receiver receives a signal, signal voltages V1, V2, and V3 output from the RSSI detector 1 rise. Next, when the current I starts to flow through the variable current source 21, the signal voltage V3 becomes lower than the signal voltage V2 by the voltage drop across the resistor 15. In the example of FIG. 6, since the modulation degree and signal strength of the signal voltage V1 are constant, the current value and the values of the signal voltages V2 and V3 are substantially constant during the demodulation period of the data signal included in the RX data. ing.

  Next, when the detection signal output from the RSSI detector 1 is “0”, that is, the signal voltage V1 is 0, the signal voltages V2 and V1 are not input as shown in FIG. The degree of modulation becomes zero and the amount of current flowing through the variable current source 21 increases, so that the output voltage V3 of the reference voltage control circuit 5 decreases.

  FIG. 5 is a waveform diagram showing V1, V3, and Vout during the receiving operation in the ASK demodulation circuit 60 of the present embodiment. As shown in the figure, according to the ASK demodulator circuit 60 of the present embodiment, even if the modulation degree of the received signal changes, the fluctuation of the reference value of the comparator 4 can be reduced as compared with the conventional demodulator circuit. . That is, the DUTY ratio can be made closer to a desired value (for example, 50%) without depending on the waveform of the received signal, and the received signal can be accurately demodulated. For this reason, generation | occurrence | production of a malfunction can be suppressed effectively in narrow area communications, such as an ETC system.

  Also, according to the ASK demodulator circuit of this embodiment, the DUTY ratio of the demodulated waveform can be adjusted before digitally converting the received signal, so that the signal compared to the case where the demodulated signal, which is a digital signal, is processed by the DSP. The circuit area required for receiving the signal can be greatly reduced, and the manufacturing cost can be reduced.

  The configuration of the ASK demodulator circuit is not limited to the above configuration, and various modifications are possible as long as the same effect can be obtained. For example, in the ASK demodulating circuit of the present embodiment, the signal voltage V3 serving as the reference value of the comparator 4 is constant regardless of the modulation degree of V1, but the signal voltage V3 becomes V2 as the modulation degree of the signal voltage V1 increases. Alternatively, a desired DUTY ratio may be obtained by decreasing more slowly.

(Second Embodiment)
FIG. 7 is a block diagram showing a configuration of an ASK demodulation circuit according to the second embodiment of the present invention. In this figure, the same parts as those of the ASK demodulator circuit of the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The ASK demodulator circuit of this embodiment controls the variable current source of the modulation degree detection circuit using a carrier sense signal (hereinafter referred to as “CS signal”) in the ASK demodulator circuit of the first embodiment. is there. Here, the CS signal means a signal indicating the reception period of the data signal shown in FIG.

  As shown in FIG. 7, the ASK demodulation circuit of the present embodiment includes a second comparator 31 and a switch 50 in addition to the circuit configuration of the first embodiment. The second comparator 31 receives the signal voltage V2 output from the second integrator 3 and the DC reference voltage Vref at the non-inverting input terminal and the inverting input terminal, respectively. Output CS signal. The switch 50 is provided between the variable current source 21 and the ground, and is turned ON or OFF by a CS signal. The DC power supply 70 that supplies Vref may be provided outside the ASK demodulator circuit or may be provided inside the ASK demodulator circuit.

  In the ASK demodulation circuit of this embodiment, when the received signal strength exceeds a predetermined level that can be arbitrarily set, for example, −65 dBm, “Low” is switched to “High”, or “High” is switched to “Low”. That is, the signal voltage V2 and the reference voltage Vref supplied from the outside are compared by a comparator with hysteresis, and when the signal voltage V2 is higher than the reference voltage Vref, “High” is output and when it is lower, “Low” is output. Alternatively, “Low” may be output when the signal voltage V2 is higher than the reference voltage Vref, and “High” may be output when the signal voltage V2 is lower. FIG. 9 is a diagram illustrating a change example of the CS signal. In the ASK demodulating circuit of the present embodiment, a normal comparator may be used as the second comparator 31. However, in the case of an ETC system, if a comparator with hysteresis is used, the received signal strength is instantaneous due to the position of the vehicle, noise, or the like. Even if it is blurred, it is preferable because the CS signal High and Low are not frequently switched.

  The demodulation operation in the ASK demodulation circuit having the above configuration will be described. 10A is a waveform diagram of the CS signal in the ASK demodulator circuit according to the second embodiment, FIG. 10B is a waveform diagram of the signal voltages V1, V2, and V3, and FIG. 10C is a variable current source. 21 is a waveform diagram of a current I flowing from 21 to the ground, (d) is a waveform diagram of a command signal (RX data) included in a received signal, and (e) is a waveform diagram of a demodulated signal Vout.

  As shown in FIG. 10A, the modulation degree detection circuit 6 is configured such that, for example, when the signal voltage V2 of the RSSI detector 1 becomes higher than the reference voltage Vref of the second comparator 31, the CS signal changes from “Low” to “High”. This becomes the CS signal start trigger, and the current I flows to the variable current source 21 in the modulation degree detection circuit 6 as shown in FIG. Then, according to the modulation degree of the detection signal, as described above, the output voltage V3 in the reference voltage control circuit 5 becomes lower than the signal voltage V2 due to a voltage drop. Thereafter, for example, when the CS signal is switched from “High” to “Low”, this becomes the CS signal end trigger, and the current I flowing through the variable current source 21 is stopped as shown in FIG. As a result, since no current flows through the resistor 15 in the reference voltage control circuit 5, no voltage drop occurs in the resistor 15, and the signal voltage V3 becomes the same as the input voltage V2 of the reference voltage control circuit 5.

  FIG. 8 is a flowchart showing a receiving operation in the ASK demodulator circuit of this embodiment. In the receiving method of the present embodiment, the level of the CS signal changes after step S3 (see FIG. 3) of the receiving method described in the first embodiment (step S11). In the example of FIG. 10C, the CS signal changes from “Low” to “High”, the switch 50 is turned on, and the current I starts to flow through the variable current source 21. Thereafter, in steps S4 to S6, the binarized signal Vout is output by the same operation as in the first embodiment. When reception of data in the RX data ends, the CS signal changes from “High” to “Low”, the switch 50 is turned off, and the current I flowing through the variable current source 21 is stopped.

  In this way, the operation of the modulation degree detection circuit 6 is controlled by the CS signal, and the current I flowing through the variable current source 21 in the modulation degree detection circuit 6 is stopped when there is no response, that is, when the CS signal is “Low”. Thus, accurate demodulation can be performed, and power consumption can be suppressed as compared with the conventional and ASK demodulation circuits of the first embodiment.

  In the ASK demodulation circuit of this embodiment, the result of comparing the detection signal with the reference voltage by the second comparator 31 is used as the CS signal. However, the CS signal is generated directly using the received baseband signal. Also good.

  In the ASK demodulating circuit of the present embodiment, the variable current source 21 may be a current source that changes the current value in an analog manner, or a digital current by turning on / off a plurality of current sources with a switch. It may be a current source that changes the value.

(Third embodiment)
FIG. 11 is a block diagram showing an ASK demodulation circuit configuration according to the third embodiment of the present invention. In this figure, the same parts as those of the ASK demodulator circuit of the second embodiment shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the ASK demodulation circuit of this embodiment, the modulation degree detection circuit 6 digitally controls the peak hold circuit 19, the bottom hold circuit 20, and the plurality of current sources 54 a and 54 b with the switches 52 a, 52 b and 50. The circuit includes a variable current source circuit 32 that can change the current value, a counter circuit 34 that can set an arbitrary time, and a latch circuit 33. Each current source in the variable current source circuit 32 can be set to either a sink or a source. The output of the counter circuit 34 is connected to the variable current source circuit 32 and the control terminal of the latch circuit 33.

  The latch circuit 33 receives a value obtained by A / D conversion or digitizing the output voltages of the peak hold circuit 19 and the bottom hold circuit 20 of the modulation degree detection circuit 6 by a plurality of comparators. The output terminal of the latch circuit 33 is connected to switches 52 a and 52 b that control each current source in the variable current source circuit 32. Note that the number of output terminals and the number of current sources of the latch circuit 33 can be arbitrarily set.

  The demodulation operation in the ASK demodulation circuit having the above configuration will be described. FIG. 13A is a waveform diagram of a CS signal in the ASK demodulator circuit according to the third embodiment, FIG. 13B is a waveform diagram of an output signal of the counter circuit 34, and FIG. 13C is a signal voltage V1, V2. , V3, (d) is a waveform diagram of the current I flowing from the variable current source circuit 32 to the ground, and (e) is a waveform diagram of a command signal (RX data) included in the received signal. (F) is a waveform diagram of the demodulated signal Vout.

  As shown in FIGS. 13A to 13F, when the signal voltage V2 of the RSSI detector 1 becomes higher than the reference voltage Vref of the second comparator 31, the CS signal is switched from “Low” to “High”. As a signal start trigger, the output of the counter circuit 34 switches from “Low” to “High”. This becomes a start trigger of the counter circuit 34, and the current I flows into the variable current source circuit 32 in the modulation degree detection circuit 6. Then, as described above, a voltage drop of the signal voltage V3 that is the output of the reference voltage control circuit 5 occurs according to the modulation degree of the detection signal.

  After that, for example, when the CS signal switches from “High” to “Low”, this becomes the CS signal end trigger, and the latch circuit 33 holds the output voltages of the peak hold circuit 19 and the bottom hold circuit 20 at that time. The fixed voltage is output to the switches 52a and 52b. The latch circuit 33 holds this state until there is a CS signal end trigger, such as when the CS signal switches from “High” to “Low”. As a result, the value of the current flowing through the variable current source circuit 32 is fixed to a constant value until the CS signal switches from “High” to “Low”. Therefore, even if the modulation degree of the detection signal varies after the end trigger of the counter circuit 34, the output of the latch circuit 33 is constant and the current flowing through the reference voltage control circuit 5 is constant, so that the signal voltage V3 becomes a fixed value. Become.

  Next, when the CS signal is switched from “High” to “Low”, this becomes the CS signal end trigger, and the current I flowing through the variable current source circuit 32 is stopped as shown in FIG.

  FIG. 12 is a flowchart showing a receiving operation in the ASK demodulator circuit of this embodiment. As described above, when the CS signal is output in step S11 and the modulation degree of the signal voltage V1 is detected in step S4, the signal output from the counter circuit 34 in step S21 is “High”. A voltage drop corresponding to the degree of modulation occurs in the voltage V3 (step S22). If the level of the signal output from the counter circuit 34 is “Low”, a fixed voltage drop occurs in the signal voltage V3 (step S23).

  13C and 13E, the received signal is in a low amplitude state corresponding to logic “0” (ie, A × (1-m) / (1 + m)) at times t1 to t3. After a long time, the signal voltage V2 decreases, and after the time t2, matches the signal voltage V1, where A is the amplitude width corresponding to “1”, that is, the input level, and m is the modulation. In addition, since the modulation degree of the signal voltage V1 is 0, the value of the current flowing through the variable current source circuit 32 is increased, and a voltage drop of the signal voltage V3 that is the output of the reference voltage control circuit 5 occurs. After t2, the signal voltage V3 becomes lower than the detection signal V1, and the logic “0” is originally set to the period from time t2 to t3 when the signal corresponding to the next logic “1” is input. Should be output, "1" is output. That is, the same may malfunction lasted a period of no signal instead of persistent. Logic "0" is generated.

  FIG. 14A is a waveform diagram of the CS signal when the setting of the counter circuit 34 is changed in the ASK demodulating circuit according to the third embodiment, and FIG. 14B is a waveform diagram of the output signal of the counter circuit 34. (C) is a waveform diagram of the signal voltages V1, V2, and V3, (d) is a waveform diagram of the current I flowing from the variable current source circuit 32 to the ground, and (e) is included in the received signal. (F) is a waveform diagram of a demodulated signal Vout.

  In the ASK demodulating circuit of this embodiment, the above-described problems can be solved by setting the setting time of the counter circuit 34 within the preamble signal period, for example, about 8 μs in the case of ETC. That is, as shown in FIGS. 14A to 14F, by setting the set time t1 of the counter circuit 34 within the period of the preamble signal, even if the period of “0” or no signal continues for a long time, Prior to time t2 when the “0” period starts, the output voltage V3 of the reference voltage control circuit 5 is fixed. Therefore, during the period from time t2 to time t3 when the signal corresponding to logic “1” is next input, V3, which is the reference voltage of the comparator 4, is higher than the signal voltage V2, so that logic “0” is output. The data can be demodulated correctly. Note that the setting time of the counter circuit 34 is about 2 μs when the signal voltage V2 rises and the time required for detecting the modulation degree of the signal voltage V1 is 4 μs. When a margin of about 2 μs is taken, this value is about 8 μs. It is not limited to.

  In the above description, the “preamble signal” is a control signal for establishing synchronization, and is a special bit string that continues repeatedly for a period of “1” and “0” periodically, for example, about 16 μs in the case of ETC. It is. As shown in FIG. 16, the ETC frame configuration is generally in the order of a preamble signal, a unique word signal, and a data signal. Since the length of the preamble signal is determined by the communication method, it is easy to set the setting time of the counter circuit 34 within the preamble signal period in advance.

  As described above, according to the ASK demodulating circuit of the present embodiment, it is possible to demodulate data without error even when the received signal is “0” or when there is no input for a long time. Note that the conventional demodulation circuits described in Patent Documents 1 and 2 cannot prevent a decrease in the reference voltage of the comparator when “0” or no input continues, which may cause a malfunction. On the other hand, according to the ASK demodulation circuit of the present embodiment, data demodulation can be performed more accurately than the conventional demodulation circuit.

  The configuration of the ASK demodulator circuit of the present invention is not limited to the above-described specific configuration, and can be variously modified as long as the same effect can be obtained.

  The demodulation circuit of the present invention described above is preferably used for a receiver for narrow band communication such as ASK communication.

It is a block diagram which shows the structure of the receiver containing the ASK demodulation circuit which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the detailed structure of the ASK demodulation circuit which concerns on 1st Embodiment. 4 is a flowchart showing a reception operation in the ASK demodulation circuit according to the first embodiment. (A) is a figure which shows the relationship between the electric current I which flows through the variable current source 21, and the modulation degree of signal voltage V1, (b) shows the relationship between the signal voltage V2, V3 and the modulation degree of signal voltage V1. FIG. FIG. 4 is a waveform diagram showing V1, V3, and Vout during a receiving operation in the ASK demodulation circuit according to the first embodiment. (A) is a waveform diagram showing signal voltages V1, V2, and V3 in the ASK demodulating circuit according to the first embodiment, and (b) is a waveform diagram showing a current I flowing from the variable current source to the ground. (C) is a waveform diagram showing a command signal (RX data) included in the received signal, and (d) is a waveform diagram showing a demodulated signal Vout. It is a block diagram which shows the structure of the ASK demodulation circuit which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the receiving operation in the ASK demodulation circuit which concerns on 2nd Embodiment. It is a figure which shows the example of a change of CS signal in the ASK demodulation circuit which concerns on 2nd Embodiment. (A) is a waveform diagram of the CS signal in the ASK demodulator circuit according to the second embodiment, (b) is a waveform diagram of the signal voltages V1, V2, and V3, and (c) is a ground from the variable current source. 4D is a waveform diagram of a command signal (RX data) included in the received signal, and FIG. 4E is a waveform diagram of the demodulated signal Vout. It is a block diagram which shows the ASK demodulation circuit path structure concerning the 3rd Embodiment of this invention. 10 is a flowchart illustrating a reception operation in an ASK demodulation circuit according to a third embodiment. (A) is a waveform diagram of the CS signal in the ASK demodulator circuit according to the third embodiment, (b) is a waveform diagram of an output signal of the counter circuit, and (c) is a signal voltage V1, V2, (D) is a waveform diagram of the current I flowing from the variable current source circuit to the ground, (e) is a waveform diagram of the command signal (RX data) included in the received signal, f) is a waveform diagram of the demodulated signal Vout. (A) is a waveform diagram of the CS signal when the setting of the counter circuit 34 is changed in the ASK demodulation circuit according to the third embodiment, and (b) is a waveform diagram of an output signal of the counter circuit 34. (C) is a waveform diagram of the signal voltages V1, V2, and V3, (d) is a waveform diagram of the current I flowing from the variable current source circuit 32 to the ground, and (e) is a command included in the received signal. It is a wave form diagram of a signal (RX data), and (f) is a wave form diagram of demodulated signal Vout. It is a figure which shows the frame structure of the communication data in ETC. It is a figure which shows the structure of the ASK demodulation circuit which concerns on a 1st prior art example. It is a block diagram which shows the ASK demodulation circuit which concerns on a 2nd prior art example. It is a figure which shows the case where the DUTY ratio of an output waveform fluctuates in the ASK demodulator circuit according to the first conventional example.

Explanation of symbols

1 detector
2 First integrator
3 Second integrator
4 Comparator
5 Reference voltage control circuit
6 Modulation degree detection circuit
7 Antenna
8 LNA
9 Mixer
10 Local oscillator
11 First resistor
12 First capacitor
13 Second resistor
14 Second capacitor
15 Resistance
16 Buffer circuit
19 Peak hold circuit
20 Bottom hold circuit
21 Variable current source
31 Second comparator
32 Variable current source circuit
33 Latch circuit
34 Counter circuit
50, 52a, 52b switch
54a, 54b Current source
60 ASK demodulation circuit
70 DC power supply
V1, V2, V3 signal voltage

Claims (11)

A detector for logarithmically detecting the received signal;
A first integrator that receives the output of the detector and outputs a first signal voltage that is an analog signal;
Receiving the output of the detector and outputting a second signal voltage; a second integrator having a larger time constant than the first integrator;
A modulation degree detection circuit for detecting a modulation degree of the first signal voltage;
A reference voltage that receives the second signal voltage and outputs a third signal voltage obtained by increasing or decreasing the second signal voltage according to the modulation degree of the first signal voltage detected by the modulation degree detection circuit. A control circuit;
An ASK demodulator circuit comprising: a first comparator that binarizes the first signal voltage with reference to the third signal voltage. The modulation degree detection circuit includes: a peak hold circuit that holds the maximum value of the first signal voltage; a bottom hold circuit that holds the minimum value of the first signal voltage; and the reference voltage control circuit and ground. A current having a value corresponding to a voltage difference between a maximum value of the first signal voltage output from the peak hold circuit and a minimum value of the first signal voltage output from the bottom hold circuit is provided. A variable current source,
2. The ASK demodulator according to claim 1, wherein the reference voltage control circuit increases or decreases the second signal voltage in accordance with a current value supplied from the variable current source, and outputs the third signal voltage. circuit.   3. The ASK demodulator circuit according to claim 2, wherein the variable current source digitally changes a current value according to a modulation degree of the first signal voltage.   4. The ASK demodulator circuit according to claim 2, wherein a value of a current flowing from the variable current source to the ground increases as a modulation degree of the first signal voltage decreases. 5. A second comparator for comparing the second signal voltage with a predetermined reference voltage;
5. The ASK demodulator circuit according to claim 2, wherein whether or not a current flows to the variable current source is controlled by an output of the second comparator. 6.   In the modulation degree detection circuit, the variable current source modulates the first signal voltage from when the output of the second comparator is switched from the first level to the second level until the lapse of a predetermined period. The variable current source supplies a current of a fixed value during a period until the output of the second comparator switches from the second level to the first level after the predetermined period has passed. 6. The ASK demodulator circuit according to claim 5, wherein the third signal voltage is fixed by flowing.   The modulation degree detection circuit is provided between the output unit of the second comparator and the variable current source, and includes a counter that counts the predetermined period, an output of the peak hold circuit, and an output of the bottom hold circuit The ASK demodulating circuit according to claim 6, further comprising: a latch circuit that receives the output of the counter and outputs a fixed voltage after the predetermined period has elapsed.   The ASK demodulating circuit according to claim 6 or 7, wherein the predetermined period is within a preamble period of a received signal.   The ASK demodulator according to claim 5 or 6, wherein the second comparator is a comparator with hysteresis. An antenna that captures the received signal;
A detector for logarithmically detecting the received signal converted into an intermediate frequency signal, a first integrator for receiving a first signal voltage which is an analog signal in response to an output of the detector, and an output of the detector The second integrator having a time constant larger than that of the first integrator, a modulation degree detection circuit for detecting a modulation degree of the first signal voltage, Reference voltage control for receiving a second signal voltage and outputting a third signal voltage obtained by increasing or decreasing the second signal voltage in accordance with the modulation degree of the first signal voltage detected by the modulation degree detection circuit A receiver comprising: a circuit; and an ASK demodulation circuit having a comparator that binarizes the first signal voltage with reference to the third signal voltage. The modulation degree detection circuit includes: a peak hold circuit that holds the maximum value of the first signal voltage; a bottom hold circuit that holds the minimum value of the first signal voltage; and the reference voltage control circuit and ground. A current having a value corresponding to a voltage difference between a maximum value of the first signal voltage output from the peak hold circuit and a minimum value of the first signal voltage output from the bottom hold circuit is provided. A variable current source,
11. The receiver according to claim 10, wherein the reference voltage control circuit increases or decreases the second signal voltage according to a current value supplied from the variable current source, and outputs the third signal voltage. .

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