JP2009188548A - Multiplexer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiplexer capable of reducing distortion in an output signal wave and suppressing enlargement in the scale of the multiplexer. <P>SOLUTION: The multiplexer 1 comprises a CMOS switch 10<SB>1</SB>for receiving a first input signal through a first capacitor, a CMOS switch 10<SB>2</SB>for receiving a second input signal through a second capacitor, a clamp circuit 30, and a clamp circuit 40. The clamp circuit 30 is synchronized with the first input signal and clamps the first input signal by Vclp1 when the conduction of CMOS switch 10<SB>1</SB>is carried out, and synchronized with the second input signal and clamps the second input signal by Vclp1 when the conduction of CMOS switch 10<SB>2</SB>is carried out. The clamp circuit 40 detects the second input signal and clamps the detected second input signal so as to bring it close to Vclp2 when the conduction of CMOS switch 10<SB>1</SB>is carried out, and detects the first input signal and clamps the detected first input signal so as to bring it close to Vclp2 when the conduction of CMOS switch 10<SB>2</SB>is carried out. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multiplexer that selectively outputs an analog signal.

  Patent Document 1 discloses a multiplexer using a plurality of CMOS switches. This CMOS switch has an NMOS transistor and a PMOS transistor connected in parallel. The CMOS switch has the input terminal connected to the sources of these transistors and the output terminal connected to the drains of these transistors.

  In order to turn on the CMOS switch, the power supply voltage Vdd on the high potential side higher than the voltage of the input signal input to the source is input to the gate of the NMOS transistor, and the source is connected to the gate of the PMOS transistor. The power supply voltage Vss on the low potential side, which is lower than the voltage of the input signal input to, must be input.

On the other hand, in order to turn off the CMOS switch, the power supply voltage Vss on the low potential side lower than the voltage of the input signal input to the source is input to the gate of the NMOS transistor, and the gate of the PMOS transistor is input. A high-potential power supply voltage Vdd higher than the voltage of the input signal input to the source must be input.
JP 2005-303347 A

  By the way, with the recent reduction in power supply voltage due to the reduction in power consumption, the power supply voltage of the preceding circuit may become higher than the power supply voltage of the multiplexer. As a result, the voltage of the multiplexer input signal may be higher than the power supply voltage Vdd on the high potential side of the multiplexer. In some cases, the voltage of the input signal of the multiplexer may be higher than the power supply voltage Vdd by the threshold voltage Vthp of the PMOS transistor. As a result, the PMOS transistor originally intended to be turned off is turned on, and a leak current flows through the PMOS transistor.

  Also, the voltage of the input signal of the multiplexer may be lower than the power supply voltage Vss on the low potential side of the multiplexer. In some cases, the voltage of the input signal of the multiplexer may be lower than the power supply voltage Vss by the threshold voltage Vthn of the NMOS transistor. As a result, the NMOS transistor that is supposed to be turned off is turned on, and a leak current flows through the NMOS transistor.

  As a result, in the multiplexer, a leak current may flow through a CMOS switch that is not selected. Further, since the leakage current is unstable, there is a problem that the output signal waveform is distorted. MOS transistors used to improve the analog characteristics of minute processes and switches in recent years tend to make the above-mentioned problem prominent because the threshold voltages Vthn and Vthp are small.

  In the MOS transistor, even when the gate-source voltage Vgs is in the off state of not less than the threshold voltage Vthn or not more than Vthp, the leakage current is not generated when the gate-source voltage Vgs is close to the threshold voltages Vthn and Vthp. May occur. This is conspicuous in a finely processed MOS transistor, which further affects the characteristics of the multiplexer.

  In order to solve this problem, a method of clamping an input signal after removing a DC component from the input signal using a capacitive element has been devised.

  For example, as a multiplexer using this method, there is a multiplexer used in a video signal processing apparatus. This multiplexer uses a technique in which a video signal is clamped using a predetermined DC voltage value only during a period of a certain reference level periodically present in the video signal in synchronization with the video signal as an input signal. ing.

  However, in the multiplexer of the above-described method, it is assumed that only the output input signal, that is, the selected video signal is clamped.

  If the unselected video signal is not clamped, the source potential of the MOS transistor in the non-selected CMOS switch becomes unstable, and the non-selected CMOS switch is turned on. As a result, there arises a problem that a leak current flows through the non-selected CMOS switch and the output signal waveform is distorted.

  In order to solve this problem, it is also conceivable to clamp an unselected video signal. However, the clamp to the video signal needs to be controlled in synchronization with a synchronization signal (for example, a horizontal synchronization signal) that is synchronized with the video signal. Therefore, the clamp circuit requires a PLL circuit having a large circuit scale. Therefore, if a clamp circuit is provided for each video signal (in other words, for each input terminal to which a video signal is input) in order to clamp an unselected video signal, the circuit becomes large.

  Accordingly, an object of the present invention is to provide a multiplexer capable of reducing distortion of an output signal waveform, and further to provide a multiplexer that suppresses an increase in size.

  The multiplexer according to the present invention includes a first input terminal that receives a first input signal via a first capacitive element, a second input terminal that receives a second input signal via a second capacitive element, An output terminal for outputting either the first or second input signal, a source connected to the first input terminal, a drain connected to the output terminal, and a control signal A first CMOS switch having a first NMOS transistor and a first PMOS transistor each including a gate, a source connected to the second input terminal, and a source connected to the output terminal A second CMOS switch having a second NMOS transistor and a second PMOS transistor each including a drain and a gate to which the control signal is input; A control circuit that generates the control signal for turning on one of the first and second CMOS switches, and when the first CMOS switch is turned on, is synchronized with the first input signal. When the first input signal is clamped at the first DC voltage value and the second CMOS switch is turned on, the first DC voltage value is synchronized with the second input signal. When conducting the first clamp circuit for clamping the second input signal and the first CMOS switch, the second input signal detected while detecting the second input signal is set to the second input signal. When the second CMOS switch is clamped to be close to a DC voltage value and the second CMOS switch is turned on, the detected first input signal is brought close to the second DC voltage value while detecting the first input signal. Yo Clan It comprises a second clamp circuit for, a.

  According to this multiplexer, the second clamp circuit clamps the input signal of the CMOS switch that is not turned on, that is, the CMOS switch on the non-selection side, close to the second DC voltage value. As a result, even if the voltage value of the input signal on the non-selection side from the CMOS switch fluctuates, the input signal can be brought close to the second DC voltage level. Stabilization can be suppressed, and distortion of the output signal waveform can be easily reduced.

  The second clamp circuit detects the second input signal when the first CMOS switch is turned on, and the second input signal detected thereby detects the second DC voltage value. When the second input signal is clamped and the second CMOS switch is turned on, the first input is decreased when the second input voltage is smaller than the second DC voltage value. The first input signal detected by detecting the signal is decreased when it is larger than the second DC voltage value, and is increased when it is smaller than the second DC voltage value. 1 input signal is clamped.

  According to this multiplexer, the second clamp circuit detects an input signal of a CMOS switch that is not turned on, that is, an unselected CMOS switch, and decreases when the detected input signal is larger than the second DC voltage value. If it is small, increase it. The second clamp circuit may be realized by a simple error amplifier such as an operational amplifier, for example, and does not require a large-scale circuit such as a PLL circuit for synchronizing with an input signal. Therefore, an increase in the size of the multiplexer can be prevented. The second DC voltage value is set so that the voltage of the input signal is not higher than the gate threshold voltage than the gate voltage of the NMOS transistor, and the voltage of the input signal is higher than the gate voltage of the PMOS transistor. It is desirable to set so that it does not become lower. As a result, the CMOS switch on the non-selection side is not turned on, and no leak current flows through the CMOS switch on the non-selection side. Therefore, the distortion of the output signal waveform caused by the non-selected side input signal can be further reduced.

  The second clamp circuit described above includes a first switch element having one end connected to the input side of the first CMOS switch, and a second switch having one end connected to the input side of the second CMOS switch. A clamping PMOS transistor having an element, a drain connected to the other ends of the first and second switch elements, and a source connected to a power supply on the high potential side, and a drain and a low potential side of the clamping PMOS transistor A current source connected between the power source of the first power source, a negative input terminal to which the second DC voltage value is input, a positive input terminal connected to the drain of the clamping PMOS transistor, and a gate of the clamping PMOS transistor And an error amplifier having a connected output terminal, the second switch element when the first CMOS switch is made conductive It is turned on, when to conduct a second CMOS switch, the first switch element to the ON state.

  According to this configuration, the clamping PMOS transistor, the current source, and the error amplifier form a feedback loop, so that the drain voltage of the clamping PMOS transistor, that is, the input signal on the non-selection side is the second DC voltage value. To be stabilized.

  The second clamp circuit described above includes a first switch element having one end connected to the input side of the first CMOS switch, and a second switch having one end connected to the input side of the second CMOS switch. A clamping NMOS transistor having an element, a gate connected to the other ends of the first and second switching elements, and a source connected to a power supply on a low potential side; a drain and a high potential side of the clamping NMOS transistor; A resistor connected between the power supply, an amplifier having an input terminal connected to the drain of the clamping NMOS transistor, a gate connected to the output terminal of the amplifier, and a power supply on the high potential side A clamping PMOS transistor having a source and a drain connected to the gate of the clamping NMOS transistor; and a clamping PM A current source connected between the drain of the S transistor and the power supply on the low potential side, and when the first CMOS switch is turned on, the second switch element is turned on, and the second CMOS switch Is turned on, the first switch element is turned on.

  According to this configuration, the clamping NMOS transistor, the resistance element, the amplifier, the clamping PMOS transistor, and the current source form a feedback loop, so that the drain voltage of the clamping PMOS transistor, that is, the non-selection side The input signal is stabilized at the gate threshold voltage of the clamping NMOS transistor.

  ADVANTAGE OF THE INVENTION According to this invention, distortion of an output signal waveform can be reduced, suppressing the enlargement of a multiplexer.

DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.
[First Embodiment]

  FIG. 1 is a circuit diagram showing a multiplexer according to the first embodiment. FIG. 2 is a diagram showing signals at various parts of the multiplexer shown in FIG. FIG. 1 shows a multiplexer used in a video signal processing apparatus as an embodiment of the multiplexer.

The multiplexer 1, via a first capacitive element _{2 1,} receiving a first input signal Vin to <1>, excluding the DC component from the first video signal Vvideo <1> to the first input terminal _{3 1} . Further, the multiplexer 1, via a second capacitive element _{2 2,} the second input signal Vin <2> to the second input terminal _{3 2} excluding the DC component from the second video signal Vvideo <2> receive. The multiplexer 1 selectively outputs one of the first and second input signals Vin <1> and Vin <2> to the output terminal 4 as the output signal Vout.

Multiplexer 1 includes a first CMOS switch 10 _1, a second CMOS switches 10 _2, and the control circuit 20, and a first clamp circuit 30, and a second clamp circuit 40. Details of these configurations will be described below.

First CMOS switch 10 ₁ is connected in series between the first input terminal _{3 1} and the output terminal 4, a first NMOS transistor 11 ₁ and the first PMOS transistor connected in parallel 12 ₁ .

The first NMOS transistor 11 ₁ has a source connected to the first input terminal 3 _1, the drain is connected to the output terminal 4. The first gate of the NMOS transistor 11 _1, the control signal SEL <1> is inputted. Meanwhile, the first PMOS transistor 12 ₁ has a source connected to the first input terminal 3 _1, the drain is connected to the output terminal 4. The first PMOS transistor 12 ₁ of the gate control signal XSEL <1> is inputted. These, and the first NMOS transistor 11 _1, a first PMOS transistor 12 _1, it is conductive when the same by the control signal to be described later, and outputs the <1> a first input signal Vin.

Likewise, the second CMOS switch 10 ₂ is connected in series between the second input terminal _{3 2} and the output terminal 4, the second NMOS transistor 11 ₂ and the second connected in parallel and a PMOS transistor 12 _2.

Second NMOS transistor 11 ₂ has a source connected to the second input terminal 3 _2, the drain is connected to the output terminal 4. The second gate of the NMOS transistor 11 _2, the control signal SEL <2> is entered. On the other hand, the second PMOS transistor 12 ₂ has a source connected to the second input terminal 3 _2, the drain is connected to the output terminal 4. The second PMOS transistor 12 and _second gate control signals XSEL <2> is entered. Similar to the first CMOS switch 10 _{1, 2} and the second NMOS transistor 11, and the second PMOS transistor 12 _2, is conductive when the same by the control signal to be described later, the second input signal Vin <2> Is output.

These control signals SEL <1>, XSEL <1>, SEL <2>, and XSEL <2> are generated by the control circuit 20. The control circuit 20 selects one of the first and second input signals Vin <1> and Vin <2> to output the selected one of the first and second CMOS switches 10 ₁ and 10 ₂ . Control signals SEL <1>, XSEL <1>, SEL <2>, and XSEL <2> are generated so that any one of them is made conductive.

Specifically, when the first input signal Vin <1> is selectively output, the control circuit 20 generates the control signals SEL <1> and XSEL <2> having the power supply voltage Vdd on the high potential side. At the same time, control signals XSEL <1> and SEL <2> having the power supply voltage Vss on the low potential side are generated. Accordingly, the first NMOS transistor 11 ₁ and the first PMOS transistor 12 ₁ is turned on, the first CMOS switch 10 ₁ is conductive. Further, the second NMOS transistor 11 ₂ and the second PMOS transistor 12 ₂ is turned off, the second CMOS switch 10 ₂ is non-conductive.

On the other hand, when the second input signal Vin <2> is selectively output, the control circuit 20 generates the control signals SEL <2> and XSEL <1> having the power supply voltage Vdd on the high potential side, Control signals XSEL <2> and SEL <1> having the power supply voltage Vss on the potential side are generated. Thus, the second NMOS transistor 11 ₂ and the second PMOS transistor 12 ₂ is turned on, the second CMOS switch 10 ₂ is conducting. The first NMOS transistor 11 ₁ and the first PMOS transistor 12 ₁ is turned off, the first CMOS switch 10 ₁ becomes nonconductive.

  As described above, the multiplexer 1 in this embodiment includes the first clamp circuit 30 and the second clamp circuit 40.

  First, the first clamp circuit 30 will be described. The first clamp circuit 30 selects and outputs the first input signal Vin <1> in synchronization with the first input signal Vin <1> when the first input signal Vin <1> is selectively output. Is clamped by the first DC voltage value Vclp1. On the other hand, when the second input signal Vin <2> is selectively output, the first clamp circuit 30 synchronizes with the second input signal Vin <2> to select the second input signal Vin on the selection side. Clamp <2>.

The first clamp circuit 30 includes switch elements 31 ₁ and 31 ₂ , a clamp timing generation circuit 32, a first clamp signal generation circuit 33, and switch elements 34 ₁ and 34 ₂ .

Clamp timing generating circuit 32, together with the first synchronizing signal SYNC undergo <1> through the switch element 31 _1, receives the second sync signal SYNC <2> via a switch element 31 _2. The first and second synchronization signals SYNC <1> and SYNC <2> are synchronization signals corresponding to the first and second video signals Vvideo <1> and Vvideo <2>, respectively. The switch elements 31 ₁ and 31 ₂ are turned on in response to the control signals SEL <1> and SEL <2>, respectively.

  When the clamp timing generation circuit 32 selects and outputs the first input signal Vin <1>, the clamp timing signal synchronized with the first video signal Vvideo <1> from the first synchronization signal SYNC <1>. CLPTIM is generated and supplied to the first clamp signal generation circuit 33.

  On the other hand, when the second input signal Vin <2> is selected and output, the clamp timing generation circuit 32 performs clamping in synchronization with the second video signal Vvideo <2> from the second synchronization signal SYNC <2>. A timing signal CLPTIM is generated and supplied to the first clamp signal generation circuit 33.

As shown in FIG. 2 (a), the video signal Vvideo, a period of time which is the reference level _{V 1} is periodically present. As shown in FIG. 2D, the clamp timing generation circuit 32 generates a pulsed clamp timing signal CLPTIM corresponding to this period.

First clamp signal generating circuit 33, in response to a clamp timing signal CLPTIM from the clamp timing generating circuit 32, a capacitor _{2 1} or _{2 2} by the first or second input signal Vin DC component has been removed <1 >, Vin <2> is clamped at the first DC voltage value Vclp1. Specifically, as illustrated in FIG. 2C, the first clamp signal generation circuit 33 is configured to input the first or second input signal Vin <1>, Vin at the timing when the clamp timing signal CLPTIM is input. <2> is clamped with the first DC voltage value Vclp1.

  By adjusting the first DC voltage value Vclp1, the voltage of the input signal after AC coupling can be set to an appropriate range, and the NMOS transistor and the PMOS transistor in the selected CMOS switch are appropriately turned on. Further, a circuit provided in the subsequent stage of the multiplexer 1 can receive an output signal (that is, an input signal) at an appropriate level.

Output terminals of the first clamp signal generating circuit 33, switching element 34 ₁ first is connected to the input side of the CMOS switches 10 ₁ through a second CMOS switch through the switching element 34 ₂ 10 ₂ Is connected to the input side. The switch elements 34 ₁ and 34 ₂ are turned on in response to the control signals SEL <1> and SEL <2>, respectively. Thus, switching element 34 ₁ is turned on in the case where the selected output <1> a first input signal Vin. On the other hand, the switching element 34 ₂ is turned on in the case where the selected output the second input signal Vin <2>.

In this way, as shown in FIG. 2 (b), the input signal Vin is a constant reference level _{V 1} is a period in the video signal Vvideo, and thus is clamped to the first DC voltage value Vclp1.

Next, the second clamp circuit 40 will be described. When the first input signal Vin <1> is selectively output, the second clamp circuit 40 clamps the non-selected second input signal Vin <2> with the second DC voltage value Vclp2. The second clamp circuit 40 clamps the first input signal Vin <1> on the non-selection side with the second DC voltage value Vclp2 when the second input signal Vin <2> is selectively output. . That is, the second clamp circuit 40 clamps the input signal on the opposite side clamped by the first clamp circuit 30. The second clamp circuit 40 includes first and second switch elements 41 ₁ and 41 ₂ and a second clamp signal generation circuit 42.

The first end of the switch element 41 ₁ is connected to a first input of the CMOS switch 10 _1, the other end is connected to the second clamp signal generating circuit 42. First switching element 41 ₁ is turned on in response to the control signal XSEL <1>. That is, the first switching element 41 _1, in the case where the selected output the second input signal Vin <2>, i.e., turned on when to conduct a second CMOS switch 10 _2.

Second end of the switching element 41 ₂ is connected to a second input of the CMOS switch 10 ₂ and the other end is connected to the second clamp signal generating circuit 42. The second switching element 41 ₂ is turned on in response to the control signal XSEL <2>. That is, the second switching element 41 _2, in the case where the selected output <1> a first input signal Vin, i.e., turned on when to conduct first the CMOS switch 10 _1.

  The second clamp signal generation circuit 42 clamps the unselected input signal with the second DC voltage value Vclp2.

  FIG. 3 is a circuit diagram of a clamp signal generation circuit in the second clamp circuit shown in FIG. The clamp signal generation circuit 42 shown in FIG. 3 includes a clamping PMOS transistor 43, an error amplifier 44, and a current source 45.

The drain of the clamping PMOS transistor 43 is connected to the other ends of the first and second switch elements 41 ₁ and 41 ₂ , and the source is connected to the power source Vdd on the high potential side. The gate of the clamping PMOS transistor 43 is connected to the output terminal of the error amplifier 44.

  The second DC voltage value Vclp2 is input to the minus input terminal of the error amplifier 44, and the plus input terminal is connected to the drain of the clamping PMOS transistor 43.

  A current source 45 is connected between the drain of the clamping PMOS transistor 43 and the power source Vss on the low potential side.

  That is, in the second clamp signal generation circuit 42, the clamping PMOS transistor 43, the current source 45, and the error amplifier 44 form a feedback loop, and the voltage of the drain of the clamping PMOS transistor 43 is set to the second voltage. The DC voltage value Vclp2 is stabilized.

  Next, the effects of the multiplexer 1 of this embodiment will be described in comparison with the multiplexer 1X of the comparative example.

  First, the multiplexer 1X of the comparative example will be described. FIG. 4 is a circuit diagram showing a multiplexer of a comparative example. A multiplexer 1X shown in FIG. 4 is different from the first embodiment of the present invention in that the multiplexer 1 does not include the second clamp circuit 40. The other configuration of the multiplexer 1X is the same as that of the multiplexer 1.

For example, when the second input signal Vin <2> is selectively output, the selected second input signal Vin <2> is clamped by the first clamp circuit 30 but not selected. <1> is not clamped. Then, the potential first CMOS switch 10 of _the input terminal becomes high impedance becomes unstable.

Thus, the first input signal Vin voltage <1> becomes possible there is higher than the gate threshold voltage Vthp than the first gate voltage Vdd of the PMOS transistor 12 _1. As a result, the first PMOS transistor 12 ₁ is desired to the original OFF state is turned on, thereby a leak current flows to the first PMOS transistor 12 _1.

The first input signal Vin voltage <1> becomes possible is low than the gate threshold voltage Vthn than the first gate voltage Vss of the NMOS transistor 11 _1. As a result, the first NMOS transistor 11 ₁ is desired to the OFF state is turned on, thereby a leak current flows to the first NMOS transistor 11 _1.

As a result, the second leakage current to the CMOS switch 10 ₁ flows not selected, due to the non-selected first side of the input signal Vin <1>, is the output signal waveform is distorted.

FIG. 5 shows an example of a distorted output signal waveform. First and second video signals Vvideo <1> and Vvideo as shown in FIGS. 5A and 5B are sent to the multiplexer 1X via the first and second capacitive elements 2 ₁ and 2 ₂ . When <2> is input, the first input signal Vin <1> is not clamped, DC level becomes unstable, for example, as shown in FIG. 5 (c), the first PMOS transistor 12 ₁ The gate voltage Vdd may be higher than the gate voltage Vdd. As a result, the first PMOS transistor 12 ₁ becomes the ON state, thereby a leak current flows to the first CMOS switch 10 _1. As a result, as shown in FIG. 5D, the output signal waveform is clamped after the DC component is originally removed from the second video signal Vvideo <2> shown in FIG. The waveform of the output signal Vout is distorted due to the signal Vin <1>.

  As a solution to this problem, each input signal may be clamped, but the clamp timing generation circuit 32 is configured using a PLL circuit or the like because it is necessary to generate a timing signal based on the synchronization signal SYNC. . Since the circuit scale of the PLL circuit is relatively large, if a clamp timing generation circuit is arranged for each input signal, the circuit scale becomes very large. Further, since the first clamp circuit 30 is also composed of an analog circuit, the circuit scale is relatively large. For this reason, the multiplexer becomes large.

Therefore, in the multiplexer 1 of the first embodiment, the input signal on the non-selection side is clamped by the second clamp circuit 40. For example, a case where the second input signal Vin <2> is selectively output as described above will be described. In this case, the first switching element 41 ₁ is turned on, the second switching element 41 ₂ is turned off.

When the first input signal Vin <1> on the non-selection side rises, the output voltage of the error amplifier 44, that is, the gate voltage of the clamping PMOS transistor 43 rises and flows between the drain and source of the clamping PMOS transistor 43. The current decreases. Then, the current source 45 draws current from the input side of the multiplexer 1 to the power source Vss on the low potential side. As a result, the voltage of the first CMOS switch 10 of _the input terminal is stabilized to a second DC voltage value Vclp2. This can first input signal Vin voltage <1> is suppressed so as not gate threshold voltage Vthp or more higher than the first gate voltage Vdd of the PMOS transistor 12 _1.

On the other hand, when the first input signal Vin <1> on the non-selection side decreases, the output voltage of the error amplifier 44, that is, the gate voltage of the clamping PMOS transistor 43 decreases, and the drain-source region of the clamping PMOS transistor 43 falls. The current that flows through increases. Then, a current flows from the clamping PMOS transistor 43 to the input side of the multiplexer 1. As a result, the voltage of the first CMOS switch 10 of _the input terminal is stabilized to a second DC voltage value Vclp2. This can first input signal Vin voltage <1> is suppressed so as not gate threshold voltage Vthn or more lower than the first gate voltage Vss of the NMOS transistor 11 _1.

  Here, in the multiplexer 1, when the input signal falls below the second DC voltage value Vclp2, it is necessary to return to an appropriate voltage relatively quickly. On the other hand, when the input signal rises, it is necessary to prevent the data in the second input signal Vin <2> from being lost suddenly. The multiplexer 1 of the first embodiment is preferably applicable to this type of video signal processing apparatus. This point will be described in detail with reference to FIG.

The multiplexer 1 of the first embodiment, by adjusting the size of the clamping PMOS transistor 43, it is possible to set a large capacity to raise the voltage of the first CMOS switch 10 of _the input terminal. As a result, as shown in FIG. 6, when the input signal Vin is decreased, it is possible to raise the voltage of the short time the first CMOS switch 10 of _the input end to the second DC voltage value Vclp2.

On the other hand, in the multiplexer 1 of the first embodiment, the current value of the current source 45 is set to a value larger than the parasitic leakage of the device. By setting larger than the parasitic leakage current of the current source 45 device, as shown in FIG. 6, so that the voltage value of the first CMOS switch 10 of _the input terminal is reliably pulled in the desired direction be able to. Note that the current value of the current source 45 be operated at all times the circuit, the voltage of the first CMOS switch 10 of _the input terminal is pulled to abruptly supply Vss on the low potential side in one cycle period of the input signal It is desirable to have a value that can be avoided.

  Thus, according to the multiplexer 1 of the first embodiment, the second clamp circuit 40 clamps the input signal of the CMOS switch that is not turned on, that is, the non-selected CMOS switch. It can be suppressed so as not to be higher than the gate threshold voltage than the gate voltage of the NMOS transistor and not lower than the gate threshold voltage than that of the PMOS transistor. As a result, the CMOS switch on the non-selection side is not turned on, and no leak current flows through the CMOS switch on the non-selection side. Therefore, distortion of the output signal waveform due to the input signal on the non-selection side can be reduced.

Further, according to the multiplexer 1 of the first embodiment, the second clamp circuit 40 only has to control the input signal to be close to the DC voltage value by comparing the input signal and the DC voltage value. A circuit having a large circuit size such as a PLL circuit for synchronizing with a signal is not required. Therefore, enlargement can be suppressed.
[Second Embodiment]

  A multiplexer 1A according to the second embodiment of the present invention is different from the first embodiment in that the multiplexer 1 shown in FIG. 1 includes a second clamp circuit 40A instead of the second clamp circuit 30. . The other configuration of the multiplexer 1A is the same as that of the multiplexer 1.

  The second clamp circuit 40A is different from the second clamp circuit 40 in that the second clamp circuit 40 includes a clamp signal generation circuit 42A instead of the clamp signal generation circuit 42. Other configurations of the second clamp circuit 40A are the same as those of the second clamp circuit 40.

  FIG. 7 is a circuit diagram of a clamp signal generation circuit according to the second embodiment. The clamp signal generation circuit 42A shown in FIG. 7 includes a clamping NMOS transistor 46, a resistance element 47, and an amplifier 48 instead of the error amplifier 44.

The clamp NMOS transistor 46 has its gate connected to the other ends of the first and second switch elements 41 ₁ and 41 ₂ , and its source connected to the low-power-side power supply Vss. The drain of the clamping NMOS transistor 46 is connected to the power source Vdd on the high potential side via the resistance element 47 and also connected to the input terminal of the amplifier 48. The output terminal of the amplifier 48 is connected to the gate of the clamping PMOS transistor 43.

  The source of the clamping PMOS transistor 43 is connected to the power supply Vdd on the high potential side, and the drain is connected to the gate of the NMOS transistor 46 for clamping. A current source 45 is connected between the drain of the clamping PMOS transistor 43 and the low-potential-side power supply Vss.

  That is, in the second clamp signal generation circuit 42A, the clamp NMOS transistor 46, the resistor element 47, the amplifier 48, the clamp PMOS transistor 43, and the current source 45 form a feedback loop, and the clamp The drain voltage of the PMOS transistor 43 is stabilized at the threshold voltage Vth of the clamping NMOS transistor 46 (assuming that the resistance element 47 has a sufficiently large resistance value) (however, the resistance value of the resistance element 47 is small). (It depends on the resistance value and the characteristics of the transistor 46).

For example, a case where the second input signal Vin <2> is selectively output as described above will be described. In this case, the first switching element 41 ₁ is turned on, the second switching element 41 ₂ is turned off.

  When the first input signal Vin <1> on the non-selection side, that is, the gate voltage of the clamping NMOS transistor 46 rises, the drain-source current of the clamping NMOS transistor 46 increases, and the voltage drop amount of the resistance element 47, That is, the input voltage of the amplifier 48 is lowered.

Then, the output voltage of the amplifier 48, that is, the gate voltage of the clamping PMOS transistor 43 increases, and the source-drain current of the clamping PMOS transistor 43 decreases. Then, the current source 45 draws current from the input side of the multiplexer 1 to the power source Vss on the low potential side. As a result, the drain voltage of the clamping PMOS transistor 43 is stabilized at the threshold voltage Vth of the clamping NMOS transistor 46 (this is referred to as the second DC voltage value Vclp2). This can first input signal Vin voltage <1> is suppressed so as not gate threshold voltage Vthp or more higher than the first gate voltage Vdd of the PMOS transistor 12 _1.

On the other hand, when the first input signal Vin <1> on the non-selection side, that is, the gate voltage of the clamping NMOS transistor 46 is lowered, the drain-source current of the clamping NMOS transistor 46 is reduced, and the voltage drop of the resistance element 47 The quantity, that is, the input voltage of the amplifier 48 increases. Then, the output voltage of the amplifier 48, that is, the gate voltage of the clamping PMOS transistor 43 decreases, and the source-drain current of the clamping PMOS transistor 43 increases. Then, a current flows from the clamping PMOS transistor 43 to the input side of the multiplexer 1. As a result, the drain voltage of the clamping PMOS transistor 43 is stabilized at the threshold voltage Vth of the clamping NMOS transistor 46 (this is referred to as the second DC voltage value Vclp2). This can first input signal Vin voltage <1> is suppressed so as not gate threshold voltage Vthn or more lower than the first gate voltage Vss of the NMOS transistor 11 _1.

  As described above, the multiplexer 1A of the second embodiment can obtain the same advantages as those of the first embodiment.

The present invention is not limited to the above-described embodiment, and various modifications can be made. As shown in FIG. 8, the multiplexer of this embodiment may be configured to selectively output any one of three or more input signals Vin <1> to Vin <n>. The multiplexer 1B according to this modification includes first to nth CMOS switches 10 _{1 to} 10n. The first to nth CMOS switches 10 _{1 to} 10n have first to nth input signals, respectively. Vin <1> to Vin <n> are input. The first to nth input signals Vin <1> to Vin <n> are input through the first to nth capacitive elements 21 and 2n, respectively. This is a signal obtained by removing a DC component from the signals Vvideo <1> and Vvideo <n>.

A first clamp circuit 30B is connected to the input sides of the _first to nth CMOS switches 10 _{1 to} 10n. The first clamp circuit 30 </ b> B includes n switch elements 31 ₁ to 31 n before the clamp timing generation circuit 32 in the first clamp circuit 30, and n pieces after the first clamp signal generation circuit 33. The switch elements 41 ₁ to 41 n are different from the first clamp circuit 30. The first clamp circuit 30B clamps the selected input signal in synchronization with the input signal selected from the first to nth input signals Vin <1> to Vin <n>.

The 2 _1st to 2nth clamp circuits 40 _{1 to} 40n are connected to the input sides of the _1st to nth CMOS switches 10 _{1 to} 10n. The second _1st to 2n clamp circuits 40 _{1 to} 40n are configured to include switch elements 41 _{1 to} 41n in the second clamp circuit 40 at the subsequent stage of the second clamp signal generation circuit 42, respectively. Different from the circuit 40. The 2 _1st to 2nth clamp circuits 40 _{1 to} 40n are respectively selected when the corresponding input signal of the 1st to nth input signals Vin <1> to Vin <n> is not selected. The corresponding input signal is clamped to the DC voltage value Vclp2.

Also in the multiplexer 1B of this modified example, since the unselected input signals are clamped by the 2 _1st to 2nth clamp circuits 40 _{1 to} 40n, the leakage current is prevented from flowing to the non-selected side CMOS switch. And distortion of the output signal waveform due to the input signal on the non-selection side can be reduced.

Also in the multiplexer 1B of this modification, the 2 _1st to 2nth clamp circuits 40 _{1 to} 40n only control the input signal to be close to the DC voltage value Vclp2, so that the input signal is synchronized. A circuit with a large circuit size such as a PLL circuit is not required. Therefore, an increase in size can be prevented.

  The multiplexer of the present invention is not limited to the video signal processing device, and can be applied to various devices.

1 is a circuit diagram showing a multiplexer according to a first embodiment of the present invention. It is a figure which shows each part signal of the multiplexer shown in FIG. FIG. 3 is a circuit diagram of a second clamp signal generation circuit in the second clamp circuit shown in FIG. 1. It is a circuit diagram which shows the multiplexer of a comparative example. An example of the distorted output signal waveform is shown. It is a figure which shows stabilization of the 2nd DC voltage value by a 2nd clamp circuit. FIG. 6 shows a circuit diagram of a second clamp signal generation circuit in the second clamp circuit of the multiplexer according to the second embodiment of the present invention. It is a circuit diagram which shows the multiplexer of the modification of this invention.

Explanation of symbols

1, 1A ... multiplexer, _{2 1,} 2 2 _... first and second capacitive elements, _{3 1,} 3 2 _... first and second input terminals, 4 ... output terminal, ₁₀ 1, 10 2 _... first and Second CMOS switch, 11 ₁ , 11 ₂ ... First and second NMOS transistors, 12 ₁ , 12 ₂ ... First and second PMPS transistors, 20... Control circuit, 30. ₁ , 31 ₂ , 34 ₁ , 34 ₂ ... Switch element, 32... Clamp timing generation circuit, 33... First clamp signal generation circuit, 40, 40 A. second clamp circuit, 41 ₁ , 41 ₂ . 2nd switch element, 42, 42A ... 2nd clamp signal generation circuit, 43 ... PMOS transistor for clamping, 44 ... Error amplifier, 45 ... Current source, 46 ... NMOS transistor for clamping , 47 ... resistance element, 48 ... amplifier.

Claims (4)

A first input terminal that receives a first input signal via a first capacitive element; a second input terminal that receives a second input signal via a second capacitive element; and the first or second And an output terminal that outputs any one of the input signals,
A first NMOS transistor and a first PMOS transistor each including a source connected to the first input terminal, a drain connected to the output terminal, and a gate to which a control signal is input. CMOS switch of
A second NMOS transistor and a second PMOS transistor each including a source connected to the second input terminal, a drain connected to the output terminal, and a gate to which the control signal is input. Two CMOS switches;
A control circuit for generating the control signal for conducting one of the first and second CMOS switches;
When conducting the first CMOS switch, clamping the first input signal at a first DC voltage value in synchronization with the first input signal and conducting the second CMOS switch Includes a first clamp circuit that clamps the second input signal with the first DC voltage value in synchronization with the second input signal;
When conducting the first CMOS switch, the second input signal detected while detecting the second input signal is clamped so as to approach a second DC voltage value, and the second CMOS switch A second clamp circuit that clamps the detected first input signal close to the second DC voltage value while detecting the first input signal;
A multiplexer comprising: The second clamp circuit includes:
When the first CMOS switch is turned on, the second input signal is detected, and when the second input signal detected thereby is larger than the second DC voltage value, the first CMOS switch is decreased. When it is smaller than the second DC voltage value, the second input signal is clamped by this, and when the second CMOS switch is made conductive, the first input signal is detected, The first input signal thus detected is decreased when it is larger than the second DC voltage value, and is increased when it is smaller than the second DC voltage value, thereby increasing the first input signal. The multiplexer of claim 1 for clamping a signal. The second clamp circuit includes:
A first switch element having one end connected to the input side of the first CMOS switch;
A second switch element having one end connected to the input side of the second CMOS switch;
A clamping PMOS transistor having a drain connected to the other ends of the first and second switch elements, and a source connected to a power source on the high potential side;
A current source connected between the drain of the clamping PMOS transistor and a power source on the low potential side;
An error amplifier having a negative input terminal to which the second DC voltage value is input, a positive input terminal connected to the drain of the clamping PMOS transistor, and an output terminal connected to the gate of the clamping PMOS transistor When,
With
When conducting the first CMOS switch, the second switch element is turned on,
When conducting the second CMOS switch, the first switch element is turned on.
The multiplexer according to claim 1 or 2. The second clamp circuit includes:
A first switch element having one end connected to the input side of the first CMOS switch;
A second switch element having one end connected to the input side of the second CMOS switch;
A clamping NMOS transistor having a gate connected to the other ends of the first and second switch elements, and a source connected to a power source on a low potential side;
A resistance element connected between the drain of the NMOS transistor for clamping and the power supply on the high potential side;
An amplifier having an input terminal connected to the drain of the clamping NMOS transistor;
A clamping PMOS transistor having a gate connected to the output terminal of the amplifier, a source connected to the power supply on the high potential side, and a drain connected to the gate of the clamping NMOS transistor;
A current source connected between the drain of the clamping PMOS transistor and the power source on the low potential side;
With
When conducting the first CMOS switch, the second switch element is turned on,
When conducting the second CMOS switch, the first switch element is turned on.
The multiplexer according to claim 1 or 2.

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