JP2009183017A - Active gate circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable not only the suppression of the overvoltage of a collector and an emitter at turn on of the semiconductor switching element of its own arm but also the suppression of the overvoltage of the recovery voltage of the reflux diode of the semiconductor switching element of the other arm. <P>SOLUTION: The recovery overvoltage suppressing means 16a of an active gate circuit 12a regulates the gate current of the semiconductor switching element S1 of one arm, so as to suppress the overvoltage of the recovery voltage of the reflux diode D2 of the other arm, at turn on of the semiconductor switching element S1 of one arm out of a pair of arms that form the leg of a power converter. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active gate circuit that applies a gate current so as to suppress an increase in a collector-emitter voltage of a semiconductor switching element of a power converter.

  In order to prevent an overvoltage from being applied to the semiconductor switching element when the semiconductor switching element of the power converter is turned on / off, active gate control for adjusting the gate voltage / current of the semiconductor switching element is performed instead of the snubber circuit. As active gate control of the power converter, when the semiconductor switching element is turned on and off, the gate voltage and current are adjusted by the collector-emitter voltage of the semiconductor switching element, and the overvoltage of the collector-emitter voltage is suppressed in series. There is one in which voltage sharing between semiconductor switching elements is equalized (for example, see Non-Patent Document 1).

  In addition, a current source connected to the gate circuit side is used to adjust the gate voltage and current, and when the semiconductor switching element is turned off, the voltage rise rate between the collector and emitter is moderated and applied between the collector and emitter. There is one that suppresses the peak value of high voltage and minimizes the increase in collector loss (see, for example, Patent Document 1).

  FIG. 13 is a block diagram showing an example of a conventional active gate circuit when the power converter is a half-bridge inverter circuit. In the half-bridge inverter circuit, each of a pair of arms forming a leg is formed of semiconductor switching elements S1 and S2 in which free-wheeling diodes D1 and D2 are connected in antiparallel, and the two semiconductor switching elements S1 and S2 are turned on and off. The direct current of the direct current power sources E1 and E2 is converted into alternating current, and electric power is supplied to the alternating current load Zload via the reactors Ldc1 and Ldc2. The magnitudes of the voltages of the DC power supplies E1 and E2 are equal (E1 = E2).

  The semiconductor switching elements S1, S2 are on / off controlled by gate signals Gate1, Gate2 from the gate drive circuits 10a, 10b. The gate drive circuits 10a and 10b generate gate voltages Vge1 and Vge2 by the gate power supplies 11a and 11b by the gate signals Gate1 and Gate2, respectively, and the gate voltages Vge1 and Vge2 are supplied to the gate resistances Rg1 and Rg2 as absolute values of gate current command values. Get. The semiconductor switching elements S1 and S2 are controlled by the gate currents Ig1 and Ig2 in consideration of the gate compensation currents ΔIg1 and ΔIg2 from the active gate circuits 12a and 12b.

  The active gate circuits 12a and 12b are provided in the semiconductor switching elements S1 and S2, respectively. The active gate circuit 12a detects the collector-emitter voltage Vce1 of the semiconductor switching element S1, and calculates a correction signal for preventing the collector-emitter voltage Vce1 from becoming an overvoltage by the collector-emitter overvoltage suppression means 13a. Then, the current conversion means 14a converts the current into a current and outputs the gate compensation current ΔIg1 to the subtraction means (not shown). As a result, the gate compensation current ΔIg1 is subtracted from the absolute value of the gate current command value from the gate drive circuit 10a, and the gate current Ig1 is output to the semiconductor switching element S1. However, in detecting the collector-emitter voltages Vce1 and Vce2, voltage information is also obtained from the emitter side, but it is omitted in the figure. Hereinafter, the same applies to other drawings.

  Similarly to the active gate circuit 12a, the active gate circuit 12b detects the collector-emitter voltage Vce2 of the semiconductor switching element S2, and the collector-emitter overvoltage suppression means 13b prevents the collector-emitter voltage Vce2 from becoming an overvoltage. A correction signal for the calculation is calculated and converted into a current by the current conversion means 14b to output a gate compensation current ΔIg2. Thereby, the gate compensation current ΔIg2 is subtracted from the absolute value of the gate current command value from the gate drive circuit 10b by a subtracting means (not shown), and the gate current Ig2 is output to the semiconductor switching element S2. In FIG. 13, Iload is the load current of the AC load Zload, Is1 is the element current of the semiconductor switching element S1, Is2 is the element current of the semiconductor switching element S2, Id1 is the return diode current of the return diode D1, and Id2 is the return diode D2. Of the reflux current.

  In addition, there is a type in which the switching speed is controlled according to the collector current value by detecting not only the collector-emitter voltage but also the collector current (see, for example, Patent Document 2).

  FIG. 14 is a block diagram showing another example of a conventional active gate circuit when the power converter is a half-bridge inverter circuit. It is intended to suppress not only the overvoltage of the collector-emitter voltage but also the temporal change of the collector current.

The active gate circuits 12a and 12b are provided in the semiconductor switching elements S1 and S2, respectively. The active gate circuits 12a and 12b detect the collector-emitter voltages Vce1 and Vce2 and the collector currents Ic1 and Ic2 of the semiconductor switching elements S1 and S2. To do. The collector-emitter overvoltage suppression means 13a, 13b calculates a correction signal for preventing the collector-emitter voltages Vce1, Vce2 from becoming an overvoltage, and the collector-emitter overvoltage suppression means 15a, 15b calculates the collector currents Ic1, Ic2. A correction signal for suppressing a temporal change is calculated. Then, the current conversion means 14a, 14b converts these correction signals into currents and outputs gate compensation currents ΔIg1, ΔIg2. As a result, the gate compensation currents ΔIg1 and ΔIg2 are subtracted from the absolute value of the gate current command value from the gate drive circuits 10a and 10b by a subtracting unit (not shown), and the gate currents Ig1 and Ig2 are output to the semiconductor switching elements S1 and S2. The
R & D News Kansai, 2002.5.408, pages 30-31, published by Kansai Electric Power Co., Inc. Japanese Patent No. 3569192 Japanese Patent No. 3141613

  However, in Patent Documents 1 and 2, although the overvoltage of the collector-emitter voltage can be suppressed, the recovery voltage of the freewheeling diode cannot be controlled. This is because the active gate circuit suppresses overvoltage of the collector-emitter voltage based on the collector-emitter voltage and collector current of its own semiconductor switching element, and reverses to the other semiconductor switching element connected in series. This is because the control taking into account the current flowing through the parallel freewheeling diodes and the recovery voltage is not performed. A surge voltage is generated in its own semiconductor switching element due to the recovery voltage of the freewheeling diode that is anti-parallel to the other semiconductor switching element.

  FIG. 15 is a signal waveform diagram of each part when the semiconductor switching elements S1 and S2 of the half-bridge inverter circuit are turned on and off in a short period. The gate signals Gate1 and Gate2 to the semiconductor switching elements S1 and S2 of the half-bridge inverter circuit are signals that are turned on and off. That is, when the gate signal Gate1 to the semiconductor switching element S1 is on, the gate signal Gate2 to the semiconductor switching element S2 is off, and when the gate signal Gate1 to the semiconductor switching element S1 is off, to the semiconductor switching element S2. The gate signal Gate2 is on.

  From the state where the gate signal Gate1 to the semiconductor switching element S1 is on and the gate signal Gate2 to the semiconductor switching element S2 is off, the gate signal Gate1 to the semiconductor switching element S1 is off and the semiconductor switching element S2 at time t1. The gate signal Gate2 is switched on, and further, after a time point t2, a forward current flows through the freewheeling diode D2 and the semiconductor switching element S2 does not turn on even if the gate signal Gate2 to the semiconductor switching element S2 is on. Assume that the gate signal Gate1 to the semiconductor switching element S1 is turned on and the gate signal Gate2 to the semiconductor switching element S2 is turned off at the time point t3 of the state.

  At time t1, since the gate signal Gate1 to the semiconductor switching element S1 is off and the gate signal Gate2 to the semiconductor switching element S2 is turned on, the element current Is1 of the semiconductor switching element S1 starts to decrease, and the semiconductor switching element S2 returns. A current is commutated to the diode D2, and a forward return current Id2 flows. As a result, the load voltage Vload of the AC load Zload changes from positive to negative, and the load current ILoad of the AC load Zload hardly changes. However, in the off-transition period of the semiconductor switching element S1 from time t1 to time t2, the semiconductor switching element A surge voltage is generated in the collector-emitter voltage Vce1 of S1.

  On the other hand, at the time t3 when the semiconductor switching element S2 is not turned on even when the gate signal Gate2 to the semiconductor switching element S2 is turned on (the return current Id2 flows through the return diode D2), the signal to the semiconductor switching element S1 is turned on. When the gate signal Gate1 is turned on and the gate signal Gate2 to the semiconductor switching element S2 is switched off, the current starts to decrease in the freewheeling diode D2, and commutates to the semiconductor switching element S1 and the element current Is1 begins to flow. At this time, a surge voltage is generated in the collector-emitter voltage Vce2 of the semiconductor switching element S2 during the off-transition period of the return diode D2 from the time point t3 to the time point t4.

  In Patent Documents 1 and 2, the surge voltage of the collector-emitter voltage Vce1 of the semiconductor switching element S1 during the off-transition period of its own semiconductor switching element S1 from time t1 to time t2 can be suppressed, but at time t3 From the time point t4, it is impossible to suppress the surge voltage of the collector-emitter voltage Vce2 of the other semiconductor switching element S2 during the off-transition period of the free-wheeling diode D2 of the other semiconductor switching element S2.

  An object of the present invention is to provide an active gate circuit capable of suppressing not only the collector-emitter overvoltage at the time of turn-on of the semiconductor switching element of its own arm but also the overvoltage of the recovery voltage of the return diode of the semiconductor switching element of the other arm. Is to provide.

  The active gate circuit according to the invention of claim 1 is formed by a semiconductor switching element in which each of a pair of arms forming a leg of a power converter is connected in parallel with a freewheeling diode, and when the semiconductor switching element is turned off or turned on In an active gate circuit for adjusting a gate current of the semiconductor switching element so as to suppress an increase in the collector-emitter voltage based on a collector-emitter voltage and a collector current of the semiconductor switching element, It is characterized by comprising recovery overvoltage suppression means for adjusting the gate current of the semiconductor switching element of one arm so as to suppress the overvoltage of the recovery voltage of the return diode of the other arm when the semiconductor switching element of one arm is turned on. To do.

  According to a second aspect of the present invention, there is provided the active gate circuit according to the first aspect of the present invention, wherein the recovery overvoltage suppressing means adds a gain to a deviation from the threshold when the recovery voltage of the return diode of the other arm exceeds a certain threshold. The gate current adjustment current value is determined by multiplying the gate current adjustment value by subtracting the gate current adjustment current value from the absolute value of the gate current command value from the gate drive circuit.

  An active gate circuit according to a third aspect of the present invention is the active gate circuit according to the first aspect, wherein the recovery overvoltage suppressing means is configured such that when the rate of decrease in the return current of the return diode of the other arm exceeds a certain threshold, the deviation from the threshold The gate current adjustment current value is determined by multiplying the gain by adjusting the gate current, and the gate current adjustment current value is subtracted from the absolute value of the gate current command value from the gate drive circuit to adjust the gate current.

  According to a fourth aspect of the present invention, there is provided the active gate circuit according to the first aspect of the present invention, wherein the recovery overvoltage suppression means is based on the collector-emitter voltage of the own arm, the collector current, and the DC power supply voltage. Estimate the recovery voltage, and when the estimated recovery voltage exceeds a certain threshold, determine the gate current adjustment current value by multiplying the deviation from the threshold by a gain, and calculate the gate from the absolute value of the gate current command value from the gate drive circuit. The gate current is adjusted by reducing the current adjustment current value.

  According to a fifth aspect of the present invention, there is provided the active gate circuit according to the first aspect of the invention, wherein the recovery overvoltage suppressing means estimates a reduction rate of the return diode current of the other arm based on the collector current and the AC load current of the own arm. When the estimated decrease rate of the return diode current of the other arm exceeds a certain threshold, the gate current adjustment current value is determined by multiplying the deviation from the threshold by a gain, and the absolute value of the gate current command value from the gate drive circuit The gate current is adjusted by subtracting the gate current adjustment current value from.

  An active gate circuit according to a sixth aspect of the present invention is the active gate circuit according to any one of the second to fifth aspects, wherein the gate current adjustment current value is subtracted from the absolute value of the gate current command value from the gate drive circuit. Instead of adjusting the gate current, the gate current is adjusted by changing the gate voltage or the gate resistance corresponding to the gate current adjustment current value.

  An active gate circuit according to a seventh aspect of the present invention is the active gate circuit according to any one of the second to fifth aspects, wherein the gain is in a return period of the return diode current before the current or previous turn-off of the return diode of the other arm. It is determined by a function of the average value of the freewheeling diode current.

  An active gate circuit according to an eighth aspect of the present invention is the active gate circuit according to any one of the second to fifth aspects, wherein the gain is in a turn-on period of a collector current at the current or previous turn-on of the semiconductor switching element of its own arm. It is determined by a function of the average value of the collector current.

  The active gate circuit according to the invention of claim 9 is characterized in that, in any one of claims 2 to 5, the gain is determined by a function of a recovery voltage of another arm or a collector-emitter voltage of its own arm. To do.

  An active gate circuit according to a tenth aspect of the present invention is the active gate circuit according to any one of the second to fifth aspects, wherein the recovery overvoltage suppressing means adds a gain to a deviation from the threshold when each detected value is lower than the threshold. The gate current adjustment current value is determined by multiplying, and the gate current is adjusted by adding the gate current adjustment current value to the absolute value of the gate current command value from the gate drive circuit.

  An active gate circuit according to an invention of claim 11 is the invention of claim 10, wherein instead of adjusting the gate current by adding the gate current adjustment current value to the absolute value of the gate current command value from the gate drive circuit, The gate current is adjusted by changing the gate voltage or the gate resistance corresponding to the gate current adjustment current value.

  According to the present invention, the recovery overvoltage suppressing means adjusts the gate current so as to suppress the overvoltage of the recovery voltage of the return diode of the other arm when the self semiconductor switching element is turned on. Recovery voltage overvoltage can be suppressed.

  FIG. 1 is a block diagram showing an example of an active gate circuit according to the first embodiment of the present invention. In the first embodiment, recovery overvoltage suppression means 16a and 16b for suppressing the overvoltage of the recovery voltage of the freewheeling diode of the other arm are added to the conventional example shown in FIG. The same elements as those in FIG. 13 are denoted by the same reference numerals, and redundant description is omitted.

  In the half-bridge inverter circuit that is a power converter, each of a pair of arms forming a leg is formed by semiconductor switching elements S1 and S2 in which free-wheeling diodes D1 and D2 are connected in antiparallel. The active gate circuit 12a is provided on the arms of the semiconductor switching element S1 and the freewheeling diode D1, and includes a collector / emitter overvoltage suppressing unit 13a and a recovery overvoltage suppressing unit 16a.

  The collector-emitter overvoltage suppression means 13a detects the collector-emitter voltage Vce1 of the semiconductor switching element S1 of its own arm, and calculates a correction signal for preventing the collector-emitter voltage Vce1 from becoming an overvoltage. On the other hand, the recovery overvoltage suppressing means 16a detects the collector-emitter voltage Vce2 of the semiconductor switching element S2 of the other arm, and when the semiconductor switching element S1 of its own arm is turned on, A correction signal for suppressing overvoltage is calculated. These correction signals are converted into currents by the current conversion means 14a and output to the subtraction means (not shown) as gate compensation current ΔIg1, and the gate compensation current ΔIg1 is subtracted from the absolute value of the gate current command value from the gate drive circuit 10a. Then, the gate current Ig1 is output to the semiconductor switching element S1.

  Similarly, the collector-emitter overvoltage suppression means 13b detects the collector-emitter voltage Vce2 of the semiconductor switching element S2 of its own arm, and calculates a correction signal for preventing the collector-emitter voltage Vce2 from becoming an overvoltage. To do. On the other hand, the recovery overvoltage suppressing means 16b detects the collector-emitter voltage Vce1 of the semiconductor switching element S1 of the other arm, and the recovery voltage of the freewheeling diode D1 of the other arm when the semiconductor switching element S2 of its own arm is turned on. A correction signal for suppressing overvoltage is calculated. These correction signals are converted into currents by the current conversion means 14b and output to the subtraction means (not shown) as gate compensation current ΔIg2, and the gate compensation current ΔIg2 is subtracted from the absolute value of the gate current command value from the gate drive circuit 10b. Then, the gate current Ig2 is output to the semiconductor switching element S2.

  FIG. 2 is a block diagram showing an example of the recovery overvoltage suppressing means 16a in the first embodiment of the present invention. The recovery overvoltage suppressing means 16a detects the collector-emitter voltage Vce2 of the semiconductor switching element S2 of the other arm and inputs it to the comparator 17. Then, the comparator 17 compares it with a predetermined threshold value Vce2 *, and the difference between the collector-emitter voltage Vce2 and the threshold value Vce2 * is multiplied by a predetermined gain kv2 with a proportional unit 18, and is used as a correction signal to convert the current into the current conversion means 14a. Output to. Here, since the collector-emitter voltage Vce2 of the semiconductor switching element S2 of the other arm is equal to the recovery voltage of the freewheeling diode D2 of the other arm, this suppresses the overvoltage of the recovery voltage of the freewheeling diode D2 of the other arm. A correction signal to be obtained is obtained.

  The comparator 17 is provided with a dead zone for outputting 0 when the difference between the collector-emitter voltage Vce2 and the threshold value Vce2 * is negative. Therefore, when the collector-emitter voltage Vce2 of the semiconductor switching element S2 of the other arm exceeds a certain threshold value Vce2 *, a correction signal is obtained by multiplying the deviation from the threshold value Vce2 * by a gain.

  When the recovery voltage of the freewheeling diode D2 of the other arm exceeds a certain threshold value, the gate current adjustment current value is determined by the current conversion means 14a by multiplying the deviation from the threshold value Vce2 * by the gain kv2, and this is determined based on the control pulse. By reducing from the current from the drive circuit 10a, the turn-on speed is suppressed.

  Next, FIGS. 3 and 4 are explanatory diagrams of operation modes of the semiconductor switching elements S1 and S2 and the freewheeling diodes D1 and D2 that form the arms of the half-bridge inverter circuit that is a power converter. The magnitudes of the voltages of the DC power supplies E1 and E2 are equal (E1 = E2). First, FIG. 3A shows mode 1 in which an ON command is output to the semiconductor switching element S1 and an OFF command is output to the semiconductor switching element S2. In this mode 1, since the semiconductor switching element S1 is on and the semiconductor switching element S2 is off, a current flows as shown by a dotted line, and a load current flows from the DC power source E1 through the semiconductor switching element S1 to the AC load Zload. It is being supplied.

  FIG. 3B shows mode 2 in which an off command is output to the semiconductor switching element S1 and an on command is output to the semiconductor switching element S2 from the state of mode 1 in FIG. In this mode 2, since the semiconductor switching element S1 is in the process of transitioning from on to off, the current flowing from the DC power supply E1 to the semiconductor switching element S1 decreases. On the other hand, since the current to the semiconductor switching element S2 has a reverse polarity, even if an ON command is output to the semiconductor switching element S2, no current flows through the semiconductor switching element S2, and the semiconductor switching element S2 is connected in reverse parallel. A reflux current flows through the reflux diode D2.

  FIG. 3C shows mode 3 in which the semiconductor switching element S1 is turned off from the state of mode 2 in FIG. In this mode 3, no current flows through the semiconductor switching element S1 as the semiconductor switching element S1 is turned off. Even in this state, the current to the semiconductor switching element S2 has a reverse polarity. Even if an ON command is output to S2, no current flows through the semiconductor switching element S2, and a reflux current flows through the freewheeling diode D2 connected in reverse parallel to the semiconductor switching element S2.

  FIG. 3D shows mode 4 in which an ON command is output to the semiconductor switching element S1 and an OFF command is output to the semiconductor switching element S2 from the state of mode 3 in FIG. In Mode 4, since the semiconductor switching element S1 is in the process of transitioning from OFF to ON, the current flowing from the DC power supply E1 to the semiconductor switching element S1 increases. On the other hand, since an OFF command is output to the semiconductor switching element S2, a reflux current flows through the free-wheeling diode D2 connected in reverse parallel to the semiconductor switching element S2 without a current flowing through the semiconductor switching element S2.

  Next, FIG. 4A shows mode 5 in which an off command is output to the semiconductor switching element S1 and an on command is output to the semiconductor switching element S2. In this mode 5, since the semiconductor switching element S1 is off and the semiconductor switching element S2 is on, a current flows as shown by a dotted line, and a load current flows from the DC power source E2 to the AC load Zload through the semiconductor switching element S2. It is being supplied.

  FIG. 4B shows mode 6 in which an ON command is output to the semiconductor switching element S1 and an OFF command is output to the semiconductor switching element S2 from the mode 5 state of FIG. 4A. In mode 6, since the semiconductor switching element S1 is in the process of transitioning from OFF to ON, the current flowing from the DC power supply E2 to the semiconductor switching element S2 decreases. On the other hand, since the current to the semiconductor switching element S1 has a reverse polarity, even if an ON command is output to the semiconductor switching element S1, no current flows through the semiconductor switching element S1, and the semiconductor switching element S1 is connected in reverse parallel. A reflux current flows through the reflux diode D1.

  FIG. 4C shows a mode 7 in which the semiconductor switching element S2 is turned off from the state of the mode 6 in FIG. 4B. In this mode 7, no current flows through the semiconductor switching element S2 as the semiconductor switching element S2 is turned off. Even in this state, the current to the semiconductor switching element S1 has a reverse polarity. Even if an ON command is output to S1, a current does not flow through the semiconductor switching element S1, but a reflux current flows through the freewheeling diode D1 connected in reverse parallel to the semiconductor switching element S1.

  FIG. 4D shows a mode 8 in which an ON command is output to the semiconductor switching element S2 and an OFF command is output to the semiconductor switching element S1 from the state of the mode 7 in FIG. 4C. In this mode 8, since the semiconductor switching element S2 is in the process of transition from OFF to ON, the current flowing from the DC power supply E2 to the semiconductor switching element S2 increases. On the other hand, since the OFF command is output to the semiconductor switching element S1, the return current flows through the return diode D1 connected in reverse parallel to the semiconductor switching element S1 without flowing the current through the semiconductor switching element S1.

  As described above, the operation modes of the semiconductor switching elements S1 and S2 and the freewheeling diodes D1 and D2 that form each arm of the half-bridge inverter circuit that is a power converter include eight modes of mode 1 to mode 8.

  FIG. 5 is a signal waveform diagram of each part of the half-bridge inverter circuit that is the power converter according to the first embodiment of the present invention. In FIG. 5, the mode 7 shown in FIGS. 3 and 4 (the mode in which the semiconductor switching element S2 is turned off from the state of the mode 6) → mode 8 → mode 5 → mode 6 → mode 7 → mode 1 → mode In this case, the state is changed sequentially from 2 → mode 3 → mode 4 → mode 1.

  The semiconductor switching elements S1 and S2 of the half-bridge inverter circuit operate by alternately turning on and off. That is, the gate signals Gate1 and Gate2 to the semiconductor switching elements S1 and S2 are signals that are turned on and off, and when the gate signal Gate1 to the semiconductor switching element S1 is on, the gate signal Gate2 to the semiconductor switching element S2 is When the gate signal Gate1 to the semiconductor switching element S1 is off, the gate signal Gate2 to the semiconductor switching element S2 is on.

  The load voltage Vload of the AC load Zload is a positive voltage when the semiconductor switching element S1 is on and the semiconductor switching element S2 is off, and is a negative voltage when the semiconductor switching element S1 is off and the semiconductor switching element S2 is on. AC voltage. The load current Iload of the AC load Zload becomes a current approximate to a sine wave. The element current Is1 of the semiconductor switching element S1 flows in a region where the load current Iload is positive, and the return current Id1 of the return diode D1 is a region where the load current Iload is negative. It flows in. Further, the element current Is2 of the semiconductor switching element S2 flows in a region where the load current Iload is negative, and the return current Id2 of the freewheeling diode D2 flows in a region where the load current Iload is positive. The collector-emitter voltage Vce1 of the semiconductor switching element S1 is only a forward voltage drop when the semiconductor switching element S1 is on, and becomes a predetermined voltage E when the semiconductor switching element S1 is off. Similarly, the collector-emitter voltage Vce2 of the semiconductor switching element S2 is only a forward voltage drop when the semiconductor switching element S2 is on, and becomes a predetermined voltage E when the semiconductor switching element S2 is off.

  FIG. 6 is a signal waveform diagram of each part of the half-bridge inverter circuit according to the first embodiment of the present invention at the portion changed from mode 1 → mode 2 → mode 3 → mode 4 → mode 1 in FIG.

  From the state where the gate signal Gate1 to the semiconductor switching element S1 is on and the gate signal Gate2 to the semiconductor switching element S2 is off (mode 1), the gate signal Gate1 to the semiconductor switching element S1 is off at time t11. The gate signal Gate2 to the semiconductor switching element S2 is switched on (mode 2). Further, at time t12, a forward current flows through the freewheeling diode D2, and the semiconductor switching is performed even if the gate signal Gate2 to the semiconductor switching element S2 is on. The element S2 is not turned on (mode 3), and at time t13, an on command is output from the mode 3 to the semiconductor switching element S1, and an off command is output to the semiconductor switching element S2, and the mode 4 is entered, and at time t14. , Gate signal Gat to semiconductor switching element S1 Assume that e1 is on and the gate signal Gate2 to the semiconductor switching element S2 is switched off (mode 1).

  At time t11, since the gate signal Gate1 to the semiconductor switching element S1 is off and the gate signal Gate2 to the semiconductor switching element S2 is turned on, the element current Is1 of the semiconductor switching element S1 starts to decrease, and the semiconductor switching element S2 returns. A current is commutated to the diode D2, and a forward return current Id2 flows. As a result, the load voltage Vload of the AC load Zload changes from positive to negative, and the load current ILoad of the AC load Zload hardly changes. However, in the off-transition period of the semiconductor switching element S1 from time t11 to time t12, the semiconductor switching element A surge voltage is generated in the collector-emitter voltage Vce1 of S1.

  The surge voltage of the collector-emitter voltage Vce1 of the semiconductor switching element S1 is suppressed by the collector-emitter overvoltage suppression means 13a of the active gate circuit 12a of the first embodiment of the present invention. That is, the collector-emitter overvoltage suppression means 13a calculates a correction signal for preventing the collector-emitter voltage Vce1 from becoming an overvoltage, and the current conversion means 14a converts it into a current to obtain a gate compensation current ΔIg1. A gate current Ig1 obtained by subtracting the gate compensation current ΔIg1 from the absolute value of the gate current command value from the gate drive circuit 10a is output to the semiconductor switching element S1. The waveforms shown by dotted lines are the gate current Ig1, the gate voltage Vge1, and the collector-emitter voltage Vce1 suppressed by the collector / emitter overvoltage suppressing means 13a.

  On the other hand, at time t13 when the semiconductor switching element S2 is not turned on even when the gate signal Gate2 to the semiconductor switching element S2 is turned on (mode 3), the gate signal Gate1 to the semiconductor switching element S1 is turned on and the semiconductor switching element S2 is turned on. When the gate signal Gate2 is switched off (mode 4), the current of the freewheeling diode D2 begins to decrease and commutates to the semiconductor switching element S1, and the element current Is1 begins to flow. At this time, a surge voltage is generated in the collector-emitter voltage Vce2 of the semiconductor switching element S2 during the off-transition period of the return diode D2 from the time point t13 to the time point t14.

  The surge voltage of the collector-emitter voltage Vce2 of the semiconductor switching element S2 is suppressed by the recovery overvoltage suppression means 16a of the active gate circuit 12a of the first embodiment of the present invention. That is, the recovery overvoltage suppression means 16a detects the collector-emitter voltage Vce2 of the semiconductor switching element S2 of the other arm, and the recovery voltage of the freewheeling diode D2 of the other arm when the semiconductor switching element S1 of its own arm is turned on. A correction signal for suppressing overvoltage is calculated. Then, the correction signal is converted into a current by the current conversion means 14a to obtain the gate compensation current ΔIg1, and the gate current Ig1 obtained by subtracting the gate compensation current ΔIg1 from the absolute value of the gate current command value from the gate drive circuit 10a is switched to the semiconductor. Output to element S1. The waveforms shown by dotted lines are the gate current Ig1, the gate voltage Vge1, and the collector-emitter voltage Vce2 suppressed by the collector / emitter overvoltage suppressing means 13a.

  According to the first embodiment, not only the collector-emitter overvoltage is suppressed when the semiconductor switching element S1 of its own arm is turned on, but also the recovery overvoltage suppressing means 16a causes the other of the other semiconductor switching element S1 to turn on. Since the gate current is adjusted so as to suppress the overvoltage of the recovery voltage of the freewheeling diode D2 of the arm, the overvoltage of the recovery voltage of the freewheeling diode D2 of the other arm can be suppressed.

  FIG. 7 is a block diagram showing an example of an active gate circuit according to the second embodiment of the present invention. The second embodiment is different from the first embodiment shown in FIG. 1 in that the recovery overvoltage suppressing means 16a detects the return current of the return diode D2 of the other arm and returns the return current of the return diode of the other arm. When the current reduction rate exceeds a certain threshold, the gate current adjustment current value is determined by multiplying the deviation from the threshold by gain, and the gate current adjustment current value is subtracted from the absolute value of the gate current command value from the gate drive circuit. The function to adjust the gate current is added.

  In FIG. 7, the recovery overvoltage suppression means 16a detects the collector current Ic2 and the gate signal Gate1 to the semiconductor switching element S1 in addition to the collector-emitter voltage Vce2 of the semiconductor switching element S2 of the other arm. Since the collector current Ic2 flowing to the other arm when the semiconductor switching element S1 of its own arm is turned on is equal to the return current Id2 of the return diode D2 of the other arm, the collector current Ic2 is used as the return current Id2 of the return diode D2 of the other arm. To detect.

  Then, when the semiconductor switching element S1 of its own arm is turned on, a correction signal for suppressing the overvoltage of the recovery voltage of the free wheel diode D2 of the other arm is calculated. The correction signal is converted into a current by the current conversion means 14a and output to the subtraction means (not shown) as a gate compensation current ΔIg1, and the gate compensation current ΔIg1 is subtracted from the absolute value of the gate current command value from the gate drive circuit 10a. Ig1 is output to the semiconductor switching element S1.

  FIG. 8 is a configuration diagram showing an example of the recovery overvoltage suppressing means 16a in the second embodiment of the present invention. The recovery overvoltage suppression means 16a includes a comparator 17 that compares the collector-emitter voltage Vce2 of the semiconductor switching element S2 of the other arm with a predetermined constant threshold Vce2 *, and the collector-emitter voltage Vce2 and the threshold Vce2 *. And a differentiator 19 for calculating a reduction rate dIc2 / dt of the collector current Ic2 of the other arm, and a differentiator 19 The comparator 20 for obtaining the difference between the decrease rate dIc2 / dt of the collector current Ic2 of the other arm obtained in step 4 and a predetermined constant threshold value dIc2 * / dt, and the difference obtained by the comparator 20 is multiplied by a predetermined gain ki2. And a proportional device 21 that outputs the correction signal to the current conversion means 14a. Further, the averaging processing means 22 for calculating the average value Ic2av of the collector current Ic2 of the other arm during the ON period of the collector current Ic2 of the other arm, and the proportional value from the average value Ic2av of the collector current Ic2 obtained by the averaging processing means 22 Gain optimum value calculating means 23 for obtaining an appropriate gain ki2 of the device 21.

  Since the collector current Ic2 flowing to the other arm when the semiconductor switching element S1 of its own arm is turned on is equal to the return current Id2 of the return diode D2 of the other arm, the differentiator 19 of the recovery overvoltage suppressing means 16a is the collector current Ic2 Is detected as the freewheeling current Id2 of the freewheeling diode D2 of the other arm and differentiated to calculate the decrease rate dIc2 / dt of the collector current Ic2 of the other arm. The differentiator 19 is provided with a dead zone for outputting 0 when the decrease rate dIc2 / dt of the collector current Ic2 of the other arm is positive. The decrease rate dIc2 / dt of the collector current Ic2 of the other arm obtained by the differentiator 19 is input to the comparator 20, and a difference from a predetermined constant threshold value dIc2 * / dt is obtained. The difference is multiplied by a predetermined gain ki2 and output to the current conversion means 14a as a correction signal.

On the other hand, the averaging processing means 22 calculates the collector current Ic2 of the other arm during the ON period of the collector current Ic2 of the other arm, that is, the average value Ic2av of the return current Id2 of the freewheeling diode D2 of the other arm. Whether the collector current Ic2 of the other arm is in the ON period is determined by the fact that the gate signal Gate1 to the semiconductor switching element S1 is an OFF command. During this OFF command period, it is determined that the change in the return current Id2 is not more than a certain threshold value, and only the period is averaged. Then, an appropriate gain ki2 of the proportional device 21 is obtained by the optimum gain calculation means 23 based on the average value Ic2av of the collector current Ic2 obtained by the averaging processing means 22. For example, an appropriate gain ki2 of the proportional device 21 is obtained by the following equation (1). (1) A and B in the formula are constants.
ki2 = A · Ic2av + B (1)
That is, when the average value Ic2av of the freewheeling current Id2 of the freewheeling diode D2 of the other arm is large, the gain ki2 is increased to increase the gate current adjustment current value, which is larger than the absolute value of the gate current command value from the gate drive circuit. The gate current adjustment current value is subtracted to suppress the turn-on speed of its own semiconductor switching element S1.

  In this case, when the average processing means 22 calculates the average value Ic2av of the return current Id2 in real time, the average value of the current return diode current at the turn-on time of the current semiconductor switching element S1 is obtained. Use. Here, the current average value of the freewheeling diode current is an average value in the OFF period of S1 immediately before commutation from the diode by switching. On the other hand, when it takes time to calculate the average value Ic2av of the freewheeling diode current Id2 in the averaging processing means 22, the average value of the previous freewheeling diode current at the time of turning on the previous semiconductor switching element S1 is used. . Here, the previous average value of the freewheeling diode current is an average value in the OFF period of S1 immediately before the commutation from the diode by switching.

  According to the second embodiment, not only the collector-emitter overvoltage is suppressed when the semiconductor switching element S1 of its own arm is turned on, but also the recovery overvoltage suppressing means 16a causes the other of the other semiconductor switching element S1 to turn on. Since the gate current is adjusted so as to suppress the overvoltage of the recovery voltage based on the decrease rate of the return diode current of the return diode D2 of the arm, the turn-on speed of its own semiconductor switching element S1 can be suppressed, and the return of the other arm The overvoltage of the recovery voltage of the diode D2 can be suppressed.

  FIG. 9 is a block diagram showing an example of an active gate circuit according to the third embodiment of the present invention. In this third embodiment, the recovery overvoltage suppressing means 16a estimates the recovery voltage of the freewheeling diode D2 of the other arm based on the collector-emitter voltage Vce1, the collector current Ic1, and the DC power supply voltage Vdc of its own arm. When the estimated recovery voltage exceeds a certain threshold, determine the gate current adjustment current value by multiplying the deviation from the threshold by gain, and subtract the gate current adjustment current value from the absolute value of the gate current command value from the gate drive circuit. Thus, the gate current is adjusted.

  In FIG. 9, the recovery overvoltage suppression means 16a detects the collector-emitter voltage Vce1, the collector current Ic1, and the DC power supply voltage Vdc of its own arm. When the semiconductor switching element S1 of its own arm is turned on, the recovery voltage of the freewheeling diode D2 of the other arm is estimated based on the collector-emitter voltage Vce1, its collector current Ic1, and the DC power supply voltage Vdc of its own arm. Since the recovery voltage of the freewheeling diode D2 of the other arm is equal to the collector-emitter voltage Vce2 of the semiconductor switching element S2 of the other arm, the collector-emitter voltage Vce2 of the semiconductor switching element S2 is estimated. Then, a correction signal is calculated so that the estimated recovery voltage (collector-emitter voltage V′ce2) does not exceed a certain threshold. The correction signal is converted into a current by the current conversion means 14a and output to the subtraction means (not shown) as a gate compensation current ΔIg1, and the gate compensation current ΔIg1 is subtracted from the absolute value of the gate current command value from the gate drive circuit 10a. Ig1 is output to the semiconductor switching element S1.

  FIG. 10 is a block diagram showing an example of the recovery overvoltage suppressing means 16a in the third embodiment of the present invention. In the third embodiment, the recovery voltage (collector-emitter voltage V′ce2) of the return diode of the other arm is calculated based on the collector-emitter voltage Vce1, the collector current Ic1, and the DC power supply voltage Vdc of its own arm. The gate current is adjusted by estimation.

  The recovery overvoltage suppressing means 16a estimates the recovery voltage (collector-emitter voltage V'ce2) of the return diode of the other arm based on the collector-emitter voltage Vce1, the collector current Ic1, and the DC power supply voltage Vdc of its own arm. And a comparator 25 for obtaining a deviation between the collector-emitter voltage V′ce2 estimated by the estimator 24 and a constant threshold value V′ce2 *, and outputting the deviation when the deviation is 0 or more, and an estimation And a proportional unit 26 that obtains a gate current adjustment current value by multiplying the deviation between the collector-emitter voltage V'ce2 and the constant threshold value V'ce2 * by a gain.

Based on the collector-emitter voltage Vce1, the collector current Ic1, and the DC power supply voltage Vdc of the self-arm, the estimator 24 uses, for example, the following equation (2) to recover the recovery voltage (collector-emitter voltage V 'ce2) is estimated. In the equation (2), Vdc is a DC power supply voltage (E + E), and Ldc1 is a DC side equivalent inductance (wiring inductance).
V'ce2 = Vdc-Vce1-Ldc1. (D / dt) .Ic1 (2)
That is, in the steady state, the relationship between the collector-emitter voltage Vce1 of its own arm and the collector-emitter voltage Vce2 of the other arm is expressed by the following equation (3), and the collector current Ic1 of the semiconductor switching element S1 changes. Is shown by the following formula (4).
Vce2 = Vdc-Vce1 (3)
Vce2 = Vdc−Vce1−Ldc1 · (d / dt) · Ic1 (4)
Therefore, based on the equation (4), the estimator 24 calculates the collector-emitter voltage Vce2 of the other arm, and obtains the estimated collector-emitter voltage V'ce2 as shown in the equation (2). The estimated collector-emitter voltage V′ce2 estimated by the estimator 24 is compared with a certain threshold value V′ce2 * by the comparator 25, and the deviation is obtained. The comparator 25 is provided with a dead zone for outputting 0 when the difference between the estimated collector-emitter voltage V′ce2 and the threshold value V′ce2 * is negative. Therefore, when the estimated collector-emitter voltage V'ce2 of the semiconductor switching element S2 of the other arm exceeds a certain threshold value V'ce2 *, the estimated collector-emitter voltage V'ce2 and the threshold value V'ce2 * The deviation is output from the comparator 25 to the proportional unit 26. The proportional device 26 obtains a gate current adjustment current value by multiplying the deviation between the estimated collector-emitter voltage V′ce2 and the constant threshold value V′ce2 * by a gain, and from the absolute value of the gate current command value from the gate drive circuit. The gate current adjustment current value is reduced to adjust the gate current, and the turn-on speed of the semiconductor switching element S1 is suppressed.

  According to the third embodiment, the gate current is adjusted by estimating the recovery voltage of the freewheeling diode D2 of the other arm based on the collector-emitter voltage Vce1, the collector current Ic1, and the DC power supply voltage Vdc of its own arm. It is not necessary to detect the collector current Ic2 of the other arm, the turn-on speed of the semiconductor switching element S1 can be suppressed, and the overvoltage of the recovery voltage of the free wheel diode D2 of the other arm can be suppressed.

  FIG. 11 is a block diagram showing an example of the recovery overvoltage suppressing means 16a in the fourth embodiment of the present invention. This fourth embodiment is different from the third embodiment shown in FIG. 9 in that the recovery overvoltage suppressing means 16a is based on the collector current Ic1 and the AC load current Iload of its own arm, and the freewheeling diode current of the other arm. The function of adjusting the gate current of its own semiconductor switching element S1 when the estimated decrease rate of the return diode current Id2 of the other arm exceeds a certain threshold is provided. .

  In addition to the collector-emitter voltage Vce1, the collector current Ic1, and the DC power supply voltage Vdc of the self arm, the recovery overvoltage suppressing means 16a also detects the AC load current Iload and the gate signal Gate1 to its own semiconductor switching element S1. The reason why the gate signal Gate1 to the semiconductor switching element S1 is detected is to determine that the collector current Ic2 of the other arm is in the ON period.

  Then, the recovery overvoltage suppression means 16a estimates and estimates the decrease rate of the return diode current of the other arm based on the collector current Ic1 and the AC load current Iload of the own arm when the semiconductor switching element S1 of the own arm is turned on. Based on the decreasing rate of the free-wheeling diode current Id2 of the other arm, a correction signal for suppressing the overvoltage of the recovery voltage of the free-wheeling diode D2 of the other arm is calculated. The correction signal is converted into a current by the current conversion means 14a and output to the subtraction means (not shown) as a gate compensation current ΔIg1, and the gate compensation current ΔIg1 is subtracted from the absolute value of the gate current command value from the gate drive circuit 10a. Ig1 is output to the semiconductor switching element S1.

  FIG. 12 is a block diagram showing an example of the recovery overvoltage suppressing means 16a in the fourth embodiment of the present invention. The recovery overvoltage suppressing means 16a estimates the recovery voltage (collector-emitter voltage V'ce2) of the return diode of the other arm based on the collector-emitter voltage Vce1, the collector current Ic1, and the DC power supply voltage Vdc of its own arm. And a comparator 25 for obtaining a deviation between the collector-emitter voltage V′ce2 estimated by the estimator 24 and a constant threshold value V′ce2 *, and outputting the deviation when the deviation is 0 or more, and an estimation In addition to the proportional device 26 that calculates the gate current adjustment current value by multiplying the deviation between the collector-emitter voltage V'ce2 and the constant threshold value V'ce2 * by gain, the collector current Ic1 of the own arm and the AC load current Iload The estimator 27 for estimating the return diode current of the other arm (collector current Ic2 of the other arm) based on the above, the derivative of the collector current I′c2 of the other arm estimated by the estimator 27 Then, the differentiator 28 for calculating the decrease rate dI'c2 / dt of the collector current Ic2 of the other arm, the decrease rate dI'c2 / dt obtained by the differentiator 28 and the constant threshold value dI'c2 * / dt A comparator 29 for obtaining the difference, and a proportional unit 30 for multiplying the difference obtained by the comparator 29 by a predetermined gain ki1 and outputting it as a correction signal to the current conversion means 14a.

  Further, the average processing means 31 for calculating the average value I′c2av of the estimated collector current I′c2 of the other arm during the ON period of the estimated collector current I′c2 of the other arm, and the averaging processing means 31 A gain optimum value calculating means 32 for obtaining an appropriate gain ki1 of the proportional device 30 from the average value I'c2av of the estimated collector current I'c2.

The estimator 27 estimates the return diode current of the other arm (collector current I′c2 of the other arm) by the following equation (5) based on the collector current Ic1 of the own arm and the AC load current Iload. This is because when the semiconductor switching element S1 of its own arm is turned on, the freewheeling diode current of the other arm is equal to the collector current Ic2 of the other arm.
I'c2 = Iload-Ic1 (5)
The differentiator 28 differentiates the collector current I′c2 of the other arm estimated by the estimator 27 and calculates an estimated decrease rate dI′c2 / dt of the collector current Ic2 of the other arm. The differentiator 28 is provided with a dead zone that outputs 0 when the estimated decrease rate dI′c2 / dt of the collector current Ic2 of the other arm is 0 or more. Therefore, when the estimated decrease rate dI′c2 / dt is 0 or less, the estimated decrease rate dI′c2 / dt is output to the comparator 29. The decrease rate dI'c2 / dt of the collector current Ic2 of the other arm obtained by the differentiator 28 is input to the comparator 29, and a difference from a predetermined constant threshold value dI'c2 * / dt is obtained. 30 multiplies the difference by a predetermined gain ki1 and outputs it to the current conversion means 14a as a correction signal.

  On the other hand, the averaging processing means 31 calculates the average value I′c2av of the estimated collector current I′c2 of the other arm during the ON period of the estimated collector current I′c2 of the other arm. Whether the estimated collector current I'c2 of the other arm is in the ON period is determined by the fact that the gate signal Gate1 to the semiconductor switching element S1 is an OFF command. The determination method is the same as in the second embodiment. Then, an appropriate gain ki1 of the proportional device 30 is obtained by the optimum gain value computing means 32 based on the average value I'c2av of the estimated collector current I'c2 obtained by the averaging processing means 31. This is obtained using the above-described equation (1). That is, when the estimated average value I′c2av of the freewheeling diode current Id2 of the freewheeling diode D2 of the other arm is large, the gain ki1 is increased to increase the gate current adjustment current value, and the gate current command value from the gate drive circuit is increased. A large gate current adjustment current value is subtracted from the absolute value to suppress the turn-on speed of its own semiconductor switching element S1.

  In this case, if the calculation processing of the estimated average value I′c2av of the freewheeling diode current Id2 in the averaging processing means 31 can be processed in real time, the current freewheeling diode current at the turn-on time of the current semiconductor switching element S1. The estimated average value of is used. On the other hand, when it takes time to calculate the estimated average value I′c2av of the freewheeling diode current Id2 in the averaging processing means 31, the previous freewheeling diode current is estimated when the semiconductor switching element S1 is turned on. Use the average value. That is, the gain ki1 is determined by a function of the average value of the collector current during the turn-on period of the collector current at the current or previous turn-on of the semiconductor switching element S1 of its own arm. Here, the previous definition is the same as that of the second embodiment.

  According to the fourth embodiment, the reduction rate of the return diode current of the other arm is estimated based on the collector current Ic1 of the own arm and the AC load current Iload, and the estimated reduction rate of the return diode current Id2 of the other arm is calculated. When a certain threshold value is exceeded, the gate current of its own semiconductor switching element S1 is adjusted, so that it is not necessary to detect the collector current Ic2 of the other arm, and the turn-on speed of its own semiconductor switching element S1 can be suppressed, The overvoltage of the recovery voltage of the return diode D2 of the other arm can be suppressed.

  Here, the gain kv2 of the proportional device 18 and the gain kv1 of the proportional device 26 may be predetermined constants, or may be determined by a function of the recovery voltage of the other arm or the collector-emitter voltage of its own arm. For example, the gain kv2 of the proportional device 18 and the gain kv1 of the proportional device 26 are obtained by the following equation (6). (6) C and D in the formula are constants.

kv1 (kv2) = C · Vce1 (Vce2) + D (6)
That is, when the recovery voltage Vce2 of the other arm or the collector-emitter voltage Vce1 of its own arm is large, the gain kv1 (kv2) is increased to increase the gate current adjustment current value, and the gate current command value from the gate drive circuit is increased. A large gate current adjustment current value is subtracted from the absolute value to suppress the turn-on speed of its own semiconductor switching element S1.

  In the above description, the dead zones are provided in the comparators 17, 20, and 25. However, the dead current is not provided, and the gate current adjustment current value is determined by multiplying the deviation from the threshold value by the gain, and the gate current from the gate drive circuit. The gate current may be adjusted by adding the gate current adjustment current value to the absolute value of the command value. This is because when each detected value is lower than the threshold value, the recovery voltage is not in an overvoltage state, and it is not necessary to suppress the turn-on speed of the semiconductor switching element. As a result, the switching speed is increased and the switching loss can be reduced.

  In the above description, the gate current is adjusted by subtracting the gate current adjustment current value from the absolute value of the gate current command value from the gate drive circuit or adding the gate current adjustment current value to the absolute value of the gate current command value. Although the adjustment is made, it goes without saying that the gate current may be adjusted by changing the gate voltage or the gate resistance corresponding to the gate current adjustment current value.

1 is a configuration diagram showing an example of an active gate circuit according to a first embodiment of the present invention. The block diagram which shows an example of the recovery overvoltage suppression means in the 1st Embodiment of this invention. Explanatory drawing of the operation mode of the semiconductor switching element which forms each arm of the half bridge inverter circuit which is a power converter, and a free-wheeling diode (the 1). Explanatory drawing of the operation mode of the semiconductor switching element which forms each arm of the half bridge inverter circuit which is a power converter, and a free-wheeling diode (the 2). The signal waveform diagram of each part of the half bridge inverter circuit which is a power converter in the 1st Embodiment of this invention. FIG. 6 is a signal waveform diagram of each part of the half-bridge inverter circuit according to the first embodiment of the present invention at a portion changed from mode 1 → mode 2 → mode 3 → mode 4 → mode 1 in FIG. 5; The block diagram which shows an example of the active gate circuit concerning the 2nd Embodiment of this invention. The block diagram which shows an example of the recovery overvoltage suppression means in the 2nd Embodiment of this invention. The block diagram which shows an example of the active gate circuit concerning the 3rd Embodiment of this invention. The block diagram which shows an example of the recovery overvoltage suppression means in the 3rd Embodiment of this invention. The block diagram which shows an example of the recovery overvoltage suppression means in the 4th Embodiment of this invention. The block diagram which shows an example of the recovery overvoltage suppression means in the 4th Embodiment of this invention. The block diagram which shows an example of the conventional active gate circuit in case a power converter is a half-bridge inverter circuit. The block diagram which shows another example of the conventional active gate circuit in case a power converter is a half-bridge inverter circuit. The signal waveform diagram of each part when the semiconductor switching element of a half-bridge inverter circuit carries out on-off operation in a short period.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Gate drive circuit, 11 ... Gate power supply, 12 ... Active gate circuit, 13 ... Collector-emitter overvoltage suppression means, 14 ... Current conversion means, 15 ... Collector-emitter overvoltage suppression means, 16 ... Recovery overvoltage suppression means, 17 ... Comparator, 18 ... Proportionator, 19 ... Differentiator, 20 ... Comparator, 21 ... Proportionator, 22 ... Averaging processing means, 23 ... Optimal gain calculation means, 24 ... Estimator, 25 ... Comparator, 26 ... Proportionator, 27 ... Estimator, 28 ... Differentiator, 29 ... Comparator, 30 ... Proportionator, 31 ... Averaging processing means, 32 ... Optimal gain calculation means

Claims (11)

  Each of the pair of arms forming the legs of the power converter is formed of a semiconductor switching element in which freewheeling diodes are connected in antiparallel, and the collector-emitter voltage and collector of the semiconductor switching element when the semiconductor switching element is turned off or turned on. In an active gate circuit that adjusts a gate current of the semiconductor switching element so as to suppress an increase in the collector-emitter voltage based on a current, when the semiconductor switching element of one arm of the pair of arms is turned on, the other An active gate circuit comprising recovery overvoltage suppressing means for adjusting a gate current of a semiconductor switching element of one arm so as to suppress an overvoltage of a recovery voltage of a return diode of an arm.   The recovery overvoltage suppression means determines the gate current adjustment current value by multiplying the deviation from the threshold by a gain when the recovery voltage of the freewheeling diode of the other arm exceeds a certain threshold, and determines the gate current command value from the gate drive circuit 2. The active gate circuit according to claim 1, wherein the gate current is adjusted by subtracting the gate current adjustment current value from the absolute value of.   The recovery overvoltage suppression means determines the gate current adjustment current value by multiplying the deviation from the threshold by a gain when the rate of decrease of the return diode current of the return diode of the other arm exceeds a certain threshold, 3. The active gate circuit according to claim 1, wherein the gate current is adjusted by subtracting the gate current adjustment current value from the absolute value of the gate current command value.   The recovery overvoltage suppression means estimates the recovery voltage of the return diode of the other arm based on the collector-emitter voltage of the own arm, the collector current, and the DC power supply voltage, and when the estimated recovery voltage exceeds a certain threshold value, The gate current is adjusted by multiplying the deviation from the threshold by a gain to determine a gate current adjustment current value, and subtracting the gate current adjustment current value from the absolute value of the gate current command value from the gate drive circuit. 2. The active gate circuit according to 1.   The recovery overvoltage suppression means estimates the reduction rate of the return diode current of the other arm based on the collector current and AC load current of the own arm, and the estimated reduction rate of the return diode current of the other arm exceeds a certain threshold value. When the gate current adjustment current value is determined by multiplying the deviation from the threshold by gain, and the gate current adjustment current value is subtracted from the absolute value of the gate current command value from the gate drive circuit, the gate current is adjusted. The active gate circuit according to claim 1 or 4.   Instead of adjusting the gate current by subtracting the gate current adjustment current value from the absolute value of the gate current command value from the gate drive circuit, the gate voltage or the gate resistance corresponding to the gate current adjustment current value is changed. 6. The active gate circuit according to claim 2, wherein the gate current is adjusted.   4. The active gate circuit according to claim 3, wherein the gain is determined by a function of an average value of the freewheeling diode current during a freewheeling period of the freewheeling diode current before or the last turn-off of the freewheeling diode of the other arm.   6. The active gate circuit according to claim 5, wherein the gain is determined by a function of an average value of the collector current during the turn-on period of the collector current at the current or previous turn-on of the semiconductor switching element of its own arm.   5. The active gate circuit according to claim 2, wherein the gain is determined by a function of a recovery voltage of another arm or a collector-emitter voltage of its own arm.   The recovery overvoltage suppression means determines the gate current adjustment current value by multiplying the deviation from the threshold value by a gain when each detected value is below the threshold value, and sets the gate current command value from the gate drive circuit to the absolute value. 6. The active gate circuit according to claim 2, wherein a gate current is adjusted by adding a current adjustment current value.   Instead of adjusting the gate current by adding the gate current adjustment current value to the absolute value of the gate current command value from the gate drive circuit, the gate voltage or gate resistance corresponding to the gate current adjustment current value is changed. The active gate circuit according to claim 10, wherein the gate current is adjusted.

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