JP2009182361A - Thin-film transistor and active matrix substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably obtain good properties of a thin-film transistor. <P>SOLUTION: The thin-film transistor (135) includes: a first ohmic contact layer (139A); a second ohmic layer (139B) disposed a predetermined distance apart from the first ohmic layer (139A); a source electrode (138) at least part of which is formed on the first ohmic layer (139A); a drain electrode (137) at least part of which is formed on the second ohmic layer (139B); and a semiconductor layer (140) which is formed on the first ohmic layer (139A), the second ohmic layer (139B), the source electrode (138) and the drain electrode (137). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thin film transistor and an active matrix substrate. More specifically, the present invention relates to a thin film transistor that can be used for a liquid crystal display, a flat panel display using an EL (electroluminescence) display such as an organic EL or an inorganic EL, an image sensor, and the like. The present invention relates to a matrix substrate.

  A conventional active matrix substrate having a top gate type amorphous silicon TFT element has a structure as shown in Non-Patent Document 1, for example.

  FIG. 5A shows a plan view of a conventional active matrix substrate 500.

  As shown in FIG. 5A, in the active matrix substrate 500, a plurality of signal lines 503 are provided in parallel with each other, and a plurality of scanning lines 504 are in parallel with each other so as to be orthogonal to each signal line 503. Is provided. A plurality of pixel electrodes 506 are provided so as to cover a region surrounded by each signal line 503 and each scanning line 504.

  A thin film transistor (hereinafter referred to as TFT) 505 is provided in the vicinity of the intersection where each signal line 503 and each scanning line 504 intersect.

  The TFT 505 includes a gate electrode 512, a source electrode 508, and a drain electrode 507. A gate electrode 512 of the TFT 505 extends from the scanning line 504, and a source electrode 508 of the TFT 505 extends from the signal line 503. The drain electrode 507 of the TFT 505 is connected to the drain electrode connection wiring 516, and the drain electrode connection wiring 516 is connected to the pixel electrode 506 through the contact hole 515.

  FIG. 5B is a cross-sectional view taken along line A-A ′ in FIG. 5A, showing the structure in the vicinity of the TFT 505.

  As shown in FIG. 5B, in the active matrix substrate 500, a base coat 502 made of silicon nitride or the like is provided on the entire surface of a glass substrate 501. On the base coat 502, a signal line 503, a source electrode 508, a drain electrode 507, and a drain electrode connection wiring 516 are provided. As described above, the source electrode 508 extends from the signal line 503. The source electrode 508 and the drain electrode 507 are arranged on the base coat 502 so as to be separated from each other at an appropriate interval. In the source electrode 508, a step portion is provided so as to face the drain electrode 507. Further, a step portion is provided in the drain electrode 507 so as to face the source electrode 508.

  A part of the source electrode 508 is covered with an ohmic contact layer 509A, and a part of the drain electrode 507 is covered with an ohmic contact layer 509B. The ohmic contact layer 509 </ b> A covers the step portion of the source electrode 508 and is in contact with the base coat 502. The ohmic contact layer 509 </ b> B covers the step portion of the drain electrode 507 and is in contact with the base coat 502.

  A semiconductor layer 510 made of i-type amorphous silicon is provided to cover the base coat 502 on the ohmic contact layer 509A and the ohmic contact layer 509B and between the ohmic contact layer 509A and the ohmic contact layer 509B. The source electrode 508 and the drain electrode 507 are electrically connected.

  A gate insulating film 511 made of silicon nitride is provided over the semiconductor layer 510, and a gate electrode 512 is provided over the gate insulating film 511. As described above, the gate electrode 512 extends from the scanning line 504.

  Further, a protective film 513 is provided over the entire glass substrate 501 so as to cover the base coat 502, the signal line 503, the source electrode 508, the gate electrode 512, the drain electrode 507, and the drain electrode connection wiring 516.

  An interlayer insulating film 514 is provided over the protective film 513, and a pixel electrode 506 is formed on the surface of the interlayer insulating film 514.

  FIG. 5C is a cross-sectional view taken along line B-B ′ in FIG. 5A, showing a structure in the vicinity of the contact hole 515 from the scanning line 504.

  As shown in FIG. 5C, the above-described base coat 502 is provided on the entire surface of the glass substrate 501.

  On the base coat 502, the drain electrode connection wiring 516 and the semiconductor layer 510 are each provided in a predetermined pattern.

  A gate insulating film 511 is stacked over the semiconductor layer 510, and a scanning line 504 is stacked over the gate insulating film 511.

  The base coat 502, the drain electrode connection wiring 516, and the scanning line 504 are covered with a protective film 513, and an interlayer insulating film 514 is provided so as to cover the protective film 513.

  A part of the interlayer insulating film 514 is removed so that the drain electrode connection wiring 516 is exposed.

  A pixel electrode 506 is provided on the interlayer insulating film 514, and a contact hole 515 is provided so as to be in contact with the drain electrode connection wiring 516 from which the pixel electrode 506 is exposed.

  Here, referring again to FIG. 5B, in the active matrix substrate 500, the current (drain current) flowing between the source electrode 508 and the drain electrode 507 is controlled by the voltage applied to the gate electrode 512. In the active matrix substrate 500, when a predetermined voltage is applied to the gate electrode 512, the drain current is disposed on the source electrode 508, the ohmic contact layer 509A disposed on the source electrode 508, the semiconductor layer 510, and the drain electrode 507. The ohmic contact layer 509 </ b> B and the drain electrode 507 flowed in the reverse direction or the reverse direction.

  Next, a method for manufacturing such an active matrix substrate 500 will be described.

  FIG. 6 is a cross-sectional view showing a method for manufacturing the active matrix substrate 500. In FIG. 6, the A-A ′ line corresponds to the A-A ′ line in FIG. 5B, and the B-B ′ line corresponds to the B-B ′ line in FIG. 5C.

  6A, first, a silicon nitride film to be the base coat 502 is formed on the entire surface of the glass substrate 501 by a sputtering method, and then a metal film made of aluminum or the like is formed on the base coat 502. The metal film is etched into a predetermined pattern by photolithography to form a signal line 503, a source electrode 508, a drain electrode 507, and a drain electrode connection wiring 516. A dry etching method is used for the etching at this time. Since the source electrode 508 and the drain electrode 507 are formed in this manner, the end portions of the source electrode 508 and the drain electrode 507 serve as step portions.

  Next, an n + type silicon film to be the ohmic contact layer 509A and the ohmic contact layer 509B is formed by a CVD method, and etched into a predetermined pattern by photolithography to form ohmic contact layers 509A and 509B. A dry etching method is also used for the etching process at this time.

  In FIG. 6B, i-type amorphous silicon to be the semiconductor layer 510 and silicon nitride to be the gate insulating film 511 are formed by CVD, and then a metal film to be the gate electrode 512 and the scanning line 504 is formed by sputtering. Is deposited. These are etched by photolithography and patterned into a predetermined pattern. A dry etching method is also used for the etching process at this time. Thus, the semiconductor layer 510, the gate insulating film 511, the gate electrode 512, and the scanning line 504 are formed.

  Next, in FIG. 6C, a silicon nitride film to be the protective film 513 is formed by a CVD method. Subsequently, an acrylic photosensitive resin to be the interlayer insulating film 514 is applied, and exposure, development, baking, and the like are performed, so that the interlayer insulating film 514 is formed.

  Subsequently, a part of the silicon nitride film is patterned by dry etching to remove a part of the silicon nitride film so that the drain electrode connection wiring 516 is exposed.

  Further, an aluminum film is formed thereon by sputtering and patterned into a predetermined pattern by photolithography, thereby forming a pixel electrode 506. A wet etching method is used for the etching process at this time. Thus, the contact hole 515 where the exposed drain electrode connection wiring 516 and the pixel electrode 506 are in contact is formed.

  As described above, the active matrix substrate 500 can be manufactured.

  Next, another conventional active matrix substrate will be described.

  FIG. 7A is a plan view of another conventional active matrix substrate 700.

  7A, the plan view structure of the active matrix substrate 700 is the same as the plan view structure of the active matrix substrate 500 described with reference to FIG. 5A.

  FIG. 7B is a cross-sectional view taken along line A-A ′ in FIG. 7A, showing the structure in the vicinity of the TFT 705. Also in FIG. 7B, the structure of the cross-sectional view of the active matrix substrate 700 is as shown in FIG. 5B except that the structure of the ohmic contact layer 717A and the ohmic contact layer 717B is different from the structure of the ohmic contact layer 509A and the ohmic contact layer 509B. This is the same as the structure of the sectional view of the active matrix substrate 500 described above.

  The ohmic contact layer 509A and the ohmic contact layer 509B illustrated in FIG. 5B are in contact with the base coat 502, whereas the ohmic contact layer 717A and the ohmic contact layer 717B illustrated in FIG. 7B are not in contact with the base coat 702. In FIG. 7B, the ohmic contact layer 717A is not provided so as to cover the step portion of the source electrode 708, and the ohmic contact layer 717B is not provided so as to cover the step portion of the drain electrode 707. In other words, a region where the ohmic contact layer 717A is formed is included in a region where the source electrode 708 is formed, and a region where the ohmic contact layer 717B is formed is a region where the drain electrode 707 is formed. include.

  FIG. 7C is a cross-sectional view taken along line B-B ′ in FIG. 7A, showing a structure in the vicinity of the contact hole 715 from the scanning line 704.

  7C, the structure of the active matrix substrate 700 taken along line B-B ′ in FIG. 7A is the same as the structure of the active matrix substrate 500 taken along line B-B ′ described with reference to FIG. 5C.

  Also in the active matrix substrate 700, the drain current flowing between the source electrode 708 and the drain electrode 707 is controlled by the voltage applied to the gate electrode 712. Also in the active matrix substrate 700, when a predetermined voltage is applied to the gate electrode 712, the drain current is disposed on the source electrode 708, the ohmic contact layer 717A disposed on the source electrode 708, the semiconductor layer 710, and the drain electrode 707. The ohmic contact layer 717B, the drain electrode 707, or the opposite direction of the flow flows.

  The structure of the ohmic contact layers 717A and 717B in the active matrix substrate 700 is different from the structure of the ohmic contact layers 509A and 509B in the active matrix substrate 500. In the active matrix substrate 700, the ohmic contact layer 717A, the ohmic contact layer 717B, the signal line 703, the source electrode 708, the drain electrode 707, and the drain electrode connection wiring 716 can be formed by the same photolithography. In addition, the active matrix substrate 700 can reduce photolithography in the manufacturing process once compared to the active matrix substrate 500. Therefore, the manufacturing cost of the active matrix substrate 700 can be suppressed.

  A method for manufacturing the active matrix substrate 700 will be described below.

  FIG. 8 is a cross-sectional view showing a method for manufacturing the active matrix substrate 700. In FIG. 8, the A-A ′ line corresponds to the A-A ′ line in FIG. 7B, and the B-B ′ line corresponds to the B-B ′ line in FIG. 7C.

  In FIG. 8A, a silicon nitride film to be the base coat 702 is formed over the entire surface of the glass substrate 701 by a sputtering method. Next, a metal film made of aluminum or the like to be the signal line 703, the source electrode 708, the drain electrode 707, and the drain electrode connection wiring 716 is formed over the base coat 702.

  On top of this, n + -type silicon 720 that will later become ohmic contact layers 717A and 717B is formed by CVD.

  Subsequently, the metal film and the n + type silicon 720 are etched by the same photolithography to be patterned into a predetermined pattern. As described above, in the manufacturing method of the active matrix substrate 700, the metal film and the n + -type silicon 720 are patterned by the same photolithography, so that the photomask is different from the manufacturing method of the active matrix substrate 500 described with reference to FIG. The number of lithography can be reduced. A dry etching method is used for the etching process at this time. At this stage, the pattern of the n + -type silicon film 720 is the same as the pattern of the signal line 703, the source electrode 708, the drain electrode 707, and the drain electrode connection wiring 716.

  In FIG. 8B, i-type amorphous silicon to be the semiconductor layer 710 and silicon nitride to be the gate insulating film 711 are formed by CVD, and then a metal film is formed by sputtering. These are etched by photolithography and patterned into a predetermined pattern. In this etching step, the n + type silicon film 720 is also patterned again by using a dry etching method. In this manner, the semiconductor layer 710, the gate insulating film 711, the gate electrode 712, the scanning line 704, the ohmic contact layer 717A, and the ohmic contact layer 717B are formed.

  In FIG. 8C, as described with reference to FIG. 6C, the protective film 713, the interlayer insulating film 714, the contact hole 715, and the pixel electrode 706 are formed.

Liquid Crystal Display Technology-Active Matrix LCD-P. 56-P. 57

  In the TFT 505 of the active matrix substrate 500, an ohmic contact layer 509 </ b> A, an ohmic contact layer 509 </ b> B, and a semiconductor layer 510 are provided over the step portion of the source electrode 508 or the drain electrode 507 in the region 518. In view of the current path of the active matrix substrate 500, the step coverage of the ohmic contact layer 509A, the ohmic contact layer 509B, and the semiconductor layer 510 in this region 518 is very important in order to obtain good characteristics of the TFT 505. It is.

  The step coverage of the ohmic contact layer 509A, the ohmic contact layer 509B, and the semiconductor layer 510 is greatly affected by the cross-sectional shape of the source electrode 508 or the drain electrode 507 and the film thickness of the source electrode 508 or the drain electrode 507.

  When the step of the step portion of the source electrode 508 or the drain electrode 507 formed by etching is steep, the ohmic contact layer 509A, the ohmic contact layer 509B, and the semiconductor layer 510 are in a poor step coverage state. Specifically, in the vicinity of the step portion of the source electrode 508 or the drain electrode 507, the ohmic contact layer 509A, the ohmic contact layer 509B, and the semiconductor layer 510 are in a state where cracks or nests are formed. At this time, the semiconductor layer 510 in the vicinity of the step portion of the source electrode 508 or the drain electrode 507 does not have a target property and adversely affects the characteristics of the TFT 505.

  Further, as the thickness of the source electrode 508 or the drain electrode 507 is larger, the lengths of the step portions of the ohmic contact layers 509A and 509B and the semiconductor layer 510 that perform step coverage become longer. Easy to spread. As a result, the characteristics of the TFT 505 are adversely affected.

  Thus, when the step coverage of the ohmic contact layers 509A and 509B and the semiconductor layer 510 in the step portion of the source electrode 508 or the drain electrode 507 is poor, good characteristics of the TFT 505 cannot be obtained. As an example, in a similar structure shown in the document “Top-gate а-Si TFT and its application, Ikuhiro Tsukai, Press Journal Co., Ltd.”, the step angle of the step portion of the source electrode 508 or the drain electrode 507 is the active matrix substrate. It is said that it should be 40 degrees or less with respect to 500 planes.

  However, it is not easy to form the step portions of the source electrode 508 and the drain electrode 507 in the active matrix substrate 500 so as to be stably at 40 degrees or less as in the previous example, and the process is greatly restricted. Will give. In particular, when these are formed by laminated multilayer metal films, it is difficult to reduce the step angle because the etching rate differs for each metal film to be formed. For these reasons, it is difficult to improve the step coverage of the ohmic contact layer 509A, the ohmic contact layer 509B, and the semiconductor layer 510 in the region 518, and it is difficult to stably obtain good characteristics of the TFT 505.

  Furthermore, in the active matrix substrate 500 that is becoming increasingly larger in recent years, the thickness of the signal line 503 must be increased. For convenience of manufacturing, the film thickness of the source electrode 508 and the drain electrode 507 formed simultaneously with the signal line 503 also increases accordingly. When the active matrix substrate 500 is used for a liquid crystal display, the signal line 503, the source electrode 508, and the drain electrode 507 generally require a film thickness of at least 1500 mm for driving the display. Even in the aluminum wiring, which is currently said to have the lowest resistance, for example, a large display of 20 inches UXGA class or higher requires the same film thickness. However, the film thickness in this case is a thickness including a metal layer such as a barrier metal layer necessary for an aluminum wiring, for example.

  These factors greatly impose restrictions on the selection of metal used for wiring or wiring formation in the conventional manufacturing process, and may impair the stability of the process. In particular, in the case where the source electrode 508 or the drain electrode 507 having a large film thickness is used for a panel to be enlarged, the manufacturing process is further difficult. This is a structural defect of the active matrix substrate 500 having the conventional top gate type TFT.

  The same applies to the active matrix substrate 700.

  Similarly, it is difficult for the active matrix substrate 700 to improve the step coverage of the semiconductor layer 710 in the region 719 with respect to the ohmic contact layer 717A and the source electrode 708 or the ohmic contact layer 717B and the drain electrode 707. It is very difficult to uniformly manufacture an active matrix substrate 700 including TFTs 705 having good characteristics.

  These impose great restrictions on the selection of metal used for wiring or wiring formation in the manufacturing method of the active matrix substrate 700, and impair process stability. In particular, in the case where the source electrode 708 or the drain electrode 707 having a large film thickness is used for a panel to be enlarged, the manufacturing method becomes more difficult. This is a structural defect of an active matrix substrate having a conventional top gate type TFT.

  The thin film transistor of the present invention is provided with a substrate, a first ohmic contact layer provided on the substrate, and the first ohmic contact layer separated on the substrate at an appropriate interval. A second ohmic contact layer; a source electrode provided at least in part on the first ohmic contact layer; and a drain electrode provided at least in part on the second ohmic contact layer; The first ohmic contact layer, the second ohmic contact layer, the source so as to be in contact with the first ohmic contact layer, the second ohmic contact layer, the source electrode, and the drain electrode A semiconductor layer provided on the electrode and the drain electrode; a gate insulating film provided on the semiconductor layer; And a gate electrode provided on the gate insulating film.

  The shape of the first ohmic contact layer region is substantially the same as the shape of the source electrode region, and the shape of the second ohmic contact layer region is substantially the same as the shape of the drain electrode region. May be identical.

  The ohmic contact layer may be made of n + type silicon.

  The active matrix substrate of the present invention includes a plurality of thin film transistors described above, a plurality of signal lines connected to source electrodes of the thin film transistors, and a plurality of scanning lines connected to gate electrodes of the thin film transistors. And a plurality of pixel electrodes respectively connected to the drain electrodes of the thin film transistors.

  The substrate may be a plastic substrate or a substrate having at least one surface covered with a resin.

  According to the present invention, in the thin film transistor formed on the active matrix substrate, the ohmic contact layer is disposed under the source electrode and the drain electrode, so that the path of the drain current between the source electrode and the drain electrode is changed from the conventional one. ing. As a result, the characteristics of the thin film transistor can be satisfactorily and stably formed, and an advantage in the manufacturing process can be obtained.

  Further, according to the present invention, photolithography of the ohmic contact layer can be performed together with photolithography of the source electrode and drain electrode of the thin film transistor, and the number of photolithography can be minimized. Thereby, the manufacturing cost can be suppressed.

  Further, according to the present invention, since the ohmic contact layer is made of n + type amorphous silicon, the step of the ohmic contact layer can be easily provided, and the characteristics of the thin film transistor are improved.

  In addition, according to the present invention, the manufacturing cost of the active matrix substrate including the thin film transistor described above is suppressed, and the manufacturing process is stabilized.

  In addition, according to the present invention, an active matrix substrate can be manufactured with a small amount of photolithography, so that the present invention is particularly suitable for forming an active matrix substrate on a substrate having a large dimensional change such as a plastic substrate. When the dimensional change of the substrate is large, alignment for each photolithography becomes difficult. Therefore, it is advantageous to manufacture an active matrix substrate by a minimum number of photolithography.

FIG. 1A shows a plan view of an active matrix substrate according to Embodiment 1 of the present invention. FIG. 1B is a cross-sectional view taken along line A-A ′ in FIG. 1A, showing the structure in the vicinity of the TFT. FIG. 1C is a cross-sectional view taken along line B-B ′ in FIG. 1A, showing a structure near the contact hole from the scanning line. FIG. 2 is a cross-sectional view showing the method of manufacturing the active matrix substrate according to the first embodiment. FIG. 3A shows a plan view of an active matrix substrate according to Embodiment 2 of the present invention. FIG. 3B is a cross-sectional view taken along the line A-A ′ in FIG. 3A, showing the structure near the TFT. FIG. 3C is a cross-sectional view taken along line B-B ′ in FIG. 3A, showing the structure near the contact hole from the scanning line. FIG. 4 is a cross-sectional view showing a method of manufacturing the active matrix substrate according to the second embodiment. FIG. 5A shows a plan view of a conventional active matrix substrate. FIG. 5B is a cross-sectional view taken along line A-A ′ in FIG. 5A, showing the structure in the vicinity of the TFT. FIG. 5C is a cross-sectional view taken along line B-B ′ in FIG. 5A, showing the structure near the contact hole from the scanning line. FIG. 6 is a cross-sectional view showing a conventional method for manufacturing an active matrix substrate. FIG. 7A is a plan view of another conventional active matrix substrate. FIG. 7B is a cross-sectional view taken along line A-A ′ in FIG. 7A, showing the structure in the vicinity of the TFT. FIG. 7C is a cross-sectional view taken along line B-B ′ in FIG. 7A, showing the structure near the contact hole from the scanning line. FIG. 8 is a cross-sectional view showing another conventional method for manufacturing an active matrix substrate.

(Embodiment 1)
FIG. 1A shows a plan view of an active matrix substrate 100 according to the first embodiment.

  As shown in FIG. 1A, in the active matrix substrate 100, a plurality of signal lines 133 are provided in parallel with each other, and a plurality of scanning lines 134 are in parallel with each other so as to be orthogonal to each signal line 133. Is provided. A plurality of pixel electrodes 136 are provided so as to cover a region surrounded by each signal line 133 and each scanning line 134.

  In the vicinity of the intersection where each signal line 133 and each scanning line 134 intersect, a thin film transistor (hereinafter referred to as TFT) 135 is provided.

  The TFT 135 includes a gate electrode 142, a source electrode 138, and a drain electrode 137. The gate electrode 142 of the TFT 135 extends from the scanning line 134, and the source electrode 138 of the TFT 135 extends from the signal line 133. The drain electrode 137 of the TFT 135 is connected to the drain electrode connection wiring 146, and the drain electrode connection wiring 146 is connected to the pixel electrode 136 through the contact hole 145.

  FIG. 1B is a cross-sectional view taken along line A-A ′ in FIG. 1A, showing a structure in the vicinity of the TFT 135.

  As shown in FIG. 1B, a base coat 132 made of silicon nitride is provided on the glass substrate 131 over the entire surface of the glass substrate 131.

  On the base coat 132, an n + type silicon ohmic contact layer 139A and an ohmic contact layer 139B are provided in an island shape with an appropriate interval.

  The ohmic contact layer 139A and the ohmic contact layer 139B are preferably composed of a single layer of n + type amorphous silicon.

  In this case, the step portions of the ohmic contact layer 139A and the ohmic contact layer 139B can be easily formed at a desired step, whereby the characteristics of the TFT 335 are improved. However, the ohmic contact layer 139A and the ohmic contact layer 139B are not necessarily limited to this.

  In the present embodiment, the size of each of the ohmic contact layer 139A and the ohmic contact layer 139B is vertical: 15 μm, horizontal: 10 μm, and the film thickness is 300 mm.

  At least a part of the source electrode 138 is provided so as to cover the ohmic contact layer 139A, and at least a part of the source electrode 138 covers the base coat 132. At least a part of the drain electrode 137 is provided so as to cover the ohmic contact layer 139B, and at least a part of the drain electrode 137 covers the base coat 132.

  As described above, the source electrode 138 is provided so as to extend from the signal line 133, and the drain electrode 137 is provided integrally with the drain electrode connection wiring 146. The signal line 133, the source electrode 138, the drain electrode 137, and the drain electrode connection wiring 146 are preferably formed of the same material from the viewpoint of manufacturing cost.

  The semiconductor layer 140 made of i-type amorphous silicon covers the base coat 132 between the ohmic contact layer 139A and the ohmic contact layer 139B, and covers the ohmic contact layer 139A, the ohmic contact layer 139B, the source electrode 138, and the drain electrode 137. It is provided to touch.

  A gate insulating film 141 is stacked over the semiconductor layer 140, and a gate electrode 142 is stacked over the gate insulating film 141.

  Here, the line width of the gate electrode 142, the gate insulating film 141, and the semiconductor layer 140 is 15 μm.

  The ohmic contact layer 139 </ b> A and the ohmic contact layer 139 </ b> B are provided so that the step portion and a part of the upper surface thereof are in contact with the semiconductor layer 140.

  The base coat 132 is provided for the purpose of improving the adhesion between the glass substrate 131 and the semiconductor layer 140. The material of the base coat 132 is not limited to silicon nitride, and the material of the base coat 132 may be many materials such as silicon oxide and tantalum oxide. It should also be noted that the base coat 132 itself is not necessarily required for the thin film transistor according to the present invention.

  The material constituting the ohmic contact layers 139A and 139B is not necessarily n + type silicon.

  Further, a protective film 143 made of silicon nitride or the like is provided so as to cover the base coat 132, the signal line 133, the source electrode 138, the gate electrode 142, the drain electrode 137, and the drain electrode connection wiring 146.

  An interlayer insulating film 144 made of an acrylic photosensitive resin is provided so as to cover the protective film 143.

  A pixel electrode 136 made of aluminum or the like is provided on the surface of the interlayer insulating film 144.

  FIG. 1C is a cross-sectional view taken along line B-B ′ in FIG. 1A, showing a structure in the vicinity of the contact hole 145 from the scanning line 134.

  As shown in FIG. 1C, the above-described base coat 132 is provided over the entire surface of the glass substrate 131.

  On the base coat 132, the drain electrode connection wiring 146 and the semiconductor layer 140 are provided in a predetermined pattern.

  A gate insulating film 141 is stacked on the semiconductor layer 140, and a scanning line 134 is stacked on the gate insulating film 141.

  A protective film 133 is provided so as to cover the base coat 132, the drain electrode connection wiring 146 and the scanning line 134.

  An interlayer insulating film 144 is provided so as to cover the protective film 133.

  A part of the interlayer insulating film 144 is removed so that the drain electrode connection wiring 146 is exposed.

  A pixel electrode 136 is provided on the interlayer insulating film 144, and a contact hole 145 is provided so as to contact the drain electrode connection wiring 146 where the pixel electrode 136 is exposed.

  Here, in the active matrix substrate 100, both the protective film 143 and the interlayer insulating film 144 are not necessarily required, and only one of them may be used in the structure of the present embodiment. In the above description, the materials of the protective film 143 and the interlayer insulating film 144 are silicon nitride and acrylic photosensitive resin, respectively, but are not limited thereto, and may be other materials. Similarly, the material of the pixel electrode 136 is not limited to aluminum, and may be an aluminum alloy, a silver alloy, or a laminate of other metals.

  In the active matrix substrate 100, a plurality of signal lines 133 made of an alloy of titanium and aluminum, a source electrode 138, a drain electrode 137, a plurality of signal lines 133 and an insulating film (same layer as the gate insulating film 141) are formed on the base coat 132. A plurality of scanning lines 134 made of titanium intersecting with each other are arranged. Here, the signal line 133 and the scanning line 134 are not limited to titanium and aluminum, but tantalum, chromium, molybdenum, tungsten, niobium, or the like, or nitrides or oxides thereof, ITO (indium tin oxide), silver alloy, or the like. However, it may be composed of a single layer or a stacked layer.

  Here, referring again to FIG. 1B, in the active matrix substrate 100, the current (drain current) flowing between the source electrode 138 and the drain electrode 137 is controlled by the voltage applied to the gate electrode 142.

  In the active matrix substrate 100, when a predetermined voltage is applied to the gate electrode 142, the drain current is disposed under the source electrode 138, the ohmic contact layer 139 A disposed under the source electrode 138, the semiconductor layer 140, and the drain electrode 137. The ohmic contact layer 139B, the drain electrode 137, or the opposite direction of the ohmic contact layer 139B flows.

  Here, in the two conventional examples described above, since the ohmic contact layer and / or the semiconductor layer formed so as to cover the step portions of the source electrode and the drain electrode are used as the path of the drain current, the source electrode and the drain electrode If these steps are gently formed and the semiconductor layer is not well covered, good TFT characteristics cannot be obtained.

  However, in this embodiment, unlike such a conventional example, the ohmic contact layer 139A and the ohmic contact layer 139B are provided below the source electrode 138 or the drain electrode 137 (on the glass substrate 131 side). As part of the drain current path. Thereby, the characteristics of the TFT 135 in the active matrix substrate 100 according to the present embodiment are not affected by the step coverage of the semiconductor layer 140 with respect to the step portions of the source electrode 138 and the drain electrode 137. In this embodiment, the step coverage of the semiconductor layer 140 with respect to the ohmic contact layer 139A and the ohmic contact layer 139B can affect the characteristics of the TFT 135, but this influence can be easily reduced as compared with the conventional example.

  In this embodiment mode, the source electrode 138 or the drain electrode 137 is formed with a thickness of 1500 mm in accordance with a driving request. The ohmic contact layer 139A and the ohmic contact layer 139B are formed to a thickness of 300 mm, which is much thinner than the source electrode 138 or the drain electrode 137. Here, even if the film thickness of the ohmic contact layer 139A and the ohmic contact layer 139B is 300 to 500 mm, the same effect can be obtained.

  In this embodiment, since the ohmic contact layer 139A and the ohmic contact layer 139B are thin, and the step portions of the ohmic contact layer 139A and the ohmic contact layer 139B are short, even if the ohmic contact layer 139A and the ohmic contact layer 139B are Even if the step is not a good step, the portion with poor step coverage remains in a much narrower region, and the influence on the characteristics of the TFT 135 can be greatly reduced.

  In addition, since the ohmic contact layer 139A and the ohmic contact layer 139B have a single-layer structure made of only n + type silicon, the step portion can be easily formed in steps.

  These two factors overlap, and in this embodiment, the step coverage of the semiconductor layer 140 can be formed better than the conventional example, and the good TFT 135 can be formed uniformly.

  In the conventional example described above, it is not easy for the semiconductor layer to have good step coverage with respect to the steps of the source electrode and the drain electrode. However, in the active matrix substrate 100 of the present embodiment, the path of the drain current is changed. Therefore, unlike the conventional example, the active matrix substrate 100 including the TFT 135 having good characteristics can be stably manufactured.

  Next, a method for manufacturing the active matrix substrate 100 according to the present embodiment will be described.

  FIG. 2 is a cross-sectional view showing a method for manufacturing the active matrix substrate 100 according to the present embodiment. In FIG. 2, the A-A ′ line corresponds to the A-A ′ line in FIG. 1B, and the B-B ′ line corresponds to the B-B ′ line in FIG. 1C.

  In FIG. 2A, a base coat 132 made of silicon nitride or the like is formed over the entire surface of the glass substrate 131 to a thickness of 1000 to 5000 by sputtering.

  Next, after forming an n + type silicon film with a film thickness of 300 mm by CVD, it is etched into a predetermined pattern by photolithography. Thereby, the ohmic contact layer 139A and the ohmic contact layer 139B are formed.

In this embodiment, this etching process uses a dry etching method in which the control of the steps is relatively easy. Here, RIE (reactive ion)
etching, reactive ion etching) type dry etching apparatus, introduced gas CF ₄ (carbon tetrafluoride) and O ₂ (oxygen), source output 5 mW / cm ^{2 to} 9 mW / cm ² , process chamber vacuum degree 50 mTorr to 200 mTorr Under the conditions of The step portion is formed by a resist receding method. However, this embodiment is not limited to such a dry etching method. In the above description, the film thickness of the n + type silicon film is 300 mm, but the film thickness of the n + type silicon film is preferably in the range of 300 to 500 mm.

  Next, a laminated film in which aluminum is formed to a thickness of 1000 Å and titanium is formed to a thickness of 500 に よ り is formed by a sputtering method.

  The laminated film is etched by photolithography and patterned into a predetermined pattern, whereby the signal line 133, the source electrode 138, the drain electrode 137, and the drain electrode connection wiring 146 are formed.

  The etching process at this time is preferably performed by a wet etching method in order to selectively etch the ohmic contact layers 139A and 139B without damaging them. Here, an aqueous solution containing hydrogen fluoride having a concentration of 0.5% to 2% and nitric acid having a concentration of 0.5% to 2% is used, but is not limited thereto.

  In FIG. 2B, an i-type amorphous silicon film that will later become the semiconductor layer 140 is formed by a CVD method to a film thickness of 1000 mm, and a silicon nitride film that will be the gate insulating film 141 is further formed.

  Next, titanium (film thickness 500 mm) and aluminum (film thickness 1000 mm) are sequentially formed by sputtering.

  Subsequently, the semiconductor layer 140, the gate insulating film 141, the gate electrode 142, and the scanning line 134 are formed by etching by photolithography and patterning into a predetermined pattern.

  A dry etching method is used for the etching process at this time. Here, etching is performed in two stages using the RIE method.

First, in the first stage, aluminum and titanium are introduced under the conditions of introduced gases BCl ₃ (boron trichloride) and Cl ₂ (chlorine), source output 5 mW / cm ^{2 to} 9 mW / cm ² , and process chamber vacuum 20 mTorr to 200 mTorr. Etch the film.

In the next second stage, a silicon nitride film under the conditions of introduced gas CF ₄ (carbon tetrafluoride) and O ₂ (oxygen), source output 5 mW / cm ^{2 to} 9 mW / cm ² , and process chamber vacuum 50 mTorr to 200 mTorr And i-type amorphous silicon are etched.

  In FIG. 2C, a silicon nitride film to be a protective film 143 later is formed by a CVD method. Subsequently, an acrylic photosensitive resin is applied, and exposure, development, baking, and the like are performed to form an interlayer insulating film 144 having a predetermined pattern.

  Subsequently, a part of the silicon nitride film is removed by a dry etching method. Further, an aluminum film is formed thereon by sputtering, and patterning is performed by photolithography to form pixel electrodes 136 and contact holes 145.

(Embodiment 2)
FIG. 3A shows a plan view of an active matrix substrate 300 according to Embodiment 2 of the present invention.

  In FIG. 3A, the structure of the plan view of the active matrix substrate 300 is the same as the structure of the plan view of the active matrix substrate 100 described with reference to FIG. 1A.

  FIG. 3B is a cross-sectional view taken along line A-A ′ in FIG. 3A, showing the structure in the vicinity of the TFT 335. Also in FIG. 3B, the structure of the active matrix substrate 300 in the cross-sectional view is the structure of the ohmic contact layer 349A, the ohmic contact layer 349B, the signal line 333, the source electrode 351, the drain electrode 350, and the drain electrode connection wiring 346. 139A, the ohmic contact layer 139B, the signal line 133, the source electrode 138, the drain electrode 137, and the structure of the sectional view of the active matrix substrate 100 described with reference to FIG. It is the same.

  In the active matrix substrate 100 described in Embodiment 1, at least a part of the source electrode 138 is in contact with the base coat 132 and at least a part of the drain electrode 137 is in contact with the base coat 132. In the active matrix substrate 300, the signal line 133 and the source electrode 138 are provided on the ohmic contact layer 349A, and the drain electrode 350 and the drain electrode connection wiring 346 are provided on the ohmic contact layer 349B.

  In other words, the region where the signal line 333 and the source electrode 351 are provided is included in the region where the ohmic contact layer 349A is provided, and the region where the drain electrode 350 and the drain electrode connection wiring 346 are provided is provided by the ohmic contact layer 349B. It is included in the provided area.

  FIG. 3C is a cross-sectional view taken along the line B-B ′ in FIG.

  In FIG. 3C, the structure of the cross-sectional view taken along line BB ′ in FIG. 3A of the active matrix substrate 300 refers to FIG. 1C except that an ohmic contact layer 349 is provided below the drain electrode connection wiring 346. This is the same as the structure of the cross-sectional view taken along the line BB ′ of the active matrix substrate 100 described above.

  The structures of the ohmic contact layer 349A and the ohmic contact layer 349B in the active matrix substrate 300 described above are different from the structures of the ohmic contact layers 139A and 139B in the active matrix substrate 100.

  In the active matrix substrate 300, the ohmic contact layer 349A, the source electrode 351, and part of the side surfaces of the signal line 333 are substantially on the same plane, and the ohmic contact layer 349B, the drain electrode 350, and part of the side surfaces of the drain electrode connection wiring 346 Are on the same plane.

  In the active matrix substrate 300, the ohmic contact layer 349A, the ohmic contact layer 349B, the signal line 333, the source electrode 351, the drain electrode 350, and the drain electrode connection wiring 346 are formed in the same photolithography process; Compared with the active matrix substrate 100 described in 1, photolithography can be reduced by one time, and thus the manufacturing cost of the active matrix substrate 300 can be suppressed.

  Hereinafter, a method for manufacturing the active matrix substrate 300 according to the present embodiment will be described.

  FIG. 4 is a cross-sectional view showing a method for manufacturing the active matrix substrate 300 according to the present embodiment. In FIG. 4, the A-A ′ line corresponds to the A-A ′ line in FIG. 3B, and the B-B ′ line corresponds to the B-B ′ line in FIG. 3C.

  As shown in FIG. 4A, a base coat 332 made of silicon nitride or the like is formed over the entire surface of the glass substrate 331 by sputtering.

  Next, an n + type silicon film (film thickness of 300 mm) is formed by CVD. Further, a laminated film in which aluminum (thickness: 1000 mm) and titanium (thickness: 500 mm) are formed in this order by sputtering is obtained. This laminated film will later become the signal line 333, the drain electrode 350, the source electrode 351, and the drain electrode connection wiring 346.

  In the present embodiment, these n + type silicon film and laminated film are etched by the same photolithography. As a result, the photolithography process is reduced once compared with the active matrix substrate 100 described in the first embodiment.

The etching process will be described in detail. First, using a resist film formed on the substrate as a mask, the n + type silicon film and the laminated film are patterned to have the same pattern by using a dry etching method. Here, dry etching is performed under the conditions of introduced gases BCl ₃ (boron trichloride) and Cl ₂ (chlorine), a source output of 5 mW / cm ^{2 to} 9 mW / cm ² , and a process chamber vacuum of 20 mTorr to 200 mTorr. However, the etching method is not limited to this.

  Subsequently, only a metal laminated film made of aluminum and titanium is formed by a wet etching method using an acid mixture made of an aqueous solution containing 0.5% to 2% hydrogen fluoride and 0.5% to 2% nitric acid. Etch shift in the film surface direction. However, this etching shift can be achieved by setting appropriate conditions even in the dry etching method, and is not limited to the wet etching method.

  Although the etching shift is performed as described above, the shape of the region of the ohmic contact layer 349A is substantially the same as the shape of the region of the source electrode 351, and the shape of the region of the ohmic contact layer 349B is The shape of the drain electrode 350 region is substantially the same.

  Similar to the active matrix substrate 100 according to Embodiment 1 described with reference to FIG. 2B, in FIG. 4B, i-type amorphous silicon, silicon nitride, and metal film are sequentially formed, and photolithography is performed. Patterning into a predetermined pattern. In this etching step, the n + -type silicon film 353 is further patterned to form an ohmic contact layer 349, an ohmic contact layer 349A, and an ohmic contact layer 349B.

  Similar to the active matrix substrate 100 described in Embodiment 1 with reference to FIG. 2C, as shown in FIG. 4C, a protective film 343, an interlayer insulating film 344, a contact hole 345, and a pixel electrode 336 are formed. Form.

  In the second embodiment, the same effect as in the first embodiment can be obtained.

  Also in the second embodiment, the drain current path is in order of the source electrode 351, the ohmic contact layer 349A disposed under the source electrode 351, the semiconductor layer 340, the ohmic contact layer 349B disposed under the drain electrode 350, and the drain electrode. The route is 350, or the opposite route.

  Also in this embodiment, unlike the conventional example, the ohmic contact layer 349A and the ohmic contact layer 349B are provided below the source electrode 351 or the drain electrode 350 (on the glass substrate 331 side), and this is part of the drain current path. It is said. Thereby, the characteristics of the TFT 335 in the active matrix substrate 300 of this embodiment are not affected by the step coverage of the semiconductor layer 340 with respect to the step portions of the source electrode 351 and the drain electrode 350. Therefore, it is easy to obtain good characteristics of the TFT 335.

  In the conventional example, since the drain current passes through the portion of the semiconductor layer made of i-type amorphous silicon over the step portion of the source electrode and the drain electrode, it is not easy to obtain good TFT characteristics. The active matrix substrate of the present invention is not affected by changing the path of the drain current so as to pass through the ohmic contact layer disposed below the source electrode and the drain electrode. An active matrix substrate having the same can be manufactured stably.

131 Glass substrate 132 Base coat 133 Signal line 134 Scan line 135 TFT
136 Pixel electrode 137 Drain electrode 138 Source electrode 139A, 139B Ohmic contact layer 140 Semiconductor layer 141 Gate insulating film 142 Gate electrode 143 Protective film 144 Interlayer insulating film 145 Contact hole 146 Drain electrode connection wiring

Claims (1)

A thin film transistor as described herein.

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