JP2009182274A5 - - Google Patents

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Publication number
JP2009182274A5
JP2009182274A5 JP2008022013A JP2008022013A JP2009182274A5 JP 2009182274 A5 JP2009182274 A5 JP 2009182274A5 JP 2008022013 A JP2008022013 A JP 2008022013A JP 2008022013 A JP2008022013 A JP 2008022013A JP 2009182274 A5 JP2009182274 A5 JP 2009182274A5
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JP
Japan
Prior art keywords
insulating resin
resin layer
protruding electrode
wiring layer
metal plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2008022013A
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Japanese (ja)
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JP5028291B2 (en
JP2009182274A (en
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Publication date
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Priority to JP2008022013A priority Critical patent/JP5028291B2/en
Priority claimed from JP2008022013A external-priority patent/JP5028291B2/en
Priority to CN2009101346932A priority patent/CN101540299B/en
Priority to US12/364,084 priority patent/US8309864B2/en
Publication of JP2009182274A publication Critical patent/JP2009182274A/en
Publication of JP2009182274A5 publication Critical patent/JP2009182274A5/ja
Application granted granted Critical
Publication of JP5028291B2 publication Critical patent/JP5028291B2/en
Active legal-status Critical Current
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Claims (8)

絶縁樹脂層と、
前記絶縁樹脂層の一方の主表面に設けられた配線層と、
前記配線層と電気的に接続され、前記配線層から前記絶縁樹脂層側に突出している突起電極と、を備え、
前記突起電極の側面は、突起電極の中心軸を含む断面視で前記中心軸方向に湾曲するとともに、側面の曲率半径が配線層側端部から先端側端部にかけて連続的に変化することを特徴とする素子搭載用基板。 An insulating resin layer;
A wiring layer provided on one main surface of the insulating resin layer;
A protruding electrode that is electrically connected to the wiring layer and protrudes from the wiring layer toward the insulating resin layer,
The side surface of the protruding electrode is curved in the direction of the central axis in a cross-sectional view including the central axis of the protruding electrode, and the curvature radius of the side surface continuously changes from the wiring layer side end to the tip side end. An element mounting board. 前記側面の曲率半径は、前記配線層側端部および前記先端側端部の近傍よりも中央領域で小さいことを特徴とする請求項１に記載の素子搭載用基板。   2. The element mounting substrate according to claim 1, wherein a radius of curvature of the side surface is smaller in a central region than in the vicinity of the wiring layer side end and the tip end. 前記突起電極の基底部の径に対する頂部の径の比率は、０．２５〜０．６０であることを特徴とする請求項１または２に記載の素子搭載用基板。   The element mounting substrate according to claim 1, wherein a ratio of a diameter of a top portion to a diameter of a base portion of the protruding electrode is 0.25 to 0.60. 絶縁樹脂層と、
前記絶縁樹脂層の一方の主表面に設けられた配線層と、
前記配線層と電気的に接続され、前記配線層から前記絶縁樹脂層側に突出している突起電極と、を備え、
前記突起電極は、略富士山形状であることを特徴とする素子搭載用基板。 An insulating resin layer;
A wiring layer provided on one main surface of the insulating resin layer;
A protruding electrode that is electrically connected to the wiring layer and protrudes from the wiring layer toward the insulating resin layer,
The protruding electrode has a substantially Mt. Fuji shape. 請求項１ないし４のいずれか１項に記載の素子搭載用基板と、
前記突起電極に対向する素子電極が設けられた半導体素子と、
を備え、
前記突起電極が前記絶縁樹脂層を貫通し、前記突起電極と前記素子電極とが電気的に接続されていることを特徴とする半導体モジュール。 The element mounting substrate according to any one of claims 1 to 4,
A semiconductor element provided with an element electrode facing the protruding electrode;
With
The semiconductor module, wherein the protruding electrode penetrates the insulating resin layer, and the protruding electrode and the element electrode are electrically connected. 金属板の一方の主表面の所定領域にマスクを設けた状態でエッチング液を吹き付けて、前記マスクの中心軸を含む断面視で、側面が前記中心軸方向に湾曲するとともに、前記側面の曲率半径が金属板側端部から先端側端部にかけて連続的に変化する突起電極を形成すAn etching solution is sprayed in a state where a mask is provided in a predetermined region of one main surface of the metal plate, and the side surface is curved in the direction of the central axis in a cross-sectional view including the central axis of the mask, and the curvature radius of the side surface Forms protruding electrodes that continuously change from the metal plate side end to the tip side end
る工程と、And the process
前記突起電極が形成された側の前記金属板の主表面に絶縁樹脂層を積層する工程と、Laminating an insulating resin layer on the main surface of the metal plate on the side where the protruding electrodes are formed;
前記金属板を選択的に除去して配線層を形成する工程と、Selectively removing the metal plate to form a wiring layer;
を含むことを特徴とする素子搭載用基板の製造方法。A method for manufacturing an element mounting board, comprising: 金属板の一方の主表面の所定領域にマスクを設けた状態でエッチング液を吹き付けて、前記マスクの中心軸を含む断面視で、側面が前記中心軸方向に湾曲するとともに、前記側面の曲率半径が金属板側端部から先端側端部にかけて連続的に変化する突起電極を形成する工程と、An etching solution is sprayed in a state where a mask is provided in a predetermined region of one main surface of the metal plate, and the side surface is curved in the direction of the central axis in a cross-sectional view including the central axis of the mask, and the curvature radius of the side surface Forming a protruding electrode that continuously changes from the metal plate side end to the tip side end,
前記金属板と、前記突起電極に対応する素子電極が設けられた半導体素子とを、絶縁樹脂層を介して圧着し、前記突起電極が前記絶縁樹脂層を貫通することにより、前記突起電極と前記素子電極とを電気的に接続させる圧着工程と、The metal plate and a semiconductor element provided with an element electrode corresponding to the protruding electrode are pressure-bonded via an insulating resin layer, and the protruding electrode penetrates the insulating resin layer. A crimping step for electrically connecting the device electrodes;
前記金属板を選択的に除去して配線層を形成する工程と、  Selectively removing the metal plate to form a wiring layer;
を含むことを特徴とする半導体モジュールの製造方法。A method for manufacturing a semiconductor module, comprising: 前記絶縁樹脂層は、加圧によって塑性流動を起こすことを特徴とする請求項７に記載の半導体モジュールの製造方法。 The method for manufacturing a semiconductor module according to claim 7 , wherein the insulating resin layer causes plastic flow by pressurization .
JP2008022013A 2008-01-31 2008-01-31 Device mounting substrate, device mounting substrate manufacturing method, semiconductor module, and semiconductor module manufacturing method Active JP5028291B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008022013A JP5028291B2 (en) 2008-01-31 2008-01-31 Device mounting substrate, device mounting substrate manufacturing method, semiconductor module, and semiconductor module manufacturing method
CN2009101346932A CN101540299B (en) 2008-01-31 2009-02-01 Device mounting board, semiconductor module and manufacturing method thereof , and portable equipment
US12/364,084 US8309864B2 (en) 2008-01-31 2009-02-02 Device mounting board and manufacturing method therefor, and semiconductor module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008022013A JP5028291B2 (en) 2008-01-31 2008-01-31 Device mounting substrate, device mounting substrate manufacturing method, semiconductor module, and semiconductor module manufacturing method

Publications (3)

Publication Number Publication Date
JP2009182274A JP2009182274A (en) 2009-08-13
JP2009182274A5 true JP2009182274A5 (en) 2011-03-10
JP5028291B2 JP5028291B2 (en) 2012-09-19

Family

ID=41035973

Family Applications (1)

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JP2008022013A Active JP5028291B2 (en) 2008-01-31 2008-01-31 Device mounting substrate, device mounting substrate manufacturing method, semiconductor module, and semiconductor module manufacturing method

Country Status (2)

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JP (1) JP5028291B2 (en)
CN (1) CN101540299B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101669534B1 (en) * 2009-12-07 2016-10-26 해성디에스 주식회사 Circuit board with bumps and method of manufacturing the same
JP5830702B2 (en) * 2010-04-28 2015-12-09 パナソニックＩｐマネジメント株式会社 Circuit device manufacturing method
US9398389B2 (en) * 2013-05-13 2016-07-19 Knowles Electronics, Llc Apparatus for securing components in an electret condenser microphone (ECM)
JP7226472B2 (en) 2020-05-26 2023-02-21 株式会社村田製作所 Electronic components with component interconnection elements

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5823943B2 (en) * 1975-07-16 1983-05-18 松下電器産業株式会社 Method for forming through electrodes in insulators
DE69634597T2 (en) * 1995-11-17 2006-02-09 Kabushiki Kaisha Toshiba, Kawasaki MULTILAYERED PCB, PRE-PRODUCED MATERIAL FOR THIS PCB, METHOD FOR PRODUCING A MULTILAYER PCB, PACKAGING OF ELECTRONIC COMPONENTS AND METHOD FOR PRODUCING VERTICAL, ELECTRICALLY CONDUCTIVE CONNECTIONS
JP2951882B2 (en) * 1996-03-06 1999-09-20 松下電器産業株式会社 Semiconductor device manufacturing method and semiconductor device manufactured using the same
JP3050807B2 (en) * 1996-06-19 2000-06-12 イビデン株式会社 Multilayer printed wiring board
JP3769587B2 (en) * 2000-11-01 2006-04-26 株式会社ノース Wiring circuit member, manufacturing method thereof, multilayer wiring circuit board, and semiconductor integrated circuit device
JP2004095913A (en) * 2002-08-30 2004-03-25 Dainippon Printing Co Ltd Printed wiring board and its manufacturing method
JP2006310530A (en) * 2005-04-28 2006-11-09 Sanyo Electric Co Ltd Circuit device and its manufacturing process
JP4568215B2 (en) * 2005-11-30 2010-10-27 三洋電機株式会社 CIRCUIT DEVICE AND CIRCUIT DEVICE MANUFACTURING METHOD

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