JP2009182252A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that allows an interface level of a semiconductor layer to be set to a desired energy level by a simple method in a MIS-type semiconductor device and in a MS-type semiconductor device. <P>SOLUTION: The semiconductor device is provided with a conductor, a semiconductor having a source region and a drain region, and a monomolecular layer provided between the conductor and the semiconductor while being in contact with the conductor and the semiconductor respectively between the source region and the drain region. In the interface between the semiconductor and the monomolecular layer, an electron level of a molecule constituting the monomolecular layer forms the maximum of the density of states in a band gap of the semiconductor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and specifically to a semiconductor device having a metal / semiconductor (MS) structure or a metal / insulator / semiconductor (MIS) structure.

  In order to facilitate device operation in a MIS field effect transistor (MISFET) using a metal gate electrode or a MS type semiconductor device (Schottky junction type semiconductor device), a threshold voltage (Vth) , Hereinafter referred to as “threshold voltage”). That is, at the interface between a normal semiconductor or insulator and metal, the threshold voltage varies due to the interface state in the band gap, and it is required to control the threshold voltage.

  A related art related to this is a field effect transistor having an organic thin film containing a donor molecule and an acceptor molecule between a gate electrode and a semiconductor surface, and a threshold is selected by selecting the type and structure of the organic thin film. There is one that makes it possible to arbitrarily set a value voltage and a difference between drain-source currents when on and off (Patent Document 1).

However, this is because application of a predetermined voltage to the gate electrode causes charge transfer between the donor molecule and the acceptor molecule of the organic thin film, thereby controlling the semiconductor surface potential. It is difficult to predict the surface potential in advance. That is, it is necessary to perform trial and error to measure each surface potential using various kinds of organic thin films.
JP-A-62-222675

  The present invention has been made based on recognition of such a problem, and in a MIS type semiconductor device or an MS type semiconductor device, the interface state of the semiconductor layer can be set to a desired energy level by a simple method. A semiconductor device is provided.

  According to one embodiment of the present invention, a conductor, a semiconductor having a source region and a drain region, and the conductor in contact with the conductor and the semiconductor between the source region and the drain region, respectively. And a monomolecular layer provided between the semiconductor and the semiconductor, and at the interface between the semiconductor and the monomolecular layer, the electronic levels of the molecules constituting the monomolecular layer are within the band gap of the semiconductor. A semiconductor device characterized by forming a local density of states is provided.

  According to another embodiment of the present invention, a semiconductor having a conductor, a source region and a drain region, and the semiconductor layer in contact with the semiconductor between the source region and the drain region, and the semiconductor layer An insulator provided between the insulator and a monomolecular layer provided between the insulator and the conductor in contact with the insulator and the conductor, respectively, and the insulator There is provided a semiconductor device characterized in that an electronic level of a molecule constituting the monomolecular layer forms a local density maximum in a band gap of the insulator at an interface between the monomolecular layer and the monomolecular layer. The

  According to another embodiment of the present invention, a semiconductor having a first conductor, a source region and a drain region, and the semiconductor in contact with the semiconductor between the source region and the drain region. A first insulator provided between a layer and the first conductor; and provided between the first insulator and the first conductor in contact with the first insulator. A second conductor, a second insulator provided in contact with the second conductor and between the second conductor and the first conductor, and the second insulator And a monomolecular layer provided between and in contact with the first conductor and between the second insulator and the first conductor, the second insulator and the monomolecule At the interface with the layer, the electronic level of the molecules constituting the monomolecular layer is within the band gap of the second insulator, and the state density pole Wherein a obtained by forming a is provided.

  According to the present invention, there is provided a semiconductor device capable of setting the interface state of a semiconductor layer to a desired energy level by a simple method in the MIS type semiconductor device and the MS type semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and detailed description is abbreviate | omitted suitably.

(First embodiment)
FIG. 1 is a sectional view conceptually showing the basic structure of the semiconductor device according to the first embodiment of the present invention. That is, FIG. 1 shows an MS type semiconductor device (Schottky junction type semiconductor device) in which a monomolecular layer 12 is introduced between a semiconductor layer (semiconductor) 10 and a metal layer (conductor) 14.

  FIG. 2 is a cross-sectional view illustrating a specific example of the semiconductor device according to the first embodiment of the present invention. The structure is basically the same as that shown in FIG. 1, and a monomolecular layer 22 is introduced between a semiconductor layer (semiconductor) 20 and a metal layer (conductor) 24. The semiconductor layer 20 includes a pair of source / drain diffusion layers 20A and 20A sandwiching a region that forms an interface with the monomolecular layer 22 from both sides in the gate length direction, thereby forming an MS field effect transistor. Yes.

  3 and 4 are schematic views showing examples of chemical structural formulas of molecules constituting the monomolecular layers 12 and 22. One kind of molecule is selected from these molecules based on the desired interface state, and the monomolecular layer is formed. That is, the monomolecular layers 12 and 22 are formed by arranging these molecules two-dimensionally and having substantially only a single molecule in the thickness direction.

The effect of the first embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a schematic cross-sectional view of a semiconductor device of a comparative example compared with the first embodiment. In this comparative example, the semiconductor 30 having the pair of source / drain diffusion layers 30A and the metal layer 32 are merely joined, and no monomolecular layer is provided.
FIGS. 6A to 6D are conceptual diagrams for explaining the effect of the first embodiment, and are schematic diagrams showing a state density distribution. The density of state is represented by a curve, and the area where the state is satisfied is represented by shading. For simplicity, the case where the interface does not include defects is shown.

  6A shows the state density distribution in the comparative example (in the case where the monomolecular layers 12 and 22 are not introduced), and shows the state density distribution in the vicinity of the band gap between the metal layer 32 and the semiconductor layer 30. FIG. In this case, the Fermi level is pinned (FLP) to an electrical neutral level (CNL) determined by the energy band structure of the bulk crystal.

  On the other hand, FIGS. 6B to 6D are schematic views for explaining the state density distribution in the semiconductor device according to the present embodiment (when the monomolecular layers 12 and 22 are introduced). That is, FIG. 6B shows a state density distribution when the semiconductor layers 10 and 20 exist alone, and FIG. 6C shows a state density distribution when the monomolecular layers 12 and 22 exist alone. FIG. 6D shows a state density distribution in the vicinity of the interface when the stacked structure of the metal layers 14, 24 / monomolecular layers 12, 22 / semiconductor layers 10 and 20 is formed. As shown in FIG. 6D, the density of states locally increases in the band gap of the semiconductor layers 10 and 20 and in the vicinity of a specific energy level. Hereinafter, the energy level with the highest density of states is referred to as the “maximum level in the band gap”. As a result, the electric neutral level moves to the maximum level in the band gap, and the Fermi level is pinned here.

  The maximum level in the band gap is derived from the monomolecular layers 12 and 22. That is, the maximum level in the band gap is derived from the energy level (hereinafter referred to as “molecular level”) at which the density of states of the molecules of the monomolecular layers 12 and 22 when present alone is the highest. The positional relationship between the conduction band minimum (CBM) or the valence band maximum (VBM) of the semiconductor layers 10 and 20 of the semiconductor layers 10 and 20 and the maximum level in the band gap is a semiconductor when each exists independently. This generally corresponds to the positional relationship between the CBM or VBM of the layers 10 and 20 and the electronic level of the molecules of the monomolecular layers 12 and 22.

  The molecular level can be derived from the ionization potential (IP) or electron affinity (EA) of the molecule. 3 and 4 show the ionization potential (IP) and electron affinity (EA) of each molecule.

  In this way, by selecting an appropriate organic compound based on the ionization potential or electron affinity, the Fermi level can be pinned to a desired energy level without trial and error, and the semiconductor interface state can be pinned. The position can be set to a desired energy level. Thereby, the effective work function of the metal layer can be set to a desired value by a simple method, and various device operations can be performed.

As the semiconductor layers 10 and 20, single crystal Si is generally used, but polycrystalline Si, amorphous Si, Ge, compound semiconductor, SOI (Silicon On Insulator), organic polymer, and the like are also included.
As for the metal layers 14 and 24, typical n metals when silicon is used include Al and Ta, for example, and typical p metals include Pt and Au, for example. Besides these, for example, Co, Be, Ni, Rh, Pd, Te, Re, Mo, Hf, Mn, Zn, Zr, In, Bi, Ru, W, Ir, Er, La, Ti, and A simple metal or a metal compound containing one or more elements selected from Y can be used. Furthermore, metal-based conductive materials such as silicides, borides, nitrides, and carbides of these metals can be used.

As for the monomolecular layers 12 and 22 and the molecules of the monomolecular layer, the positional relationship between the lower end of the conduction band (CBM) or the upper end of the valence band (VBM) of the semiconductor layers 10 and 20 and the molecular level is not changed. From the viewpoint, it is desirable to adopt a molecular structure or a molecular layer structure that does not generate a special electron level (energy level at which the density of states is maximized) or dipole moment due to the interaction with the interface structure.
As the molecules used in the monolayer, organic molecules having various electronic states are desirable, and those that do not easily react with metals and oxides are desirable.

  From the viewpoint of suppressing the equivalent oxide thickness (EOT: hereinafter referred to as “equivalent film thickness”), the size of the molecule is preferably smaller. The molecular shape is preferably one or two-dimensional rather than three-dimensional from the viewpoint of suppressing the equivalent film thickness, and in order to prevent the molecular aggregation state from becoming bulky, it is more circular or flat than linear. The shape is desirable. From the viewpoint of thermal stability, it is desirable to use a 5-membered or 6-membered aromatic ring as a main component. In order to suppress the polarity of the molecule itself, it is desirable to have a symmetric structure. From the viewpoint of the stability of the molecular level and the maximum level in the band gap, it is preferable to select based on the electron level generated by, for example, a hetero atom in the heterocyclic ring, rather than the electron level generated by the substituent.

Here, when the interface atom density is 10 ¹⁵ cm ⁻² , the Fermi level is fixed (pinned) when the interface state density is about 10 ¹² cm ⁻² / eV, which is three orders of magnitude lower than this. Is known (Surface Science Vol.21, No.12, pp.791-799, 2000). From this, when the interface atomic density is 10 ¹⁵ cm ⁻² , if a substance having a state density of 10 ¹³ cm ⁻² / eV or higher, which is one digit higher than 10 ¹² cm ^−2, is introduced, the molecular level of the substance is increased. It can be said that the Fermi level is pinned. Therefore, the density of the monomolecular layer is desirably 1% or more of the interfacial atom density.

Also, when the dangling bond density at the interface is relatively high, reactions such as charge transfer and covalent bond formation occur between the dangling bond and the non-bonding orbitals of the molecules, and this causes the maximum level in the band gap. Fluctuates from the molecular level. Conversely, from the same consideration as above, it can be said that the molecular level is not affected by dangling bonds if the dangling bond density is lower than 10 ¹¹ cm ^−2, which is one digit lower than 10 ¹² cm ⁻² . For this reason, it is desirable that the metal layer / semiconductor layer interface has a dangling bond density lower than 10 ¹¹ cm ⁻² . On the other hand, when the dangling bond density is 10 ¹¹ cm ⁻² or more and 10 ¹³ cm ⁻² or less, it is desirable that the molecules of the monomolecular layer do not have nonbonding orbitals in the semiconductor band gap.

  When the metal used for the metal layers 14 and 24 is an n metal, the molecules of the monomolecular layers 12 and 22 have a LUMO (Lowest Unoccupied Molecular Orbital) level near the bottom of the Si conduction band (CBM) (4.05 eV). A molecule with it is desirable. The LUMO level can be estimated from the value of electron affinity (EA) (EA becomes the LUMO level). Specific examples include a cyano compound, a compound having a quinone structure, a nitro compound, and a compound having an oxadiazole structure. FIG. 3 shows specific examples thereof. (A) is bispropanedinitrile-2,2 ′-(4,4 ′, 5,5 ′, 7,7′-hexachloro [2,2′-bi-9H-fluorene] -9,9′-diylidene ), (B) are bis [3,6-dichloro-5- (4-chlorophenyl) -2,5-cyclohexadiene-1,4-dione] -2,2 ′-(1,3-phenylene), ( c) is bisbenzonitrile-4,4 ′-[[1,1′-biphenyl] -4,4′-diyl-bis (1,3,4-oxadiazole-5,2-diyl)], ( d) 4,4 ′, 5,5 ′, 7,7′-hexachloro [2,2′-bi-9H-fluorene] -9,9′-dione, (e) bis [3,5-bis (Naphthalene-1,8-dicarboxylic anhydride-4-yl) phenyl] methylene. Each EA is (e) 4.3 eV, (b) 3.9 eV, (c) 3.7 eV, (d) 4.0 eV, (e) 4.0 eV. Other examples include fullerene and silole (silacyclopentadiene, a compound in which carbon of cyclopentadiene is replaced by silicon). In particular, since the silole system is a heterocyclic ring, it has good thermal stability, and since there is no nonbonding orbital in the band gap, it is effective even when the dangling bond density is high.

  When the metal used for the metal layers 14 and 24 is p metal, the HOMO (Highest Occupied Molecular Orbital) level in the vicinity of the valence band upper end (VBM) (5.17 eV) of Si is used as the molecule of the monomolecular layers 12 and 22. A molecule with is desirable. The HOMO level can be estimated from the value of (first) ionization potential (IP) (IP becomes the HOMO level). Specifically, a compound having a fulvalene structure, a compound containing a 5- or 6-membered heterocyclic ring containing sulfur or nitrogen as a heteroatom and a polymer thereof, an aromatic amine having an unshared electron pair of nitrogen, a cyanine dye, And metal complexes (porphyrin complex, metallocene, metal phthalocyanine) and the like. Here, when the monomolecular layers 12 and 22 are formed of a polymer, one obtained by polymerizing monomers one-dimensionally or two-dimensionally can be used. FIG. 4 shows specific examples thereof. (A) is 5,5 ′ ″ ″-diphenyl-2,2 ′: 5 ′, 2 ″: 5 ″, 2 ′ ″: 5 ′ ″, 2 ″ ″: 5 ″ '', 2 '' '' '-sexithiophene, (b) is N, N, N ′, N′-tetraphenylbenzidine, (c) is copper phthalocyanine, (d) is poly (3,4-ethylene Dioxythiophene), (e) is 1,1,2,2-tetra [4- (diphenylamino) phenyl] ethane, (f) is 4,4'-bis [bis (m-tolyl) amino] -1 , 1 ′: 4 ′, 1 ″ -terphenyl, (g) is tetra [4- (diphenylamino) phenyl] ethene, (h) is 1,3,4,6-tetra [4- (diphenylamino) Phenyl] cyclohexane, (i) is N, N′-diphenyl-N, N′-bis (m-tolyl) benzidine. For each IP, (a) is 5.0 eV, (b) is 5.5 eV, (c) is 5.0 eV, (d) is 5.2 eV, (e) is 5.4 eV, (f) is 5 0.2 eV, (g) is 5.3 eV, (h) is 5.0 eV, and (i) is 5.5 eV. (B) and (i) have a structure of TPD (triphenyldiamine, N, N, N ′, N′-tetraphenylbenzidine), and are also used as a hole transport material of an organic EL device. Other substituted TPDs are also considered to have similar IP.

  The monomolecular layers 12 and 22 can be created by any method for laminating the surfaces of the semiconductor layers 10 and 20 from the outside. For example, a Langmuir-Blodget (LB) film or a self-assembled monolayer (SAM) film having a self-assembling ability can be used because it forms an excellent interface with excellent coverage. . The SAM film is thermally stable and can prevent molecular diffusion. Moreover, when self-integration is good, the bulk becomes high and the equivalent film thickness becomes large. For this reason, a vapor phase method can be used in SAM film formation. Thereby, a monomolecular layer and a two-dimensional amorphous film are generated, and the equivalent film thickness is suppressed. The layer thickness of the monomolecular layer is desirably 0.3 nm or less.

A silane coupling agent having excellent SAM film forming ability can be introduced as a terminal group of the molecules of the monomolecular layers 12 and 22. For this purpose, for example, a silyl group is introduced into the molecule, and then a silane coupling reaction is performed on the surfaces of the semiconductor layers 10 and 20. Thereby, the monomolecular layers 12 and 22 and the semiconductor layers 10 and 20 are connected by a siloxane bond, and a SAM film having thermal stability can be formed on the semiconductor layers 10 and 20.
Next, it will be described that according to the present embodiment, it is resistant to process deterioration and a wide process window can be taken.

  So far, the description has been made on the assumption that the interface has no defects. However, even if there is a defect at the interface, fluctuations in the threshold voltage can be suppressed by causing a more effective FLP (Fermi level pinning). For this reason, according to this embodiment, the process for defect reduction becomes essentially unimportant, and it is strong against process deterioration. Further, details of the interface state are not important, and it is not necessary to introduce organic compound molecules into the interface region with high accuracy, so that a wide process window can be taken.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 7 is a sectional view conceptually showing the basic structure of the semiconductor device according to the second embodiment of the present invention. In the present embodiment, in the MIS type semiconductor device of the metal layer (conductor) 46 / insulating layer (insulator) 42 / semiconductor layer (semiconductor) 40, the monomolecular layer 44 is interposed between the insulating layer 42 and the metal layer 46. Has been introduced.

FIG. 8 is a cross-sectional view illustrating a specific example of a semiconductor device according to the second embodiment of the present invention.
On the surface of a silicon substrate (semiconductor) 50, for example, a metal silicate insulating film (insulator) 52 composed of a silicon oxide film and a hafnium silicate film, a TPD molecular SAM film (monomolecular layer) 54, and a gate electrode (conductor) ) 56 is formed. The metal silicate film 52, the SAM film 54, and the gate electrode 56 have, for example, a strip shape extending in a direction (gate width direction) perpendicular to the paper surface in FIG.

  The gate electrode 56 is made of, for example, Au. Sidewall insulating films 58 are formed on both side walls of the gate electrode 56. The silicon substrate 50 has a pair of shallow diffusion regions 50B sandwiching a region forming an interface with the metal silicate film 52 from both sides in the gate length direction, and a pair of deep diffusion regions 50A outside the diffusion regions 50B. . In the diffusion regions 50A and 50B, impurities are diffused at a high concentration. A metal silicide layer 50C is formed on the deep diffusion region 50A.

  A channel region 50D formed by applying a voltage to the gate is formed between the pair of shallow diffusion regions 50B. In the channel region 50D, the amount of impurities to be added is appropriately adjusted in order to adjust the threshold voltage of the transistor. Note that, on both sides of the MISFET, for example, element isolation regions that are electrically insulated from adjacent elements are formed (not shown).

  Here, the semiconductor device can be a P-type MOSFET or an N-type MOSFET. Alternatively, the semiconductor device may be a complementary metal oxide semiconductor (CMOS) device including a P-type MOSFET and an N-type MOSFET.

The effect of the second embodiment of the present invention will be described with reference to FIGS.
FIGS. 9A to 9D are conceptual diagrams for explaining the effect of the second embodiment, and are schematic diagrams showing a state density distribution. Similar to FIG. 6, the state density is represented by a curve, and the region where the state is satisfied is represented by a shadow. As in FIG. 6, for simplicity, the case where the interface does not include a defect is shown.

  FIG. 9A shows the state density distribution in the comparative example (in the case where the monomolecular layers 44 and 54 are not introduced), and shows the state density distribution in the vicinity of the band gap between the metal layers 46 and 56 and the insulating layers 42 and 52. Yes. In this case, as in the first embodiment, the Fermi level is pinned to the electrical neutral level determined by the energy band structure of the bulk crystal.

  On the other hand, FIGS. 9B to 9D are schematic views for explaining the state density distribution in the semiconductor device according to the present embodiment (when the monomolecular layers 44 and 54 are introduced). That is, FIG. 9B shows a state density distribution when the insulating layers 42 and 52 exist alone, and FIG. 9C shows a state density distribution when the monomolecular layers 44 and 54 exist alone. FIG. 9D shows a state density distribution in the vicinity of the interface when the laminated structure of the metal layers 46, 56 / monomolecular layers 44, 54 / insulating layers 42, 52 is formed. As shown in FIG. 9D, the band gap maximum level exists in the band gap of the insulating layers 42 and 52. As a result, the electric neutral level moves to the maximum level in the band gap, and the Fermi level is pinned here.

  As described above with reference to the first embodiment, the maximum level in the band gap is determined by trial and error by appropriately selecting an organic compound based on the ionization potential or electron affinity of the molecules of the monomolecular layers 44 and 54. The Fermi level can be pinned to a desired energy level, and the interface level of the insulating layers 42 and 52 can be set to a desired energy level. Thereby, the effective work function of the metal layers 46 and 56 can be set to a desired value by a simple method, and various device operations can be performed.

As an example showing the significance of this effect, a specific example in which the effective work function and the vacuum work function of the metal layer are made equal will be described below.
In the MIS structure using the metal gate electrode, the work function of the metal electrode obtained from the threshold voltage during device operation is called the effective work function (φ _eff ). On the other hand, the work function specific to the electrode metal is called a vacuum work function (φ _vac ). From the viewpoint of ease of control of the threshold voltage, it is ideal that φ _eff = φ _vac , but this is not generally true. φ _eff <φ _vac for p metal and φ _eff > φ _vac for n metal. As a result, the actual threshold voltage becomes smaller than the ideal threshold voltage, and the device operation becomes difficult. On the other hand, according to the present embodiment, as described above, the effective work function and the vacuum work function of the metal electrode can be easily made equal, and the threshold voltage can be easily controlled.

FIG. 10 is a conceptual diagram for explaining the action of the molecular layer in the semiconductor device disclosed in Patent Document 1. In FIG. 10A and 10B are diagrams schematically showing the state density distribution. Here, the state density is represented by a curve, and the region where the state is satisfied is represented by shading.
Here, also in Patent Document 1 described above, the problem to be solved is control of the threshold voltage of the interface.

  FIG. 10A shows a state density distribution in the vicinity of the band gap between the metal layer and the insulating layer when no monomolecular layer is introduced. In this case, the Fermi level is pinned to the electrical neutral level determined by the energy band structure of the bulk crystal. That is, at the interface between a normal semiconductor or insulator and metal, the threshold voltage fluctuates due to the interface state in the band gap.

  In order to avoid this, Patent Document 1 uses a technique of introducing a monomolecular layer made of organic molecules to eliminate the interface state. FIG. 10B shows the density of states in the vicinity of the interface when a stacked structure composed of a metal layer / monomolecular layer / insulating layer is formed in the semiconductor device disclosed in Patent Document 1 (when a monomolecular layer is introduced). Represents the distribution. In the state shown in FIG. 10B, the interface state is changed by reacting the valence electrons of the organic molecules with the dangling bonds on the surface of the insulating layer, or by moving the charge between molecules or between the electrodes and molecules. ing. The molecular level of the organic molecule used here is originally located in the donor / acceptor level, but moves out of the band gap as a result of charge transfer. As a result, no interface state exists. Further, the surface potential is controlled by the electric dipole generated by the charge transfer between the donor molecule and the acceptor molecule. Even in this case, the surface potential can be changed to the desired position, but since this phenomenon occurs as a result of interaction between valence electrons of organic molecules and dangling bonds, the surface potential is predicted in advance. It is difficult. That is, it is necessary to perform trial and error to measure each surface potential using various kinds of organic thin films. For this reason, the semiconductor device disclosed in Patent Document 1 is relatively expensive in order to obtain a desired surface potential.

On the other hand, according to the present embodiment, as described above with reference to FIG. 9, the Fermi level is pinned to a desired energy level by providing a monomolecular layer having a predetermined maximum level in the band gap. it can. That is, the effective work function and the vacuum work function of the metal electrode can be easily made equal, and the threshold voltage can be easily controlled.
In Patent Document 1, the Fermi level is pinned, and on the premise that the FET (field effect transistor) does not operate due to the high-density interface level, the main purpose is to eliminate this interface level. Measures have been taken. In contrast, the present embodiment uses the phenomenon of Fermi level pinning to pin the Fermi level to a desired energy level using the molecular level, and thereby threshold control (FET Operation) is possible.

  The semiconductor layers 40 and 50, the metal layers 46 and 56, and the monomolecular layers 44 and 54 in the present embodiment can be the same as those described in the first embodiment.

  As the insulating layers 42 and 52, any material system having a finite band gap is an object. For example, a metal oxide film having a high dielectric constant such as an oxide, nitride, or oxynitride containing at least one element selected from Al, Hf, Y, Ti, Zr, Si, Ta, and a lanthanoid element (High-k film). Here, the lanthanoid elements include La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. In the semiconductor device of this embodiment, these high-k films can be made amorphous by adding nitrogen to Hf silicate, Zr silicate, etc. constituting the high-k film. Thereby, the heat resistance of the high-k film can be improved and the gate leakage current can be suppressed.

On the other hand, when a silane coupling agent is introduced as a molecular end group of the monomolecular layers 44 and 54, a SAM film is easily formed. In particular, the material of the insulating layers 42 and 52 is often a metal oxide, and the silane coupling agent promotes the formation of a SAM film on the metal oxide. It is valid. Thereby, the monomolecular layer and the insulating layer are connected by a siloxane bond, and a SAM film having thermal stability can be formed on the high-k film. It has been found that this SAM film is not broken up to at least 300 ° C. (Jpn. J. Appl. Phys. Vol. 40 (2001) pp. 4344-4348).
As in the first embodiment, this embodiment is also resistant to process deterioration and can take a wide process window.

Hereinafter, the case where a metal oxide is used as the material of the insulating layers 42 and 52 will be described.
When a metal oxide is used as the material of the insulating layers 42 and 52, oxygen vacancies generally occur and charge transfer occurs between the metals. As countermeasures, there are techniques such as (1) additional oxidation and heat treatment, and (2) introduction of different elements. However, with respect to (1), there is a problem that the converted film thickness increases when additional oxidation is performed, and the threshold voltage fluctuates when heat treatment is performed. With regard to (2), process control at the atomic level is required. There is a problem that the process window is narrow.

  On the other hand, in this embodiment, the equivalent film thickness does not increase as in the technique (1), and it is not necessary to control at the atomic level as in the technique (2). Therefore, the process window can be widened. That is, the process management in this embodiment uses organic compound molecules that are difficult to diffuse because they are larger than the atoms, rather than using atoms that are easily diffused by heat treatment, and do not depend on the details of the interface structure. Therefore, the management of selecting the structure of the organic compound, not the management of controlling the composition at the atomic level, can be widened, so that the process window can be widened.

In this embodiment, when the monomolecular layers 44 and 54 made of the SAM film of TPD molecules were used, φ _eff was measured and found to be 5.2 eV. This is a value close to the original φ _vac = 5.5 eV compared to 4.7 eV which is a value measured when the SAM film of TPD molecules is not introduced, and it can be confirmed that there is an effect. Moreover, it turns out that process deterioration has not occurred.

(Third embodiment)
Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS.
11-14 is sectional drawing showing the manufacturing process of this embodiment. The semiconductor device of the present embodiment is a CMOS device including a P-type MOSFET and an N-type MOSFET. This manufacturing method uses a so-called replacement gate method.

  First, as shown in FIG. 11, an N-type well region 102 and a P-type well region 104 separated by an element isolation layer 106 having an STI (Shallow Tranch Isolation) structure are formed on a semiconductor substrate 100. Subsequently, dummy gates (not shown) are formed in the N-type well region 102 and the P-type well region 104, respectively. Using these dummy gates as a mask, a P-type impurity is implanted into the N-type well region 102 to form a P-type extension layer 110, and an N-type impurity is implanted into the P-type well region 104 to form an N-type extension layer 114. To do. Thereafter, a sidewall layer 116 is formed on the side of the dummy gate. Thereafter, using the dummy gate and sidewall layer 116 as a mask, a P-type impurity is implanted into the N-type well region 102 to form a P-type diffusion layer 108, and an N-type impurity is implanted into the P-type well region 104 to form an N-type impurity. A diffusion layer 112 is formed.

  Thereafter, an interlayer insulating film 118 is deposited, and the interlayer insulating film 118 is planarized. Thereafter, the dummy gate is removed to obtain the structure shown in FIG. As can be seen from FIG. 11, the trench 120 is formed after the dummy gate is removed. A salicide layer (not shown) may be formed on the P-type diffusion layer 108 and the N-type diffusion layer 112.

  Next, a gate insulating material film 122 is deposited as shown in FIG. In the present embodiment, for example, the gate insulating material film 122 made of hafnium silicate having an atomic concentration of Hf of 30% can be deposited to 3 nm. As a deposition method, an ALD (Atomic Layer Deposition) method can be used. The deposition method may be any method that can form the gate insulating material film 122 along the bottom and side surfaces of the trench 120 after the dummy gate is removed. For example, CVD (Chemical Vapor Deposition) The deposition method may be used.

  Next, as illustrated in FIG. 13, the monomolecular layer 124 is deposited on the gate insulating material film 122 along the gate insulating material film 122. Here, the monomolecular layer 124 may be, for example, an LB film or a SAM film. As the molecular species, the molecule shown in FIG. 3E can be used. Thereafter, the region 124a is selectively etched, and then a monomolecular layer 124a is deposited. The monomolecular layer 124a may be, for example, an LB film or a SAM film. For example, the molecule of FIG. 4E can be used as the molecular species.

  Next, a description will be given with reference to FIG. First, a metal gate layer 126 is deposited so as to fill the trench 120. The metal gate layer 126 may be made of, for example, W (tungsten). An example of the deposition method is MOCVD. Thereafter, the entire upper surface is flattened by an ordinary CMP (Chemical Mechanical Polishing) method. Thus, the gate insulating films 122 and 122a, the monomolecular layers 124 and 124a, and the gate electrode 126 are formed on the P-channel MIS transistor formation region and the N-channel MIS transistor formation region, and the structure shown in FIG. Get. Since W has a work function of 4.1 to 5.2 eV, it can be used for both n metal and p metal.

  The effects of this embodiment are the same as those described above with respect to the first embodiment and the second embodiment. In addition, as the respective constituent elements and the like, those described in the first embodiment and the second embodiment can be used as appropriate without departing from the spirit of the present embodiment.

(Fourth embodiment)
Next, the organic transistor which is the 4th Embodiment of this invention, and its manufacturing method are demonstrated using FIGS.
FIG. 15 is a cross-sectional view conceptually showing the basic structure of the semiconductor device according to the fourth embodiment of the present invention. The configuration of this embodiment is as follows. An insulating layer 72 is formed on the substrate 70, and a channel forming semiconductor layer (semiconductor) 78 made of an organic semiconductor is formed on the insulating layer 72. Source / drain electrodes 76, 76 are formed on both sides of the semiconductor layer 78. An insulating layer (insulator) 80 is formed so as to cover the semiconductor layer 78 and the source / drain electrodes 76 and 76. A monomolecular layer 82 is formed on the insulating layer 80, and a gate electrode (conductor) 84 is formed on the monomolecular layer 82.

Next, a specific example of a semiconductor device according to the fourth embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.
FIG. 18 is a sectional view showing an organic transistor according to the fourth embodiment of the present invention.
An insulating layer 72 containing insulating fine particles is formed on a substrate 70 made of a sufficiently thick liquid crystalline polymer, and a channel forming semiconductor layer 78 made of pentacene, which is an organic semiconductor, is formed on the insulating layer 72. Source / drain electrodes 76, 76 made of metal are formed on both sides of the semiconductor layer 78. An insulating layer 80 made of hafnium silicate is formed so as to cover the semiconductor layer 78 and the source / drain electrodes 76 and 76. Between the insulating layer 72 and the semiconductor layer 78 and between the insulating layer 72 and the insulating layer 80, an insulating layer 74 made of polyimide having a fluorine-based side chain is formed. A monomolecular layer 82 made of a SAM film of TPD molecules is formed on the insulating layer 80, and a gate electrode 84 made of metal is formed on the monomolecular layer 82.

Below, the specific example of the manufacturing method of the semiconductor device of this embodiment is shown.
16 to 18 are cross-sectional views showing the manufacturing process of the semiconductor device of this embodiment.
For a top gate type organic field effect transistor (organic FET), an example using an ink jet drawing method as a method of forming a source / drain and a gate will be given.

As represented in FIG. 16, on a substrate 70 composed of a liquid crystal polymer is coated with a SiO ₂ based oxide containing SiO ₂ particles with a diameter of 50nm in offset printing to form an insulating layer 72 including the insulating fine particles. At this time, the portion other than the fine particles can have a thickness of about 20 nm. This is irradiated with ultraviolet light and then baked in an oven at 250 ° C. for 60 minutes. The unevenness of the SiO ₂ fine particle portion is exposed to an average of about 40 nm with respect to the SiO ₂ oxide layer. The density of the SiO ₂ fine particles is, for example, about 50 / μm ² . Next, low surface energy polyimide having fluorine side chains is printed to a thickness of 10 nm to form an insulating layer 74 that does not contain insulating fine particles. Thereafter, firing is performed. Thereafter, etching is performed only on the regions to be the source portion and the drain portion, and the insulating layer 74 is removed from these regions.

  Thereafter, source / drain electrodes 76 and 76 are formed by using an ink jet drawing method. As the electrode material, for example, a colloidal gold colloid dispersed in an aqueous solution can be used. This colloidal gold solution is applied to the region (the region where the semiconductor layer 78 is formed) of the upper surface of the insulating layer 74 by ink-jet drawing. Here, since the surface energy of the polyimide having a fluorine side chain constituting the insulating layer 74 is as low as 30 mN / m, the colloidal gold solution is separated into two on the insulating layer 74 and provided on both sides of the channel portion. It spontaneously moves to the source and drain portions and stabilizes. In this state, for example, baking is performed in an oven at 250 ° C. for 60 minutes, and the gold colloidal particles are fused to be completely metallized to form source / drain electrodes 76 and 76. Thereafter, the substrate is cleaned.

  After that, as shown in FIG. 17, a pentacene precursor chloroform solution is formed to a thickness of 100 nm on the upper surface of the insulating layer 74 by an inkjet drawing method in a region that becomes a channel portion. Thereafter, baking is performed in an oven at 200 ° C. for 60 minutes to crystallize pentacene. Thereby, the semiconductor layer 78 can be formed. The channel length can be set to 5 μm, for example.

  Next, a description will be given with reference to FIG. A hafnium silicate layer is deposited on the substrate formed as described above so as to cover the semiconductor layer 78 and the source / drain electrodes 76, 76, thereby forming an insulating layer 80 that does not contain insulating fine particles. Thereafter, a monomolecular layer 82 made of a SAM film of TPD molecules is formed. Thereafter, a gate electrode 84 made of metal is formed in a region directly above the channel portion by an ink jet drawing method. As the electrode material, for example, a gold colloid dispersion solution can be used in the same manner as the source / drain electrodes. The droplet diameter can be set to 20 μm, for example. Firing is performed, for example, in an oven at 250 ° C. for 60 minutes.

As for the insulating fine particles and the insulating layer 72 containing the insulating fine particles, SiO ₂ is used for both of them in the above-described specific examples. In addition to this, other examples such as Al ₂ O ₃ and Ta ₂ O ₅ are also used. An inorganic insulating material can also be used. Further, for example, an organic insulating material such as polyimide, polyamide, and polyamideimide can be used.

  For the semiconductor layer 78, pentacene is used in the above-described specific example, but a soluble precursor of other low-molecular semiconductor material or a low-molecular semiconductor material in which the material itself is soluble can also be used. Alternatively, a high molecular weight organic semiconductor material in which hopping conduction is more dominant than main chain conduction can be used.

  As the conductive material for the source / drain electrodes 76 and 76 and the gate electrode 84, a solution in which a colloidal gold is dispersed is used in the above-described specific example, but other than this, for example, low-temperature firing using nanoparticles is performed. Any highly conductive metal colloidal solution such as possible Pt can also be used. An organic conductive material such as PEDOT-PSS (Polystyrenesulfonate doped PEDOT (Poly (3,4-ethylenedioxythiophene))) that can be applied by ink jet drawing can also be used.

  The effects of this embodiment are the same as those described above with respect to the first embodiment and the second embodiment. In addition, as the respective constituent elements and the like, those described in the first embodiment and the second embodiment can be used as appropriate without departing from the spirit of the present embodiment.

(Fifth embodiment)
Next, the non-volatile semiconductor memory cell which is the 5th Embodiment of this invention, and its manufacturing method are demonstrated using FIGS.
FIG. 19 is a cross-sectional view conceptually showing the semiconductor device according to the fifth embodiment of the present invention. The semiconductor device of this embodiment includes a control gate layer (first conductor) 210 / monomolecular layer 208 / insulating layer (second insulator) 206 / floating gate layer (second conductor) 204 / insulating layer. It has a stacked structure of (first insulator) 202 / semiconductor layer (semiconductor) 200. This represents, for example, one cell portion of a NAND type nonvolatile semiconductor memory device.

FIG. 20 is a cross-sectional view showing a nonvolatile semiconductor memory cell according to the fifth embodiment of the present invention.
A floating gate electrode 304 made of an n + type polycrystalline Si layer is formed on a p-type Si substrate 300 via a tunnel insulating film 302 made of a thermal oxynitride film (SiON film). An interelectrode insulating film 306 made of HfAlOx is formed on the floating gate electrode 304. A monomolecular layer 308 made of a SAM film of TPD molecules is formed on the interelectrode insulating film 306, and a control gate electrode 310 made of Au is formed thereon.

  The film thickness of the tunnel insulating film 302 is, for example, about 7 nm to 8 nm. The film thickness of the floating gate electrode 304 and the control gate electrode 310 is, for example, about 30 nm to 60 nm. The film thickness of the interelectrode insulating film 306 is, for example, about 10 nm to 30 nm. The work function of n + type polycrystalline Si constituting the floating gate electrode 304 is about 4 eV, and the work function of Au constituting the control gate electrode 310 is about 5 eV.

  For the floating gate electrode 304, n + type polycrystalline Si is used in this embodiment, but other than that, for example, Au, Pt, Co, Be, Ni, Rh, Pd, Te, Re, Mo, Al, Hf, A metal simple substance or a metal compound containing one or more elements selected from Ta, Mn, Zn, Zr, In, Bi, Ru, W, Ir, Er, La, Ti, and Y can also be used. In addition, metallic conductive materials such as silicides, borides, nitrides, and carbides can be used.

  For the control gate electrode 310, Au is used in this embodiment, but other than that, for example, Pt, Co, Be, Ni, Rh, Pd, Te, Re, Mo, Al, Hf, Ta, Mn, Zn, A simple metal or a metal compound containing one or more elements selected from Zr, In, Bi, Ru, W, Ir, Er, La, Ti, and Y can also be used. In addition, metallic conductive materials such as silicides, borides, nitrides, and carbides can be used.

  For the high dielectric constant material constituting the interelectrode insulating film 306, HfAlOx is used in this embodiment, but other than this, for example, selected from Al, Hf, La, Y, Ce, Ti, Zr, Si, and Ta An oxide, nitride, or oxynitride containing at least one kind of element can be used, and a stack of these films can also be used. Further, a laminate in which these high dielectric insulating films and a Si oxide film, a Si nitride film, or a Si oxynitride film are combined may be used.

Next, a method for manufacturing the semiconductor device of this embodiment will be described.
21 to 25 are cross-sectional views showing a manufacturing process of the nonvolatile semiconductor memory cell according to the fifth embodiment of the present invention. In each figure, (a) and (b) represent cross sections orthogonal to each other.

  First, as shown in FIG. 21, a SiON film 402 having a thickness of about 7 nm to 8 nm serving as a tunnel insulating film is formed on the upper surface of a p-type Si substrate 400 doped with a desired impurity by a thermal oxidation method. Thereafter, a phosphorus-doped n + -type polycrystalline Si layer 404 having a thickness of 60 nm serving as a floating gate electrode is deposited by a CVD method. The temperature at this time can be set to 620 ° C., for example. Thereafter, a mask material 406 for element isolation processing is deposited by the CVD method.

  Thereafter, the mask material 406, the polycrystalline Si layer 404, and the SiON film 402 are sequentially etched by RIE (Reactive Ion Etching) using a resist mask (not shown). Thereafter, the exposed region of the Si substrate 400 is etched to form an element isolation groove 408 having a depth of 100 nm.

  Thereafter, as shown in FIG. 22, a silicon oxide film 410 for element isolation is deposited on the entire surface, and the element isolation trench 408 is completely filled. Thereafter, the upper surface of the silicon oxide film 410 is removed by CMP to planarize the surface. At this time, the upper surface of the mask material 406 is exposed.

Next, a description will be given with reference to FIG. The exposed mask material 406 is selectively removed by etching. Thereafter, the exposed surface of the silicon oxide film 410 is etched away with a dilute hydrofluoric acid solution to expose the sidewall surface 412 of the n + polycrystalline Si layer 404. Thereafter, a 15 nm thick HfAlO _x film 414 to be an interelectrode insulating film is formed on the entire upper surface. For example, the HfAlO _x film 414 is subjected to the ALD method at 250 ° C. using Al (CH ₃ ) ₃ , Hf [N (CH ₃ ) ₂ ] ₄ and H ₂ O as raw materials, followed by 1000 ° C., N ₂ , 1 It can be formed by annealing in an atmosphere of atmospheric pressure.
Thereafter, as shown in FIG. 24, a SAM film 416 of TPD molecules is deposited and Au is evaporated to form a control metal gate electrode 418.

  In addition, the manufacturing method of these films | membranes is not restricted to the method illustrated here. Other source gases may be used, and other than ALD and CVD, for example, sputtering, vapor deposition, laser ablation, MBE (Molecular Beam Epitaxy), or these A film forming method combining these methods may be used.

Thereafter, the control metal gate electrode 418, the SAM film 416, the HfAlO _x film 414, the polycrystalline Si layer 404, and the SiON film 402 are sequentially etched by the RIE method using a resist mask (not shown), and the word line direction The slit part 420 is formed. Thereby, the shapes of the floating gate electrode and the control gate electrode are determined.
Finally, as shown in FIG. 25, a silicon oxide film 422 called an electrode sidewall oxide film is formed on the exposed surface by a thermal oxidation method. Thereafter, an n + type source / drain diffusion layer 400A is formed by ion implantation. Thereafter, an interlayer insulating film 424 such as a silicon oxide film is formed by a CVD method so as to cover the entire surface. Thereafter, a wiring layer and the like are formed to complete the nonvolatile memory cell.

  The effect of this embodiment is as described above with respect to the first embodiment and the second embodiment. In addition, as the respective constituent elements and the like, those described in the first embodiment and the second embodiment can be used as appropriate without departing from the spirit of the present embodiment.

(Example of simulation)
Next, simulation examples regarding the effects of introducing a monomolecular layer will be described with reference to FIGS. 26 and 27. FIG.
In order to verify the effect of introducing the above-described monomolecular layer, simulation was performed as follows.

Aluminum (Al), which is an n metal, was used for the metal layer, and HfO ₂ was used for the insulating layer. By setting a monomolecular layer between the two, the effective work function (WF _eff ) of the metal layer (aluminum which is n metal) is set to a desired value (here, the effective work function of p metal). We investigated whether it was possible.

  Triphenylamine (TPA) was used for the monomolecular layer. TPA is a molecule obtained by cutting TPD in half and has almost the same electronic structure as TPD. For this reason, it can be estimated that the ionization potential (IP) of TPA is about 5.5 eV. This value is close to the effective work function of p metal. That is, TPA is expected to be a molecule (p-type pinning molecule) having a function of pinning the Fermi level to the p metal type. In addition, substituted TPA is considered to have the same effect.

FIG. 26 is a schematic diagram illustrating structures according to Examples and Comparative Examples.
FIG. 26A is a schematic diagram illustrating a structure according to an example. A monomolecular layer made of TPA is introduced between the Al crystal and the HfO ₂ crystal. FIG. 26B is a schematic diagram showing the molecular structure of TPA.
On the other hand, FIG.26 (c) is a schematic diagram showing the structure which concerns on the comparative example contrasted with an Example. There is no monomolecular layer, and only an Al crystal and a HfO ₂ crystal are used.
These unit cells were analyzed under three-dimensional periodic boundary conditions. The surface of the uppermost Al crystal was in contact with vacuum, and a vertically symmetrical structure was used around the bottom surface of the lowermost HfO ₂ crystal. That is, the structure of Al / TPA / HfO ₂ / TPA / Al was used for the examples, and the structure of Al / HfO ₂ / Al was used for the comparative examples.

  In order to obtain the effective work functions of the structures according to Examples and Comparative Examples, structural relaxation simulation was performed by first-principles electronic structure calculation software using first-principle pseudopotentials based on density functional theory. In this software, a plane wave basis is used as a basis function.

The change in the effective work function (WF _eff ) is considered to result from a relative change in the band edge levels of the metal and the insulator due to the dipole moment of the interface. Here, the effective work function is predicted from the following theoretical formula using the energy value (Valence Band Offset: VBO) of the valence band upper end (VBM) measured with the Fermi level as zero. Can do.

WF _eff = χ + (kα + 1) E′g−VBO ′

The meaning of each symbol is as follows.
χ is the electron affinity.
k = Eg / E′g−1. Here, Eg is an actually measured band gap, and E′g is a band gap obtained by calculation.
α = Dc / (Dc + Dv). However, Dc is an effective density of states of the conduction band of the insulator, and Dv is an effective density of states of the valence band of the insulator.
VBO ′ = − VBO (valence band offset).
“(Kα + 1)” is a coefficient provided for correction because the band gap (E′g) calculated by the first principle calculation is too small.

For the Al / HfO ₂ structure, the values are as follows:

χ = 2.5, k = 0.667, α = 0.383, E′g = 3.6

Next, a structure according to a comparative example, that is, a structure in which a monolayer composed of TPA is not introduced (Al / HfO ₂ / Al), and a structure according to an example, that is, a structure in which a monolayer composed of TPA is introduced (Al For each of / TPA / HfO ₂ / TPA / Al), the valence band offset (VBO) is determined.

  In general, the band edge can be obtained from the density of states (DOS). Since the structural model of the metal / insulator interface is always metal, there is no band gap. For this reason, the band edge of the insulator region is obtained by examining the density of states around atoms located away from the interface.

FIG. 27 is a graph illustrating simulation results according to the example and the comparative example.
FIG. 27A is a graph showing the density of states according to the comparative example. That is, this graph shows a structure (Al / HfO ₂ / Al) that does not include a monomolecular layer made of TPA, hafnium (Hf) atoms and oxygen (O) present at a location away from the metal layer / insulating layer interface. This represents the density of states (ALDOS) projected onto the area around the atom. As described above, the valence band offset (VBO) is an energy value at the upper end of the valence band measured with the Fermi level set to zero. Therefore, in FIG. 27A, the position where the peak on the low energy side begins to rise is the valence band upper end (VBM), and the energy value is the valence band offset (VBO). From the figure, it can be read that VBO = -3.

On the other hand, FIG. 27B is a graph showing the density of states according to the example. That is, this graph shows the structure (Al / TPA / HfO ₂ / TPA / Al) including a monomolecular layer made of TPA, hafnium (Hf) atoms and oxygen existing at a location away from the metal layer / insulating layer interface. (O) represents the density of states (ALDOS) of atoms projected onto atomic orbitals. Each element was examined by picking up two atoms (Hf1, Hf25, O9, and O33). In the same manner as described above, the VBO of this structure can be read as VBO = −1.3.

Therefore, for the Al / HfO ₂ / Al structure, VBO ′ = 3.0 and WF _eff = 4.02 eV. The value of this WF _eff closely reproduces the actual measurement value (4.2 eV, M. Koyama et al., Tech. Digest IEDM, p499 (2004)).
On the other hand, for the Al / TPA / HfO ₂ / TPA / Al structure, VBO ′ = 1.3 and WF _eff = 5.7 eV. The value of this _{WF eff} is close to the value of _{WF eff} of p metal.

From the above, by introducing a monomolecular layer composed of TPA (ionization potential (IP) ≈5.5 eV) considered to be a p-type pinning molecule, the electrical neutral level (CNL) at the metal layer / insulating layer interface is reduced. It was confirmed that the effective work function (4.02 eV) of Al, which is an n metal, was changed to a value (5.7 eV) close to the effective work function of the p metal. Here, the effective work function (5.7 eV) after the change is close to the ionization potential (about 5.5 eV) of TPA. That is, the Fermi level is pinned to a specific energy level by introducing a monomolecular layer.
Therefore, it was confirmed by this example that the effective work function of the metal layer can be set to a desired value by introducing a monomolecular layer made of molecules having a specific ionization potential.

The embodiment of the present invention has been described above. However, the present invention is not limited to these descriptions. As long as the features of the present invention are provided, those skilled in the art appropriately modified the design of the above-described embodiments are also included in the scope of the present invention. For example, each element provided in the embodiment of the present invention and the arrangement thereof are not limited to those illustrated, but can be changed as appropriate.
Moreover, each element with which each embodiment mentioned above is provided can be combined as long as technically possible, and the combination of these is also included in the scope of the present invention as long as it includes the features of the present invention.

1 is a cross-sectional view conceptually showing the basic structure of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing showing the specific example of the semiconductor device which concerns on the 1st Embodiment of this invention. 2 is a schematic diagram illustrating an example of chemical structural formulas of molecules constituting the monomolecular layers 12 and 22. FIG. 2 is a schematic diagram illustrating an example of chemical structural formulas of molecules constituting the monomolecular layers 12 and 22. FIG. It is a schematic cross section of a semiconductor device of a comparative example compared with the first embodiment. It is a conceptual diagram for demonstrating the effect of 1st Embodiment, and is the schematic diagram showing the state density distribution. It is sectional drawing which represents notionally the basic composition of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing the specific example of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a conceptual diagram for demonstrating the effect of 2nd Embodiment, and is a schematic diagram showing state density distribution. 10 is a conceptual diagram for explaining the action of a molecular layer in a semiconductor device disclosed in Patent Document 1. FIG. It is sectional drawing showing the manufacturing process of 3rd Embodiment. It is sectional drawing showing the manufacturing process of 3rd Embodiment. It is sectional drawing showing the manufacturing process of 3rd Embodiment. It is sectional drawing showing the manufacturing process of 3rd Embodiment. It is sectional drawing which represents notionally the basic composition of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing showing the manufacturing process of the semiconductor device of the 4th Embodiment of this invention. It is sectional drawing showing the manufacturing process of the semiconductor device of the 4th Embodiment of this invention. It is sectional drawing showing the organic transistor which concerns on the 4th Embodiment of this invention. It is sectional drawing which represents notionally the semiconductor device which concerns on the 5th Embodiment of this invention. FIG. 7 is a cross-sectional view illustrating a nonvolatile semiconductor memory cell according to a fifth embodiment of the invention. It is sectional drawing showing the manufacturing process of the non-volatile semiconductor memory cell which concerns on the 5th Embodiment of this invention. It is sectional drawing showing the manufacturing process of the non-volatile semiconductor memory cell which concerns on the 5th Embodiment of this invention. It is sectional drawing showing the manufacturing process of the non-volatile semiconductor memory cell which concerns on the 5th Embodiment of this invention. It is sectional drawing showing the manufacturing process of the non-volatile semiconductor memory cell which concerns on the 5th Embodiment of this invention. It is sectional drawing showing the manufacturing process of the non-volatile semiconductor memory cell which concerns on the 5th Embodiment of this invention. It is a schematic diagram showing the structure which concerns on an Example and a comparative example. It is a graph showing the simulation result which concerns on an Example and a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor layer 12 Monomolecular layer 14 Metal layer 20 Semiconductor layer 20A Source / drain diffused layer 22 Monomolecular layer 30 Semiconductor layer 30A Source / drain diffused layer 32 Metal layer 40 Semiconductor layer 42 Insulating layer 44 Monomolecular layer 46 Metal layer 50 Silicon Substrate 50A Diffusion region 50B Diffusion region 50C Metal silicide layer 50D Channel region 52 Metal silicate film 54 Monomolecular layer 56 Gate electrode 58 Side wall insulation film 70 Substrate 72 Insulation layer 74 Insulation layer 76 Source / drain electrode 78 Semiconductor layer 80 Insulation layer 82 Single Molecular layer 84 Gate electrode 102 N-type well region 104 P-type well region 106 Element isolation layer 108 P-type diffusion layer 110 P-type extension layer 112 N-type diffusion layer 114 N-type extension layer 116 Side wall layer 118 Interlayer insulating film 120 Groove 122 Gate Insulation Material films 122 and 122a Gate insulating film 124 Monomolecular layer 124a Monomolecular film 126 Gate electrode 126 Metal gate layer 208 Monomolecular layer 300 Substrate 302 Tunnel insulating film 304 Floating gate electrode 306 Interelectrode insulating film 308 Monomolecular film 310 Control gate electrode 400 Substrate 400A Source / drain diffusion layer 402 SiON film 404 Si layer 406 Mask material 408 Element isolation trench 410 Silicon oxide film 412 Side wall surface 418 Control metal gate electrode 420 Slit part 422 Silicon oxide film 424 Interlayer insulating film

Claims (11)

A conductor;
A semiconductor having a source region and a drain region;
A monomolecular layer provided between the conductor and the semiconductor in contact with the conductor and the semiconductor, respectively, between the source region and the drain region;
With
A semiconductor device, wherein an electronic level of a molecule constituting the monomolecular layer forms a local state density maximum in a band gap of the semiconductor at an interface between the semiconductor and the monomolecular layer.   The molecule constituting the monomolecular layer has a LUMO (Lowest Unoccupied Molecular Orbital) level near the lower end of the conduction band of the semiconductor, or a HOMO (Highest Occupied Molecular Orbital) level near the upper end of the valence band of the semiconductor. The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 1, wherein the monomolecular layer has a siloxane bond at a boundary with the semiconductor. A conductor;
A semiconductor having a source region and a drain region;
An insulator provided between the semiconductor region and the conductor in contact with the semiconductor between the source region and the drain region;
A monomolecular layer provided between the insulator and the conductor in contact with the insulator and the conductor, respectively.
With
A semiconductor device characterized in that, at the interface between the insulator and the monomolecular layer, the electron levels of the molecules constituting the monomolecular layer form a maximum of the state density in the band gap of the insulator. . A first conductor;
A semiconductor having a source region and a drain region;
A first insulator provided between the semiconductor and the first conductor in contact with the semiconductor between the source region and the drain region;
A second conductor provided between the first insulator and the first conductor in contact with the first insulator;
A second insulator provided between the second conductor and the first conductor in contact with the second conductor;
A monomolecular layer provided between the second insulator and the first conductor in contact with each of the second insulator and the first conductor;
With
At the interface between the second insulator and the monomolecular layer, the electron levels of the molecules constituting the monomolecular layer form a maximum density of states within the band gap of the second insulator. A semiconductor device characterized by the above.   The semiconductor device according to claim 4, wherein the monomolecular layer has a siloxane bond at a boundary with the insulator.  The semiconductor device according to claim 1, wherein the level of the molecule is substantially the same as a vacuum work function of the conductor in contact with the monomolecular layer.   The monomolecular layer includes a cyano compound, a compound having a quinone structure, a nitro compound, a compound having an oxadiazole structure, a fullerene, a silacyclopentadiene, a compound having a fulvalene structure, 5 or 6 members containing sulfur or nitrogen as a hetero atom. 8. The method according to claim 1, wherein the compound is formed of any one selected from the group consisting of a compound containing a heterocyclic ring and a polymer thereof, an aromatic amine, a cyanine dye, and a metal complex. The semiconductor device described in one.   The monomolecular layer is bispropanedinitrile-2,2 ′-(4,4 ′, 5,5 ′, 7,7′-hexachloro [2,2′-bi-9H-fluorene] -9,9 ′. -Diylidene), bis [3,6-dichloro-5- (4-chlorophenyl) -2,5-cyclohexadiene-1,4-dione] -2,2 '-(1,3-phenylene), bisbenzonitrile -4,4 '-[[1,1'-biphenyl] -4,4'-diyl-bis (1,3,4-oxadiazole-5,2-diyl)], 4,4', 5 5 ′, 7,7′-hexachloro [2,2′-bi-9H-fluorene] -9,9′-dione, bis [3,5-bis (naphthalene-1,8-dicarboxylic anhydride-4- Yl) phenyl] methylene, 5,5 ′ ″ ″-diphenyl-2,2 ′: 5 ′, 2 ″: 5 ″, '' ': 5' '', 2 '' '': 5 '' '', 2 '' '' '-sexithiophene, substituted or unsubstituted N, N, N ′, N′-tetraphenylbenzidine , Copper phthalocyanine, poly (3,4-ethylenedioxythiophene), 1,1,2,2-tetra [4- (diphenylamino) phenyl] ethane, 4,4′-bis [bis (m-tolyl) amino ] -1,1 ′: 4 ′, 1 ″ -terphenyl, tetra [4- (diphenylamino) phenyl] ethene, 1,3,4,6-tetra [4- (diphenylamino) phenyl] cyclohexane, and 8. The semiconductor device according to claim 1, wherein the semiconductor device is formed of any one selected from the group consisting of substituted or unsubstituted triphenylamine.   The semiconductor device according to claim 1, wherein the monomolecular layer is formed by a self-assembled monolayer method.   The semiconductor device according to claim 1, wherein the semiconductor is an organic semiconductor.

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