JP2009177066A - Transistor structure and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor, as a power semiconductor device, capable of preventing thermal runaway and thermal destruction during operation, and having an enlarged safe operating area SOA. <P>SOLUTION: The transistor includes a collector layer 2 of a first conductivity type, an island base layer 3 formed on the collector layer and having a second conductivity type which is different from the first conductivity type, at least one island emitter layer 4a and 4b formed on the base layer and having the first conductivity type, a base electrode electrically connected with the base layer and forming a base contact 9, an emitter electrode electrically connected with the emitter layers and forming an emitter contact 10, and a collector electrode electrically connected with the collector layer, in which a first resistive layer 11 of the first conductive type is formed on the emitter layers so as to surround the base contact in a planar view. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a transistor structure and a semiconductor device in which semiconductor elements including transistors are integrated.

One of the performance indicators of a transistor applied to a power supply circuit or the like as a power semiconductor element is a specification item called safe operating area SOA (Safe Operating Area). The SOA is an area showing allowable values of current and voltage that allow the transistor to operate normally without failure such as element destruction, and the power supply circuit using the transistor operates so that the transistor operates within the area indicated by the SOA. It is necessary to provide an external circuit. That is, expanding the SOA is one of means for improving the reliability of the transistor and simplifying the power supply circuit.

FIG. 3 is a planar structure of a conventional NPN transistor described in Patent Document 1, and FIG. 4 is a cross-sectional structure thereof.
An N + type semiconductor substrate 1;
An N− type collector layer 2 formed on the semiconductor substrate 1 and having an impurity concentration lower than that of the semiconductor substrate 1;
A P-type base layer 3 formed in an island shape on the collector layer 2;
An N + type emitter layer 4 formed in an island shape on the base layer 3;
An insulating film 5 formed on each surface of the collector layer 2, the base layer 3, and the emitter layer 4;
A base electrode 7 which is electrically connected to the base layer 3 in the opening of the insulating film 5 and forms a base contact 9;
An emitter electrode 8 electrically connected to the emitter layer 4 at the opening of the insulating film 5 to form an emitter contact 10;
A collector electrode 6 electrically connected to the semiconductor substrate 1,
An N + type first resistance layer 11 is formed on the base layer 3 in an island shape and so as to surround the emitter contact 10 in plan view.

In the conventional transistor, the first resistance layer 11 is formed on the base layer and surrounds the emitter layer 4, so that a current path flowing from the base electrode 7 to the emitter layer 4 is narrowed, The resistance value can be increased. Such a first resistance layer 11 is called a ballast resistor. By forming a ballast resistor in the base layer 3, the base current flowing from the base electrode 7 to the emitter electrode 9 is limited, and current concentration at the emitter contact is reduced. This can be prevented and has the effect of expanding the SOA.

JP-A 64-59857

By the way, when the transistor switches a large voltage and a large current, a large amount of heat is generated due to the collector current, particularly in the emitter contact 10, and the collector current further increases due to the heat generation, causing further heat generation. As a result, there is a concern that the safe operation area SOA is conversely narrowed because it tends to concentrate in the vicinity of the emitter contact 10 and thermal runaway or thermal breakdown occurs.

Therefore, when the electric resistance value of the first resistance layer 11 is increased in order to limit the base current and reduce the collector current, there is a problem that the static characteristics of the transistor deteriorate. Further, when the resistance region is formed in the emitter layer 4, heat generation at the emitter contact can be suppressed, but heat generation also occurs in the resistance region and thermal runaway occurs, so that it is not effective for SOA expansion.

SUMMARY OF THE INVENTION An object of the present invention is to provide a transistor capable of preventing thermal runaway and thermal breakdown during operation and expanding the SOA.

In order to solve the above problems and achieve the above object, the transistor structure of the present invention according to claim 1 comprises:
A first conductivity type collector layer;
A base layer of a second conductivity type formed in an island shape on the collector layer and different from the first conductivity type;
An emitter layer of at least one island type and of the first conductivity type formed on the base layer;
A base electrode electrically connected to the base layer to form a base contact;
An emitter electrode electrically connected to the emitter layer to form an emitter contact;
A collector electrode electrically connected to the collector layer,
The first resistance layer of the first conductivity type formed on the emitter layer is formed so as to surround the base contact in a plan view.

In order to solve the above problems and achieve the above object, the transistor structure of the present invention according to claim 2 is characterized in that the first resistance layer has an impurity concentration lower than that of the emitter layer.

Furthermore, in order to solve the above problems and achieve the above object, the transistor structure of the present invention according to claim 3 is the emitter layer in which the first resistance layer is formed in a plurality of island shapes on the base layer. Consists of regions that overlap in the horizontal direction.

Furthermore, in order to solve the above problems and achieve the above object, a transistor structure of the present invention according to claim 4 is formed in an island shape on the base layer between the base contact and the emitter contact, and A second resistance layer having the first conductivity type is provided.

Furthermore, in order to solve the above problems and achieve the above object, the transistor structure of the present invention according to claim 5 is a mesh emitter structure.

Further, in order to solve the above problems and achieve the above object, a semiconductor device according to a sixth aspect of the present invention is a semiconductor device including the transistor structure.

According to the invention of each claim, thermal runaway and thermal destruction during operation can be prevented, and the safe operation area SOA can be expanded.

Next, an example of a transistor according to an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows a plan structure of an NPN transistor according to an embodiment of the present invention, and FIG. 2 shows a sectional structure thereof.
A transistor according to an embodiment of the present invention includes:
An N + type semiconductor substrate 1;
An N − -type collector layer 2 formed on the semiconductor substrate 1 and having an impurity concentration lower than that of the semiconductor substrate 1;
A P-type base layer 3 formed in an island shape on the collector layer 2;
N + type emitter layers 4a and 4b formed in an island shape on the base layer 3,
An insulating film 5 formed on each surface of the collector layer 2, the base layer 3, and the emitter layers 4a and 4b;
A base electrode 7 which is electrically connected to the base layer 3 in the opening of the insulating film 5 and forms a base contact 9;
An emitter electrode 8 electrically connected to the emitter layer 4a in the opening of the insulating film 5 and forming an emitter contact 10;
A collector electrode 6 electrically connected to the semiconductor substrate 1,
Furthermore, an N + type second resistance layer 12 is formed on the base layer 3 and is formed in an island shape so as to surround the base contact 9 in a plan view.
An N-type first resistance layer 11 is formed on the emitter layers 4a and 4b in an island shape so as to surround the base contact 9 and the second resistance layer 12 in plan view. Yes.

In the transistor of the embodiment, ballast resistors are formed on the base layer 3 and the emitter layer 4 so as to surround the base contact 9. That is, the first resistance layer 11 is formed on the emitter layer 4 so as to surround the base contact 9 and the second resistance layer 12 is formed on the base layer 3 so as to surround the base contact 9. In this respect, unlike the conventional transistor, the other components are the same as the conventional transistor.

In the transistor of the embodiment, the first resistance layer 11 and the second resistance layer 12 are formed simultaneously with the emitter layers 4a and 4b by a known selective diffusion method. Specifically, the surface of the region where the emitter layers 4a, 4b and the second resistance layer 12 are to be formed becomes an opening, and the surface of the region where the first resistance layer 11 is to be formed and the surface of the other region are covered with a mask. A mask for selective diffusion is formed. When the N-type impurity is diffused into the base layer 3 with such a mask provided, the N-type impurity is diffused from the opening of the mask to form the N + -type emitter layers 4a and 4b and the second resistance layer 12. . At the same time, the N-type impurity is diffused in the region covered with the mask on the base layer 3 by the lateral diffusion of the N-type impurity, and the N− type first resistance layer 11 having a low impurity concentration is formed. The
In the transistor structure according to the embodiment of the present invention, the impurity concentration of the semiconductor substrate 1 is 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ , and the impurity concentration of the collector layer 2 is 5 × 10 ^{13 to} 5 × 10 ¹⁵ cm ^−3. The impurity concentration of the base layer 3 is 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , and the impurity concentrations of the emitter layer 4 and the second resistance layer 12 are 3 × 10 ^{19 to} 3 × 10 ²⁰ cm ⁻³ . Furthermore, the thickness of the semiconductor substrate 1 is 50 to 400 μm, the thickness of the collector layer 2 is 5 to 50 μm, the thickness of the base layer 3 is 3 to 30 μm, the thickness of the emitter layer 4 and the second resistance layer 12 is 1 to 20 μm.

According to the transistor of the embodiment, the following effects can be obtained.
(1) Since the first resistance layer 11 is formed so as to surround the base contact 9, heat generated in the emitter contact 10 and the first resistance layer 11 is dispersed to prevent thermal runaway of the transistor or junction breakdown due to heat. it can.

(2) Since the first resistance layer 11 is formed on the emitter layers 4a and 4b, the collector current flowing from the collector electrode 6 to the emitter electrode 8 can be directly limited. Furthermore, since the second resistance layer 12 is formed on the base layer 3, the base current flowing from the base electrode 7 to the emitter electrode 8 can be limited. Therefore, current concentration at the emitter contact can be prevented more effectively and the SOA can be expanded.

(3) Since the first resistance layer 11 and the second resistance layer 12 are formed at the same time as the emitter layers 4a and 4b, they can be easily obtained in manufacturing.

The transistor of the present invention is not limited to the above embodiment, and various modifications are possible. For example, the first resistance layer 11 is formed in a double triple on the emitter layer 4, so that an effect of preventing current concentration at the emitter contact and further expanding the SOA of the transistor can be obtained. Further, in the PNP type transistor as well, the second resistance layer 12 is formed on the base layer 3 and the first resistance layer 11 is formed on the emitter layer 4 in the same manner as in the above embodiment. The same effect as in the embodiment can be obtained.

It is a top view which shows the structure of the transistor of the Example of this invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1. It is a top view which shows the structure of the conventional transistor. FIG. 4 is a B-B ′ sectional view of FIG. 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Collector layer 3 Base layer 4, 4a, 4b Emitter layer 5 Insulating film 6 Collector electrode 7 Base electrode 8 Emitter electrode 9 Base contact 10 Emitter contact 11 1st resistance layer 12 2nd resistance layer

Claims (6)

A first conductivity type collector layer;
A base layer of a second conductivity type formed in an island shape on the collector layer and different from the first conductivity type;
An emitter layer of at least one island type and of the first conductivity type formed on the base layer;
A base electrode electrically connected to the base layer to form a base contact;
An emitter electrode electrically connected to the emitter layer to form an emitter contact;
A collector electrode electrically connected to the collector layer,
The transistor structure, wherein the first resistance layer of the first conductivity type is formed on the emitter layer so as to surround the base contact in a plan view.
2. The transistor structure according to claim 1, wherein the first resistance layer has an impurity concentration lower than that of the emitter layer.
3. The transistor structure according to claim 2, wherein the first resistance layer comprises a region in which the emitter layers formed in a plurality of islands on the base layer overlap in the horizontal direction.
4. The transistor structure according to claim 2, further comprising a second resistance layer formed in an island shape on the base layer between the base contact and the emitter contact and having the first conductivity type.
5. The transistor structure according to claim 1, wherein the transistor structure is a mesh emitter structure.
  A semiconductor device comprising the transistor structure according to claim 1.

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