JP2009175532A - Driving method of plasma display panel and plasma display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving method of a plasma display panel for driving even an ultra high definition plasma display panel having 2,160 or more lines with sufficient luminance, and to provide a plasma display apparatus. <P>SOLUTION: The driving method of a plasma display panel is provided in which: display electrode pairs composed of a scan electrode (SC) and a sustain electrode (SU) forming a pair are divided into a plurality of groups; the phase of a voltage pulse train applied to the display electrode pair is made different from each other between the groups; selection of a group is repeated in the order of the advance of the phase of the voltage pulse train; one-line writing processing is performed on the cell line corresponding to one or a plurality of display electrode pairs in the selected group each time a group is selected; and then oneline sustaining processing is performed on the cell line on which the oneline writing processing is performed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a driving method and a plasma display apparatus for an AC surface discharge type plasma display panel.

  An AC surface discharge type PDP, which is a typical plasma display panel (hereinafter referred to as “PDP”), has a large number of discharge cells between a front substrate and a rear substrate that are arranged to face each other.

  A plurality of pairs of display electrodes composed of scan electrodes and sustain electrodes are formed in parallel on the front substrate, and a plurality of data electrodes are formed in parallel on the back substrate. Then, the front substrate and the rear substrate are disposed opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a region where one display electrode pair and one data electrode intersect with each other across the discharge space and a region in the vicinity thereof constitute one discharge cell that contributes to image display.

  As a method of driving the PDP, a subfield method is used in which one field is divided into a plurality of subfields and gradation display is performed by combining subfields that emit light. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address operation are formed. In the address period, address discharge is selectively generated in the discharge cells in accordance with the image to be displayed to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode to generate a sustain discharge, and the phosphor layer of the corresponding discharge cell emits light to display an image.

  Among the subfield methods, an address / maintenance separation method (ADS method) in which an address period and a sustain period are completely separated in time is generally used. In the ADS system, there is no timing for coexistence of a discharge cell that performs an address discharge and a discharge cell that performs a sustain discharge. The PDP can be driven. Therefore, discharge control is relatively simple, and the drive margin of the PDP can be set large.

  On the other hand, in the ADS system, since the sustain period is set in the period excluding the address period, if the time required for the address period becomes long due to high definition of the PDP or the like, a sufficient time for sustain discharge cannot be secured. was there.

In order to solve such a problem, a write / maintenance simultaneous drive method has been proposed (see, for example, Non-Patent Document 1). In the address / maintenance simultaneous drive system, the sustain discharge is started immediately after the end of the address discharge for each line. As described above, by performing the sustain discharge even during the time when the address discharge is performed in another line, the time for the sustain discharge can be secured, and the light can be emitted with a necessary luminance.
(Science Technical Report: TECHNICAL REPORT OF EICE. EID96-71, ED96-149, SDM96-175 (1997-01), pp-19-24)

  However, even when this method is used, when driving an ultra-high definition plasma display panel such as 2160 lines or 4320 lines, it takes a long time to perform address discharge on all lines, and sustain discharge is performed. Time cannot be secured, and it is difficult to drive with sufficient luminance.

  The present invention has been made to solve the above-described problems, and even for an ultra-high-definition plasma display panel having 2160 lines or more, a sufficient time for sustaining discharge can be secured. It is an object of the present invention to provide a plasma display panel driving method and a plasma display device that can be driven with sufficient luminance.

  In order to achieve the above object, the plasma display panel driving method of the present invention is arranged such that a plurality of display electrode pairs comprising a pair of scan electrodes and sustain electrodes and a plurality of data electrodes intersect with a gap. A plasma display having a plurality of discharge cells provided, the discharge space having a gap between the display electrode pair and the data electrode, and the display electrode pair and the data electrode forming the gap to be the discharge space A panel driving method, wherein the plurality of display electrode pairs are divided into first to Nth (N is a plurality) groups, and each cell line including a plurality of discharge cells corresponding to the display electrode pairs is provided. 1-line addressing process for generating an address discharge in the discharge cells to be lit, and 1-line maintaining for generating a sustain discharge in the discharge cells causing the address discharge And a one-line sustaining end process for generating an erasing discharge in the discharge cells that have generated the sustain discharge in order to stop the sustain discharge, each having a different luminance weight respectively determined in advance. 1-line display processing including 1st to M-th (M is plural) 1-line write maintenance processing having the 1-line maintenance processing in accordance with the P-th (P is 1 to M−) for all the cell lines. After the one-line write processing included in the one-line write maintenance processing is completed, the one-line write processing included in the (P + 1) th one-line write maintenance processing is started, and all the cells By performing the one-line display process on the line, one field image is displayed, and while the first to Mth one-line writing maintenance processes are performed, An alternating polarity voltage pulse train that switches between a positive voltage and a negative voltage is applied to the display electrode pair corresponding to the cell line to be subjected to the one-line write maintenance process. A process for generating the address discharge by applying a scan selection potential to the scan electrode corresponding to the cell line to be subjected to a line address process and applying an address potential to the data electrode of the discharge cell to be lit. In order to apply a scan selection potential to the scan electrodes, a scan voltage in which a first predetermined voltage is superimposed on the positive voltage or the negative voltage of the voltage pulse is applied to the display electrode pair. The one line maintenance process is performed by applying the write potential simultaneously with the application, and the one line maintenance process includes the one line maintenance process. The number of voltage pulses corresponding to a predetermined luminance weight is applied to the display electrode pair for the write sustain process, and the one-line sustain end process is performed by the positive voltage or the negative voltage of the voltage pulse. The display is performed by applying an erasing voltage in which a second predetermined voltage is superimposed on the voltage to the display electrode pair, and the display of the Kth group (K is an integer of 2 to N) with respect to the first group. The phase of the voltage pulse train applied to the electrode pair is delayed by different angles, the one-line writing process is performed at different timings for each of the cell lines, and the phase of the voltage pulse train applied to the display electrode pair Repeatedly selecting each of the groups in the order of the group in which each is proceeding, each time selecting each of the groups, one or more of the selected groups And to perform the 1-line write process on the cell lines corresponding to the plurality of the display electrodes pairs.

  According to this driving method, the display electrode pairs provided in the plasma display panel are divided into a plurality of first to Nth groups, and the phase of the voltage pulse train applied to the one-line write maintenance process is made different between the groups. One line write processing is performed for cell lines corresponding to one or a plurality of predetermined number of display electrode pairs in the selected group each time a group is selected by repeating the sequential selection of groups in the order in which the phase of the voltage pulse train advances. By performing the above, it is possible to efficiently perform the one-line writing process for all the cell lines, and to shorten the time required for the one-line writing process for all the cell lines. Further, by performing the one-line maintaining process on the cell line that has been subjected to the one-line writing process, the one-line maintaining process can be performed while the one-line writing process is being performed on the other cell lines. . From the above, the time required for the one-line maintenance process included in each of the M pieces of one-line write maintenance processes performed for all the cell lines within the limited time for displaying an image of one field, that is, Sufficient time for the sustain discharge can be secured. Therefore, even an ultra-high-definition plasma display panel having 2160 lines or more can secure a sufficient time for sustain discharge and can be driven with sufficient luminance.

  Further, each time each group is selected, a plurality of cell lines corresponding to the plurality of display electrode pairs in the selected group are applied to the plurality of display electrode pairs in the group at the same timing. The one-line writing process may be performed within the application period of the positive voltage or the negative voltage of the voltage pulse.

  As described above, by performing the one-line writing process a plurality of times within the application period of the voltage pulse applied at the same timing, the interval of the one-line writing process performed in the same group is shortened or eliminated. It becomes possible to carry out continuously, and it is possible to secure a sufficient time for the sustain discharge.

  Further, a period during which the one-line writing process is performed on the cell line corresponding to the display electrode pair of one group among the first to Nth groups is included in the display electrode pair of any other group. You may make it overlap with the rising or falling period of the said applied voltage pulse.

  As a result, it is possible to reduce the interval of the one-line writing process performed for all the cell lines, or to perform it continuously without the interval, and to perform the one-line writing process for all the cell lines. The time required to perform the operation can be further shortened, and the time required for the sustain discharge can be sufficiently secured.

  Further, the phase of the voltage pulse train applied to the display electrode pairs of the Kth group may be delayed by [360 × (K−1) / N] degrees with respect to the first group.

  The number of the groups may be 2 to 4 (N = 2 to 4).

  In addition, during the period in which the image display of the one field is performed, in the first to Nth groups, a part of the display electrode pairs in the group is partially subjected to the one-line write maintaining process. A common voltage pulse train having a fixed period that becomes the voltage pulse train to be applied may be applied.

  As described above, in each group, a common voltage pulse train having a constant period is applied during a period in which image display of one field is performed regardless of the timing of M one-line write maintenance processing performed on each cell line. As a result, it is possible to easily apply the voltage pulse train to the display electrode pair corresponding to the cell line to be subjected to the one-line writing maintenance process.

  Further, an initialization period for generating an initialization discharge for charging all the discharge cells into a chargeable state capable of address discharge may be provided immediately before the period during which the image display of one field is performed.

  Further, the luminance weight for the Mth one-line write maintaining process among the first to Mth one-line write maintaining processes may be the smallest.

  Since the M-th one-line write maintenance process is the last one-line write maintenance process, if the M-th one-line write maintenance process for all the cell lines is finished, the one-field image display process may be finished. it can. Therefore, the time required for the image display processing for one field can be minimized by making the Mth one-line writing maintenance processing the one-line writing maintenance processing with the smallest luminance weight. In other words, since the image display process for one field is performed in one field period of a fixed time, the time for sustaining discharge can be maximized.

  Further, the plasma display device of the present invention is arranged such that a plurality of display electrode pairs formed of a pair of scan electrodes and sustain electrodes and a plurality of data electrodes intersect with a gap, and the display electrode pairs A plasma display panel having a plurality of discharge cells each having a discharge space having a gap with the data electrode, the display electrode pair forming the gap to be the discharge space, and the data electrode; and the plasma display panel. A drive device for driving, wherein the drive device divides the plurality of display electrode pairs into first to Nth groups (N is a plurality), and each of the plurality of discharge cells corresponding to the display electrode pairs. 1 line addressing process for generating an address discharge in the discharge cells to be lit, and maintaining the discharge cell in which the address discharge is generated 1 line maintenance process for generating electricity and 1 line maintenance end process for generating an erasing discharge in the discharge cells that have generated the sustain discharge to stop the sustain discharge, 1-line display processing including 1st to M-th (M is a plurality) 1-line write maintenance processing having the 1-line maintenance processing according to different predetermined luminance weights is performed, and the P-th for all the cell lines After the one-line writing process included in the one-line writing maintaining process (P is an integer from 1 to M−1), the one-line writing process included in the (P + 1) th one-line writing maintaining process is performed. The image display of one field is performed by performing the one-line display process for all the cell lines, and each of the first to Mth one lines is displayed. While performing the write address maintenance process, a voltage pulse train of alternating polarity that switches between a positive voltage and a negative voltage is applied to the display electrode pair corresponding to the cell line that is the target of the one line write maintenance process, In the one-line write process, a scan selection potential is applied to the scan electrode corresponding to the cell line to be subjected to the one-line write process, and a write potential is applied to the data electrode of the discharge cell to be lit. A process for generating an address discharge, wherein a scanning voltage obtained by superimposing a first predetermined voltage on the positive voltage or the negative voltage of the voltage pulse in order to give a scanning selection potential to the scanning electrode is applied to the display electrode pair. And applying the write potential simultaneously with the application of the scanning voltage. The number of voltage pulses corresponding to a predetermined luminance weight is applied to the display electrode pair with respect to the one-line write maintaining process including a holding process, and the one-line maintaining end process is performed using the voltage An erasing voltage in which a second predetermined voltage is superimposed on the positive voltage or the negative voltage of the pulse is applied to the display electrode pair, and the Kth (K is 2 to N) with respect to the first group. The phase of the voltage pulse train applied to the display electrode pairs in the group of integers) is delayed by different angles, and the one-line writing process is performed at different timings for the cell lines, The selection of each group is repeated in the order of the group in which the phase of the applied voltage pulse train is advanced, each time the group is selected. It is configured to perform the one-line write processing with respect to the cell line corresponding to one or more of the display electrode pairs in the group was.

  According to this configuration, the display electrode pairs provided in the plasma display panel are divided into a plurality of first to N-th groups, and the phase of the voltage pulse train applied to the one-line writing maintenance process is made different between the groups. Repeatedly selecting groups sequentially in the order in which the phase of the pulse train progresses, and each time a group is selected, one line write processing is performed for the cell lines corresponding to one or a plurality of display electrode pairs in the selected group. By doing so, it is possible to efficiently perform the one-line writing process for all the cell lines, and to shorten the time required for the one-line writing process for all the cell lines. Further, by performing the one-line maintaining process on the cell line that has been subjected to the one-line writing process, the one-line maintaining process can be performed while the one-line writing process is being performed on the other cell lines. . From the above, the time required for the one-line maintenance process included in each of the M pieces of one-line write maintenance processes performed for all the cell lines within the limited time for displaying an image of one field, that is, Sufficient time for the sustain discharge can be secured. Therefore, even an ultra-high-definition plasma display panel having 2160 lines or more can secure a sufficient time for sustain discharge and can be driven with sufficient luminance.

  In addition, the driving device applies a plurality of display electrode pairs in the group to a plurality of cell lines corresponding to the plurality of display electrode pairs in the group selected each time the group is selected. The one-line writing process may be performed within the application period of the positive voltage or the negative voltage of the voltage pulse applied at the same timing.

  As described above, by performing the one-line writing process a plurality of times within the application period of the voltage pulse applied at the same timing, the interval of the one-line writing process performed in the same group is shortened or eliminated. It becomes possible to carry out continuously, and it is possible to secure a sufficient time for the sustain discharge.

  In the driving device, a period during which the one-line writing process is performed on the cell line corresponding to the display electrode pair of one of the first to Nth groups is in any other group. The voltage pulse applied to the display electrode pair may overlap the rising or falling period of the voltage pulse.

  As a result, it is possible to reduce the interval of the one-line writing process performed for all the cell lines, or to perform it continuously without the interval, and to perform the one-line writing process for all the cell lines. The time required to perform the operation can be further shortened, and the time required for the sustain discharge can be sufficiently secured.

  The driving device is configured to delay the phase of the voltage pulse train applied to the display electrode pairs of the Kth group by [360 × (K−1) / N] degrees with respect to the first group. May be.

  The number of the groups may be 2 to 4 (N = 2 to 4).

  In addition, in the first to Nth groups, a part of the driving device writes the one line to the display electrode pairs in the first to Nth groups during a period during which the one-field image display is performed. It may be configured to apply a common voltage pulse train having a fixed period to be the voltage pulse train to be applied during the maintenance process.

  As described above, in each group, a common voltage pulse train having a constant period is applied during a period in which image display of one field is performed regardless of the timing of M one-line write maintenance processing performed on each cell line. As a result, it is possible to easily apply the voltage pulse train to the display electrode pair corresponding to the cell line to be subjected to the one-line writing maintenance process.

  Further, the drive device has an initialization period for generating an initialization discharge for bringing all the discharge cells into a charged state capable of address discharge immediately before the period for performing the image display of the one field. It may be configured.

  Further, the luminance weight for the Mth one-line write maintaining process among the first to Mth one-line write maintaining processes may be the smallest.

  Since the M-th one-line write maintenance process is the last one-line write maintenance process, if the M-th one-line write maintenance process for all the cell lines is finished, the one-field image display process may be finished. it can. Therefore, the time required for the image display processing for one field can be minimized by making the Mth one-line writing maintenance processing the one-line writing maintenance processing with the smallest luminance weight. In other words, since the image display process for one field is performed in one field period of a fixed time, the time for sustaining discharge can be maximized.

  The present invention has the above-described configuration, and even for an ultra-high-definition plasma display panel having 2160 lines or more, a sufficient time for sustaining discharge can be ensured and it is driven with sufficient luminance. The plasma display panel driving method and the plasma display apparatus can be provided.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of the plasma display panel used in Embodiment 1 of the present invention.

  The plasma display PDP 10 (hereinafter referred to as “PDP 10”) is configured such that a glass front substrate 21 and a rear substrate 31 are disposed so that their main surfaces face each other, and a discharge space is formed therebetween. On the main surface of the front substrate 21, a plurality of scanning electrodes 22 and sustaining electrodes 23 constituting the display electrode pair 24 are formed in parallel with each other. In order to generate discharge in the discharge gap between the scan electrode 22 and the sustain electrode 23 constituting the display electrode pair 24 and to extract light, the scan electrode 22 has a wide transparent electrode 22a. It has a wide transparent electrode 23a. Narrow bus electrodes 22b and 23b are stacked at positions far from the discharge gap on the transparent electrodes 22a and 23a. Further, a black stripe 29 that blocks light is provided between adjacent display electrode pairs 24. A dielectric layer 25 is formed so as to cover the scan electrode 22, the sustain electrode 23, and the black stripe 29, and a protective layer 26 is further formed so as to cover the dielectric layer 25.

  A plurality of data electrodes 32 are formed on the main surface of the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by barrier ribs 34, and a region where display electrode pair 24 and data electrode 32 intersect and a region in the vicinity thereof are discharge cells. These discharge cells discharge and emit light to display an image.

  The structure of the PDP 10 is not limited to that described above. For example, instead of the cross-shaped partition walls 34, a stripe shape provided in parallel with the data electrodes 32 on the dielectric layer 33 between the data electrodes 32. These may be provided.

  FIG. 2 is an electrode array diagram of PDP 10 used in Embodiment 1 of the present invention. In the PDP 10, n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 23 in FIG. 1) that are long in the row direction (line direction) are alternately arranged. The m data electrodes D1 to Dm (data electrode 32 in FIG. 1) that are long in the column direction are arranged. A region where the scan electrode SCi and the sustain electrode SUi (i = 1 to n) and one data electrode Dj (j = 1 to m) forming a pair intersect with each other across the discharge space and its vicinity are displayed as an image. One discharge cell 11 contributes to the above. Therefore, each discharge cell 11 includes a pair of display electrodes (scan electrode SCi and sustain electrode SUi) and one data electrode, and includes a discharge space between them. In this PDP 1, m × n discharge cells 11 are formed.

  The n display electrode pairs of the n scan electrodes SC1 to SCn and the n sustain electrodes SU1 to SUn are divided into a plurality of display electrode pair groups. Although the number of display electrode pairs is not particularly limited, in the present embodiment, description will be made assuming that n = 2160. As shown in FIG. 2, the display electrode pair positioned in the upper half of the PDP 10 is a first display electrode pair group, and the display electrode pair positioned in the lower half of the PDP 10 is a second display electrode pair group. That is, 1080 scan electrodes SC1 to SC1080 (first scan electrode group G1sc) and 1080 sustain electrodes SU1 to SU1080 (first sustain electrode group G1su) belong to the first display electrode pair group. Scan electrodes SC1081 to SC2160 (second scan electrode group G2sc) and 1080 sustain electrodes SU1081 to SU2160 (second sustain electrode group G2su) belong to the second display electrode pair group.

  Next, a method for driving the PDP according to the present embodiment will be described. In the present embodiment, this PDP driving method is performed as an operation of a plasma display device described later.

  FIG. 3 is a waveform diagram of a drive potential signal applied to each electrode of PDP 10 in Embodiment 1 of the present invention. FIG. 3 shows an initialization period and a part of the first SF and the second SF. FIG. 4 is an enlarged view of the drive potential signal waveform applied to the scan electrode of PDP 10 in the first embodiment of the present invention. Scan electrodes SC1 to SC4, SC1081 to SC1084 and data electrodes D1 to D1 are displayed at the beginning of the display period. The details of the drive potential signal waveform applied to Dm are shown. FIG. 5 is a diagram schematically showing the approximate timing for performing the write operation and the erase operation for each line (a plurality of discharge cells corresponding to the display electrode pair) in one field period in the first embodiment of the present invention. It is. The vertical axis in FIG. 5 shows scan electrodes SC1 to SC2160 representing the display electrode pairs of each line, and the horizontal axis shows time.

  In the present embodiment, one field period is composed of an initialization period and a display period that follows. The initializing period is a period in which initializing discharge is simultaneously generated in all the discharge cells, and is provided as the same period for all the lines. The display period is a period in which operations of a plurality of subfields that generate address discharge and sustain discharge are performed on each line. In this embodiment, the first SF, the second SF,. -It has 9 sub-fields of 9th SF. Each subfield of the first SF to the ninth SF is assumed to have a luminance weight of (60, 44, 30, 18, 11, 6, 3, 2, 1). However, the present invention is not limited to the above number of subfields and luminance weight. One field period is determined to be a predetermined time (for example, approximately 16.7 ms when the frequency is 60 Hz).

  As shown in FIG. 3, in the initialization period, the data electrodes D1 to Dm are held at a potential of 0 (V). In the first half of the initialization period, a potential of 0 (V) is applied to sustain electrodes SU1 to SU2160, and scan electrodes SC1 to SC2160 are discharged from potential Vi1 that is lower than the discharge start voltage with respect to sustain electrodes SU1 to SU2160. A ramp waveform potential that gradually increases toward the potential Vi2 exceeding the start voltage is applied. While this ramp waveform potential rises, weak initialization discharges occur between scan electrodes SC1 to SC2160, sustain electrodes SU1 to SU2160, and data electrodes D1 to Dm, respectively. Negative wall charges are accumulated on scan electrodes SC1 to SC2160, and positive wall charges are accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SU2160.

  Next, in the latter half of the setup period, positive potential Ve is applied to sustain electrodes SU1 to SU2160, and scan electrodes SC1 to SC2160 start to discharge from potential Vi3 that is equal to or lower than the discharge start voltage with respect to sustain electrodes SU1 to SU2160. A ramp waveform potential that gently falls toward the potential Vi4 exceeding the voltage is applied. During this time, weak initialization discharges occur between scan electrodes SC1 to SC2160, sustain electrodes SU1 to SU2160, and data electrodes D1 to Dm, respectively. As a result, the negative wall charges on the scan electrodes SC1 to SC2160 are reduced, and the positive wall charges on the sustain electrodes SU1 to SU2160 and the data electrodes D1 to Dm are reduced to adjust the wall charge amount suitable for the write operation. The Thereafter, a potential of 0 (V) is applied to all scan electrodes SC1 to SC2160. Thus, the initialization operation for performing the initialization discharge on all the discharge cells is completed.

  Next, the display period will be described. Scan electrodes SC1 to SC2160 and sustain electrodes SU1 to SU2160 are supplied with a sustain pulse train in which a potential of 0 (V) and a potential Vs are alternately repeated. Here, the phases of sustain pulse trains applied to scan electrode SCi and sustain electrode SUi constituting the display electrode pair are shifted from each other by 180 °. Further, the phases of scan electrodes SC1 to SC1080 belonging to the first display electrode pair group and sustain pulse trains applied to scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group are also shifted from each other by 180 °.

  At the beginning of the display period, potential Vs is applied to scan electrodes SC1 to SC1080 belonging to the first display electrode pair group, and 0 (V) potential is applied to sustain electrodes SU1 to SU1080. Further, a potential of 0 (V) is applied to scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group, and potential Vs is applied to sustain electrodes SU1081 to SU2160. Here, since the wall charges on scan electrodes SC1 to SC2160 and sustain electrodes SU1 to SU2160 are reduced in the initialization period, no sustain discharge occurs.

  Next, at time t1, a potential of 0 (V) is applied to scan electrodes SC1 to SC1080 belonging to the first display electrode pair group, and potential Vs is applied to sustain electrodes SU1 to SU1080. Further, potential Vs is applied to scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group, and 0 (V) potential is applied to sustain electrodes SU1081 to SU2160. Further, the voltage (Va) for setting the scanning potential (scanning selection potential) Va to the potential of 0 (V) is applied to the scanning electrode SC1 of the first line in an overlapping manner (that is, the scanning electrode SC1 is set to the scanning potential Va). In addition, the address pulse potential Vd is applied to the data electrode Dk (k = 1 to m) of the discharge cell to be lit in the first line among the data electrodes D1 to Dm. At this time, the voltage at the intersection of the data electrode Dk and the scan electrode SC1 is set to the externally applied voltage (Vd−Va), the voltage generated by the wall charge on the data electrode Dk and the voltage generated by the wall charge on the scan electrode SC1. The magnitude is added and exceeds the discharge start voltage. Then, an address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall charges are accumulated on scan electrode SC1, and negative wall is accumulated on sustain electrode SU1. Charge is accumulated.

  In this way, an address operation is performed in which address discharge is caused in the discharge cell to emit light on the first line and wall charges are accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm and the scan electrode SC1 to which the address pulse potential Vd is not applied does not exceed the discharge start voltage, so that address discharge does not occur.

  Similarly, after the scanning potential Va is applied to the scanning electrode SC1 of the first line, the scanning potential Va is applied to the scanning electrode SC2 of the second line, and the discharge to be emitted to the second line among the data electrodes D1 to Dm. An address pulse potential Vd is applied to the data electrode Dk of the cell. As a result, address discharge occurs between data electrode Dk and scan electrode SC2, and between sustain electrode SU2 and scan electrode SC2, positive wall charges are accumulated on scan electrode SC2, and negative wall charges are accumulated on sustain electrode SU2. Charge is accumulated.

  In this manner, the address operation is performed in which the discharge discharge is caused in the second line to cause the address discharge to accumulate wall charges on each electrode.

  Next, at time t2, potential Vs is applied to scan electrodes SC1 to SC1080 belonging to the first display electrode pair group, and 0 (V) potential is applied to sustain electrodes SU1 to SU1080. Further, a potential of 0 (V) is applied to scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group, and potential Vs is applied to sustain electrodes SU1081 to SU2160. As a result, in the discharge cell that has caused the address discharge among the discharge cells in the first line, the voltage between the portion near the scan electrode SC1 and the portion near the sustain electrode SU1 in the discharge space is changed to the sustain pulse voltage (Vs). The voltage generated by the wall charge on SC1 and the voltage generated by the wall charge on sustain electrode SU1 are added together and exceed the discharge start voltage. A sustain discharge occurs between scan electrode SC1 and sustain electrode SU1, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Negative wall charges are accumulated on scan electrode SC1, and positive wall charges are accumulated on sustain electrode SU1. Similarly, a sustain discharge occurs in a discharge cell that has caused an address discharge among the discharge cells in the second line. In the discharge cells in which the address discharge has not occurred, the sustain discharge does not occur, and the wall charge state at the end of the initialization period is maintained.

  At time t2, scan potential Va is applied to scan electrode SC1081 belonging to the second display electrode pair group, and address pulse potential is applied to data electrode Dk of the discharge cell that should emit light on line 1081 among data electrodes D1 to Dm. Vd is given. As a result, an address discharge occurs between data electrode Dk and scan electrode SC1081, and between sustain electrode SU1081 and scan electrode SC1081, positive wall charges are accumulated on scan electrode SC1081, and negative charge is applied on sustain electrode SU1081. Wall charges are accumulated. In this way, the address operation is performed in which the address discharge is caused in the discharge cell to emit light on the 1081 line and the wall charges are accumulated on each electrode.

  Then, after applying the scanning potential Va to the scanning electrode SC1081 of the 1081st line, the scanning potential Va is applied to the scanning electrode SC1082 of the 1082th line, and the discharge cell to be emitted on the 1082th line among the data electrodes D1 to Dm. An address pulse potential Vd is applied to the data electrode Dk. As a result, an address discharge is generated between data electrode Dk and scan electrode SC1082 and between sustain electrode SU1082 and scan electrode SC1082, positive wall charges are accumulated on scan electrode SC1082, and a negative wall is formed on sustain electrode SU1082. Charge is accumulated.

  Thereafter, the same address operation is performed until the discharge cell on the 2160th line. In the discharge cell in which the address discharge has occurred, the sustain discharge is generated by the subsequent application of the sustain pulse.

  As can be seen from FIG. 4 and the like, the scanning potential Va is applied to a desired scanning electrode while the potential of the paired sustaining electrode is maintained at the sustaining pulse potential Vs, and an address operation is performed. Then, while the sustain electrode is maintained at the sustain pulse potential Vs, an address operation is performed on the discharge cells of the two lines, and during the period A corresponding to the rise and fall periods of the sustain pulse applied to the display electrode pair. No write operation is performed during this time. For example, the sustain pulse period may be about 5 to 6 μs, the time during which the potential Vs is maintained may be about 2 to 3 μs, and the application time of the scanning potential Va may be about 1 to 1.5 μs. Then, for each display electrode pair group, an address operation is alternately performed by two display electrode pairs (two lines). Write operation for two lines corresponding to two display electrode pairs belonging to the first display electrode pair group, and write operation for two lines corresponding to two display electrode pairs belonging to the second display electrode pair group Are performed alternately.

  Then, at time t3 after applying sustain pulse train corresponding to luminance weight “60” of the first subfield to scan electrode SC1 and sustain electrode SU1, 0 is applied to scan electrodes SC1 to SC1080 belonging to the first display electrode pair group. The potential (V) is applied, and the potential Vs is applied to the sustain electrodes SU1 to SU1080. Further, potential Vs is applied to scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group, and 0 (V) potential is applied to sustain electrodes SU1081 to SU2160. Further, immediately after time t3, a voltage (Vb−Vs) for making the erase potential Vb superimpose on the potential Vs is applied to the sustain electrode SU1 in the first line (that is, the sustain electrode SU1 is made the erase potential Vb). . As a result, an erasing discharge is generated between the scan electrode SC1 and the sustain electrode SU1 of the discharge cell of the first line where the sustain discharge has occurred, and the sustain discharge of the discharge cell of the first line thereafter is generated. Stop. Thus, the first SF in the discharge cell on the first line is completed.

  In the present embodiment, scan pulse SC2 and sustain electrode SU2 are given a sustain pulse train corresponding to luminance weight “60” at the same timing as scan electrode SC1 and sustain electrode SU1, so two lines are applied at the same timing as sustain electrode SU1. The voltage (Vb−Vs) is also applied to the sustain electrode SU2 of the eye in a superimposed manner (that is, the sustain electrode SU2 is set to the erase potential Vb). As a result, an erasing discharge is generated between the scan electrode SC2 and the sustain electrode SU2 of the discharge cell of the second line in which the sustain discharge has occurred, and the sustain discharge of the subsequent discharge cells of the second line is stopped. Thus, the first SF in the discharge cell on the second line is completed.

  At the next time t4, the potential Vs is applied to scan electrodes SC1 to SC1080 belonging to the first display electrode pair group, and the potential of 0 (V) is applied to sustain electrodes SU1 to SU1080. Further, a potential of 0 (V) is applied to scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group, and a potential of Vs is applied to sustain electrodes SU1081 to SU2160. At this time, since the sustain pulse train corresponding to the luminance weight “60” is given to the display electrode pairs of the 1081st line and the 1082th line, the sustaining of the 1081st line and the 1082th line is further performed immediately after time t4. A voltage (Vb−Vs) is applied to electrodes SU1081 and SU1082 in a superimposed manner (that is, sustain electrodes SU1081 and SU1082 are set to erase potential Vb). As a result, wall charges are reduced between scan electrode SC1081 and sustain electrode SU1081 of the discharge cell in the 1081th line where sustain discharge has occurred, and between scan electrode SC1082 and sustain electrode SU1082 of the discharge cell in the 1082th line. The erasing discharge is generated, and the sustain discharges of the discharge cells on the 1081st line and the 1082th line thereafter are stopped. Thus, the first SF in the discharge cells of the 1081st line and the 1082th line is completed.

  Thereafter, the same erase operation is performed until the discharge cell on the 2160th line.

  At time t4, if the first SF address operation has been completed in all the discharge cells, the scan potential Va is sequentially applied to the scan electrodes SC1 and SC2 of the first line and the second line to perform the address operation in the second SF. It can be carried out.

  In each line, when the operation of the first SF ends, the operation of the next second SF is performed. In this way, the subfield operation is performed in the order of the first SF, the second SF, the third SF,..., The ninth SF. When the operation of the ninth SF (last subfield) for all lines ends, the field ends and the next field starts.

  As shown in FIG. 5, the initialization period is provided as the same period for all lines at the beginning of one field period. In FIG. 5, the timing for performing the writing operation (in this embodiment, the timing for applying the scanning potential Va to the scanning electrode) in the display period is indicated by a thick solid line, and the timing for performing the erasing operation (in this embodiment, the sustaining electrode). The timing at which the erasing potential Vb is applied) is indicated by a broken line. A period between the solid line and the broken line is a period in which the number of sustain pulses corresponding to the luminance weight is applied, and this period indicates a subfield for each display electrode pair.

  As can be seen from FIG. 5, the length of each subfield period is equal to the number of sustain pulses corresponding to the time and luminance weight required for performing the write operation on all the scan electrodes belonging to each display electrode pair group. Depends on the longer time required to provide the display electrode pair. In FIG. 5, the time of each subfield of the first SF and the second SF depends on the time required to give the sustain pulse, and the time of each subfield of the third SF to the ninth SF is a scan electrode belonging to the display electrode pair group. Depends on the time required to perform the write operation. However, since the ninth SF is the last subfield, the ninth SF is completed and the field can be completed when the erase operation is performed on the display electrode pair having the scan electrode SC2160. For this reason, the subfield having the smallest luminance weight (the smallest number of sustain pulses) is arranged in the last subfield so that the last write operation is performed on the display electrode pair having the scan electrode SC2160 and then erased. The time until the operation is performed can be minimized, and the time required for the image display processing of one field can be minimized. In other words, since the image display process for one field is performed in one field period of a fixed time, the time required for the sustain discharge can be maximized. Therefore, it is desirable that the last subfield of one field period is the subfield having the smallest luminance weight, that is, the smallest number of sustain pulses corresponding to the luminance weight.

  In the present embodiment, the display electrode pairs provided in the PDP 10 are divided into two display electrode pair groups, and the phase of the sustain pulse train applied during the display period is shifted by 180 degrees between the display electrode pair groups to perform the write operation. By alternately selecting the display electrode pair groups, and performing the write operation on the two lines corresponding to the two display electrode pairs in the selected display electrode pair group every time the display electrode pair group is selected, The write operation for the line can be performed efficiently, and the time required for the write operation for all the lines can be shortened. Furthermore, the sustain discharge can be continuously performed on the line on which the address operation has been performed, so that the sustain discharge can be performed while the address operation is being performed on another line. From the above, it is possible to secure sufficient time for sustaining discharge in each subfield. Therefore, even for an ultra-high definition panel having 2160 lines or more, a sufficient time for sustaining discharge can be secured, and the panel can be driven with sufficient luminance.

  FIG. 6 is a block diagram showing a configuration of plasma display apparatus 100 in the first exemplary embodiment of the present invention.

  The plasma display device 100 includes a PDP 10 and a driving device thereof. The drive device includes an image signal processing circuit 41, a data electrode drive circuit 42, a display electrode pair drive circuit 43, a timing generation circuit 44, and a power supply circuit (not shown) that supplies power necessary for each circuit (41 to 44). I have.

  The timing generation circuit 44 generates a timing signal for controlling the operation of each circuit 41, 42, 43 on the basis of the synchronization signal (horizontal synchronization signal and vertical synchronization signal), and supplies the timing signal to each circuit 41, 42, 43. .

  The image signal processing circuit 41 converts the input image signal into image data indicating light emission / non-light emission for each subfield, and outputs the image data to the data electrode drive circuit 42.

  The data electrode driving circuit 42 includes m switches for applying the address pulse potential Vd or 0 (V) to each of the m data electrodes D1 to Dm. The image data output from the image signal processing circuit 41 is converted into address pulses corresponding to the data electrodes D1 to Dm and applied to the data electrodes D1 to Dm.

  Display electrode pair drive circuit 43 drives each of scan electrodes SC1 to SC2160 and sustain electrodes SU1 to SU2160 based on a timing signal provided from timing generation circuit 44.

  FIG. 7 is a circuit diagram of the display electrode pair drive circuit 43 of the plasma display device 100 according to the first embodiment of the present invention. The display electrode pair drive circuit 43 includes two sustain pulse generation circuits 50 and 60, two initialization waveform generation circuits 70 and 80, two scan pulse generation circuits 91 and 96, two erase pulse generation circuits 92, 97.

  The sustain pulse generation circuit 50 includes a power recovery capacitor C51, switching elements Q51 and Q52, backflow prevention diodes D51 and D52, and a resonance inductor L51 that constitute the power recovery unit 51, and further includes a voltage clamp unit. It has the switching elements Q55 and Q56 which comprise. Sustain pulses are applied to scan electrodes SC1 to SC1080 and sustain electrodes SU1081 to SU2160.

  The power recovery unit 51 performs LC resonance between the interelectrode capacitance between the display electrodes (hereinafter referred to as “interelectrode capacitance Cp”) and the inductor L51 to rise and fall the sustain pulse. When the sustain pulse rises, the electric charge stored in the power recovery capacitor C51 is moved to the interelectrode capacitance Cp via the switching element Q51, the diode D51, and the inductor L51. When the sustain pulse falls, the charge stored in the interelectrode capacitance Cp is returned to the power recovery capacitor C51 via the inductor L51, the diode D52, and the switching element Q52. In this way, the power recovery unit 51 drives the display electrode by LC resonance without being supplied with power from the power source, so that power consumption is ideally zero. The power recovery capacitor C51 has a sufficiently large capacity compared to the interelectrode capacitance Cp, and is charged to about Vs / 2, which is half of the sustain pulse voltage (Vs), so as to serve as a power source for the power recovery unit 51. ing.

  The voltage clamp unit connects the display electrode driven via the switching element Q55 to the power source and clamps it to the potential Vs. Further, the display electrode driven via the switching element Q56 is grounded and clamped to 0 (V). Therefore, the impedance at the time of voltage application by a voltage clamp part is small, and the big discharge current by strong sustain discharge can be sent stably.

  Thus, sustain pulse generating circuit 50 provides sustain pulses to scan electrodes SC1 to SC1080 and sustain electrodes SU1081 to SU2160 by controlling switching elements Q51, Q52, Q55, and Q56. Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.

  Initialization waveform generation circuit 70 includes Miller integration circuit 71 for applying a gently rising ramp waveform potential to scan electrodes SC1 to SC1080 during the initialization period, and Miller integration circuit 72 for applying a gently falling ramp waveform potential. And. In addition, a potential applying circuit 75 for applying a potential Ve to the sustain electrodes SU1081 to SU2160 via the switching element Q75 is provided. Switching elements Q73 and Q74 are separation switches, and are provided to prevent a current from flowing back through the parasitic diodes of the switching elements constituting sustain pulse generating circuit 50 and initialization waveform generating circuit 70. .

  Each of the sustain pulse generation circuit 50 and the initialization waveform generation circuit 70 has a known configuration that has been conventionally used.

  Scan pulse generation circuit 91 has a DC power supply V91 of a voltage (−Va) for applying scan potential Va to scan electrodes SC1 to SC1080, and switching for applying scan potential Va to scan electrode SC1 as necessary. Elements Q91H1 and Q91L1, switching elements Q91H2 and Q91L2 for applying to scan electrode SC2,..., Switching elements Q91H1080 and Q91L1080 for applying to scan electrode SC1080 are provided. By controlling switching elements Q91H1 to Q91H1080 and Q91L1 to Q91L1080, scan potential Va is sequentially applied to scan electrodes SC1 to SC1080 at the timing described above.

  Erase pulse generation circuit 92 has a DC power supply V92 of a voltage (Vs−Vb) for applying erase potential Vb to sustain electrodes SU1081 to SU2160, and applies erase potential Vb to sustain electrode SU1081 as necessary. Switching elements Q92H1081 and Q92L1081, switching elements Q92H1082 and Q92L1082 for applying to sustain electrode SU1082,..., And switching elements Q92H2160 and Q92L2160 for applying to sustain electrode SU2160. Then, by controlling switching elements Q92H1081 to Q92H2160 and Q92L1081 to Q92L2160, erase potential Vb is applied to sustain electrodes SU1081 to SU2160 at the timing described above.

  Sustain pulse generation circuit 60 has the same configuration as sustain pulse generation circuit 50, and initialization waveform generation circuit 80 has the same configuration as initialization waveform generation circuit 70, and therefore description thereof is omitted. Scan pulse generation circuit 96 has a configuration similar to that of scan pulse generation circuit 91, has a DC power supply V96 of voltage (−Va), and sequentially applies scan potential Va to scan electrodes SC1081 to SC2160 at the timing described above. Further, erase pulse generating circuit 97 has the same configuration as erase pulse generating circuit 92, has a DC power supply V97 of voltage (Vs−Vb), and applies erase potential Vb to sustain electrodes SU1 to SU1080 at the timing described above.

  Next, the operation of the display electrode pair drive circuit 43 in the display period will be described. FIG. 8 is a timing chart showing the operation of the display electrode pair drive circuit 43 according to Embodiment 1 of the present invention. One period (Ts1, Ts2, etc.) of the sustain pulse repetition period (hereinafter abbreviated as “sustain period”) is divided into six periods indicated by T1 to T6, and each period will be described. In the following description, the conduction state of the switching element is expressed as ON, and the cutoff state is expressed as OFF.

  In the display period, the switching elements Q73, Q74, Q83, Q84 are ON, and the Miller integrating circuits 71, 72, 81, 82 and the potential applying circuits 75, 85 do not operate.

  Here, the first display electrode pair group will be described, but the same applies to the second display electrode pair group.

(Period T1)
At time t1, switching element Q52 is turned on. Then, current starts to flow from scan electrodes SC1 to SC1080 through switching elements Q91H1 to Q91H1080, switching elements Q74 and Q73, inductor L51, diode D52 and switching element Q52 to capacitor C51, and the voltages of scan electrodes SC1 to SC1080 start to drop. Here, since the inductor L51 and the interelectrode capacitance Cp form a resonance circuit, the potential of the scan electrodes SC1 to SC1080 drops to near 0 (V) after the time ½ of the resonance period has elapsed.

(Period T2)
At time t2, switching element Q56 is turned on. Then, since scan electrodes SC1 to SC1080 are grounded through switching element Q56, the potentials of scan electrodes SC1 to SC1080 are clamped to 0 (V).

  At time t2, switching element Q61 is turned on. Then, a current begins to flow from the power recovery capacitor C61 to the sustain electrodes SU1 to SU1080 through the switching element Q61, the diode D61, the inductor L61, and the switching elements Q97H1 to Q97H1080, and the voltage of the sustain electrodes SU1 to SU1080 starts to rise. Here, since inductor L61 and interelectrode capacitance Cp form a resonance circuit, the potential of sustain electrodes SU1 to SU1080 rises to the vicinity of potential Vs after the time ½ of the resonance period has elapsed.

(Period T3)
At time t3, switching element Q65 is turned on. Then, since sustain electrodes SU1 to SU1080 are connected to the power source of potential Vs through switching element Q65, sustain electrodes SU1 to SU1080 are clamped to potential Vs.

  When sustain electrodes SU1 to SU1080 are clamped at potential Vs, the potential difference between scan electrodes SC1 to SC1080 and sustain electrodes SU1 to SU1080 exceeds the discharge start voltage in the discharge cell in which the address discharge has occurred, and sustain discharge occurs. .

  Note that in the period T3, the potentials of scan electrodes SC1 to SC1080 are maintained at 0 (V), and the potentials of sustain electrodes SU1 to SU1080 are maintained at sustain pulse potential Vs. During this period T3, scan potential Va can be applied to any of scan electrodes SC1 to SC1080 as necessary. For example, to apply scan potential Va to scan electrode SCi, switching element Q91Hi is turned off and switching element Q91Li is turned on at time t3a. At time t3b, switching element Q91Hi is returned to ON, and switching element Q91Li is returned to OFF.

(Period T4)
At time t4, switching element Q62 is turned on. Then, current starts to flow from sustain electrodes SU1 to SU1080 through switching elements Q97H1 to Q97H1080, inductor L61, diode D62 and switching element Q62 to capacitor C61, and the voltages of sustain electrodes SU1 to SU1080 begin to drop. Here, since inductor L61 and interelectrode capacitance Cp form a resonance circuit, the potentials of sustain electrodes SU1 to SU1080 drop to near 0 (V) after a time ½ of the resonance period has elapsed.

(Period T5)
At time t5, switching element Q66 is turned on. Then, since sustain electrodes SU1 to SU1080 are grounded through switching element Q66, the potentials of sustain electrodes SU1 to SU1080 are clamped to 0 (V).

  At time t5, switching element Q51 is turned on. Then, a current starts to flow from scanning capacitor Q51, diode D51, inductor L51, switching elements Q73, Q74 and switching elements Q91H1-Q91H1080 to scan electrodes SC1-SC1080 from power recovery capacitor C51, and the voltages of scan electrodes SC1-SC1080 are changed. Start to rise. Here, since the inductor L51 and the interelectrode capacitance Cp also form a resonance circuit, the potential of the scan electrodes SC1 to SC1080 rises to the vicinity of the potential Vs after the time ½ of the resonance period has elapsed.

(Period T6)
At time t6, switching element Q55 is turned on. Then, scan electrodes SC1 to SC1080 are connected to the power source of potential Vs through switching element Q55, so that scan electrodes SC1 to SC1080 are clamped to potential Vs.

  When scan electrodes SC1 to SC1080 are clamped at potential Vs, the potential difference between scan electrodes SC1 to SC1080 and sustain electrodes SU1 to SU1080 exceeds the discharge start voltage in the discharge cell in which the address discharge has occurred, and sustain discharge occurs. .

  Note that during the period T3 and the period T4, the erase potential Vb can be applied to any of the sustain electrodes SU1 to SU1080 as necessary. For example, in order to apply sustain pulse potential Vb to sustain electrode SUi, switching element Q97Hi is turned off and switching element Q97Li is turned on at time t3c of sustain period Ts2. At time t4c, switching element Q97Hi is turned back on and switching element Q97Li is turned off.

  As described above, the operation shown in the period T1 to the period T6 is repeated, so that the sustain pulse is applied to the display electrode pair in the display period. Switching element Q51 may be turned off after time t6 and before time t1 of the next sustain period, and switching element Q52 may be turned off after time t2 and before time t5. Switching element Q61 may be turned off after time t3 and before time t4, and switching element Q62 may be turned off after time t5 and before time t2 of the next sustain period. Further, in order to lower the output impedance of sustain pulse generating circuits 50 and 60, switching element Q55 is switched immediately before time t1 of the next sustain period, switching element Q56 is switched immediately before time t5, and switching element Q65 is switched immediately before time t4. It is desirable to turn off element Q66 immediately before time t2 of the next sustain period.

  In the present embodiment, the display electrode pair located in the upper half of the PDP 10 is described as a first display electrode pair group, and the display electrode pair located in the lower half of the PDP 10 is described as a second display electrode pair group. However, the method of grouping the display electrode pair groups is not limited to this. For example, scan electrodes SC1, SC3,..., SC2159 for odd lines and sustain electrodes SU1, SU3,..., SU2159 for odd lines are set as the first display electrode pair group, and scan electrodes SC2, SC4 for even lines are used. ,..., SC2160 and even-numbered sustain electrodes SU2, SU4,..., SU2160 can also be applied to the second display electrode pair group.

  In the present embodiment, the case where all the display electrode pairs are divided into two display electrode pair groups has been described. However, the present invention can be achieved by dividing all the display electrode pairs into three or more display electrode pair groups. Can be applied. In the following second embodiment, an example in which the display electrode pairs are divided into four display electrode pair groups will be described.

(Embodiment 2)
FIG. 9 is an electrode array diagram of PDP 10 in accordance with the second exemplary embodiment of the present invention. PDP 10 shown in FIG. 9 has the same configuration as PDP 10 in the first embodiment.

  In the second embodiment, the first display electrode pair group, the second display electrode pair group, the third display electrode pair group, and the fourth display electrode are sequentially arranged from the display electrode pair positioned at the top of the PDP 10. VS group. That is, 540 scan electrodes SC1 to SC540 (first scan electrode group g1sc) and 540 sustain electrodes SU1 to SU540 (first sustain electrode group g1su) belong to the first display electrode pair group. Scan electrodes SC541 to SC1080 (second scan electrode group g2sc) and 540 sustain electrodes SU541 to SU1080 (second sustain electrode group g2su) belong to the second display electrode pair group, and 540 scan electrodes SC1081. SC1620 (third scan electrode group g3sc) and 540 sustain electrodes SU1081 to SU1620 (third sustain electrode group g3su) belong to the third display electrode pair group, and 540 scan electrodes SC1621 to SC2160 (first scan electrode group g3sc). 4 scan electrode groups g4sc) and 54 Sustain electrodes SU1621～SU2160 (Fourth sustain electrode group G4su) belong to the fourth display electrode pair group.

  Next, a method for driving the PDP in the second embodiment will be described. This PDP driving method is performed in the second embodiment as the operation of the plasma display device as in the first embodiment.

  FIG. 10 is an enlarged view of the drive potential signal waveform applied to the scan electrode of the PDP 10 according to the second embodiment of the present invention, and the scan electrodes SC1, SC2, SC541, SC542, SC1081, SC1082, SC1621, SC1622 at the beginning of the display period. 3 shows details of drive potential signal waveforms applied to the data electrodes D1 to Dm. FIG. 11 is a diagram schematically showing the approximate timing for performing the write operation and the erase operation for each line in one field period in the second embodiment of the present invention. In FIG. 11, the vertical axis represents scan electrodes SC1 to SC2160 representing the display electrode pairs of each line, the horizontal axis represents time, and the timing of performing the writing operation in the display period (this embodiment) as in FIG. In the embodiment, the timing at which the scanning potential Va is applied to the scanning electrode is indicated by a thick solid line, and the timing at which the erasing operation is performed (in this embodiment, the timing at which the erasing potential Vb (see FIG. 3 and the like is applied)) is indicated by a broken line. Show.

  Also in the second embodiment, as in the first embodiment, an initializing period in which initializing discharge is performed simultaneously in all the discharge cells is provided at the beginning of one field period, and a display period is provided after the initializing period. The driving method in the second embodiment is different from the first embodiment in that the display electrode pairs are divided into four display electrode pair groups, and the phase of the sustain pulse train applied to the display electrode pairs belonging to each of these groups in the display period is set. The groups are shifted by 90 degrees between the groups, the groups are selected in the order in which the phase of the sustain pulse train is advanced, and the write operation is performed by two lines for the selected group.

  In the present embodiment, in the display period, the sustain pulse train whose phase is delayed by 90 degrees with respect to the sustain pulse train applied to scan electrodes SC1 to SC540 belonging to the first display electrode pair group is scanned in the second display electrode pair group. Scan electrodes SC1081 belonging to the third display electrode pair group are provided with sustain pulse trains having a phase delayed by 180 degrees with respect to sustain pulse trains applied to electrodes SC541 to SC1080 and applied to scan electrodes SC1 to SC540 belonging to the first display electrode pair group. A sustain pulse train whose phase is delayed by 270 degrees with respect to sustain pulse trains applied to SC1620 and applied to scan electrodes SC1 to SC540 belonging to the first display electrode pair group is applied to scan electrodes SC1621 to SC2160 belonging to the fourth display electrode pair group. .

  As in the case of the first embodiment, the sustain electrodes are given a sustain pulse train that is 180 degrees out of phase with the sustain pulse train applied to the scan electrodes belonging to the same display electrode pair group. Therefore, a sustain pulse train whose phase is delayed by 90 degrees with respect to sustain pulse trains applied to sustain electrodes SU1 to SU540 belonging to the first display electrode pair group is applied to sustain electrodes SU541 to SU1080 belonging to the second display electrode pair group, and A sustain pulse train whose phase is delayed by 180 degrees with respect to sustain pulse trains applied to sustain electrodes SU1 to SU540 belonging to one display electrode pair group is applied to sustain electrodes SU1081 to SU1620 belonging to the third display electrode pair group, and the first display A sustain pulse train whose phase is delayed by 270 degrees with respect to sustain pulse trains applied to sustain electrodes SU1 to SU540 belonging to the electrode pair group is applied to sustain electrodes SU1621 to SU2160 belonging to the fourth display electrode pair group.

  In the first embodiment, as described in the period T3 of the sustain period Ts1 in FIG. 8, the scan potential Va is set to 0 (V) in the display electrode pair, and the sustain electrode potential is the sustain pulse in the display electrode pair. When the potential is kept at Vs, it is applied to a desired scan electrode. On the other hand, since the sustain pulse has a rise time and a fall time, in the first embodiment, as shown in period A in FIG. 4, there is a time during which scan potential Va cannot be applied to any scan electrode. To do. Since the write operation cannot be performed during this time, the time required for performing the write operation on all the lines becomes long.

  On the other hand, in the second embodiment, as shown in FIG. 10, there is always a display electrode pair in which the potential of the scan electrode is 0 (V) and the potential of the sustain electrode is maintained at the sustain pulse potential Vs. Therefore, the write operation can be continuously performed, and the time required for performing the write operation on all the lines can be further shortened.

  In the second embodiment, an address operation is sequentially performed on each display electrode pair group by two display electrode pairs (two lines). An address operation is performed on two lines corresponding to two display electrode pairs belonging to the first display electrode pair group, and then two lines corresponding to two display electrode pairs belonging to the second display electrode pair group are performed. A write operation is performed on the lines, then a write operation is performed on two lines corresponding to the two display electrode pairs belonging to the third display electrode pair group, and then 2 2 belonging to the fourth display electrode pair group. A write operation is performed on two lines corresponding to the pair of display electrodes. This operation is repeated to perform the write operation for all lines.

  In the second embodiment, as described above, the time required for performing the write operation on all the display electrode pairs can be shortened to about ½ of the time in the first embodiment. Therefore, as compared with the case of Embodiment 1, it is possible to secure a sufficient time for sustaining discharge and drive with sufficient luminance even for an ultra-high definition panel.

  The plasma display device according to the second embodiment is shown in the same block diagram as FIG. 6, but each circuit (41 to 44) of the driving device may be configured so that the above driving method can be performed.

  For example, in the case of the first embodiment, the display electrode pair drive circuit 43 includes a sustain pulse generation circuit 50, an initialization waveform generation circuit 70, a scan pulse generation circuit 91, and an erase pulse generation circuit, as shown in FIG. 92, a first sustain scan electrode drive circuit, a sustain pulse generation circuit 60, an initialization waveform generation circuit 80, a scan pulse generation circuit 96, and a second sustain scan drive circuit 97. I have. On the other hand, in the case of the second embodiment, the sustain scan electrode drive circuit has four sustain scan electrode drive circuits similar to the first and second sustain scan electrode drive circuits. It is only necessary to drive the scan electrode and the sustain electrode that give the sustain pulse train having the same phase. That is, if the four sustain scan electrode drive circuits are the first to fourth sustain scan electrode drive circuits, the first sustain scan electrode drive circuit can be configured to have scan electrodes SC1 to SC540 belonging to the first display electrode pair group. The sustain electrodes SU1081 to SU1620 belonging to the third display electrode pair group are driven, and the second sustain scan electrode drive circuit is configured to drive scan electrodes SC541 to SC1080 belonging to the second display electrode pair group and the fourth The sustain electrodes SU1621 to SU2160 belonging to the first display electrode pair group are driven, and the third sustain scan electrode driving circuit is configured to drive scan electrodes SC1081 to SC1620 and the first display belonging to the third display electrode pair group. The sustain electrodes SU1 to SU540 belonging to the electrode pair group are configured to be driven, and the fourth sustain scan electrode drive circuit is configured to It may be configured to drive the sustain electrodes SU541~SU1080 the scan electrodes SC1621~SC2160 belonging to the display electrode pair groups and belonging to the second display electrode pair group.

  Also in the second embodiment, the grouping method of the display electrode pair group is not limited to the above-described method. For example, scan electrodes SC1, SC5,..., SC2157 of (4p + 1) lines (p = 0, 1, 2,...) And sustain electrodes SU1, SU5,. (4p + 2) lines of scan electrodes SC2, SC6,..., SC2158 and sustain electrodes SU2, SU6,..., SU2158 are set as a second display electrode pair group, and (4p + 3) lines of scan electrodes. SC3, SC7,..., SC2159 and sustain electrodes SU3, SU7,..., SU2159 are set as a third display electrode pair group, and (4p + 4) -line scan electrodes SC4, SC8,. The present invention can also be applied to the sustain electrodes SU4, SU8,..., SU2160 as the fourth display electrode pair group.

  In the first and second embodiments, when performing the write operation, the display electrode pair group is selected in order, and the write operation is performed on a plurality of (two in the above example) lines in the selected display electrode pair group. However, it is not limited to this. For example, it is possible to perform an address operation for each line for each selected display electrode pair group.

  In the first and second embodiments, the erasing potential Vb is applied to the sustain electrode in order to stop the sustain discharge. Instead, a predetermined potential is applied to the scan electrode when the sustain electrode is at the potential Vs. For example, an erasing potential of (Vs−Vb) may be applied.

  In addition, the specific numerical values used in the first and second embodiments are merely examples, and should be appropriately set to optimum values according to the characteristics of the PDP, the specifications of the plasma display device, and the like. Is desirable.

  In the present invention, even for an ultra-high definition plasma display panel having 2160 lines or more, a sufficient time for sustaining discharge can be secured, and the plasma display panel can be driven with sufficient luminance. It is useful as a driving method and a plasma display device.

It is a disassembled perspective view which shows the structure of the plasma display panel used for Embodiment 1 of this invention. It is an electrode arrangement | sequence figure of the plasma display panel used for Embodiment 1 of this invention. It is a wave form diagram of the drive potential signal given to each electrode of the plasma display panel in Embodiment 1 of the present invention. It is an enlarged view of the drive potential signal waveform given to the scan electrode of the plasma display panel in Embodiment 1 of the present invention. In Embodiment 1 of this invention, it is a figure which shows typically the approximate timing which performs the write-in operation | movement and the erase | elimination operation | movement with respect to each line in 1 field period. It is a block diagram which shows the structure of the plasma display apparatus in Embodiment 1 of this invention. It is a circuit diagram of the display electrode pair drive circuit of the plasma display apparatus in Embodiment 1 of the present invention. 3 is a timing chart showing the operation of the display electrode pair drive circuit according to the first embodiment of the present invention. It is an electrode arrangement | sequence figure of the plasma display panel used for Embodiment 2 of this invention. It is an enlarged view of the drive potential signal waveform given to the scan electrode of the plasma display panel in Embodiment 2 of the present invention. In Embodiment 2 of this invention, it is a figure which shows typically the approximate timing which performs the write-in operation | movement and the erasure operation | movement with respect to each line in 1 field period.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Plasma display panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 42 Data electrode drive circuit 43 Display electrode pair drive circuit 44 Timing generation circuit 100 Plasma display apparatus

Claims (16)

A plurality of display electrode pairs each including a pair of scan electrodes and sustain electrodes and a plurality of data electrodes are arranged so as to intersect with a gap, and a discharge space including a gap between the display electrode pair and the data electrode. And a method of driving a plasma display panel having a plurality of discharge cells having the display electrode pair and the data electrode forming the gap serving as the discharge space,
Dividing the plurality of display electrode pairs into first to Nth (N is plural) groups;
For each cell line composed of a plurality of discharge cells corresponding to the display electrode pair, a one-line address process for generating an address discharge in the discharge cells to be lit, and a discharge cell in which the address discharge is generated A process of continuously performing a one-line maintenance process for generating a sustain discharge and a one-line maintenance end process for generating an erasing discharge in the discharge cells that have generated the sustain discharge in order to stop the sustain discharge, 1-line display processing including 1st to M-th (M is a plurality) 1-line writing maintenance processing having the 1-line maintenance processing corresponding to different predetermined luminance weights, respectively,
After the one-line write processing included in the P-th (P is an integer of 1 to M-1) one-line write maintenance processing for all the cell lines, the (P + 1) th one-line write maintenance processing is performed. The one-line writing process is started, and one-field image display is performed by performing the one-line display process for all the cell lines.
While performing each of the first to Mth one-line write maintaining processes, the display electrode pair corresponding to the cell line that is the target of the one-line write maintaining process is switched to a positive voltage and a negative voltage. Apply a polarity voltage pulse train,
In the one-line address process, a scan selection potential is applied to the scan electrode corresponding to the cell line to be subjected to the one-line address process, and an address potential is applied to the data electrode of the discharge cell to be lit. In the processing for generating the address discharge, a scanning voltage obtained by superimposing a first predetermined voltage on the positive voltage or the negative voltage of the voltage pulse in order to give a scanning selection potential to the scanning electrode is applied to the display electrode. Applying to the pair and applying the write potential simultaneously with the application of the scanning voltage,
The one-line maintaining process is performed by applying a number of the voltage pulses corresponding to a predetermined luminance weight to the one-line writing maintaining process including the one-line maintaining process, to the display electrode pair,
The one-line maintenance end process is performed by applying an erasing voltage in which a second predetermined voltage is superimposed on the positive voltage or the negative voltage of the voltage pulse to the display electrode pair,
The phase of the voltage pulse train applied to the display electrode pair of the Kth group (K is an integer of 2 to N) is delayed from the first group by different angles, respectively.
Performing the one-line writing process at different timings for each of the cell lines, and repeatedly selecting each of the groups in the order of the group in which the phase of the voltage pulse train applied to the display electrode pair is advanced, A method for driving a plasma display panel, wherein the one-line writing process is performed on the cell lines corresponding to one or a plurality of the display electrode pairs in the selected group each time each of the groups is selected.   Applied to the plurality of display electrode pairs in the group at the same timing with respect to the plurality of cell lines corresponding to the plurality of display electrode pairs in the selected group each time the group is selected. The plasma display panel driving method according to claim 1, wherein the one-line writing process is performed within an application period of the positive voltage or the negative voltage of a voltage pulse.   A period for performing the one-line write process on the cell lines corresponding to the display electrode pairs in one group among the first to Nth groups is applied to the display electrode pairs in any other group. The method for driving a plasma display panel according to claim 1, wherein the voltage pulse overlaps a rising or falling period of the voltage pulse.   2. The plasma display panel according to claim 1, wherein the phase of the voltage pulse train applied to the display electrode pairs of the Kth group is delayed by [360 × (K−1) / N] degrees with respect to the first group. Driving method.   The method of driving a plasma display panel according to claim 4, wherein the number of the groups is 2 to 4 (N = 2 to 4).   During the period in which the one-field image display is performed, a part of the first to Nth groups is applied to all the display electrode pairs in the group while the one-line write maintenance process is performed. The method of driving a plasma display panel according to claim 1, wherein a common voltage pulse train having a fixed period to be the voltage pulse train is applied.   2. The plasma according to claim 1, further comprising an initializing period for generating an initializing discharge for bringing all the discharge cells into a chargeable state capable of address discharge immediately before the period for performing image display of the one field. Display panel drive method.   2. The method of driving a plasma display panel according to claim 1, wherein a luminance weight for the M-th one-line write maintaining process is the smallest among the first to M-th one-line write sustain processes. A plurality of display electrode pairs each including a pair of scan electrodes and sustain electrodes and a plurality of data electrodes are arranged so as to intersect with a gap, and a discharge space including a gap between the display electrode pair and the data electrode. A plasma display panel having a plurality of discharge cells having the display electrode pair and the data electrode forming the gap serving as the discharge space, and a driving device for driving the plasma display panel,
The driving device includes:
Dividing the plurality of display electrode pairs into first to Nth (N is plural) groups;
For each cell line composed of a plurality of discharge cells corresponding to the display electrode pair, a one-line address process for generating an address discharge in the discharge cells to be lit, and a discharge cell in which the address discharge is generated A process of continuously performing a one-line maintenance process for generating a sustain discharge and a one-line maintenance end process for generating an erasing discharge in the discharge cells that have generated the sustain discharge in order to stop the sustain discharge, 1-line display processing including 1st to M-th (M is a plurality) 1-line writing maintenance processing having the 1-line maintenance processing corresponding to different predetermined luminance weights, respectively,
After the one-line write processing included in the P-th (P is an integer of 1 to M-1) one-line write maintenance processing for all the cell lines, the (P + 1) th one-line write maintenance processing is performed. The one-line writing process is started, and one-field image display is performed by performing the one-line display process for all the cell lines.
While performing each of the first to Mth one-line write maintaining processes, the display electrode pair corresponding to the cell line that is the target of the one-line write maintaining process is switched to a positive voltage and a negative voltage. Apply a polarity voltage pulse train,
In the one-line address process, a scan selection potential is applied to the scan electrode corresponding to the cell line to be subjected to the one-line address process, and an address potential is applied to the data electrode of the discharge cell to be lit. In the processing for generating the address discharge, a scanning voltage obtained by superimposing a first predetermined voltage on the positive voltage or the negative voltage of the voltage pulse in order to give a scanning selection potential to the scanning electrode is applied to the display electrode. Applying to the pair and applying the write potential simultaneously with the application of the scanning voltage,
The one-line maintaining process is performed by applying a number of the voltage pulses corresponding to a predetermined luminance weight to the one-line writing maintaining process including the one-line maintaining process, to the display electrode pair,
The one-line maintenance end process is performed by applying an erasing voltage in which a second predetermined voltage is superimposed on the positive voltage or the negative voltage of the voltage pulse to the display electrode pair,
The phase of the voltage pulse train applied to the display electrode pair of the Kth group (K is an integer of 2 to N) is delayed from the first group by different angles, respectively.
Performing the one-line writing process at different timings for each of the cell lines, and repeatedly selecting each of the groups in the order of the group in which the phase of the voltage pulse train applied to the display electrode pair is advanced, A plasma display device configured to perform the one-line writing process on the cell line corresponding to one or a plurality of the display electrode pairs in the selected group each time the group is selected.   The driving device performs the same timing for the plurality of display electrode pairs in the group with respect to the plurality of cell lines corresponding to the plurality of display electrode pairs in the group selected each time the group is selected. The plasma display device according to claim 9, wherein the one-line writing process is performed within an application period of the positive voltage or the negative voltage of the voltage pulse applied in step 1.   In the driving device, a period during which the one-line writing process is performed on the cell lines corresponding to the display electrode pairs in one group among the first to Nth groups is performed in the display in any other group. The plasma display device according to claim 9, wherein the plasma display device is configured to overlap a rising or falling period of the voltage pulse applied to the electrode pair.   The driving device is configured to delay the phase of the voltage pulse train applied to the display electrode pairs of the Kth group by [360 × (K−1) / N] degrees with respect to the first group. The plasma display device according to claim 9.   The plasma display apparatus according to claim 12, wherein the number of the groups is 2 to 4 (N = 2 to 4).   In the first to Nth groups, a part of all the display electrode pairs in the group is partly in the one-line write maintaining process during the period in which the one-field image display is performed. The plasma display device according to claim 9, configured to apply a common voltage pulse train having a fixed period, which is the voltage pulse train to be applied during the operation.   The drive device is configured to have an initialization period in which an initialization discharge is generated immediately before the period during which the image display of the one field is performed so that all of the discharge cells are in a charged state capable of address discharge. The plasma display device according to claim 9.   10. The plasma display apparatus according to claim 9, wherein a luminance weight for the M-th one-line write maintaining process is the smallest among the first to M-th one-line write sustain processes.

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