JP2009171420A - Two-way divider - Google Patents

Two-way divider Download PDF

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JP2009171420A
JP2009171420A JP2008009306A JP2008009306A JP2009171420A JP 2009171420 A JP2009171420 A JP 2009171420A JP 2008009306 A JP2008009306 A JP 2008009306A JP 2008009306 A JP2008009306 A JP 2008009306A JP 2009171420 A JP2009171420 A JP 2009171420A
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output terminal
frequency
distributor
frequency line
divider
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JP4860638B2 (en
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Hiroyuki Hoshi
宏幸 星
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Nihon Dengyo Kosaku Co Ltd
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Nihon Dengyo Kosaku Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a two-way divider that can be made more compact than a conventional Wilkinson-type power divider. <P>SOLUTION: The two-way divider includes: a first high frequency line disposed between an input terminal and a first output terminal; a second high frequency line disposed between the input terminal and a second output terminal; third to sixth high frequency lines disposed between the first output terminal and the second output terminal; and a resistive element disposed between a connecting point of the third high frequency line and the fourth high frequency line and a connecting point of the fifth high frequency line and the sixth high frequency line. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、２分配器に係り、特に、従来のウィルキンソン型の電力分配器よりも小型化が可能な２分波器に関する。   The present invention relates to a two-way divider, and more particularly to a two-way duplexer that can be made smaller than a conventional Wilkinson-type power divider.

従来、２分配器として、ウィルキンソン型の電力分配器が知られている。（下記、非特許文献１参照）
図５は、従来のウィルキンソン型の電力分配器の回路構成を示す回路図、図６は、従来のウィルキンソン型の電力分配器の実際の回路パターンを示す図である。
図５、図６において、１０は誘電体基板、２０１は入力端子、２０２は出力端子１、２０３は出力端子２、Ｔ２０１、Ｔ２０２は高周波線路、Ｒ２０１は抵抗素子である。ここで、高周波線路（Ｔ２０１，Ｔ２０２）は、通常のマイクロストリップラインで構成されるλｏ／４線路である。したがって、図示は省略するが、図５では、誘電体基板１０の裏面側には、面状の接地パターンが形成されている。また、λｏは、使用中心周波数（ｆｏ）の自由空間における波長（以下、自由空間波長という）である。
この従来のウィルキンソン型の電力分配器では、例えば、抵抗素子（Ｒ２０１）の出力端子２（２０３）側の接続部において、出力端子１（２０２）から高周波線路（Ｔ２０１）、および高周波線路（Ｔ２０２）を通って出力端子２（２０３）に流れる電流Ａと、出力端子１（２０２）から抵抗素子（Ｒ２０１）を通って出力端子２（２０３）に流れる電流Ｂが、同振幅で、逆位相の電流となるようにして、出力端子１（２０２）と出力端子２（２０３）との間のアイソレーションを取るようにしている。したがって、抵抗素子（Ｒ２０１）の抵抗値は、前述の電流Ａと電流Ｂとが、同振幅、逆位相となるような抵抗値とされる。 Conventionally, a Wilkinson type power distributor is known as a two distributor. (See Non-Patent Document 1 below)
FIG. 5 is a circuit diagram showing a circuit configuration of a conventional Wilkinson type power divider, and FIG. 6 is a diagram showing an actual circuit pattern of the conventional Wilkinson type power divider.
5 and 6, 10 is a dielectric substrate, 201 is an input terminal, 202 is an output terminal 1, 203 is an output terminal 2, T201 and T202 are high-frequency lines, and R201 is a resistance element. Here, the high-frequency lines (T201, T202) are λo / 4 lines constituted by ordinary microstrip lines. Therefore, although not shown, a planar ground pattern is formed on the back surface side of the dielectric substrate 10 in FIG. Further, λo is a wavelength in the free space of the use center frequency (fo) (hereinafter referred to as free space wavelength).
In this conventional Wilkinson-type power divider, for example, at the connection portion on the output terminal 2 (203) side of the resistance element (R201), the high-frequency line (T201) and the high-frequency line (T202) from the output terminal 1 (202). Current A flowing through the output terminal 2 (203) through the output terminal 1 (202) and current B flowing through the resistance element (R201) from the output terminal 1 (202) into the output terminal 2 (203) have the same amplitude and opposite phase. Thus, the isolation between the output terminal 1 (202) and the output terminal 2 (203) is obtained. Therefore, the resistance value of the resistance element (R201) is set to such a resistance value that the current A and the current B have the same amplitude and opposite phase.

図７は、図５に示す従来のウィルキンソン型の電力分配器を３個する４分配器の回路構成を示す回路図、図８は、図７に示す４分配器の実際の回路パターンを示す図である。
図７、図８において、１０は誘電体基板、２０１は入力端子、２０４は出力端子１、２０５は出力端子２、２０６は出力端子３、２０７は出力端子４、Ｔ２０１〜Ｔ２０６は高周波線路、Ｒ２０１〜Ｒ２０３は抵抗素子である。
図７、図８に示す４分配器は、図５、図６に示すウィルキンソン型の電力分配器の各出力端子に、それぞれ図５、図６に示すウィルキンソン型の電力分配器を接続したものである。なお、高周波線路（Ｔ２０３〜Ｔ２０６）は、通常のマイクロストリップラインで構成されるλｏ／４線路である。したがって、図示は省略するが、図８でも、誘電体基板１０の裏面側には、面状の接地パターンが形成されている。 FIG. 7 is a circuit diagram showing a circuit configuration of a four distributor including three conventional Wilkinson type power distributors shown in FIG. 5, and FIG. 8 is a diagram showing an actual circuit pattern of the four distributors shown in FIG. It is.
7 and 8, 10 is a dielectric substrate, 201 is an input terminal, 204 is an output terminal 1, 205 is an output terminal 2, 206 is an output terminal 3, 207 is an output terminal 4, T201 to T206 are high-frequency lines, R201 ˜R203 is a resistance element.
The four dividers shown in FIGS. 7 and 8 are obtained by connecting the Wilkinson type power divider shown in FIGS. 5 and 6 to the output terminals of the Wilkinson type power divider shown in FIGS. 5 and 6, respectively. is there. Note that the high-frequency lines (T203 to T206) are λo / 4 lines configured by ordinary microstrip lines. Therefore, although not shown, a planar ground pattern is formed on the back side of the dielectric substrate 10 in FIG.

なお、本願発明に関連する先行技術文献としては以下のものがある。
小西 良弘：「実用マイクロ波技術講座」，第２巻，日刊工業新聞社(2003)，PP.55-98 As prior art documents related to the invention of the present application, there are the following.
Yoshihiro Konishi: “Practical microwave technology course”, Volume 2, Nikkan Kogyo Shimbun (2003), PP.55-98

図５、図６に示すウィルキンソン型の電力分配器では、回路構成上、出力端子（２０２、２０３）は、入力端子２０１に対して対向配置する必要があり、出力端子（２０２、２０３）に他のコンポーネント（例えば、図７、図８に示す他のウィルキンソン型の電力分配器等）を接続する場合、出力端子間に無駄なスペースが生まれ、誘電体基板１０の面積が大きくなってしまうという問題点がある。
本発明は、前記従来技術の問題点を解決するためになされたものであり、本発明の目的は、従来のウィルキンソン型の電力分配器よりも小型化を図ることが可能な２分波器を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかにする。 In the Wilkinson-type power divider shown in FIGS. 5 and 6, the output terminals (202, 203) must be disposed opposite to the input terminal 201 due to the circuit configuration, and other than the output terminals (202, 203). When connecting other components (for example, other Wilkinson-type power distributors shown in FIGS. 7 and 8), there is a problem that a wasteful space is generated between the output terminals, and the area of the dielectric substrate 10 is increased. There is a point.
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a duplexer that can be made smaller than a conventional Wilkinson-type power distributor. It is to provide.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記の通りである。
本発明の２分波器は、入力端子と第１出力端子との間に配置される第１高周波線路と、前記入力端子と第２出力端子との間に配置される第２高周波線路と、前記第１出力端子と前記第２出力端子との間に配置される第３ないし第６高周波線路と、前記第３高周波線路と第４高周波線路との接続点と、前記第５高周波線路と第６高周波線路との接続点との間に配置される抵抗素子とを備えることを特徴とする。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
The second duplexer of the present invention includes a first high-frequency line disposed between the input terminal and the first output terminal, a second high-frequency line disposed between the input terminal and the second output terminal, Third to sixth high-frequency lines disposed between the first output terminal and the second output terminal; a connection point between the third high-frequency line and the fourth high-frequency line; the fifth high-frequency line; And a resistance element arranged between the connection point with the six high-frequency lines.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記の通りである。
本発明の２分波器によれば、従来のウィルキンソン型の電力分配器よりも小型化を図ることが可能となる。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the duplexer of the present invention, it is possible to achieve a reduction in size as compared with the conventional Wilkinson type power divider.

以下、図面を参照して本発明の実施例を詳細に説明する。
なお、実施例を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
図１は、本発明の実施例の２分配器の回路構成を示す回路図、図２は、本発明の実施例の２分配器の実際の回路パターンを示す図である。
図１、図２において、１０は誘電体基板、１０１は入力端子、１０２は出力端子１、１０３は出力端子２、Ｔ１０１〜Ｔ１０６は高周波線路、Ｒ１０１は抵抗素子である。ここで、高周波線路（Ｔ１０１〜Ｔ１０６）は、通常のマイクロストリップラインで構成されるλｏ／４線路である。したがって、図示は省略するが、図１では、誘電体基板１０の裏面側には、面状の接地パターンが形成されている。また、λｏは、使用中心周波数（ｆｏ）の自由空間波長である。
本実施例の２分配器において、入力端子１０１から入力された信号は、出力端子１（１０２）と、出力端子２（１０３）とから同相の信号として出力される。
本実施例の２分配器では、例えば、図１のａ点から高周波線路（Ｔ１０１）、および高周波線路（Ｔ１０２）を通って図１のｄ点に流れる電流Ａと、図１のａ点から高周波線路（Ｔ１０３）、高周波線路（Ｔ１０５）、高周波線路（Ｔ１０６）、および高周波線路（Ｔ１０４）を通って図１のｄ点に流れる電流Ｂとは、同振幅で、逆位相の電流となるので、図１のｄ点の電圧は０Ｖとなる。
即ち、出力端子１（１０２）と出力端子２（１０３）との間のアイソレーションが取れているものとすると、図１のｄ点は短絡していると考えられるので、図１のｄ点は開放端になる。よって、図１のｅ−ｃ点間の高周波線路（Ｔ１０２）と高周波線路（Ｔ１０４）はないものとして考えることができる。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.
FIG. 1 is a circuit diagram showing a circuit configuration of a two distributor according to an embodiment of the present invention, and FIG. 2 is a diagram showing an actual circuit pattern of the two distributor according to the embodiment of the present invention.
1 and 2, 10 is a dielectric substrate, 101 is an input terminal, 102 is an output terminal 1, 103 is an output terminal 2, T101 to T106 are high-frequency lines, and R101 is a resistance element. Here, the high-frequency lines (T101 to T106) are λo / 4 lines configured by ordinary microstrip lines. Therefore, although not shown, a planar ground pattern is formed on the back side of the dielectric substrate 10 in FIG. Further, λo is a free space wavelength at the use center frequency (fo).
In the two distributor of the present embodiment, the signal input from the input terminal 101 is output as an in-phase signal from the output terminal 1 (102) and the output terminal 2 (103).
In the two distributors of the present embodiment, for example, the current A flowing from the point a in FIG. 1 to the point d in FIG. 1 through the high-frequency line (T101) and the high-frequency line (T102) and the point A in FIG. The current B flowing through the line (T103), the high-frequency line (T105), the high-frequency line (T106), and the high-frequency line (T104) to the point d in FIG. The voltage at point d in FIG. 1 is 0V.
That is, assuming that the output terminal 1 (102) and the output terminal 2 (103) are isolated, the point d in FIG. 1 is considered to be short-circuited, so the point d in FIG. Open end. Therefore, it can be considered that there is no high-frequency line (T102) and high-frequency line (T104) between points ec in FIG.

また、図１のｂ点から高周波線路（Ｔ１０５）、および高周波線路（Ｔ１０６）を通って図１のｃ点に流れる電流Ｃと、図１のｂ点から抵抗素子（Ｒ１０１）を通って図１のｃ点に流れる電流Ｄとは、同振幅で、逆位相の電流となるようにされる。
したがって、図１のｃ点の電圧は０Ｖとなり、結果として、図１のｂ点は終端されているもの見なせることなる。即ち、抵抗素子（Ｒ１０１）は、図１のｂ点を、入力端子１０１と同様終端されている状態にするために配置される。
したがって、本実施例において、入力ンピーダンスをＺｉｎ、出力インピーダンスをＺｏｕｔとするとき、各高周波線路（Ｔ１０１〜Ｔ１０６）の特性インピーダンス（Ｚｗ）、および、ａ−ｄ点間のインピーダンス（Ｚｏｕｔ１）は、（Ｚｗ）２＝Ｚｉｎ×Ｚｏｕｔ、Ｚｏｕｔ１＝Ｚｏｕｔを満足する必要がある。
図９は、本実施例の２分配器の周波数（ＧＨｚ）とＶＳＷＲとの関係を示すグラフであり、図９において、矢印Ａは、入力端子１０１のＶＳＷＲ、矢印Ｂは、出力端子１（１０２）と出力端子２（１０３）のＶＳＷＲである。図９から分かるように、周波数が、１．４５〜１．５５ＧＨｚの範囲において、入力端子１０１のＶＳＷＲと、出力端子１（１０２）と出力端子２（１０３）のＶＳＷＲは、それぞれ１．１以下となっている。
図１０は、本実施例の２分配器の周波数（ＧＨｚ）と分配損失（ｄＢ）との関係を示すグラフであり、出力端子１（１０２）と出力端子２（１０３）の分配損失（ｄＢ）を示すグラフである。図１０から分かるように、周波数が、１．４５〜１．５５ＧＨｚの範囲において、出力端子１（１０２）と出力端子２（１０３）の分配損失は、略−３ｄＢとなっている。
図１１は、本実施例の２分配器の周波数（ＧＨｚ）とアイソレーション（ｄＢ）との関係を示すグラフであり、出力端子１（１０２）と出力端子２（１０３）との間のアイソレーション（ｄＢ）を示すグラフである。図１１から分かるように、周波数が、１．４５〜１．５５ＧＨｚの範囲において、出力端子１（１０２）と出力端子２（１０３）との間のアイソレーションは、−２０ｄＢ以下となっている。
図９〜図１１から分かるように、本実施例の２分配器は、従来のウィルキンソン型の電力分配器と同様良好な電気特性を有していることが分かる。 Further, the current C flows from the point b in FIG. 1 through the high-frequency line (T105) and the high-frequency line (T106) to the point c in FIG. 1, and from the point b in FIG. 1 through the resistance element (R101). The current D flowing at the point c is set to have the same amplitude and opposite phase.
Accordingly, the voltage at the point c in FIG. 1 is 0 V, and as a result, the point b in FIG. 1 can be regarded as terminated. That is, the resistance element (R101) is arranged to bring the point b in FIG.
Therefore, in this embodiment, when the input impedance is Zin and the output impedance is Zout, the characteristic impedance (Zw) of each high-frequency line (T101 to T106) and the impedance (Zout1) between the points a to d are ( Zw) 2 = Zin × Zout and Zout1 = Zout must be satisfied.
FIG. 9 is a graph showing the relationship between the frequency (GHz) and the VSWR of the two dividers of this embodiment. In FIG. 9, the arrow A indicates the VSWR of the input terminal 101, and the arrow B indicates the output terminal 1 (102). ) And VSWR of the output terminal 2 (103). As can be seen from FIG. 9, in the frequency range of 1.45 to 1.55 GHz, the VSWR of the input terminal 101 and the VSWR of the output terminal 1 (102) and the output terminal 2 (103) are each 1.1 or less. It has become.
FIG. 10 is a graph showing the relationship between the frequency (GHz) and the distribution loss (dB) of the two distributor according to this embodiment, and the distribution loss (dB) between the output terminal 1 (102) and the output terminal 2 (103). It is a graph which shows. As can be seen from FIG. 10, the distribution loss between the output terminal 1 (102) and the output terminal 2 (103) is approximately -3 dB in the frequency range of 1.45 to 1.55 GHz.
FIG. 11 is a graph showing the relationship between the frequency (GHz) and the isolation (dB) of the two distributor according to this embodiment, and the isolation between the output terminal 1 (102) and the output terminal 2 (103). It is a graph which shows (dB). As can be seen from FIG. 11, the isolation between the output terminal 1 (102) and the output terminal 2 (103) is −20 dB or less in the frequency range of 1.45 to 1.55 GHz.
As can be seen from FIG. 9 to FIG. 11, it can be seen that the two distributors of the present embodiment have good electrical characteristics like the conventional Wilkinson type power distributor.

図３は、本実施例の２分配器を使用する４分配器の回路構成を示す回路図、図４は、図２に示す４分配器の実際の回路パターンを示す図である。
図３、図４において、１０は誘電体基板、１０１は入力端子、１０４は出力端子１、１０５は出力端子２、１０６は出力端子３、１０７は出力端子４、Ｔ１０１〜Ｔ１１０は高周波線路、Ｒ１０１〜Ｒ１０３は抵抗素子である。なお、高周波線路（Ｔ１０３〜Ｔ１１０）は、通常のマイクロストリップラインで構成されるλｏ／４線路である。したがって、図示は省略するが、図４でも、誘電体基板１０の裏面側には、面状の接地パターンが形成されている。
図３に示す４分配器は、初段の分配回路に、図１に示す本実施例の２分配器を使用し、本実施例の２分配器の出力端子１（１０３）と出力端子２（１０３）とに、従来のウィルキンソン型の電力分配器を接続したものである。
図４から分かるように、初段の分配回路として、本実施例の２分配回路を使用することにより、出力端子１（１０２）と、出力端子２（１０３）とを、入力端子１０１に対してＴ字形状に配置することができるので、出力端子１（１０２）と出力端子２（１０３）との間のデットスペースを排除し、小型化を図ることが可能となる。
図４と図８とを比較して分かるように、図４に示す４分配器の場合、従来の従来のウィルキンソン型の電力分配器を使用する４分配器より、誘電体基板１０の面積を３５％程度小さくすることが可能である。
このように、本実施例の２分配器では、アイソレーション特性を有するＴ字分岐回路を採用することにより、出力端子を入力端子に対してＴ字に配置することを可能とし、これにより、出力端子間のデットスペースを排除して小型化を図ることが可能となる。 FIG. 3 is a circuit diagram showing a circuit configuration of a four distributor using the two distributor of this embodiment, and FIG. 4 is a diagram showing an actual circuit pattern of the four distributor shown in FIG.
3 and 4, 10 is a dielectric substrate, 101 is an input terminal, 104 is an output terminal 1, 105 is an output terminal 2, 106 is an output terminal 3, 107 is an output terminal 4, T101 to T110 are high-frequency lines, R101 R103 is a resistance element. Note that the high-frequency lines (T103 to T110) are λo / 4 lines configured by ordinary microstrip lines. Accordingly, although not shown, a planar ground pattern is formed on the back side of the dielectric substrate 10 in FIG.
The 4-distributor shown in FIG. 3 uses the 2-distributor of this embodiment shown in FIG. 1 in the first-stage distribution circuit, and the output terminal 1 (103) and the output terminal 2 (103) of the 2-distributor of this embodiment. ) And a conventional Wilkinson type power distributor.
As can be seen from FIG. 4, the output terminal 1 (102) and the output terminal 2 (103) are connected to the input terminal 101 by using the two distribution circuit of this embodiment as the first stage distribution circuit. Since they can be arranged in a letter shape, the dead space between the output terminal 1 (102) and the output terminal 2 (103) can be eliminated, and the size can be reduced.
As can be seen by comparing FIG. 4 and FIG. 8, in the case of the 4-distributor shown in FIG. 4, the area of the dielectric substrate 10 is smaller than that of the 4-distributor using a conventional Wilkinson-type power distributor. It can be reduced by about%.
As described above, in the two dividers of the present embodiment, by adopting the T-shaped branch circuit having the isolation characteristic, the output terminal can be arranged in a T-shape with respect to the input terminal. It is possible to reduce the size by eliminating the dead space between the terminals.

図１２は、図３、図４に示す４分配器の周波数（ＧＨｚ）とＶＳＷＲとの関係を示すグラフであり、図１２において、矢印Ａは、入力端子１０１のＶＳＷＲ、矢印Ｂは、出力端子１（１０４）、出力端子２（１０５）、出力端子３（１０６）、および出力端子４（１０７）のＶＳＷＲである。図１２から分かるように、周波数が、１．４５〜１．５５ＧＨｚの範囲において、入力端子１０１のＶＳＷＲと、出力端子１（１０４）、出力端子２（１０５）、出力端子３（１０６）、および出力端子４（１０７）のＶＳＷＲは、それぞれ略１．１以下となっている。
図１３は、図３、図４に示す４分配器の周波数（ＧＨｚ）と分配損失（ｄＢ）との関係を示すグラフであり、出力端子１（１０４）、出力端子２（１０５）、出力端子３（１０６）、および出力端子４（１０７）の分配損失（ｄＢ）を示すグラフである。図１３から分かるように、周波数が、１．４５〜１．５５ＧＨｚの範囲において、出力端子１（１０４）、出力端子２（１０５）、出力端子３（１０６）、および出力端子４（１０７）の分配損失は、略−６ｄＢとなっている。
図１４は、図３、図４に示す４分配器の周波数（ＧＨｚ）とアイソレーション（ｄＢ）との関係を示すグラフであり、矢印Ａは、出力端子１（１０４）と出力端子２（１０５）との間、および出力端子３（１０６）と出力端子４（１０７）との間のアイソレーション（ｄＢ）を、矢印Ｂは、出力端子１（１０４）／出力端子２（１０５）と、出力端子３（１０６）／出力端子４（１０７）との間のアイソレーション（ｄＢ）を示すグラフである。図１４から分かるように、周波数が、１．４５〜１．５５ＧＨｚの範囲において、出力端子１（１０４）と出力端子２（１０５）との間、出力端子３（１０６）と出力端子４（１０７）との間、および、出力端子１（１０４）／出力端子２（１０５）と出力端子３（１０６）／出力端子４（１０７）との間のアイソレーション（ｄＢ）は、−３０ｄＢ以下となっている。
図１２〜図１３から分かるように、図３、図４に示す４分配器も良好な電気特性を有していることが分かる。
なお、図３の出力端子１（１０４）、出力端子２（１０５）、出力端子３（１０６）、および出力端子４（１０７）に、従来のウィルキンソン型の電力分配器をｎ段に接続することにより、２（ｎ＋２）分波器（ｎは１以上）を構成することも可能である。
以上、本発明者によってなされた発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。 FIG. 12 is a graph showing the relationship between the frequency (GHz) of the four dividers shown in FIGS. 3 and 4 and VSWR. In FIG. 12, arrow A indicates the VSWR of the input terminal 101, and arrow B indicates the output terminal. 1 (104), output terminal 2 (105), output terminal 3 (106), and output terminal 4 (107). As can be seen from FIG. 12, in the frequency range of 1.45 to 1.55 GHz, the VSWR of the input terminal 101, the output terminal 1 (104), the output terminal 2 (105), the output terminal 3 (106), and The VSWR of the output terminal 4 (107) is about 1.1 or less, respectively.
FIG. 13 is a graph showing the relationship between the frequency (GHz) and the distribution loss (dB) of the four distributors shown in FIGS. 3 and 4, and the output terminal 1 (104), the output terminal 2 (105), and the output terminal. 3 (106) and the distribution loss (dB) of the output terminal 4 (107). As can be seen from FIG. 13, in the frequency range of 1.45 to 1.55 GHz, the output terminal 1 (104), the output terminal 2 (105), the output terminal 3 (106), and the output terminal 4 (107). The distribution loss is about −6 dB.
FIG. 14 is a graph showing the relationship between the frequency (GHz) and isolation (dB) of the four distributors shown in FIGS. 3 and 4, and arrows A indicate the output terminal 1 (104) and the output terminal 2 (105). ) And between the output terminal 3 (106) and the output terminal 4 (107), the arrow B indicates the output terminal 1 (104) / output terminal 2 (105) and the output. It is a graph which shows the isolation (dB) between terminal 3 (106) / output terminal 4 (107). As can be seen from FIG. 14, in the frequency range of 1.45 to 1.55 GHz, between the output terminal 1 (104) and the output terminal 2 (105), the output terminal 3 (106) and the output terminal 4 (107 ), And between output terminal 1 (104) / output terminal 2 (105) and output terminal 3 (106) / output terminal 4 (107) (dB) is −30 dB or less. ing.
As can be seen from FIGS. 12 to 13, it can be seen that the four distributors shown in FIGS. 3 and 4 also have good electrical characteristics.
Note that a conventional Wilkinson-type power distributor is connected to n stages to output terminal 1 (104), output terminal 2 (105), output terminal 3 (106), and output terminal 4 (107) in FIG. Thus, a 2 (n + 2) duplexer (n is 1 or more) can be configured.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

本発明の実施例の２分配器の回路構成を示す回路図である。It is a circuit diagram which shows the circuit structure of 2 divider | distributor of the Example of this invention. 本発明の実施例の２分配器の実際の回路パターンを示す図である。It is a figure which shows the actual circuit pattern of 2 divider | distributor of the Example of this invention. 本発明の実施例の２分配器を使用する４分配器の回路構成を示す回路図である。It is a circuit diagram which shows the circuit structure of 4 divider | distributors which use 2 divider | distributor of the Example of this invention. 図２に示す４分配器の実際の回路パターンを示す図である。It is a figure which shows the actual circuit pattern of 4 divider | distributor shown in FIG. 従来のウィルキンソン型の電力分配器の回路構成を示す回路図である。It is a circuit diagram which shows the circuit structure of the conventional Wilkinson type power divider | distributor. 従来のウィルキンソン型の電力分配器の実際の回路パターンを示す図である。It is a figure which shows the actual circuit pattern of the conventional Wilkinson type power divider. 図５に示す従来のウィルキンソン型の電力分配器を３個する４分配器の回路構成を示す回路図である。FIG. 6 is a circuit diagram showing a circuit configuration of a four distributor including three conventional Wilkinson type power distributors shown in FIG. 5. 図７に示す４分配器の実際の回路パターンを示す図である。It is a figure which shows the actual circuit pattern of 4 divider | distributor shown in FIG. 本発明の実施例の２分配器の周波数（ＧＨｚ）とＶＳＷＲとの関係を示すグラフである。It is a graph which shows the relationship between the frequency (GHz) of 2 divider | distributor of the Example of this invention, and VSWR. 本発明の実施例の２分配器の周波数（ＧＨｚ）と分配損失（ｄＢ）との関係を示すグラフである。It is a graph which shows the relationship between the frequency (GHz) and distribution loss (dB) of the 2 divider | distributor of the Example of this invention. 本発明の実施例の２分配器の周波数（ＧＨｚ）とアイソレーション（ｄＢ）との関係を示すグラフである。It is a graph which shows the relationship between the frequency (GHz) of the 2 divider | distributor of the Example of this invention, and isolation (dB). 図３、図４に示す４分配器の周波数（ＧＨｚ）とＶＳＷＲとの関係を示すグラフである。It is a graph which shows the relationship between the frequency (GHz) of 4 divider | distributors shown to FIG. 3, FIG. 4, and VSWR. 図３、図４に示す４分配器の周波数（ＧＨｚ）と分配損失（ｄＢ）との関係を示すグラフである。It is a graph which shows the relationship between the frequency (GHz) of 4 divider | distributors shown in FIG. 3, FIG. 4, and a distribution loss (dB). 図３、図４に示す４分配器の周波数（ＧＨｚ）とアイソレーション（ｄＢ）との関係を示すグラフである。It is a graph which shows the relationship between the frequency (GHz) and isolation (dB) of 4 divider | distributors shown in FIG. 3, FIG.

符号の説明Explanation of symbols

１０ 誘電体基板
１０１，２０１ 入力端子
１０２〜１０７，２０２〜２０７ 出力端子
Ｔ１０１〜Ｔ１１０，Ｔ２０１〜Ｔ２０６ 高周波線路
Ｒ１０１〜Ｒ１０３，Ｒ２０１〜Ｒ２０３ 抵抗素子 DESCRIPTION OF SYMBOLS 10 Dielectric substrate 101,201 Input terminal 102-107,202-207 Output terminal T101-T110, T201-T206 High frequency line R101-R103, R201-R203 Resistive element

Claims (1)

入力端子と第１出力端子との間に配置される第１高周波線路と、
前記入力端子と第２出力端子との間に配置される第２高周波線路と、
前記第１出力端子と前記第２出力端子との間に配置される第３ないし第６高周波線路と、
前記第３高周波線路と第４高周波線路との接続点と、前記第５高周波線路と第６高周波線路との接続点との間に配置される抵抗素子とを備えることを特徴とする２分配器。 A first high-frequency line disposed between the input terminal and the first output terminal;
A second high-frequency line disposed between the input terminal and the second output terminal;
Third to sixth high-frequency lines disposed between the first output terminal and the second output terminal;
A two-distributor comprising: a resistance element disposed between a connection point between the third high-frequency line and the fourth high-frequency line; and a connection point between the fifth high-frequency line and the sixth high-frequency line. .
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JP2012004864A (en) * 2010-06-17 2012-01-05 Mitsubishi Electric Corp Power combiner/distributer
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