JP2009170520A - Layout method, program and system of integrated circuit device, integrated circuit device, and electronics - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout method of an integrated circuit device which can achieve reinforcement of power supply without increasing the chip area. <P>SOLUTION: The layout method of the integrated circuit device comprises a step (S14) for searching an area where a functional cell is not arranged yet, and a step (S16) for arranging a power supply reinforcement cell including first and second power supply reinforcement lines at least a part of which is formed, respectively, of first and second polysilicon wiring patterns in an area where a functional cell is not arranged yet. At step S16, the first and second polysilicon wiring patterns are made to intersect with first and second power supply lines, respectively, and at least one of the first and second power supply reinforcement cells is arranged along a second direction so that at least one of two wiring patterns connecting two first power supply lines and two second power supply lines, respectively, is formed along the second direction through the first and second power supply reinforcement lines. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated circuit device layout method, an integrated circuit device layout program, an integrated circuit device layout system, an integrated circuit device, and an electronic apparatus.

In recent years, with the miniaturization of LSI processes, the degree of integration has dramatically improved, and there is an increasing need to reinforce the power supplied to each cell in order to stably operate each cell constituting the LSI. For example, the power supply is reinforced by wiring the power supply in a mesh shape in the cell arrangement region. In general, since power supply metal wiring is laid along each cell in a predetermined direction (for example, the horizontal direction), the power supply wiring in the horizontal direction is formed only by arranging each cell in the horizontal direction. That is, it is not necessary to secure a dedicated area for the horizontal power supply wiring. On the other hand, in order to reduce the layout area, no vertical power supply wiring is laid in each cell. Accordingly, the power supply wiring in the vertical direction cannot be formed only by arranging the cells in the vertical direction. Therefore, for example, it is necessary to evaluate the power consumption, determine the required number of power supply lines in the vertical direction, and install the power supply lines in the vertical direction at regular intervals.
JP-A-8-272836

  However, since the vertical power supply wiring cannot be laid in the area where the cells are arranged, it is necessary to secure a dedicated area for laying the vertical power supply wiring. Therefore, sufficient power supply reinforcement cannot be realized unless the chip area is increased at the cost of cost.

  The present invention has been made in view of the above problems, and an object thereof is to provide an integrated circuit device layout method and the like that can realize power supply reinforcement without increasing the chip area. .

(1) The present invention
A plurality of functional cells are arranged in an array in a predetermined region in a first direction and a second direction orthogonal to the first direction, and a first power source and a second power source are respectively supplied to the plurality of functional cells. A method for laying out an integrated circuit device in which a first power supply line and a second power supply line to be supplied are laid on a predetermined metal wiring layer along the first direction,
In a layout after arranging the plurality of functional cells in the predetermined area, a non-arranged area search step for searching an unarranged area in which the functional cells are not arranged in the predetermined area;
In the non-arranged region, a first power reinforcing line formed by a first polysilicon wiring pattern at least partly laid on the polysilicon wiring layer and a first power supply line at least partly laid on the polysilicon wiring layer. A power reinforcement cell arranging step of arranging a power reinforcement cell including a second power reinforcement line formed by two polysilicon wiring patterns,
In the power reinforcing cell placement step,
The first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the second power supply line and the first power supply line, respectively, along the second direction, At least one of a wiring pattern that connects the two first power supply lines via one power reinforcing line and a wiring pattern that connects the two second power supply lines via the second power reinforcing line The at least two power reinforcing cells are arranged side by side along the second direction so as to be formed.

  The first power supply line and the second power supply line may be a VDD power supply line and a VSS power supply line, respectively.

  The predetermined metal wiring layer may be, for example, the lowermost metal 1 wiring layer.

  The layout after arranging a plurality of functional cells in a predetermined area may be a layout before arranging a plurality of functional cells in a predetermined area and before wiring a net connecting the plurality of functional cells, The layout after the arrangement of the plurality of functional cells and the wiring of the net connecting the plurality of functional cells may be used.

  According to the present invention, in the layout after the functional cells are arranged in the predetermined region, the second cell is arranged in the second direction by arranging at least two power reinforcing cells in the non-functional region. A wiring pattern for connecting two first power supply lines via a first power supply reinforcing line and a wiring pattern for connecting two second power supply lines via a second power supply reinforcing line along the direction Is formed. That is, it is possible to reinforce at least one of the first power source and the second power source only by arranging at least two power source reinforcing cells side by side along the second direction. Therefore, according to the present invention, it is possible to provide an integrated circuit device that realizes power supply reinforcement without increasing the chip area.

  According to the present invention, the first power supply line and the second power supply line are laid on a predetermined metal wiring layer, whereas the first power supply line and the second power supply line included in the power supply cell are provided. At least a part of the two power supply reinforcing lines is formed by a first polysilicon wiring pattern and a second polysilicon wiring pattern laid in a polysilicon wiring layer below the metal wiring layer, respectively. The power reinforcing cells are arranged so that the first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the second power supply line and the first power supply line, respectively. Therefore, according to the present invention, in order to reinforce the first power supply without short-circuiting the first power supply line and the second power supply reinforcement line, and the second power supply line and the first power supply reinforcement line, respectively. At least one of the wiring pattern and the wiring pattern for reinforcing the second power source can be formed.

(2) In the integrated circuit device layout method of the present invention,
The power reinforcing cell is
A part of the first power supply reinforcing line and a part of the second power supply reinforcing line are laid on the predetermined metal wiring layer, and the first polysilicon wiring pattern and the second power supply line are connected via a contact. Formed by a first metal wiring pattern and a second metal wiring pattern respectively connected to the polysilicon wiring pattern;
In the power reinforcing cell placement step,
The first power supply line is connected to the first power supply line by the first metal wiring pattern, and the second power supply line is connected to the second power supply line by the second metal wiring pattern. You may make it arrange | position the said power supply reinforcement cell so that it may be connected to.

  A power reinforcing cell is connected to a predetermined metal wiring layer in which the first metal wiring pattern and the second metal wiring pattern are laid (metal wiring layer in which the first power supply line and the second power supply line are laid). A first power supply wiring pattern and a second power supply wiring pattern that are laid on the same metal wiring layer and overlap with a part of the first metal wiring pattern and a part of the second metal wiring pattern, respectively, are configured. By arranging the power reinforcement cells so that the first power supply wiring pattern and the second power supply wiring pattern overlap the first power supply line and the second power supply line, respectively, The second power supply reinforcement line may be connected to the first power supply line and the second power supply line, respectively.

  Further, the power reinforcing cell does not include the first power wiring pattern and the second power wiring pattern, but a part of the first metal wiring pattern and a part of the second metal wiring pattern are the first. By arranging the power supply reinforcing cells so as to overlap the power supply line and the second power supply line, respectively, the first power supply line and the second power supply line are respectively connected to the first power supply line and the second power supply line. You may make it connect with a power supply line.

  According to the present invention, it is possible to connect the first power supply reinforcement line to the first power supply line and connect the second power supply reinforcement line to the second power supply line simply by disposing the power supply reinforcement cell. Therefore, an integrated circuit device that realizes power supply reinforcement without increasing the chip area can be provided.

(3) In the integrated circuit device layout method of the present invention,
The power reinforcing cell is
The first metal wiring pattern and the second metal wiring pattern are laid so as to be in contact with a first side of the cell and a second side facing the first side,
The power reinforcing cell may be arranged so that the first side and the second side are orthogonal to the second direction.

  According to the present invention, the power reinforcing cell is laid so that the first metal wiring pattern and the second metal wiring pattern are in contact with the first side of the cell and the second side facing the first side, and The power supply reinforcing cell is arranged so that the first side and the second side are orthogonal to the second direction. Therefore, when two power supply reinforcing cells are arranged so as to be adjacent to each other in the second direction, the first metal wiring patterns and the second metal wiring patterns of each power supply reinforcing cell are connected to each other. . That is, according to the present invention, it is possible to reinforce at least one of the first power source and the second power source only by arranging at least two power source reinforcing cells so as to be adjacent in the second direction. Therefore, according to the present invention, it is possible to efficiently reinforce the power supply without securing a wiring area for power supply reinforcement in advance.

(4) In the integrated circuit device layout method of the present invention,
The predetermined metal wiring layer is
The metal wiring layer may be a lower metal wiring layer than a metal wiring layer for wiring a net connecting the plurality of functional cells.

  For example, when a metal wiring layer for wiring a net connecting a plurality of functional cells is a metal 2 wiring layer to a metal 4 wiring layer, the predetermined metal wiring layer may be a metal 1 wiring layer.

  According to the present invention, each wiring pattern for reinforcing the first power supply and the second power supply is provided in a metal wiring layer and a polysilicon wiring layer lower than a metal wiring layer for wiring a net connecting functional cells. It is formed. Therefore, the arrangement of the power reinforcing cell does not affect the net wiring connecting the functional cells. That is, according to the present invention, it is possible to perform net wiring without unnecessarily increasing the wiring area, and thus it is possible to realize power supply reinforcement without increasing the chip area.

(5) An integrated circuit device layout method of the present invention includes:
In the power reinforcing cell placement step,
A wiring pattern connecting the two first power supply lines via the first power supply reinforcement line and the second power supply lines via the second power supply reinforcement line along the second direction. You may make it arrange | position at least 3 said power supply reinforcement cells along with the said 2nd direction so that both the wiring patterns which connect a power supply line may be formed.

(6) In the integrated circuit device layout method of the present invention,
The functional cell and the power supply reinforcing cell are:
It may be realized based on a basic cell as a unit of the gate array and a predetermined wiring pattern.

(7) The present invention
A plurality of functional cells are arranged in an array in a predetermined region in a first direction and a second direction orthogonal to the first direction, and a first power source and a second power source are respectively supplied to the plurality of functional cells. A layout program for laying out an integrated circuit device in which a first power supply line and a second power supply line to be supplied are laid on a predetermined metal wiring layer along the first direction,
In a layout after the plurality of functional cells are arranged in the predetermined area, an unarranged area search means for searching for an unarranged area in which the functional cells are not arranged in the predetermined area;
In the non-arranged region, a first power reinforcing line formed by a first polysilicon wiring pattern at least partly laid on the polysilicon wiring layer and a first power supply line at least partly laid on the polysilicon wiring layer. And a second power source reinforcement line formed by the polysilicon wiring pattern, and a power source reinforcement cell arrangement means for arranging a power source reinforcement cell including the second power source reinforcement line,
The power reinforcing cell arranging means is
The first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the second power supply line and the first power supply line, respectively, along the second direction, At least one of a wiring pattern that connects the two first power supply lines via one power reinforcing line and a wiring pattern that connects the two second power supply lines via the second power reinforcing line The at least two power reinforcing cells are arranged side by side along the second direction so as to be formed.

(8) The present invention
A plurality of functional cells are arranged in an array in a predetermined region in a first direction and a second direction orthogonal to the first direction, and a first power source and a second power source are respectively supplied to the plurality of functional cells. A layout system for laying out an integrated circuit device in which a first power supply line and a second power supply line to be supplied are laid on a predetermined metal wiring layer along the first direction,
In a layout after the plurality of functional cells are arranged in the predetermined area, an unarranged area search means for searching for an unarranged area in which the functional cells are not arranged in the predetermined area;
In the non-arranged region, a first power reinforcing line formed by a first polysilicon wiring pattern at least partly laid on the polysilicon wiring layer and a first power supply line at least partly laid on the polysilicon wiring layer. Power reinforcing cell arrangement means for arranging a power reinforcing cell including a second power reinforcing line formed by two polysilicon wiring patterns,
The power reinforcing cell arranging means is
The first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the second power supply line and the first power supply line, respectively, along the second direction, At least one of a wiring pattern that connects the two first power supply lines via one power reinforcing line and a wiring pattern that connects the two second power supply lines via the second power reinforcing line The at least two power reinforcing cells are arranged side by side along the second direction so as to be formed.

(9) The present invention
A plurality of functional cells are arranged in an array in a predetermined region in a first direction and a second direction orthogonal to the first direction, and a first power source and a second power source are respectively supplied to the plurality of functional cells. An integrated circuit device in which a first power supply line and a second power supply line to be supplied are laid on a predetermined metal wiring layer along the first direction,
A first power supply reinforcement line formed by a first polysilicon wiring pattern disposed in a region where the functional cell is not disposed in the predetermined region and at least a part of which is laid on a polysilicon wiring layer; and A power supply reinforcing cell including a second power supply reinforcing line formed by a second polysilicon wiring pattern partially laid on the polysilicon wiring layer,
By arranging at least two of the power reinforcing cells side by side along the second direction, the first polysilicon wiring pattern and the second polysilicon wiring pattern are connected to the second power supply line and A wiring pattern that crosses each of the first power supply lines and connects the two first power supply lines through the first power supply reinforcing line along the second direction; At least one of the wiring patterns that connect the two second power supply lines via the power reinforcing line is formed.

  According to the present invention, the at least two power reinforcing cells are arranged along the second direction in the area where the functional cells are not arranged in the predetermined area. At least one of a wiring pattern for connecting two first power supply lines via one power supply reinforcing line and a wiring pattern for connecting two second power supply lines via a second power reinforcing line is formed. ing. That is, in the integrated circuit device according to the present invention, the first power source and the second power source cell are arranged by arranging at least two power source reinforcing cells side by side along the second direction using the non-arranged region of the functional cells. At least one of the power supplies is reinforced. Therefore, according to the present invention, it is possible to provide an integrated circuit device capable of realizing power supply reinforcement without increasing the chip area.

(10) In the integrated circuit device of the present invention,
The power reinforcing cell is
A part of the first power supply reinforcing line and a part of the second power supply reinforcing line are laid on the predetermined metal wiring layer, and the first polysilicon wiring pattern and the second power supply line are connected via a contact. A first metal wiring pattern and a second metal wiring pattern respectively connected to the polysilicon wiring pattern are formed, and the first power supply reinforcing line is formed into the first power supply line by the first metal wiring pattern. The second power supply reinforcement line may be connected to the second power supply line by the second metal wiring pattern.

(11) In the integrated circuit device of the present invention,
The power reinforcing cell is
The first metal wiring pattern and the second metal wiring pattern are laid so as to contact a first side of the cell and a second side opposite to the first side, and the first side and the second side The two sides may be arranged so as to be orthogonal to the second direction.

(12) In the integrated circuit device of the present invention,
The predetermined metal wiring layer is
The metal wiring layer may be a lower metal wiring layer than a metal wiring layer for wiring a net connecting the plurality of functional cells.

(13) An integrated circuit device according to the present invention includes:
By arranging at least three of the power supply reinforcing cells side by side along the second direction, the two first power supplies are provided along the second direction via the first power supply reinforcing line. Both a wiring pattern connecting the supply lines and a wiring pattern connecting the two second power supply lines via the second power supply reinforcing line may be formed.

(14) In the integrated circuit device of the present invention,
The functional cell and the power supply reinforcing cell are:
It may be realized based on a basic cell as a unit of the gate array and a predetermined wiring pattern.

(15) The present invention provides:
An integrated circuit device as described above;
Data input means to be processed by the integrated circuit device;
An electronic device comprising: output means for outputting data processed by the integrated circuit device.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Moreover, not all of the configurations described below are essential constituent requirements of the present invention.

1. Integrated Circuit Device FIGS. 1A and 1B are diagrams for explaining an integrated circuit device according to this embodiment. The integrated circuit device of FIG. 1A is realized by including a channel type cell array having a wiring region 30 between cells between each row constituted by a plurality of cells, and the integrated circuit of FIG. The device is realized including a channelless cell array having no inter-cell wiring region between rows.

  The integrated circuit device 1 includes a plurality of functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...) In the X direction in the functional cell arrangement area 2 (predetermined area). (First direction) and Y direction (second direction orthogonal to the first direction) are arranged in an array, and a plurality of functional cells (FC101, FC102, ..., FC201, FC202, ..., VDD power supply lines (first power supply lines) 10-1, 10-2 for supplying VDD power (first power) and VSS power (second power) to FC301, FC302,. 10-3, ... and VSS power supply lines (second power supply lines) 20-1, 20-2, 20-3, ... are laid on the predetermined metal wiring layer along the X direction. Yes.

  Here, the predetermined metal wiring layer is a metal wiring layer (for example, for wiring a net connecting functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...). It may be a lower metal wiring layer (for example, the lowermost metal 1 wiring layer) than the metal 2 wiring layer to the metal 4 wiring layer.

  Further, the same as the metal wiring layer in which the VDD power supply lines 10-1, 10-2, 10-3,... And the VSS power supply lines 20-1, 20-2, 20-3,. In the wiring layer, when the internal net wiring of the functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...) Is performed, FIG. ) Of the net for connecting functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...) Wiring can be performed over the functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...). Since the integrated circuit device 1 of FIG. 1B does not have the wiring region 30, the layout area can be made smaller than that of the integrated circuit device 1 of FIG.

  The integrated circuit device 1 includes power supply reinforcement cells (PC101, PC102,..., PC201, PC202,..., PC301, PC302,...).

  The power supply reinforcement cells (PC101, PC102,..., PC201, PC202,..., PC301, PC302,...) Are at least partially formed by the first polysilicon wiring pattern laid on the polysilicon wiring layer. VSS power supply reinforcement line (first power supply reinforcement line) (not shown) formed and a VSS power supply reinforcement line (not shown) formed by a second polysilicon wiring pattern laid at least partially on the polysilicon wiring layer ( Second power supply reinforcing line) (not shown).

  The power reinforcement cells (PC101, PC102,..., PC201, PC202,..., PC301, PC302,...) Are function cells (FC101, FC102,..., FC201,. FC202,..., FC301, FC302,.

  The integrated circuit device 1 includes at least two power supply reinforcement cells (for example, PC101 and PC201, or PC202 and PC301, etc.) arranged side by side along the Y direction, so that the first polysilicon wiring pattern and the second The polysilicon wiring pattern is crossed with the VSS power supply line and the VDD power supply line, respectively, and two VDD power supply lines (for example, 10-1 and 10-2) are provided via the VDD power reinforcing line along the Y direction. Etc.) and a wiring pattern (not shown) for connecting two VSS power supply lines (for example, 20-2 and 20-3) via a VSS power supply reinforcing line. One is formed.

  Here, for example, in the integrated circuit device 1 of FIG. 1A, at least a part of the metal wiring connecting the VDD power supply reinforcing lines of the two power supply reinforcing cells PC101 and PC201 is laid in the wiring region 30. A wiring pattern for connecting the two VDD power supply lines 10-1 and 10-2 may be formed. Similarly, at least a part of the metal wiring connecting the VSS power supply reinforcing lines of the two power supply reinforcing cells PC202 and PC301 is laid in the wiring region 30, whereby the two VSS power supply lines 20-2 and 20-3 are provided. A wiring pattern for connecting the two may be formed. Further, for example, in the integrated circuit device 1 of FIG. 1B, a wiring pattern for connecting the two VDD power supply lines 10-1 and 10-2 is formed only by arranging the power reinforcing cells PC101 and PC201. May be. Similarly, a wiring pattern for connecting two VSS power supply lines 20-2 and 20-3 may be formed only by disposing the power supply reinforcing cells PC202 and PC301.

  Further, the integrated circuit device 1 includes at least three power supply reinforcement cells (for example, PC103, PC203, and PC303) arranged side by side along the Y direction, whereby the VDD power supply reinforcement line is provided along the Y direction. Two VSS power supply lines (for example, 20-2 and 20) are connected via a wiring pattern (not shown) for connecting two VDD power supply lines (for example, 10-1 and 10-2) and a VSS power supply reinforcing line. -3 etc.) both of the wiring patterns (not shown) may be formed.

  Here, for example, in the integrated circuit device 1 of FIG. 1A, at least a part of two metal wirings connecting the VDD power supply reinforcement lines and the VSS power supply reinforcement lines of the two power supply reinforcement cells PC103 and PC203, respectively. And at least a part of the two metal wirings connecting the VDD power supply reinforcement lines and the VSS power supply reinforcement lines of the two power supply reinforcement cells PC203 and PC303, respectively, are laid in the wiring region 30, thereby providing two VDD power supply lines. Both a wiring pattern for connecting 10-1 and 10-2 and a wiring pattern for connecting two VSS power supply lines 20-2 and 20-3 may be formed. Further, for example, in the integrated circuit device 1 of FIG. 1B, a wiring pattern for connecting the two VDD power supply lines 10-1 and 10-2 and 2 only by arranging the power reinforcing cells PC103, PC203, and PC303. Both wiring patterns connecting the two VSS power supply lines 20-2 and 20-3 may be formed.

  In the power supply reinforcement cells (PC101, PC102,..., PC201, PC202,..., PC301, PC302,...), A part of the VDD power supply reinforcement line and a part of the VSS power supply reinforcement line are connected via contacts. The first polysilicon wiring pattern (not shown) and the second metal wiring pattern (not shown) connected to the first polysilicon wiring pattern and the second polysilicon wiring pattern, respectively, may be used. The first metal wiring pattern and the second metal wiring pattern include VDD power supply lines 10-1, 10-2, 10-3,... And VSS power supply lines 20-1, 20-2, 20-3. Are laid on the same metal wiring layer (for example, metal 1 wiring layer) as the metal wiring layer on which are laid. The power supply reinforcement cells (PC101, PC102,..., PC201, PC202,..., PC301, PC302,...) Have a VDD power supply reinforcement line 10-1, a VDD power supply line 10-1, a first metal wiring pattern, 10-2, 10-3,..., And the VSS power supply reinforcing line is connected to one of the VSS power supply lines 20-1, 20-2, 20-3,. You may arrange | position so that it may be connected to either.

  Further, the power supply reinforcement cells (PC101, PC102,..., PC201, PC202,..., PC301, PC302,...) Have the first metal wiring pattern and the second metal wiring pattern as the first cell. The first side and the second side may be arranged so as to be in contact with the second side opposite to the first side and the first side, and the first side and the second side may be orthogonal to the Y direction.

  In addition, functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...) And power supply reinforcement cells (PC101, PC102,..., PC201, PC202,. (PC301, PC302,...) May be realized based on a basic cell as a unit of a gate array and a predetermined wiring pattern.

  According to the integrated circuit device of the present embodiment, at least two power supply reinforcing cells are arranged along the Y direction in the area where the functional cells are not arranged in the functional cell arrangement possible area. Thus, at least one of a wiring pattern connecting the two VDD power supply lines via the VDD power supply reinforcing line and a wiring pattern connecting the two VSS power supply lines via the VSS power supply reinforcing line is formed. That is, in the integrated circuit device according to the present embodiment, at least one of the VDD power supply and the VSS power supply is provided by arranging at least two power supply reinforcing cells side by side along the Y direction using the non-arranged area of the functional cells. It is reinforced. Therefore, according to the integrated circuit device of this embodiment, power supply reinforcement can be realized without increasing the chip area.

  Further, according to the integrated circuit device of the present embodiment, the VDD power supply line and the VSS power supply line are laid on a predetermined metal wiring layer (for example, a metal 1 wiring layer), but are included in the power supply reinforcement cell. At least a part of the VDD power supply reinforcement line and the VSS power supply reinforcement line are formed by a first polysilicon wiring pattern and a second polysilicon wiring pattern laid in a polysilicon wiring layer lower than the metal wiring layer, respectively. The The power reinforcing cells are arranged so that the first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the VSS power supply line and the VDD power supply line, respectively. Therefore, according to the integrated circuit device of this embodiment, the VDD power supply line and the VSS power supply reinforcing line, and the VSS power supply line and the VDD power supply reinforcing line are not short-circuited, and the wiring pattern and VSS for reinforcing the VDD power supply are provided. At least one of the wiring patterns for reinforcing the power supply can be formed.

  Further, according to the integrated circuit device of the present embodiment, the power reinforcing cell has the first metal wiring pattern and the second metal wiring pattern on the first side and the second side opposite to the first side of the cell. The power reinforcing cell is arranged so as to be in contact with each other and the first side and the second side are orthogonal to the Y direction. When the two power reinforcing cells are arranged so as to be adjacent to each other in the Y direction, the first metal wiring patterns and the second metal wiring patterns of each power reinforcing cell are connected to each other. . That is, according to the integrated circuit device of the present embodiment, when at least two power supply reinforcing cells are arranged adjacent to each other in the Y direction, at least one of the VDD power supply and the VSS power supply is reinforced. Therefore, it is possible to efficiently reinforce the power supply without securing a wiring area for power supply reinforcement in advance.

  Further, according to the integrated circuit device of the present embodiment, each wiring pattern for reinforcing the VDD power supply and the VSS power supply has a metal wiring layer (for example, a metal 2 wiring layer to a metal 4 wiring) for wiring a net connecting functional cells. The metal 1 wiring layer and the polysilicon wiring layer which are lower than the layer) are formed. Therefore, the arrangement of the power reinforcing cell does not affect the net wiring connecting the functional cells. That is, according to the integrated circuit device of the present embodiment, the net wiring can be performed without unnecessarily increasing the wiring area, so that power supply reinforcement can be realized without increasing the chip area.

2. Integrated Circuit Device Layout Method FIG. 2 is an example of a flowchart for explaining the integrated circuit device layout method of the present embodiment. Hereinafter, a layout method of an integrated circuit device using a gate array method will be described as an example. Note that the integrated circuit device 1 of FIG. 1A or FIG. 1B described above can be realized by the integrated circuit device layout method of the present embodiment.

  In the integrated circuit device layout method of the present embodiment, first, in the functional cell arrangement possible region 2, the basic cells are arrayed in the X direction (first direction) and the Y direction (second direction) orthogonal to the X direction. (Step S10 in FIG. 2). FIGS. 3A and 3B show an example of the layout of (a part of) the integrated circuit device 1 after the process of step S10 is completed. Here, FIG. 3A is a diagram in the case where the integrated circuit device 1 is realized by a channel-type gate array, and FIG. 3B is a diagram in the case where the integrated circuit device 1 is realized by a channel-less gate array. FIG.

  In the integrated circuit device 1, basic cells (BC101, BC102,..., BC201, BC202,..., BC301, BC302,...) Are arranged in an array in the X direction and the Y direction. In FIG. 3A, the basic cells in the first row (BC101, BC102,...) And the basic cells in the second row (BC201, BC202,...) And the basic cells in the second row (BC201, BC202). ,... And a basic cell (BC301, BC302,...) In the third row, and the like. On the other hand, in FIG. 3B, the basic cells in the first row (BC101, BC102,...) And the basic cells in the second row (BC201, BC202,...) And in the second row. A wiring area is not provided between (BC201, BC202,...) And the basic cells (BC301, BC302,...) In the third row, and the layout area can be further reduced.

  3A and 3B, basic cells (BC101, BC102,..., BC201, BC202,..., BC301, BC302,...) Are all cells having the same configuration. However, the basic cells (BC201, BC202,...) In the second row are arranged so that the direction is reversed along the Y direction with respect to the basic cells (BC101, BC102,...) In the first row. The basic cells (BC301, BC302,...) In the third row are arranged so that the direction is reversed along the Y direction with respect to the basic cells (BC201, BC202,...) In the second row. Yes. That is, all the basic cells are arranged while reversing the direction for each row along the Y direction.

  The functional cell arrangement possible region 2 is set with a plurality of wiring grids 3 assigned numbers (0, 1, 2,..., 47,...) Consecutive at predetermined intervals along the X direction. May be. Basic cells (BC101, BC102,..., BC201, BC202,..., BC301, BC302,...) Have a length (width) in the X direction that is an integral multiple of the interval of the wiring grid (for example, three times). ) May be created.

  FIG. 4 shows an example of a basic cell configuration. The basic cell 40 includes two P-type transistors composed of two polysilicon wirings 41 and 42 and a P-type diffusion region 43, and two parts composed of two polysilicon wirings 41 and 42 and an N-type diffusion region 44. Includes N-type transistors. In the basic cell 40, by connecting part of the polysilicon wirings 41 and 42, the P-type diffusion region 43, and the N-type diffusion region 44 with a metal one-layer wiring, a functional cell having various logics can be realized. it can.

  Further, the basic cell 40 may include an N-type diffusion region 45 and a P-type diffusion region 46 for arranging a well contact or a substrate contact.

  The basic cell 40 has a width three times the wiring grid interval, and 47-1, 47-2, 47-3, 47-4 indicate sides (boundaries) of the basic cell 40. For example, the basic cell BC202 in FIG. 3A is arranged such that the side 47-1 and the side 47-3 are in contact with the side 47-3 of the basic cell BC201 and the side 47-1 of the basic cell BC203, respectively. Yes. 3B, the sides 47-1 and 47-3 are in contact with the side 47-3 of the basic cell BC201 and the side 47-1 of the basic cell BC203, respectively, and the sides 47-4 and 47- 2 is arranged so as to be in contact with the side 47-4 of the basic cell BC102 and the side 47-2 of the basic cell BC302.

  In the integrated circuit device layout method of the present embodiment, next, functional cells are arranged (step S12 in FIG. 2). FIG. 5A and FIG. 5B show an example of the layout of (a part of) the integrated circuit device 1 after the process of step S12 is completed. 5A and 5B, in the layout of the integrated circuit device 1 shown in FIGS. 3A and 3B, basic cells (BC101, BC102,..., BC201, BC202 are respectively shown. , ..., BC301, BC302, ...) are replaced with functional cells (FC101, FC102, ..., FC201, FC202, ..., FC301, FC302, ...). Yes. Here, the functional cells (FC201, FC202,...) In the second row are arranged so that the direction is reversed along the Y direction with respect to the functional cells (FC101, FC102,...) In the first row. The functional cells (FC301, FC302,...) In the third row are arranged so that the direction is reversed along the Y direction with respect to the functional cells (FC201, FC202,...) In the second row. ing. That is, the functional cells are arranged while reversing the direction for each row along the Y direction.

  Further, in FIGS. 5A and 5B, VDD power and VSS power are respectively supplied to the functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...). VDD power supply lines 10-1, 10-2, 10-3,... And VSS power supply lines 20-1, 20-2, 20-3,. It is laid on one wiring layer.

  Functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...) Require different numbers of basic cells depending on the logic to be realized. For example, the functional cell FC101 is realized by the basic cells BC101 and BC102, and the functional cell FC102 is realized only by the basic cell BC104. Functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...) Are inverter cells that implement inverted logic, NAND cells that implement NAND logic, and OR logic. OR cell or the like.

  FIG. 6 shows an example of the configuration of an inverter cell as an example of a functional cell. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  In the inverter cell 50, metal first-layer wirings 51, 52, 53, 54 and contacts 55, 56, 57, 58, 59 are added to the basic cell 40 described in FIG.

  The contact 55 connects the metal first layer wiring 51 and the polysilicon wiring 42. Therefore, the input signal supplied to the metal first layer wiring 51 is connected to the gate of the P-type transistor constituted by the polysilicon wiring 42 and the P-type diffusion region 43 and the polysilicon wiring 42 and the N-type diffusion region via the contact 55. 44 is applied to the gate of the N-type transistor constituted by 44.

  Contacts 56 and 57 connect the metal first layer wiring 52 to the P-type diffusion region 43 and the N-type diffusion region 44, respectively. That is, the drain of the P-type transistor constituted by the polysilicon wiring 42 and the P-type diffusion region 43 and the drain of the N-type transistor constituted by the polysilicon wiring 42 and the N-type diffusion region 44 are connected.

  A contact 58 connects the metal first layer wiring 53 and the P-type diffusion region 43. The metal first layer wiring 53 is laid at a position overlapping with any one of the VDD power supply lines 10-1, 10-2, 10-3,... Shown in FIG. ing. Accordingly, VDD power is supplied to the source of the P-type transistor constituted by the polysilicon wiring 42 and the P-type diffusion region 43 through the contact 58.

  A contact 59 connects the metal first-layer wiring 54 and the N-type diffusion region 44. The metal first layer wiring 54 is laid at a position overlapping with any one of the VSS power supply lines 20-1, 20-2, 20-3,... Shown in FIG. ing. Accordingly, VSS power is supplied to the source of the N-type transistor constituted by the polysilicon wiring 42 and the N-type diffusion region 44 through the contact 59.

  The inverter cell 50 outputs the inverted logic signal of the input signal supplied to the metal first layer wiring 51 from the metal first layer wiring 52 with the above configuration.

  FIG. 7 shows an example of the configuration of a 2-input NAND cell as another example of the functional cell. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  In the 2-input NAND cell 60, metal first-layer wirings 61, 62, 63, 64, 65 and contacts 66, 67, 68, 69, 70, 71, 72 are added to the basic cell 40 described in FIG. ing.

  The contact 66 connects the metal first layer wiring 61 and the polysilicon wiring 41. Therefore, the input signal supplied to the metal first layer wiring 61 is connected to the gate of the P-type transistor constituted by the polysilicon wiring 41 and the P-type diffusion region 43 and the polysilicon wiring 41 and the N-type diffusion region via the contact 66. 44 is applied to the gate of the N-type transistor constituted by 44.

  The contact 67 connects the metal first layer wiring 62 and the polysilicon wiring 42. Accordingly, the input signal supplied to the metal first layer wiring 62 is connected to the gate of the P-type transistor constituted by the polysilicon wiring 42 and the P-type diffusion region 43 and the polysilicon wiring 42 and the N-type diffusion region via the contact 67. 44 is applied to the gate of the N-type transistor constituted by 44.

  Contacts 68 and 69 connect the metal first-layer wiring 63 to the P-type diffusion region 43 and the N-type diffusion region 44, respectively. That is, the drain of the P-type transistor constituted by the polysilicon wiring 41 and the P-type diffusion region 43, the drain of the P-type transistor constituted by the polysilicon wiring 42 and the P-type diffusion region 43, the polysilicon wiring 42 and the N-type diffusion. The drain of the N-type transistor constituted by the region 44 is connected.

  Contacts 70 and 71 connect the metal first layer wiring 64 and the P-type diffusion region 43. The metal first layer wiring 64 is laid at a position overlapping with any one of the VDD power supply lines 10-1, 10-2, 10-3,... Shown in FIG. ing. Therefore, contacts 70 and 71 are provided on the source of the P-type transistor constituted by the polysilicon wiring 41 and the P-type diffusion region 43 and the source of the P-type transistor constituted by the polysilicon wiring 42 and the P-type diffusion region 43, respectively. The VDD power is supplied through this.

  A contact 72 connects the metal first layer wiring 65 and the N-type diffusion region 44. The metal first layer wiring 65 is laid at a position overlapping with any one of the VSS power supply lines 20-1, 20-2, 20-3,... Shown in FIG. ing. Therefore, VSS power is supplied to the source of the N-type transistor constituted by the polysilicon wiring 41 and the N-type diffusion region 44 through the contact 72.

  With the above configuration, the 2-input NAND cell 60 outputs NAND logic signals from the metal 1 layer wiring 63 for the two input signals supplied to the metal 1 layer wirings 61 and 62.

  In the integrated circuit device layout method according to the present embodiment, next, in the layout after the completion of the processing in step S12 in FIG. 2 (the layout after the functional cells are arranged), the functional cells in the functional cell arrangement possible region. A non-arranged area where no is arranged is searched (unarranged area searching step, step S14 in FIG. 2). For example, in FIG. 5 (A) or FIG. 5 (B), functional cells (FC101, FC102,..., FC201, FC202,..., FC301, FC302,...) An area not arranged, that is, an area in which basic cells (BC103, BC107,..., BC203, BC205,..., BC305, BC307,...) Are searched.

  Next, at least two power reinforcement cells are arranged side by side along the Y direction in the non-arranged area searched in step S14 (power reinforcement cell placement step, step S16 in FIG. 2). The arrangement of the functional cells and the power supply reinforcing cells in the integrated circuit device 1 of FIGS. 1A and 1B described above is the integrated circuit device 1 shown in FIGS. 5A and 5B, respectively. In this layout, basic cells (BC103, BC107,..., BC203, BC205,..., BC305, BC307,...) Are connected to power supply reinforcement cells (PC101, PC102,..., PC201, PC202,... · PC301, PC302, ...).

  In the process of step S16, as shown in FIGS. 1A and 1B, at least two power supply reinforcement cells (for example, PC101 and PC201) are arranged along the Y direction in the unarranged area searched in step S14. The three power supply reinforcing cells (for example, PC103, PC203, and PC303) may be arranged side by side along the Y direction.

  In FIG. 8, an example of a structure of a power supply reinforcement cell is shown. The same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

  In the power reinforcing cell 80, metal first-layer wirings 81, 82, 83, 84, 85, 86 and contacts 87, 88, 89, 90 are added to the basic cell 40 described in FIG.

  The power supply reinforcing cell 80 includes a VDD power supply reinforcing line (first power supply reinforcing line) and a VSS power supply reinforcing line (second power supply reinforcing line). At least a part of the VDD power supply reinforcing line is formed by a polysilicon wiring 42 (first polysilicon wiring pattern) laid on the polysilicon wiring layer, and at least a part of the VSS power supply reinforcing line is formed on the polysilicon wiring layer. It is formed by a laid polysilicon wiring 41 (second polysilicon wiring pattern).

  Further, a part of the VDD power supply reinforcing line is laid in the metal 1 wiring layer, and is formed by metal 1 layer wiring 83 and 84 (first metal wiring pattern) connected to the polysilicon wiring 42 through the contacts 89 and 90. A part of the VSS power supply reinforcing line is formed and is laid on the metal 1 wiring layer, and is connected to the polysilicon wiring 41 via the contacts 87 and 88 (second metal wiring 81 and 82). Pattern).

  Here, a part of the metal first layer wiring 83 overlaps with the metal first layer wiring 85. The metal first layer wiring 85 is positioned so as to overlap with any one of the VDD power supply lines 10-1, 10-2, 10-3,... Shown in FIG. It is laid. Therefore, VDD power is supplied to the polysilicon wiring 42 and the metal first layer wiring 84 through the metal first layer wiring 85, the metal first layer wiring 83, and the contacts 89 and 90. Similarly, a part of the metal first layer wiring 82 overlaps with the metal first layer wiring 86. And the metal 1 layer wiring 86 is in the position which overlaps with any of the VSS power supply lines 20-1, 20-2, 20-3,... Shown in FIG. It is laid. Therefore, VSS power is supplied to the polysilicon wiring 41 and the metal first layer wiring 81 through the metal first layer wiring 86, the metal first layer wiring 82, and the contacts 88 and 87.

  That is, by arranging the power supply reinforcing cells 80 (PC101, PC102,..., PC201, PC202,..., PC301, PC302,...) As shown in FIG. The VDD power supply reinforcement line is connected to one of the VDD power supply lines 10-1, 10-2, 10-3,... By the metal first layer wirings 83 and 84, and the VSS power supply reinforcement is provided by the metal first layer wirings 81 and 82. The line is connected to one of the VSS power supply lines 20-1, 20-2, 20-3,.

  Further, the metal first layer wirings 83 and 84 and the metal first layer wirings 81 and 82 are on the side 47-2 (first side) and the side 47-4 (second side) opposite to the side 47-2 of the cell. You may be laid so that it may touch. In FIG. 1 (A) or FIG. 1 (B), the power supply reinforcing cells 80 (PC101, PC102,..., PC201, PC202,..., So that the sides 47-2 and 47-4 are orthogonal to the Y direction. PC301, PC302, ...) are arranged.

  Therefore, in the case of the integrated circuit device 1 in FIG. 1A, when two power supply reinforcing cells (for example, PC 101 and PC 201) are arranged along the Y direction, Metal wiring (for example, metal 1 layer wiring or metal 2) for connecting metal 1 layer wirings 81 (or between metal 1 layer wirings 82) and metal 1 layer wirings 83 (or between metal 1 layer wirings 84) of power supply reinforcing cells. Layer wiring etc.) can be laid along the Y direction. Therefore, the power supply can be efficiently reinforced without requiring a dedicated wiring area for power supply. In the case of the integrated circuit device 1 in FIG. 1B, when two power reinforcing cells (for example, PC 101 and PC 201) are arranged side by side along the Y direction (arranged so as to be adjacent to each other), two power supplies The metal 1 layer wirings 81 (or the metal 1 layer wirings 82) and the metal 1 layer wirings 83 (or the metal 1 layer wirings 84) of the reinforcing cell are connected. Therefore, the power supply can be efficiently reinforced without requiring a dedicated wiring area for power supply.

  In addition, since the power reinforcing cell 80 includes the metal first layer wirings 81, 82, 83, and 84, the distribution of the metal first layer wiring can be improved by arranging the power reinforcing cell 80 in the non-arranged region. .

  Furthermore, since the power supply reinforcing cell 80 includes a VDD power supply reinforcing line to which VDD power is supplied and a VSS power supply line to which VSS power is supplied, a shielding effect can be obtained by arranging the power reinforcing cell 80 in the non-arranged region. .

  FIG. 9 shows another example of the configuration of the power supply reinforcing cell. The same components as those in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted.

  The power reinforcing cell 100 is wired so that the metal first-layer wirings 82 and 83 overlap the P-type diffusion region 46 and the N-type diffusion region 45 with respect to the power reinforcing cell 80 described in FIG. A contact 91 for connecting the first layer wiring 82 and the P type diffusion region 46 and a contact 92 for connecting the metal first layer wiring 83 and the N type diffusion region 45 are added.

  The metal first layer wiring 85 is positioned so as to overlap with any one of the VDD power supply lines 10-1, 10-2, 10-3,... Shown in FIG. A position where the metal first layer wiring 86 is laid and overlaps one of the VSS power supply lines 20-1, 20-2, 20-3,... Shown in FIG. Is laid.

  Therefore, VDD power is supplied to the N-type diffusion region 45 via the metal first layer wiring 83 and the contact 92. The N type diffusion region 45 is disposed in the N well (or N substrate) and plays a role of stabilizing the potential of the N well (or N substrate) to VDD.

  Further, VSS power is supplied to the P-type diffusion region 46 through the metal first layer wiring 82 and the contact 91. The P-type diffusion region 46 is disposed in the P well (or P substrate) and plays a role of stabilizing the potential of the P well (or P substrate) to VSS.

  That is, by arranging the power supply reinforcing cell 100 in the non-arranged region, the potential of the N well (or N substrate) and the potential of the P well (or P substrate) can be further stabilized.

  In the integrated circuit device layout method of the present embodiment, finally, nets between functional cells are wired (step S18 in FIG. 2). In the process of step S18, the VDD power supply lines 10-1, 10-2, 10-3,..., And the VSS power supply lines 20-1, 20-2 in FIG. , 20-3,... Are wired in a metal wiring layer higher than the metal 1 wiring layer (for example, metal 2 wiring layer to metal 4 wiring layer). Here, the wiring pattern for reinforcing the VDD power source and the wiring pattern for reinforcing the VSS power source formed when at least two power source reinforcing cells are arranged side by side along the Y direction are polysilicon wiring, Since it is formed in the contact and metal 1 wiring layer, the net wiring between the functional cells is not affected.

  FIG. 10 is a diagram for explaining a wiring pattern for reinforcing the VDD power supply formed when two power supply reinforcing cells shown in FIG. 8 are arranged in the Y direction. The power reinforcing cells 80-1 and 80-2 are arranged side by side in the Y direction (arranged so as to be adjacent to each other). Here, the power supply reinforcement cell 80-2 is arranged so that the direction is reversed along the Y direction with respect to the power supply reinforcement cell 80-1.

  The power supply reinforcement cells 80-1 and 80-2 correspond to, for example, the power supply reinforcement cells PC101 and PC201 in FIG. Accordingly, for example, the VDD power supply and the VSS power are supplied from the VDD power supply line 10-1 and the VSS power supply line 20-1, respectively, to the metal first layer wirings 85-1 and 86-1 of the power supply reinforcing cell 80-1. The Similarly, for example, the VDD power supply and the VSS power supply are supplied from the VDD power supply line 10-2 and the VSS power supply line 20-2 to the metal first layer wirings 85-2 and 86-2 of the power supply reinforcing cell 80-2, respectively. Is done.

  And the metal 1 layer wiring 85-1 (VDD power supply line 10-1) of the power reinforcement cell 80-1 and the metal 1 layer wiring 85-2 (VDD power supply line 10-2) of the power reinforcement cell 80-2 are as follows. , Metal first layer wiring 83-1 of power supply reinforcing cell 80-1, contact 89-1, polysilicon wiring 42-1, contact 90-1, metal first layer wiring 84-1, and metal of power reinforcing cell 80-2. The first layer wiring 84-2, the contact 90-2, the polysilicon wiring 42-2, the contact 89-2, and the metal first layer wiring 83-2 are connected. That is, the metal 1 layer wiring 83-1, the contact 89-1, the polysilicon wiring 42-1, the contact 90-1, the metal 1 layer wiring 84-1, and the power supply reinforcing cell 80-2 of the power reinforcing cell 80-1. By using the metal first layer wiring 84-2, the contact 90-2, the polysilicon wiring 42-2, the contact 89-2, and the metal first layer wiring 83-2, the polysilicon wirings 42-1 and 42-2 are connected to the metal first layer wiring 86. -1 (VSS power supply line 20-1) and 86-2 (VSS power supply line 20-2), respectively, to reinforce the VDD power supply connecting the VDD power supply lines 10-1 and 10-2 The wiring pattern is formed.

  FIG. 11 is a diagram for explaining a wiring pattern for reinforcing the VSS power supply formed when two power supply reinforcing cells shown in FIG. 8 are arranged in the Y direction. The power reinforcing cells 80-2 and 80-3 are arranged side by side in the Y direction (arranged so as to be adjacent to each other). Here, the power supply reinforcement cell 80-2 is arranged in the same direction as the power supply reinforcement cell 80-2 of FIG. 10 along the Y direction, and the power supply reinforcement cell 80-3 is Y with respect to the power supply reinforcement cell 80-2. It arrange | positions so that direction may be reversed along a direction.

  The power supply reinforcement cells 80-2 and 80-3 correspond to, for example, the power supply reinforcement cells PC202 and PC301 in FIG. 1B, respectively. Accordingly, for example, the VDD power supply and the VSS power are supplied from the VDD power supply line 10-2 and the VSS power supply line 20-2 to the metal first layer wirings 85-2 and 86-2 of the power supply reinforcing cell 80-2, respectively. The Similarly, the VDD power supply and the VSS power supply are supplied from, for example, the VDD power supply line 10-3 and the VSS power supply line 20-3 to the metal first layer wirings 85-3 and 86-3 of the power reinforcing cell 80-3, respectively. Is done.

  And the metal 1 layer wiring 86-2 (VSS power supply line 20-2) of the power reinforcement cell 80-2 and the metal 1 layer wiring 86-3 (VSS power supply line 20-3) of the power reinforcement cell 80-3 are as follows. , Metal first layer wiring 82-2, contact 88-2, polysilicon wiring 41-2, contact 87-2, metal first layer wiring 81-2, and metal of power reinforcing cell 80-3 The first layer wiring 81-3, the contact 87-3, the polysilicon wiring 41-3, the contact 88-3, and the metal first layer wiring 82-3 are connected. That is, the metal first layer wiring 82-2, contact 88-2, polysilicon wiring 41-2, contact 87-2, metal first layer wiring 81-2, and power reinforcing cell 80-3 of the power reinforcing cell 80-2. By using the metal first layer wiring 81-3, the contact 87-3, the polysilicon wiring 41-3, the contact 88-3, and the metal first layer wiring 82-3, the polysilicon wirings 41-2 and 41-3 are connected to the metal first layer wiring 85. -2 (VDD power supply line 10-2) and 85-3 (VDD power supply line 10-3), respectively, to reinforce the VSS power supply connecting the VSS power supply lines 20-2 and 20-3. The wiring pattern is formed.

  FIG. 12 is a diagram for explaining a wiring pattern for reinforcing the VDD power source and a wiring pattern for reinforcing the VSS power source, which are formed when three power source reinforcing cells shown in FIG. 8 are arranged in the Y direction. FIG. The power reinforcing cells 80-1, 80-2, and 80-3 are arranged side by side (arranged so as to be adjacent) in the Y direction. Here, the power supply reinforcement cells 80-1, 80-2, and 80-3 are arranged in the same direction as the power supply reinforcement cells 80-1, 80-2, and 80-3 in FIGS. 10 and 11, respectively, along the Y direction. ing. That is, the power supply reinforcement cell 80-2 is arranged so that the direction is reversed along the Y direction with respect to the power supply reinforcement cell 80-1, and the power supply reinforcement cell 80-3 is in the Y direction with respect to the power supply reinforcement cell 80-2. It is arranged so that the direction is reversed along.

  The power supply reinforcement cells 80-1, 80-2, and 80-3 correspond to, for example, the power supply reinforcement cells of the PC 103, PC 203, and PC 303 in FIG. Accordingly, for example, the VDD power supply and the VSS power are supplied from the VDD power supply line 10-1 and the VSS power supply line 20-1, respectively, to the metal first layer wirings 85-1 and 86-1 of the power supply reinforcing cell 80-1. The Similarly, for example, the VDD power supply and the VSS power supply are supplied from the VDD power supply line 10-2 and the VSS power supply line 20-2 to the metal first layer wirings 85-2 and 86-2 of the power supply reinforcing cell 80-2, respectively. Is done. Similarly, the VDD power supply and the VSS power supply are supplied from, for example, the VDD power supply line 10-3 and the VSS power supply line 20-3 to the metal first layer wirings 85-3 and 86-3 of the power reinforcing cell 80-3, respectively. Is done.

  Therefore, the metal 1 layer wiring 85-1 (VDD power supply line 10-1) of the power supply reinforcing cell 80-1 and the metal 1 layer wiring 85-2 (VDD power supply line 10-2) of the power reinforcing cell 80-2 are connected. The wiring pattern and the metal 1 layer wiring 86-2 (VSS power supply line 20-2) of the power reinforcing cell 80-2 and the metal 1 layer wiring 86-3 (VSS) of the power reinforcing cell 80-3 which are connected in FIG. Both of the wiring patterns described in FIG. 11 for connecting the power supply line 20-3) are formed.

  After all, in the integrated circuit device 1 of FIG. 1B, the VDD power supply lines 10-1 and 10-2 (and 10-3) are connected in the Y direction by two sets of power supply reinforcement cells of PC101 and PC201 and PC103 and PC203. Two wiring patterns connected to are formed. In addition, three sets of power reinforcement cells, PC202 and PC301, PC203 and PC303, PC204 and PC304, have three wiring patterns for connecting the VSS power supply lines 20-2 (and 20-1) and 20-3 in the Y direction. It is formed.

  FIG. 13 is another example of a flowchart for explaining the layout method of the integrated circuit device of this embodiment. The processes in steps S20 and S22 in the flowchart shown in FIG. 13 are the same as the processes in steps S10 and S12 in the flowchart shown in FIG.

  On the other hand, while the flowchart shown in FIG. 2 performs the processing of the unplaced area searching step (step S14) and the power reinforcing cell placement step (step S16), the net between functional cells is wired in step S18. The flowchart shown in FIG. 13 is different in that the processing of the unplaced area searching step (step S26) and the power supply reinforcing cell placement step (step S28) is performed after the net between the functional cells is wired in step S24.

  In the process of step S24, the VDD power supply lines 10-1, 10-2, 10-3,..., And the VSS power supply lines 20-1, 20-2 in FIG. In the metal wiring layer (for example, metal 2 wiring layer to metal 4 wiring layer) higher than the metal 1 wiring layer on which 20-3,. On the other hand, the power reinforcing cell is wired with a polysilicon wiring layer and a metal 1 wiring layer. Accordingly, even after the net connecting the functional cells is wired in the process of step S24, the power reinforcing cell can be arranged in the non-arranged region without changing the net wiring in the process of step S28.

  As described above with reference to FIGS. 1 to 13, according to the layout method of the integrated circuit device of this embodiment, in the layout after the functional cells are arranged in the predetermined area, at least 2 in the area where the functional cells are not arranged. By arranging two power supply reinforcing cells side by side along the Y direction, a wiring pattern connecting two VDD power supply lines via the VDD power supply reinforcing line and two VSS power supply reinforcing lines along the Y direction are provided. At least one of the wiring patterns connecting the VSS power supply lines is formed. That is, at least one of the VDD power supply and the VSS power supply can be reinforced by simply arranging at least two power supply reinforcing cells side by side along the Y direction. Therefore, according to the integrated circuit device layout method of the present embodiment, it is possible to provide an integrated circuit device that realizes power supply reinforcement without increasing the chip area.

  Further, according to the layout method of the integrated circuit device of the present embodiment, the VDD power supply line and the VSS power supply line are laid in the metal 1 wiring layer, whereas the VDD power supply line included in the power supply cell and At least a part of the VSS power supply reinforcing line is formed by a first polysilicon wiring pattern and a second polysilicon wiring pattern laid in a polysilicon wiring layer below the metal 1 wiring layer, respectively. Then, the power reinforcing cell is arranged so that the first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the VSS power supply line and the VDD power supply line, respectively. Therefore, according to the layout method of the integrated circuit device of the present embodiment, the wiring for reinforcing the VDD power supply without short-circuiting the VDD power supply line and the VSS power supply line, and the VSS power supply line and the VDD power supply reinforcement line, respectively. At least one of the pattern and the wiring pattern for reinforcing the VSS power supply can be formed.

  Further, according to the layout method of the integrated circuit device of the present embodiment, the power reinforcing cell has the second metal wiring pattern and the second metal wiring pattern facing the first side and the first side of the cell. The power supply reinforcing cell is arranged so that the first side and the second side are orthogonal to the Y direction. Therefore, when two power supply reinforcing cells are arranged so as to be adjacent to each other in the Y direction, the first metal wiring patterns and the second metal wiring patterns of each power supply reinforcing cell are connected to each other. That is, according to the layout method of the integrated circuit device of the present embodiment, it is possible to reinforce at least one of the VDD power source and the VSS power source only by arranging at least two power source reinforcing cells so as to be adjacent in the Y direction. it can. Therefore, according to the layout method of the integrated circuit device of this embodiment, it is possible to efficiently reinforce the power without securing a wiring area for power reinforcement in advance.

  Further, according to the layout method of the integrated circuit device of the present embodiment, each wiring pattern for reinforcing the VDD power source and the VSS power source has a metal wiring layer (for example, a metal 2 wiring layer˜ The metal 1 wiring layer and the polysilicon wiring layer lower than the (metal 4 wiring layer) are formed. Therefore, the arrangement of the power reinforcing cell does not affect the net wiring connecting the functional cells. That is, according to the layout method of the integrated circuit device of the present embodiment, it is possible to perform net wiring without unnecessarily increasing the wiring area, thereby realizing power supply reinforcement without increasing the chip area. Can do.

3. Integrated Circuit Device Layout System, Integrated Circuit Device Layout Program FIG. 14 is a diagram for explaining the integrated circuit device layout system and layout program of this embodiment. The integrated circuit device layout system 200 of the present embodiment may have a configuration in which some of the components (parts) are omitted.

  The operation unit 220 is for inputting user operations and the like as data, and the function can be realized by hardware such as a keyboard and a mouse.

  The storage unit 230 serves as a work area such as the processing unit 210 and the communication unit 270, and its function can be realized by hardware such as a RAM.

  The storage unit 230 includes a library information storage unit 232.

  The library information storage unit 232 stores library information (logic circuit information, layout information, connection information) obtained from design data, information on the generated netlist, and the like.

  The information storage medium 240 (a computer-readable medium) stores programs, data, and the like, and functions as an optical disk (CD, DVD, etc.), a magneto-optical disk (MO), a magnetic disk, a hard disk, and a magnetic disk. It can be realized by hardware such as a tape or a memory (ROM).

  The information storage medium 240 stores programs and data that cause the computer to function as each unit of the present embodiment.

  The processing unit 210 performs various operations of the present embodiment based on a program (layout program) stored in the information storage medium 240, data read from the information storage medium 240 (function cell, power supply cell data, etc.), and the like. Perform the process. That is, the information storage medium 240 stores a program for causing a computer to function as each unit of the present embodiment (a program for causing a computer to execute the process of each unit).

  The display unit 250 outputs an image generated according to the present embodiment, and functions thereof are a CRT display, an LCD (liquid crystal display), an OELD (organic EL display), a PDP (plasma display panel), and a touch panel display. It can be realized by hardware such as.

  The sound output unit 260 outputs the sound generated according to the present embodiment, and its function can be realized by hardware such as a speaker or headphones.

  The communication unit 270 performs various controls for communicating with the outside (for example, a server device or other terminals), and functions thereof include hardware such as various processors or communication ASICs, It can be realized by a program.

  The processing unit 210 (processor) performs various processes based on operation data and programs from the operation unit 220. The processing unit 210 performs various processes using the storage unit 230 as a work area. The functions of the processing unit 210 can be realized by hardware such as various processors (CPU, DSP, etc.), ASIC (gate array, etc.), application programs, and OS (for example, general-purpose OS).

  The processing unit 210 includes a non-arranged area searching unit 212 and a power supply reinforcing cell arranging unit 214. The processing unit 210 may further include a functional cell placement unit 216 and a net wiring unit 218.

  The non-arranged area searching unit 212 performs a process of searching for an unallocated area in which a functional cell in a predetermined area is not arranged in a layout after arranging a plurality of functional cells in the predetermined area.

  The power reinforcement cell placement means 214 is a first power reinforcement formed by a first polysilicon wiring pattern at least partially laid on the polysilicon wiring layer in the unplaced area searched by the unplaced area search means 212. A process of arranging a power supply reinforcement cell including a line and a second power supply reinforcement line formed by a second polysilicon wiring pattern laid at least partially on the polysilicon wiring layer is performed. Then, the power reinforcing cell arranging means 214 intersects the first polysilicon wiring pattern and the second polysilicon wiring pattern with the second power supply line and the first power supply line, respectively, in the second direction. A wiring pattern connecting the two first power supply lines via the first power supply reinforcing line and a wiring pattern connecting the two second power supply lines via the second power reinforcing line At least two power reinforcing cells are arranged side by side along the second direction so that one is formed.

  The functional cell arrangement unit 216 performs a process of arranging a plurality of functional cells in an array in a first direction and a second direction orthogonal to the first direction in a predetermined region.

  The net wiring means 218 performs processing for wiring a net for connecting functional cells based on circuit connection information of (a part of) the integrated circuit device.

  The non-arranged area searching unit 212 and the power supply reinforcing cell arranging unit 214 arrange the process of searching for the non-arranged area and the power reinforcing cell, respectively, in the layout after the functional cell arranging unit 216 performs the process of arranging the functional cell. Processing may be performed.

  In addition, the unplaced area searching unit 212 and the power supply reinforcing cell placing unit 214 are respectively a process for searching for unplaced areas and a power source in the layout after the net wiring unit 218 performs the process of wiring nets connecting functional cells. You may make it perform the process which arrange | positions a reinforcement cell.

  According to the layout system or the layout program of the integrated circuit device of this embodiment, in the layout after the functional cells are arranged in the predetermined area, at least two power supply reinforcing cells are arranged in the second direction in the functional cell non-arranged area. By arranging the two power supply lines along the second direction, the wiring pattern connecting the two first power supply lines via the first power supply reinforcing line and the two power supply reinforcing lines along the second direction. At least one of the wiring patterns for connecting the second power supply line is formed. That is, it is possible to reinforce at least one of the first power source and the second power source only by arranging at least two power source reinforcing cells side by side along the second direction. Therefore, according to the layout system or layout program of the integrated circuit device of this embodiment, it is possible to provide an integrated circuit device that realizes power supply reinforcement without increasing the chip area.

  According to the layout system or layout program of the integrated circuit device of this embodiment, the first power supply line and the second power supply line are laid on a predetermined metal wiring layer, whereas the power supply reinforcing cell A first polysilicon wiring pattern and a second polysilicon wiring in which at least a part of the first power supply reinforcing line and the second power supply reinforcing line included in the wiring are laid in a polysilicon wiring layer lower than the metal wiring layer Each is formed by a pattern. The power reinforcing cells are arranged so that the first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the second power supply line and the first power supply line, respectively. Therefore, according to the layout system or layout program of the integrated circuit device of the present embodiment, the first power supply line and the second power supply reinforcement line, and the second power supply line and the first power supply reinforcement line are short-circuited, respectively. It is possible to form at least one of a wiring pattern for reinforcing the first power source and a wiring pattern for reinforcing the second power source.

  Note that a program (layout program) for causing a computer to function as each unit of this embodiment is an information storage medium 240 (storage unit 230) from an information storage medium included in a host device (server) via a network and communication unit 270. May be delivered to. Use of the information storage medium of such a host device (server) can also be included in the scope of the present invention.

4). Electronic Device FIG. 15 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (integrated circuit device) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 16A illustrates an example of an external view of a cellular phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 16B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 16C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the integrated circuit device of this embodiment into the electronic devices in FIGS. 16A to 16C, an electronic device that is strong against power supply noise and has high reliability can be provided.

  Note that electronic devices that can use this embodiment include, in addition to those shown in FIGS. 16A to 16C, portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, projectors, Various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

FIG. 1A and FIG. 1B are diagrams for explaining the integrated circuit device of this embodiment. An example of the flowchart for demonstrating the layout method of the integrated circuit device of this embodiment. 3A and 3B are diagrams for explaining a layout method of the integrated circuit device of the present embodiment. The figure which shows an example of a structure of a basic cell. FIG. 5A and FIG. 5B are diagrams for explaining a layout method of the integrated circuit device of this embodiment. The figure which shows an example of a structure of the inverter cell as an example of a functional cell. The figure which shows an example of a structure of 2 input NAND cell as an example of a functional cell. The figure which shows an example of a structure of a power supply reinforcement cell. The figure which shows an example of a structure of a power supply reinforcement cell. The figure for demonstrating the wiring pattern for reinforcing the VDD power supply formed when two power supply reinforcement cells are arrange | positioned along with the Y direction. The figure for demonstrating the wiring pattern for reinforcing the VSS power supply formed when two power supply reinforcement cells are arrange | positioned along with the Y direction. The figure for demonstrating the wiring pattern for reinforcing the VDD power supply formed when three power supply reinforcement cells are arrange | positioned along with the Y direction, and the wiring pattern for reinforcing a VSS power supply. An example of the flowchart for demonstrating the layout method of the integrated circuit device of this embodiment. 1 is a diagram for explaining a layout system and a layout program of an integrated circuit device according to an embodiment. 1 is an example of a block diagram of an electronic device including an integrated circuit device. 16A to 16C are examples of external views of various electronic devices.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Integrated circuit device, 2 Function cell arrangement | positioning area | region, 3 Wiring grid, 10-1 to 10-3 VDD power supply line, 20-1 to 20-3 VSS power supply line, 30 Wiring area, 40 Basic cell, 41 Poly Silicon wiring, 41-1 to 41-3 polysilicon wiring, 42 polysilicon wiring, 42-1 to 42-3 polysilicon wiring, 43P type diffusion region, 44N type diffusion region, 45N type diffusion region, 46P Diffusion region, 47-1 to 47-4 sides, 50 inverter cell, 51 metal 1 layer wiring, 52 metal 1 layer wiring, 53 metal 1 layer wiring, 54 metal 1 layer wiring, 55 contacts, 56 contacts, 57 contacts, 58 contacts, 59 contacts, 60 2-input NAND cell, 61 metal 1 layer wiring, 62 metal 1 layer wiring, 63 metal Layer wiring, 64 metal 1 layer wiring, 65 metal 1 layer wiring, 66 contact, 67 contact, 68 contact, 69 contact, 70 contact, 71 contact, 72 contact, 80 power supply reinforcement cell, 80-1 to 80-3 power supply reinforcement Cell, 81 Metal 1 layer wiring, 81-1 to 81-3 Metal 1 layer wiring, 82 Metal 1 layer wiring, 82-1 to 82-3 Metal 1 layer wiring, 83 Metal 1 layer wiring, 83-1 to 83- 3 metal 1 layer wiring, 84 metal 1 layer wiring, 84-1 to 84-3 metal 1 layer wiring, 85 metal 1 layer wiring, 85-1 to 85-3 metal 1 layer wiring, 86 metal 1 layer wiring, 86- 1-86-3 metal 1 layer wiring, 87 contacts, 87-1 to 87-3 contacts, 88 contacts, 88-1 to 88-3 contacts, 8 Contact, 89-1 to 89-3 Contact, 90 Contact, 90-1 to 90-3 Contact, 91 Contact, 92 Contact, 100 Power Reinforcement Cell, 200 Layout System, 210 Processing Unit, 212 Unplaced Area Search Means, 214 Power reinforcement cell arrangement means, 216 functional cell arrangement means, 218 net wiring means, 220 operation section, 230 storage section, 232 library information storage section, 240 information storage medium, 250 display section, 260 sound output section, 270 communication section, 800 Electronic equipment, 810 microcomputer (integrated circuit device), 820 input unit, 830 memory, 840 power generation unit, 850 LCD, 860 sound output unit, 950 mobile phone, 952 dial button, 954 LCD, 956 speaker, 960 portable game Location, 962 operation buttons 964 cross key, 966 LCD, 968 speaker, 970 personal computer, 972 keyboard, 974 LCD, 976 a sound output unit

Claims (15)

A plurality of functional cells are arranged in an array in a predetermined region in a first direction and a second direction orthogonal to the first direction, and a first power source and a second power source are respectively supplied to the plurality of functional cells. A method for laying out an integrated circuit device in which a first power supply line and a second power supply line to be supplied are laid on a predetermined metal wiring layer along the first direction,
In a layout after arranging the plurality of functional cells in the predetermined area, a non-arranged area search step for searching an unarranged area in which the functional cells are not arranged in the predetermined area;
In the non-arranged region, a first power reinforcing line formed by a first polysilicon wiring pattern at least partly laid on the polysilicon wiring layer and a first power supply line at least partly laid on the polysilicon wiring layer. A power reinforcement cell arranging step of arranging a power reinforcement cell including a second power reinforcement line formed by two polysilicon wiring patterns,
In the power reinforcing cell placement step,
The first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the second power supply line and the first power supply line, respectively, along the second direction, At least one of a wiring pattern that connects the two first power supply lines via one power reinforcing line and a wiring pattern that connects the two second power supply lines via the second power reinforcing line A method for laying out an integrated circuit device, wherein at least two of the power reinforcing cells are arranged side by side along the second direction so as to be formed. In claim 1,
The power reinforcing cell is
A part of the first power supply reinforcing line and a part of the second power supply reinforcing line are laid on the predetermined metal wiring layer, and the first polysilicon wiring pattern and the second power supply line are connected via a contact. Formed by a first metal wiring pattern and a second metal wiring pattern respectively connected to the polysilicon wiring pattern;
In the power reinforcing cell placement step,
The first power supply line is connected to the first power supply line by the first metal wiring pattern, and the second power supply line is connected to the second power supply line by the second metal wiring pattern. A layout method of an integrated circuit device, wherein the power reinforcing cell is arranged so as to be connected to a power source. In claim 2,
The power reinforcing cell is
The first metal wiring pattern and the second metal wiring pattern are laid so as to be in contact with a first side of the cell and a second side facing the first side,
A layout method of an integrated circuit device, wherein the power supply reinforcing cell is arranged so that the first side and the second side are orthogonal to the second direction. In any one of Claims 1 thru | or 3,
The predetermined metal wiring layer is
A method for laying out an integrated circuit device, characterized in that the metal wiring layer is lower than a metal wiring layer for wiring a net connecting the plurality of functional cells. In any one of Claims 1 thru | or 4,
In the power reinforcing cell placement step,
A wiring pattern connecting the two first power supply lines via the first power supply reinforcement line and the second power supply lines via the second power supply reinforcement line along the second direction. A layout method of an integrated circuit device, wherein at least three of the power reinforcing cells are arranged side by side along the second direction so that both wiring patterns connecting power supply lines are formed. In any one of Claims 1 thru | or 5,
The functional cell and the power supply reinforcing cell are:
A layout method of an integrated circuit device, which is realized based on a basic cell as a unit of a gate array and a predetermined wiring pattern. A plurality of functional cells are arranged in an array in a predetermined region in a first direction and a second direction orthogonal to the first direction, and a first power source and a second power source are respectively supplied to the plurality of functional cells. A layout program for laying out an integrated circuit device in which a first power supply line and a second power supply line to be supplied are laid on a predetermined metal wiring layer along the first direction,
In a layout after the plurality of functional cells are arranged in the predetermined area, an unarranged area search means for searching for an unarranged area in which the functional cells are not arranged in the predetermined area;
In the non-arranged region, a first power reinforcing line formed by a first polysilicon wiring pattern at least partly laid on the polysilicon wiring layer and a first power supply line at least partly laid on the polysilicon wiring layer. And a second power source reinforcement line formed by the polysilicon wiring pattern, and a power source reinforcement cell arrangement means for arranging a power source reinforcement cell including the second power source reinforcement line,
The power reinforcing cell arranging means is
The first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the second power supply line and the first power supply line, respectively, along the second direction, At least one of a wiring pattern that connects the two first power supply lines via one power reinforcing line and a wiring pattern that connects the two second power supply lines via the second power reinforcing line A layout program for an integrated circuit device, wherein at least two of the power supply reinforcing cells are arranged side by side along the second direction so as to be formed. A plurality of functional cells are arranged in an array in a predetermined region in a first direction and a second direction orthogonal to the first direction, and a first power source and a second power source are respectively supplied to the plurality of functional cells. A layout system for laying out an integrated circuit device in which a first power supply line and a second power supply line to be supplied are laid on a predetermined metal wiring layer along the first direction,
In a layout after the plurality of functional cells are arranged in the predetermined area, an unarranged area search means for searching for an unarranged area in which the functional cells are not arranged in the predetermined area;
In the non-arranged region, a first power reinforcing line formed by a first polysilicon wiring pattern at least partly laid on the polysilicon wiring layer and a first power supply line at least partly laid on the polysilicon wiring layer. Power reinforcing cell arrangement means for arranging a power reinforcing cell including a second power reinforcing line formed by two polysilicon wiring patterns,
The power reinforcing cell arranging means is
The first polysilicon wiring pattern and the second polysilicon wiring pattern intersect with the second power supply line and the first power supply line, respectively, along the second direction, At least one of a wiring pattern that connects the two first power supply lines via one power reinforcing line and a wiring pattern that connects the two second power supply lines via the second power reinforcing line An integrated circuit device layout system, wherein at least two of the power supply reinforcing cells are arranged side by side along the second direction so as to be formed. A plurality of functional cells are arranged in an array in a predetermined region in a first direction and a second direction orthogonal to the first direction, and a first power source and a second power source are respectively supplied to the plurality of functional cells. An integrated circuit device in which a first power supply line and a second power supply line to be supplied are laid on a predetermined metal wiring layer along the first direction,
A first power supply reinforcement line formed by a first polysilicon wiring pattern disposed in a region where the functional cell is not disposed in the predetermined region and at least a part of which is laid on a polysilicon wiring layer; and A power supply reinforcing cell including a second power supply reinforcing line formed by a second polysilicon wiring pattern partially laid on the polysilicon wiring layer,
By arranging at least two of the power reinforcing cells side by side along the second direction, the first polysilicon wiring pattern and the second polysilicon wiring pattern are connected to the second power supply line and A wiring pattern that crosses each of the first power supply lines and connects the two first power supply lines through the first power supply reinforcing line along the second direction; An integrated circuit device, wherein at least one of the wiring patterns connecting the two second power supply lines via the power reinforcing line is formed. In claim 9,
The power reinforcing cell is
A part of the first power supply reinforcing line and a part of the second power supply reinforcing line are laid on the predetermined metal wiring layer, and the first polysilicon wiring pattern and the second power supply line are connected via a contact. A first metal wiring pattern and a second metal wiring pattern respectively connected to the polysilicon wiring pattern are formed, and the first power supply reinforcing line is formed into the first power supply line by the first metal wiring pattern. An integrated circuit device characterized in that the second power supply reinforcing line is connected to the second power supply line by the second metal wiring pattern. In claim 10,
The power reinforcing cell is
The first metal wiring pattern and the second metal wiring pattern are laid so as to contact a first side of the cell and a second side opposite to the first side, and the first side and the second side 2. An integrated circuit device, wherein two sides are arranged so as to be orthogonal to the second direction. In any of claims 9 to 11,
The predetermined metal wiring layer is
An integrated circuit device comprising a metal wiring layer lower than a metal wiring layer for wiring a net connecting the plurality of functional cells. In any of claims 9 to 12,
By arranging at least three of the power supply reinforcing cells side by side along the second direction, the two first power supplies are provided along the second direction via the first power supply reinforcing line. An integrated circuit device, wherein both a wiring pattern for connecting a supply line and a wiring pattern for connecting the two second power supply lines through the second power supply reinforcing line are formed. In any of claims 9 to 13,
The functional cell and the power supply reinforcing cell are:
An integrated circuit device, which is realized based on a basic cell as a unit of a gate array and a predetermined wiring pattern. An integrated circuit device according to claim 9 to 14, and
Data input means to be processed by the integrated circuit device;
And an output means for outputting data processed by the integrated circuit device.

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