JP2009099588A - Power supply wiring method for semiconductor integrated circuit device, power supply wiring program for semiconductor integrated circuit device, design support system for semiconductor integrated circuit device, semiconductor integrated circuit device, and electronic instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply wiring method for a semiconductor integrated circuit device, which achieves the efficient power supply wiring for reducing the modifying work after the power supply wiring and for facilitating the signal wiring in post processing when carrying out the wiring connection of a power supply line to a power supply ring such as an IP module etc., and to provide a power supply wiring program and a design support system. <P>SOLUTION: The power supply wiring method comprises: the module arranging step (S12) of arranging a module so that one of a first direction or a second direction coincides with the power supply wiring direction; the power supply wiring candidate region setting-up step (S16) of setting up a region along the power supply wiring direction including a portion provided along the first direction or the second direction coinciding with the power supply wiring direction of the power supply ring included in the arranged module as a power supply wiring candidate region; and the power supply line wiring step (S20) of wiring the power supply line along the power supply wiring direction in the power supply wiring candidate region and connecting it to the power supply ring. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device power supply wiring method, a semiconductor integrated circuit device power supply wiring program, a semiconductor integrated circuit device design support system, a semiconductor integrated circuit device, and an electronic apparatus.

With the increasing number of functions and complexity of LSIs, design man-hours are reduced by designing LSIs by combining a plurality of IP modules (CPU, memory, etc.). In addition to the function, not only the netlist but also the layout data are prepared in the IP module that has to consider the timing of signal propagation. In such an IP module layout, a power supply ring is arranged around a core block that realizes an IP function, and power is supplied from the power supply ring to the core block.
JP-A-7-29977

  In the chip layout of the entire LSI, after arranging a plurality of IP modules, a power supply line for supplying a predetermined potential is connected to the power supply ring of each IP module. In general, the larger the number of IP modules, the more complicated the power supply wiring, and mistakes are likely to occur in the manual power supply wiring, resulting in an increase in man-hours. For this reason, automatic wiring tools are often used for automatic wiring by setting power supply wiring (setting of wiring length, wiring width, number of wiring, wiring, wiring layer, etc.). However, since the power supply wiring is performed without being aligned with the position of the power supply ring, the power supply wiring is bent at the corner portion of the power supply ring of the IP module, for example, as shown in FIG. Therefore, a space is secured between the power supply line and the power supply ring, so that it is difficult to perform efficient power supply wiring. If inefficient power supply wiring exists, the wiring area of various signal wirings performed in the process after power supply wiring is limited, so that the wiring efficiency is deteriorated and the chip area may be increased. Furthermore, if the number of IP modules increases, it becomes extremely difficult to automatically perform efficient power supply wiring, and power supply wiring that violates design rules may occur. If there is a power supply wiring that violates the design rule, it will be necessary to manually correct it, leading to an increase in design man-hours.

  The present invention has been made in view of the problems as described above, and when connecting the power supply line to the power supply ring of the IP module or the like, the correction work after the power supply wiring is reduced and the signal of the subsequent process is reduced. An object of the present invention is to provide a power supply wiring method, a power supply wiring program, and a design support system for a semiconductor integrated circuit device that realize efficient power supply wiring for facilitating wiring.

(1) The present invention
At least one module having a power ring with at least a portion laid along a given first direction and at least another portion laid along a second direction orthogonal to the first direction; A semiconductor integrated circuit device including a power supply wiring method for a semiconductor integrated circuit device, wherein a power supply line for supplying a predetermined potential to the power supply ring is provided,
A module placement step of placing the module such that at least one of the first direction or the second direction matches a power supply wiring direction in which the power supply line is wired;
An area along the power supply wiring direction including a portion laid along the first direction or the second direction of the power supply ring included in the arranged module is aligned with the power supply wiring direction. A power supply wiring candidate area setting step to be set in the wiring candidate area;
A power line wiring step for wiring the power line along the power wiring direction in the power wiring candidate region and connecting the power line to the power ring.

  The module may be a general-purpose IP module, for example. Modules may be automatically arranged on a tool such as a floor planner or manually.

  The power supply ring is disposed outside the core portion of the module (the portion that realizes the function of the module), and is formed in an annular shape only by wiring in the first direction (for example, the vertical direction) and the second direction (for example, the horizontal direction). In addition to the wiring in the first direction and the second direction, a part of the wiring in the third direction (for example, an oblique direction) may be included and formed in an annular shape. For example, the shape of the outer periphery of the power ring may be an arbitrary rectangle, or the corner portion of the power ring may be cut obliquely. Further, the power ring may be partially cut in a ring shape.

  For example, if the power supply line is wired only in one direction, the module is arranged in the module placement step so that either the first direction or the second direction matches the power supply wiring direction. Also good. In the case where the power supply lines are wired in two orthogonal directions, the first direction and the second direction match the first power supply wiring direction and the second power supply wiring direction in the module placement step, respectively. You may make it arrange | position a module.

  Based on the information for identifying the position where the module is arranged (module arrangement information), the area where the power ring of the module exists is recognized, and a predetermined part of the power ring is set as the power wiring candidate area. May be. For example, information indicating the area where the power supply ring in the module exists (for example, the relative coordinates of each vertex of the power supply ring with respect to the reference point in the module) is registered as the attribute information of the module. You may make it recognize the area | region where a power ring exists from arrangement | positioning information (the absolute coordinate of the reference point of a module).

  For example, if the power supply line is wired only in the first direction (or the second direction), in the power supply wiring candidate area setting step, the first direction (or the second direction) of the power ring of the module Only the region along the power supply wiring direction including the portion laid along the line is set as the power supply wiring candidate region. In the case where the power supply lines are wired in two orthogonal directions, the first power supply wiring direction or the second power supply direction including the portion laid along the first direction or the second direction of the power supply ring of the module. An area along the power wiring direction may be set as a power wiring candidate area.

  According to the present invention, the area along the power wiring direction including the portion of the power ring of the module that is laid along the direction corresponding to the power wiring direction is set as the power wiring candidate area. Wire the power line along the power wiring direction and connect it to the power ring. Therefore, the power supply line can be wired by being aligned with the position of the power supply ring. Therefore, according to the present invention, it is possible to reduce the correction work after the power supply wiring and to realize an efficient power supply wiring for facilitating the signal wiring in the subsequent process. Further, according to the present invention, since it is not necessary to manually perform power supply wiring at the corner portion of the power supply ring, it is possible to suppress the occurrence of wiring mistakes and to reduce the work man-hours.

(2) A power supply wiring method for a semiconductor integrated circuit device according to the present invention includes:
When the power supply wiring candidate region overlaps with a given power supply ring arrangement region supplied with a potential different from the predetermined potential, the power supply wiring prohibition region sets the power supply wiring candidate region as a power supply wiring prohibition region Including configuration steps,
In the power line wiring step,
The power supply line is not wired in the power supply wiring prohibited area.

  For example, a semiconductor integrated circuit device includes a module including a power supply ring (VDD power supply ring) formed in a second metal layer and supplied with a VDD potential, and a power supply ring (VSS) formed in the second metal layer and supplied with a VSS potential. In the case of including other modules including a power supply ring), a power supply wiring candidate area set for a VDD power supply line of an arbitrary wiring layer for supplying a VDD potential to the VDD power supply ring is an arrangement area of the VSS power supply ring. In the power supply wiring prohibited area setting step, the power supply wiring candidate area may be set as a power supply wiring prohibited area.

  According to the present invention, since no power supply wiring is provided in the power supply wiring prohibited area, it is possible to prevent a wiring short-circuit between different power supplies. Therefore, the man-hours required for the power line correction work can be reduced.

(3) A power supply wiring method for a semiconductor integrated circuit device according to the present invention includes:
In the power supply wiring prohibited area setting step,
Whether to set the power supply wiring candidate area as the power supply wiring prohibited area is determined based on a wiring layer for wiring the power supply line.

  A wiring layer for wiring a power line from a plurality of wiring layers is designated, and whether or not to set a power wiring candidate area as a power wiring prohibited area based on the designated wiring layer in the power wiring prohibited area setting step. It may be determined. The wiring layers for wiring the power supply lines may be specified, for example, by separately specifying the wiring layers for the vertical power supply lines and the horizontal power supply lines. Further, for example, a plurality of wiring layers for the vertical power supply lines and a plurality of wiring layers for the horizontal power supply lines may be designated.

  In the power supply wiring prohibition area setting step, in addition to the wiring layer for wiring the power supply line, for example, the power supply wiring in consideration of the layout rule (when connecting power supply lines of different wiring layers, be sure to connect with the stack VIA). It may be determined whether or not the candidate area is set as the power supply wiring prohibited area. For example, in the power supply wiring candidate region, when a wiring layer of a VSS potential power supply ring exists between a wiring layer of a power supply line of vertical VDD potential and a wiring layer of a power supply line of horizontal VDD potential, When these VDD power supply lines are connected by VIA, VDD and VSS are short-circuited. When such a situation may occur, the power supply wiring candidate area may be set as a power supply wiring prohibited area so that these VDD power supply lines are not generated. Further, for example, in a power supply wiring candidate region, a wiring layer of a VSS potential power supply ring exists below a wiring layer of a power supply line of vertical VDD potential and a wiring layer of a power supply line of VDD in the horizontal direction. Even if these VDD power supply lines are connected by the stack VIA, VDD and VSS do not short-circuit. In such a case, since these VDD power supply lines may be generated, the power supply wiring candidate area may not be set as the power supply wiring prohibited area.

  According to the present invention, even when the wiring layer of the power supply ring and the wiring layer of the power supply line are different, it is possible to prevent the power supply wiring from being provided in a region where a short error or the like may occur during subsequent power supply wiring. . Therefore, the man-hours required for the power line correction work can be reduced.

(4) A power supply wiring method for a semiconductor integrated circuit device according to the present invention includes:
The power line wiring step further includes a power line automatic wiring step for causing a predetermined automatic wiring tool to automatically wire a predetermined power line along the power wiring direction and to connect to the power ring after the power line wiring step. .

  According to the present invention, the power supply wiring at the corner portion of the power supply ring is completed before the power supply wiring is performed by the automatic wiring tool. For this reason, even if other power supply wiring (power supply wiring for each side of the power supply ring) is automatically routed by the automatic wiring tool, it may cause significant correction work of power supply wiring and deterioration of wiring efficiency of signal wiring in the subsequent process. The possibility of efficient power supply wiring can be reduced. Further, according to the present invention, since it is not necessary to manually perform power supply wiring, it is possible to suppress the occurrence of wiring mistakes and reduce the work man-hours.

(5) A power supply wiring method for a semiconductor integrated circuit device according to the present invention includes:
In the automatic power line wiring step,
It is specified that wiring in the power supply wiring prohibited area is prohibited, and the automatic wiring tool automatically performs wiring.

  According to the present invention, since automatic wiring is not performed in the power supply wiring prohibited area, it is possible to prevent a wiring short-circuit between different power supplies. Therefore, the man-hours required for the power line correction work can be reduced.

(6) The present invention
At least one module having a power ring with at least a portion laid along a given first direction and at least another portion laid along a second direction orthogonal to the first direction; A semiconductor integrated circuit device includes a power supply wiring program for a semiconductor integrated circuit device for wiring a power supply line for supplying a predetermined potential to the power supply ring,
Module placement means for placing the module such that at least one of the first direction or the second direction matches a power supply wiring direction in which the power supply line is wired;
An area along the power supply wiring direction including a portion laid along the first direction or the second direction of the power supply ring included in the arranged module is aligned with the power supply wiring direction. Power wiring candidate area setting means for setting the wiring candidate area;
In the power supply wiring candidate region, the computer is caused to function as power supply line wiring means for wiring the power supply line along the power supply wiring direction and connecting the power supply line to the power supply ring.

(7) The present invention
At least one module having a power ring with at least a portion laid along a given first direction and at least another portion laid along a second direction orthogonal to the first direction; A design support system for supporting the design of a semiconductor integrated circuit device including:
Module arrangement in which the modules are arranged so that at least one of the first direction or the second direction matches a power supply wiring direction in which a power supply line for supplying a predetermined potential to the power supply ring is wired Means,
An area along the power supply wiring direction including a portion laid along the first direction or the second direction of the power supply ring included in the arranged module is aligned with the power supply wiring direction. Power wiring candidate area setting means for setting the wiring candidate area;
The power supply wiring candidate region includes power supply line wiring means for wiring the power supply line along the power supply wiring direction and connecting the power supply line to the power supply ring.

(8) The present invention
Designed and manufactured using the power supply wiring method of the semiconductor integrated circuit device described above, the power supply wiring program of the semiconductor integrated circuit device described above, or the design support system of the semiconductor integrated circuit device described above. This is a semiconductor integrated circuit device.

(9) The present invention
A semiconductor integrated circuit device described above;
Data input means to be processed by the semiconductor integrated circuit device;
An electronic device comprising: output means for outputting data processed by the semiconductor integrated circuit device.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Moreover, not all of the configurations described below are essential constituent requirements of the present invention.

1. 1 is a diagram showing a first example of a flowchart of a power supply wiring method for a semiconductor integrated circuit device according to the present embodiment. The flowchart of FIG. 1 has a power ring with at least a portion laid along a given first direction and at least another portion laid along a second direction orthogonal to the first direction. In a semiconductor integrated circuit device including at least one module, it is applied when wiring a power supply line for supplying a predetermined potential to a power supply ring. The power supply ring is arranged outside the core part of the IP module (the part that realizes the function of the IP module) and is annularly formed only by wiring in the first direction (for example, the vertical direction) and the second direction (for example, the horizontal direction). The wiring may be formed, or may be formed in a ring shape including wiring in the third direction (for example, oblique direction) in part in addition to the wiring in the first direction and the second direction. Further, the power ring may be partially cut in a ring shape. Hereinafter, the flowchart of FIG. 1 will be described.

  First, an IP module is placed in the layout area (module placement step (step S12)). Here, the IP module is arranged so that at least one of the first direction (for example, the vertical direction) or the second direction (for example, the horizontal direction) matches the power supply wiring direction in which the power supply lines are wired. For example, if the power supply line is wired only in one direction, the IP module may be arranged so that either the first direction or the second direction matches the power supply wiring direction. If the power supply lines are wired in two orthogonal directions, the IP module is arranged so that the first direction and the second direction coincide with the first power supply wiring direction and the second power supply wiring direction, respectively. You may make it do.

  Next, the position of the power supply ring in the IP module may be recognized (power supply ring recognition step (step S14)). Here, the area where the power supply ring of the IP module exists may be recognized based on the arrangement information of the IP module arranged in step S10. The arrangement information may be information for specifying the position where the IP module is arranged. Also, for example, information indicating the region where the power supply ring in the IP module exists (for example, the relative coordinates of each vertex of the power supply ring with respect to the reference point in the IP module) is registered as the attribute information of the IP module. The area where the power supply ring exists may be recognized from the attribute information and the IP module arrangement information (absolute coordinates of the reference point of the IP module).

  Next, a region (power source wiring candidate region) that is a candidate for a region for wiring the power source line is set (power source wiring candidate region setting step (step S16)). Here, the portion of the power supply ring included in the IP module arranged in step S12 is laid along the first direction (for example, the vertical direction) or the second direction (for example, the horizontal direction) that matches the power supply wiring direction. An area along the direction of the power supply wiring including is set as a power supply wiring candidate area. For example, if the power supply line is wired only in the first direction (or the second direction), the portion of the power ring of the IP module laid along the first direction (or the second direction) Only the region along the direction of the power supply wiring including the line may be set as the power supply wiring candidate region. In the case where the power supply lines are wired in two orthogonal directions, the first power supply wiring direction or the first power supply direction including the portion laid along the first direction or the second direction of the power supply ring of the IP module An area along the direction of power supply wiring 2 may be set as a power supply wiring candidate area.

  Next, an area for prohibiting the wiring of the power supply line (power supply wiring prohibited area) may be set (power supply wiring prohibited area setting step (step S18)). Here, if the power supply wiring candidate area set in step S16 overlaps with the arrangement area of a given power supply ring to which a potential different from the predetermined potential is supplied, the power supply wiring candidate area becomes a power supply wiring prohibited area. You may make it set. For example, a semiconductor integrated circuit device includes an IP module including a power supply ring (VDD power supply ring) that is formed in a second metal layer and supplied with a VDD potential, and a power supply ring that is formed in the second metal layer and supplied with a VSS potential ( In the case of including other IP modules including the VSS power supply ring), if the power supply wiring candidate area for wiring the VDD power supply line of the second metal layer overlaps with the arrangement area of the VSS power supply ring, the power supply wiring candidate The area may be set as a power supply wiring prohibited area. In addition, when the power supply wiring candidate area for wiring the VDD power supply line of an arbitrary wiring layer (first to fourth metal layers, etc.) overlaps with the arrangement area of the VSS power supply ring, the power supply wiring candidate area is You may make it set to a power supply wiring prohibition area | region.

  Next, a power line is wired (power line wiring step (step S20)). Here, in the power supply wiring candidate region set in step S16, the power supply line is wired along the power supply wiring direction and connected to the power supply ring. Further, the power supply line may not be wired in the power supply wiring prohibited area set in step S18.

  Finally, other power supply lines may be automatically wired (power line automatic wiring step (step S22)). Here, a predetermined power supply line may be automatically wired along a power supply wiring direction by a given automatic wiring tool and connected to a power supply ring in the IP module. Alternatively, the automatic wiring tool may automatically perform wiring by designating that wiring in the power supply wiring prohibited area set in step S18 is prohibited. By doing so, since automatic wiring is not performed in the power supply wiring prohibition region, it is possible to prevent a wiring short-circuit between different power supplies. Therefore, the man-hours required for the power line correction work can be reduced.

  2 to 5 are diagrams for explaining an example of the state of the power supply layout after the processing at each step in the flowchart of FIG. 1 is completed. 2 to 5 will be described below with reference to the flowchart of FIG.

  FIG. 2 shows the state of the power supply layout after the processing in step S12 (module placement step) in the flowchart of FIG. 1 is completed.

  The semiconductor integrated circuit device 1 is configured to include the IP modules 10 and 20, and the IP modules 10 and 20 are arranged at predetermined positions by the processing in step S12. The IP modules 10 and 20 include VDD power supply rings 12 and 22 formed in the second metal layer, respectively. The VDD power supply rings 12 and 22 are power supply rings to which the same VDD potential is supplied. The VDD power supply rings 12 and 22 are disposed outside the core portions 14 and 24 of the IP modules 10 and 20, respectively, and serve to supply a VDD potential to the core portions 14 and 16. For example, a part of the VDD power supply rings 12 and 22 formed in an annular shape may be cut off. 3 to 5, the core portions 14 and 24 of the IP modules 10 and 20 and the power supply lines that connect the VDD power supply rings 12 and 22 and the core portions 14 and 24 are omitted and not shown.

  In the VDD power ring 12, rectangular portions 12-1 and 12-3 are laid along the first direction, and rectangular portions 12-2 and 12-4 are laid along the second direction. Further, the VDD power ring 22 has the rectangular portions 22-1 and 22-3 laid along the first direction, and the rectangular portions 22-2 and 22-4 laid along the second direction. Yes.

  In FIG. 2, since the VDD power supply line is wired in the vertical direction and the horizontal direction later and connected to the VDD power supply rings 12 and 22, the first direction and the second direction are respectively the first VDD power supply wiring direction (vertical direction). Direction) and the second VDD power supply wiring direction (lateral direction), the IP modules 10 and 20 are arranged.

  FIG. 3 shows the power layout after the processing in step S14 (power supply ring recognition step), step S16 (power supply wiring candidate area setting step) and step S18 (power supply wiring prohibited area setting step) in the flowchart of FIG. Indicates the state.

  First, in step S14, an area where the VDD power supply rings 12 and 22 of the IP modules 10 and 20 exist is recognized. Next, in step S16, the portions 12-1, 12-3, and 22-2 laid along the first direction of the VDD power supply rings 12 and 22 that coincide with the first VDD power supply wiring direction (vertical direction). Regions 30 and 40 along the first VDD power supply wiring direction (vertical direction) including 1 and 22-3 are set as power supply wiring candidate regions. Furthermore, portions 12-2, 12-4, 22-2, and 22-4 laid along the second direction of the VDD power supply rings 12 and 22 that coincide with the second VDD power supply wiring direction (lateral direction). The regions 50, 60, 70, and 80 along the second VDD power wiring direction (lateral direction) including the above are set as power wiring candidate regions. In FIG. 3, the power supply wiring candidate regions 30, 40, 50, 60, 70, and 80 reach the inner edge of the semiconductor integrated circuit device 1. For example, a VDD power supply ring is provided at the inner peripheral portion of the semiconductor integrated circuit device 1. In the case where it is arranged, it may be an area until reaching the VDD power supply ring.

  Next, in step S18, if the power supply wiring candidate areas 30, 40, 50, 60, 70 and 80 overlap with the arrangement area of a given power supply ring to which a potential different from the VDD potential is supplied, the power supply wiring Set to a prohibited area. In FIG. 3, since there is no power supply ring to which a potential different from the VDD potential is supplied, none of the power supply wiring candidate areas 30, 40, 50, 60, 70, and 80 is set as a power supply wiring prohibited area.

  FIG. 4 shows the state of the power supply layout after the processing in step S20 (power supply line wiring step) in the flowchart of FIG. 1 is completed.

  In step S20, first, in the power supply wiring candidate region 30, the VDD power supply lines 32-1, 32-2, and 32-3 are wired by the second metal layer along the first VDD power supply wiring direction (vertical direction). Connect to power rings 12 and 22. Next, in the power supply wiring candidate region 40, VDD power supply lines 42-1, 42-2, and 42-3 are wired by the second metal layer along the first VDD power supply wiring direction (vertical direction), and the VDD power supply ring 12 is connected. And 22 are connected. Next, in the power supply wiring candidate region 50, the VDD power supply lines 52-1 and 52-2 are wired by the second metal layer along the second VDD power supply wiring direction (lateral direction) and connected to the VDD power supply ring 12. Next, in the power supply wiring candidate region 60, the VDD power supply lines 62-1 and 62-2 are wired with the second metal layer along the second VDD power supply wiring direction (lateral direction) and connected to the VDD power supply ring 12. Next, in the power supply wiring candidate region 70, the VDD power supply lines 72-1 and 72-2 are wired with the second metal layer along the second VDD power supply wiring direction (lateral direction) and connected to the VDD power supply ring 22. Finally, in the power supply wiring candidate region 80, the VDD power supply lines 82-1 and 82-2 are wired with the second metal layer along the second VDD power supply wiring direction (lateral direction) and connected to the VDD power supply ring 22. Note that the order of wiring of the VDD power supply lines in the power supply wiring candidate regions 30, 40, 50, 60, 70 and 80 is not limited to this, and the wirings may be arranged in any order.

  FIG. 5 shows the state of the power supply layout after the processing in step S22 (power supply line automatic wiring step) in the flowchart of FIG. 1 is completed.

  In step S22, first, the VDD power supply lines 34-1 to 34-3, 36-1 to 36-3, and the first VDD power supply wiring direction (longitudinal direction) are provided using a given automatic wiring tool. 38-1 to 38-3 are automatically wired and connected to the VDD power supply ring 12. For example, the inside of the VDD power supply rings 12 and 24 is set as a wiring prohibition region, and three VDD power supply lines having a predetermined width and length are connected to the VDD power supply lines 32-1 to 32-3 and 42-1 to 42-. 3 is specified to be automatically routed by the second metal layer at equal intervals, and the VDD power supply lines 34-1 to 34-3, 36-1 to 36-3 and 38- 1 to 38-3 are created.

  Next, the VDD power supply lines 54-1 and 54-2 and 56-1 and 56-2 are automatically wired along the second VDD power supply wiring direction (lateral direction) to be connected to the VDD power supply ring 12. For example, the inside of the VDD ring 12 is set as a wiring prohibition region, and two VDD power supply lines having a predetermined width and length are connected between the VDD power supply lines 52-1, 52-2 and 62-1, 62-2. The VDD power lines 54-1 and 54-2 and 56-1 and 56-2 are created by designating the second metal layer to be automatically wired at equal intervals and causing the automatic wiring tool to perform wiring.

  Next, the VDD power supply lines 74-1, 74-2 and 76-1, 76-2 are automatically wired along the second VDD power supply wiring direction (lateral direction) and connected to the VDD power supply ring 22. For example, the inside of the VDD ring 22 is set as a wiring prohibition region, and two VDD power supply lines having a predetermined width and length are connected between the VDD power supply lines 72-1, 72-2 and 82-1, 82-2. The VDD power lines 74-1 and 74-2 and 76-1 and 76-2 are created by designating the second metal layer to be automatically wired at equal intervals and causing the automatic wiring tool to perform wiring.

  VDD power supply lines 34-1 to 34-3, 36-1 to 36-3, 38-1 to 38-3, 54-1, 54-2, 56-1, 56-2, 74-1, 74 -2, 76-1, and 76-2 are not limited to this order, and may be wired in an arbitrary order.

  6 to 10 are diagrams for explaining another example of the state of the power supply layout after the process at each step in the flowchart of FIG. 1 is completed. Hereinafter, FIGS. 6 to 10 will be described with reference to the flowchart of FIG.

  FIG. 6 shows the state of the power supply layout after the processing in step S12 (module placement step) in the flowchart of FIG. 1 is completed.

  The semiconductor integrated circuit device 100 includes IP modules 110 and 120, and the IP modules 110 and 120 are arranged at predetermined positions by the processing in step S12. The IP module 110 includes a VDD power ring 112 formed in the second metal layer. The VDD power ring 112 is a power ring to which a VDD potential is supplied. The VDD power ring 112 is disposed outside the core portion 114 of the IP module 110 and functions to supply a VDD potential to the core portion 114. The IP module 120 also includes a VSS power ring 122 formed in the second metal layer. The VSS power supply ring 122 is a power supply ring to which a VSS potential is supplied. The VSS power supply ring 122 is disposed outside the core portion 124 of the IP module 120 and functions to supply a VSS potential to the core portion 124. For example, a part of the VDD power ring 112 and the VSS ring 122 formed in an annular shape may be cut off. 7 to 10, the core portions 114 and 124 of the IP modules 110 and 120 and the VDD power supply ring 112, the power supply lines connecting the VSS power supply ring 122 and the core portions 114 and 124, respectively, are omitted. Not.

  In the VDD power ring 112, rectangular portions 112-1 and 112-3 are laid along the first direction, and rectangular portions 112-2 and 112-4 are laid along the second direction. In addition, the VSS power ring 122 has the rectangular parts 122-1 and 122-3 laid along the first direction, and the rectangular parts 122-2 and 122-4 laid along the second direction. Yes.

  In FIG. 6, since the VDD power supply line is wired in the vertical direction and the horizontal direction later and connected to the VDD power supply ring 112, the first direction and the second direction are respectively the first VDD power supply wiring direction (vertical direction). The IP modules 110 and 120 are arranged so as to coincide with the second VDD power supply wiring direction (lateral direction).

  FIG. 7 shows the state of the power supply layout after the processing in step S14 (power supply ring recognition step) and step S16 (power supply wiring candidate area setting step) in the flowchart of FIG.

  First, in step S14, a region where the VDD power ring 112 of the IP module 110 exists and a region where the VSS power ring 122 of the IP module 120 exists are recognized. Next, in step S16, the VDD power ring 112 includes first portions 112-1 and 112-3 that are laid along a first direction that coincides with the first VDD power supply wiring direction (vertical direction). Regions 130 and 140 along the VDD power supply wiring direction (vertical direction) are set as power supply wiring candidate regions. Further, the second VDD power supply wiring direction including the portions 112-2 and 112-4 laid along the second direction of the VDD power supply ring 112 that coincides with the second VDD power supply wiring direction (lateral direction). Regions 150 and 160 along the (lateral direction) are set as power source wiring candidate regions. In FIG. 7, the power supply wiring candidate regions 130, 140, 150, and 160 reach the inner edge of the semiconductor integrated circuit device 100. For example, a VDD power supply ring is disposed in the peripheral portion inside the semiconductor integrated circuit device 100. In such a case, the region up to the VDD power supply ring may be used.

  FIG. 8 shows the state of the power supply layout after the process in step S18 (power supply wiring prohibited area setting step) in the flowchart of FIG. 1 is completed.

  In step S18, when the power supply wiring candidate areas 130, 140, 150, and 160 overlap with the arrangement area of the VSS power supply ring 122 to which the VSS potential different from the VDD potential is supplied, the power supply wiring candidate areas 130, 140, 150, and 160 are set. In FIG. 8, the power supply wiring candidate area 140 in FIG. 7 overlaps with the arrangement area (portion 122-3) of the VSS power supply ring 122, so the power supply wiring candidate area 140 is set as the power supply wiring prohibition area 142.

  FIG. 9 shows the state of the power supply layout after the processing in step S20 (power supply line wiring step) in the flowchart of FIG. 1 is completed.

  In step S20, first, in the power supply wiring candidate region 130, the VDD power supply lines 132-1 and 132-2 are wired with the second metal layer along the first VDD power supply wiring direction (vertical direction), and the VDD power supply ring 112 is connected. Connect. Next, in the power supply wiring candidate region 150, the VDD power supply lines 152-1 and 152-2 are wired with the second metal layer along the second VDD power supply wiring direction (lateral direction) and connected to the VDD power supply ring 112. Next, in the power supply wiring candidate region 160, the VDD power supply lines 162-1 and 162-2 are wired with the second metal layer along the second VDD power supply wiring direction (lateral direction) and connected to the VDD power supply ring 112. Power supply wiring is not performed in the power supply wiring prohibition area 142. Note that the order of wiring of the VDD power supply lines in the power supply wiring candidate regions 130, 150, and 160 is not limited to this, and wiring may be performed in an arbitrary order.

  FIG. 10 shows the state of the power supply layout after the processing in step S22 (power supply line automatic wiring step) in the flowchart of FIG. 1 is completed.

  In step S22, first, using a given automatic wiring tool, VDD power lines 134-1, 134-2, 136-1 and 136-2 along the first VDD power wiring direction (vertical direction) and 138-1 and 138-2 are automatically wired and connected to the VDD power supply ring 112. For example, the inner side of the VDD ring 112 is set as a wiring prohibition region, and three VDD power supply lines having a predetermined width and length are connected to the right side of the VDD power supply lines 132-1 and 132-2 at a predetermined interval. The VDD power supply lines 134-1, 134-2, 136-1, 136-2 and 138-1, 138-2 are created by designating the automatic wiring in the layer and causing the automatic wiring tool to perform wiring.

  Next, the VDD power supply lines 154-1, 154-2 and 156-1 and 156-2 are automatically wired along the second VDD power supply wiring direction (lateral direction) to be connected to the VDD power supply ring 112. For example, the inside of the VDD ring 112 is set as a wiring prohibition region, and two VDD power supply lines having a predetermined width and length are connected between the VDD power supply lines 152-1 and 152-2 and 162-1 and 162-2. VDD power supply lines 154-1, 154-2 and 156-1, 156-2 are created by designating automatic wiring with the second metal layer at equal intervals and wiring with the automatic wiring tool.

  Next, the VDD power supply lines 174 and 176 are automatically wired along the second VDD power supply wiring direction (lateral direction) to be connected to the VDD power supply line 132-2. The VDD power supply lines 174 and 176 are used for supplying a VDD potential to other modules (not shown), for example.

  Here, it is possible to prevent the VDD power supply line from being routed in the power supply wiring prohibition region 142 by designating the wiring in the power supply wiring prohibition region 142 to be prohibited and causing the automatic wiring tool to perform automatic wiring.

  In addition, wiring of VDD power supply lines 134-1, 134-2, 136-1, 136-2, 138-1, 138-2, 154-1, 154-2, 156-1, 156-2, 174, 176 The order is not limited to this, and wiring may be performed in an arbitrary order.

  FIG. 11 is a diagram showing a second example of a flowchart of the power supply wiring method for the semiconductor integrated circuit device according to the present embodiment. The flow chart of FIG. 11 has a power ring with at least a portion laid along a given first direction and at least another portion laid along a second direction orthogonal to the first direction. In a semiconductor integrated circuit device including at least one module and having a plurality of wiring layers, this is applied when wiring a power supply line for supplying a predetermined potential to a power supply ring. Hereinafter, the flowchart of FIG. 11 will be described.

  First, a wiring layer for wiring the power supply line may be designated (power supply line wiring layer designation step (step S30)). For example, in a semiconductor integrated circuit device having four or more wiring layers, the vertical power line is wired by the second metal layer or the fourth metal layer, and the horizontal power line is the first metal layer or the third metal layer. As a wiring layer for wiring the power supply line in the horizontal direction, specify either one or both of the second metal layer and the fourth metal layer as the wiring layer for wiring the power supply line in the vertical direction. Either one or both of the first metal layer and the third metal layer may be designated.

  Next, an IP module is arranged in the layout area (module arrangement step (step S32)). The process of step S32 is the same as the process of step S12 in the flowchart of FIG.

  Next, the position of the power supply ring in the IP module is recognized (power supply ring recognition step (step S34)). The process of step S34 is the same as the process of step S14 in the flowchart of FIG.

  Next, a region (power source wiring candidate region) that is a candidate for a region for wiring the power source line is set (power source wiring candidate region setting step (step S36)). The process of step S36 is the same as the process of step S16 in the flowchart of FIG.

  Next, an area for prohibiting the wiring of the power supply line (power supply wiring prohibited area) may be set (power supply wiring prohibited area setting step (step S38)). Here, if the power supply wiring candidate region set in step S36 overlaps with a given power supply ring arrangement region to which a potential different from the predetermined potential is supplied, a wiring layer for wiring the power supply line (for example, step Based on the wiring layer designated in S30), it may be determined whether or not the power supply wiring candidate area is set as the power supply wiring prohibited area. In addition to the information on the wiring layer for wiring the power supply line, the power supply wiring candidate area is set as the power supply wiring prohibited area in consideration of the layout rule (when connecting power lines of different wiring layers, be sure to connect them with the stack VIA). You may make it determine whether it sets.

  For example, the semiconductor integrated circuit device includes an IP module including a VDD power ring formed on the second metal layer and another IP module including a VSS power ring formed on the second metal layer, and the power lines of different wiring layers are In the case of always connecting with the stack VIA, the fourth metal layer and the first metal layer are designated as wiring layers for wiring the vertical and horizontal VDD power supply lines connected to the VDD power supply ring in step S10, respectively. In this case, if the power supply wiring candidate area set for the vertical VDD power supply line overlaps with the arrangement area of the VSS power supply ring, the power supply wiring candidate area may be set as the power supply wiring prohibited area. Good (the second metal between the VDD power line of the fourth metal layer in the vertical direction and the VDD power line of the first metal layer in the horizontal direction) The so VSS supply ring is present, when a VDD power supply line of the longitudinal fourth first metal layer of the VDD power supply line and the transverse direction of the metal layer connecting the stack VIA VDD and VSS are short-circuited).

  Further, for example, the semiconductor integrated circuit device includes an IP module including a VDD power supply ring formed in the second metal layer and another IP module including a VSS power supply ring formed in the second metal layer, and the power supplies of different wiring layers When the lines are always connected by the stack VIA, the fourth metal layer and the third metal layer are respectively used as wiring layers for wiring the vertical and horizontal VDD power supply lines connected to the VDD power supply ring in step S30. If specified, if the power supply wiring candidate area set for the vertical VDD power supply line overlaps with the arrangement area of the VSS power supply ring, the power supply wiring candidate area may not be set as the power supply wiring prohibition area. Good (the second metal under the VDD power line of the fourth metal layer in the vertical direction and the VDD power line of the third metal layer in the horizontal direction) The so VSS supply ring is present, the longitudinal direction of the 4 VDD and VSS even when the VDD power supply line of the third metal layer of the VDD power supply line and the transverse direction of the metal layer is connected with the stack VIA is not shorted).

  Next, a power line is wired (power line wiring step (step S40)). The process of step S40 is the same as the process of step S20 in the flowchart of FIG.

  Finally, other power supply lines may be automatically wired (power line automatic wiring step (step S42)). The process of step S42 is the same as the process of step S22 in the flowchart of FIG.

  In the flowchart of FIG. 11, the power line wiring layer designation step (step S30) is performed before the IP module placement step (step S32). What is necessary is just to perform at arbitrary timings before step S38).

  12 to 15 are diagrams for explaining an example of the state of the power supply layout after the process in each step in the flowchart of FIG. 11 is completed. Hereinafter, FIGS. 12 to 15 will be described with reference to the flowchart of FIG.

  FIG. 12 shows the state of the power supply layout after the processing in step S30 (power supply line wiring layer selection step) and step S32 (module placement step) in the flowchart of FIG. 11 is completed.

  The semiconductor integrated circuit device 200 has, for example, four wiring layers (first metal layer to fourth metal layer in order from the lower layer), and includes IP modules 210 and 220. Further, it is assumed that there is a rule that power lines of different wiring layers are always connected by the stack VIA.

  First, by the process in step S30, for example, the fourth metal layer is designated as a wiring layer for wiring the power supply line in the first VDD power supply wiring direction (vertical direction), and the second VDD power supply wiring direction (horizontal direction) The third metal layer is designated as a wiring layer for wiring the power line in the direction.

  Next, the IP modules 210 and 220 are arranged at predetermined positions by the processing in step S32. The IP module 210 includes a VDD power ring 212 formed in the second metal layer. The VDD power ring 212 is a power ring to which a VDD potential is supplied. The VDD power ring 212 is disposed outside the core portion 214 of the IP module 210 and functions to supply a VDD potential to the core portion 214. In addition, the IP module 220 includes a VSS power ring 222 formed in the second metal layer. The VSS power supply ring 222 is a power supply ring to which a VSS potential is supplied. The VSS power supply ring 222 is disposed outside the core portion 224 of the IP module 220 and functions to supply a VSS potential to the core portion 224. For example, a part of the VDD power ring 212 and the VSS ring 222 formed in an annular shape may be cut off. 13 to 15, the core portions 214 and 224 of the IP modules 210 and 220 and the VDD power supply ring 212 and the power supply lines connecting the VSS power supply ring 222 and the core portions 214 and 224 are omitted. Not.

  In the VDD power supply ring 212, the rectangular portions 212-1 and 212-3 are laid along the first direction, and the rectangular portions 212-2 and 212-4 are laid along the second direction. In addition, the VSS power ring 222 has the rectangular portions 222-1 and 222-3 laid along the first direction, and the rectangular portions 222-2 and 222-4 laid along the second direction. Yes.

  In FIG. 12, since the VDD power supply line is wired in the vertical direction and the horizontal direction later and connected to the VDD power supply ring 212, the first direction and the second direction are respectively the first VDD power supply wiring direction (vertical direction). The IP modules 210 and 220 are arranged so as to coincide with the second VDD power supply wiring direction (lateral direction).

  FIG. 13 shows the power layout after the processing in step S34 (power supply ring recognition step), step S36 (power supply wiring candidate area setting step) and step S38 (power supply wiring prohibited area setting step) in the flowchart of FIG. Indicates the state.

  First, in step S34, a region where the VDD power ring 212 of the IP module 210 exists and a region where the VSS power ring 222 of the IP module 220 exists are recognized. Next, in step S36, the VDD power ring 212 includes first portions 212-1, 212-3 laid along a first direction that coincides with the first VDD power wiring direction (vertical direction). The regions 230 and 240 along the VDD power supply wiring direction (vertical direction) are set as power supply wiring candidate regions. Furthermore, the second VDD power supply wiring direction including the portions 212-2 and 212-4 laid along the second direction of the VDD power supply ring 212 that coincides with the second VDD power supply wiring direction (lateral direction). Regions 250 and 260 along the (lateral direction) are set as power source wiring candidate regions. In FIG. 13, the power supply wiring candidate regions 230, 240, 250, and 260 reach the inner edge of the semiconductor integrated circuit device 200. For example, a VDD power supply ring is disposed on the inner periphery of the semiconductor integrated circuit device 200. In such a case, the region up to the VDD power supply ring may be used.

  Next, in step S38, when the power supply wiring candidate areas 230, 240, 250, and 260 overlap with the arrangement area of the VSS power supply ring 222 to which the VSS potential different from the VDD potential is supplied, the wiring designated in step S30. Based on the layer, it is determined whether or not to set the power supply wiring candidate areas 230, 240, 250, and 260 as power supply wiring prohibited areas. In step S30, the fourth metal layer is designated as the wiring layer for wiring the power line in the first VDD power wiring direction (vertical direction), and the power line in the second VDD power wiring direction (lateral direction) is wired. A third metal layer is designated as a wiring layer for this purpose. Therefore, when power supply wiring of the VDD power supply line is performed in the source wiring candidate region 240 in step S40, the VDD power supply line and the second VDD power supply of the fourth metal layer in the first VDD power supply wiring direction (vertical direction). The VSS power ring 222 (222-3 portion) of the second metal layer is present below the VDD power line of the third metal layer in the wiring direction (lateral direction). Therefore, in the region where the wiring candidate region 240 and the VSS power supply ring 222 are arranged (portion 222-3), the VDD power supply line in the first VDD power supply wiring direction (vertical direction) and the second VDD power supply wiring direction Even if the VDD power supply line in the (horizontal direction) is connected by VIA, VDD and VSS do not short-circuit. Therefore, the power supply wiring candidate area 240 may not be set as the power supply wiring prohibited area.

  FIG. 14 shows the state of the power supply layout after the processing in step S40 (power supply line wiring step) in the flowchart of FIG. 11 is completed.

  In step S40, first, in the power supply wiring candidate region 230, the VDD power supply line 232 is wired with the fourth metal layer along the first VDD power supply wiring direction (vertical direction), and the VDD power supply ring 212 and the stack VIAs 232-1 and 232 are connected. -2 to connect. Next, in the power supply wiring candidate region 240, the VDD power supply line 242 is wired with the fourth metal layer along the first VDD power supply wiring direction (vertical direction), and the VDD power supply ring 212 and the stack VIAs 242-1 and 242-2 are used. Connect. Next, in the power supply wiring candidate region 250, the VDD power supply line 252 is wired with the third metal layer along the second VDD power supply wiring direction (lateral direction), and the VDD power supply ring 212 and the stack VIAs 232-1 and 242-1 are used. Connect. Next, in the power supply wiring candidate region 260, the VDD power supply line 262 is wired with the third metal layer along the second VDD power supply wiring direction (lateral direction), and the VDD power supply ring 212 and the stacks VIA 232-2 and 242-2 are used. Connect. Note that the order of wiring of the VDD power supply lines in the power supply wiring candidate regions 230, 240, 250, and 260 is not limited to this, and may be wired in an arbitrary order. Similarly, the arrangement order of the stack VIAs 232-1, 232-2, 242-1, and 242-2 is not limited to this, and the stack VIAs 232-1, 232-2, and 242-1 and 242-2 may be arranged in any order.

  FIG. 15 shows the state of the power supply layout after the processing in step S42 (power supply line automatic wiring step) in the flowchart of FIG. 1 is completed.

  In step S42, first, the VDD power supply lines 234-1, 234-2, and 236-1 of the fourth metal layer along the first VDD power supply wiring direction (vertical direction) using a given automatic wiring tool. 236-2 and 238-1 and 238-2 are automatically wired to the VDD power ring 212 of the second metal layer and the stack VIA 234-3, 234-4, 236-3, 236-4 and 238-3, 238- 4 to connect. For example, the inside of the VDD power supply ring 212 is set as a wiring prohibition region, and three VDD power supply lines having a predetermined width and length are automatically wired with a fourth metal layer at equal intervals between the VDD power supply lines 232 and 242. The power supply lines 234-1, 234-2, 236-1, 236-2, 238-1, 238-2 and the stack VIA 234-3, 234-4 236-3, 236-4, 238-3, 238-4 are created.

  Next, the VDD power supply lines 254-1, 256-1 and 254-2, 256-2 of the third metal layer are automatically routed along the second VDD power supply wiring direction (lateral direction), and the fourth metal layer The VDD power supply lines 232 and 242 are connected to the stacks VIA 254-3, 256-3 and 254-4, 256-4. For example, the inside of the VDD power supply ring 212 is set as a wiring prohibition region, and two VDD power supply lines having a predetermined width and length are automatically wired with a third metal layer at equal intervals between the VDD power supply lines 252 and 262. The VDD power lines 254-1, 254-2, 256-1, 256-2 and the stack VIAs 254-3, 256-3, 254-4, 256-4 are specified by wiring to the automatic wiring tool. Is created.

  Next, the VDD power supply lines 274-1, 276-1 and 274-2, 276-2 of the third metal layer are automatically wired along the second VDD power supply wiring direction (lateral direction), and the fourth metal layer The VDD power supply lines 232 and 242 are connected to the stacks VIA 274-3, 276-3 and 274-4, 276-4. The VDD power lines 274-1, 276-1 and 274-2 and 276-2 are used for supplying a VDD potential to other modules (not shown), for example.

  Note that the order of wiring of the VDD power supply lines 254-1, 254-2, 256-1, 256-2, 274-1, 274-2, 276-1, and 276-2 is not limited to this, and may be any order. May be wired. Similarly, the arrangement order of the stacks VIA 254-3, 254-4, 256-3, 256-4, 274-3, 274-4, 276-3, 276-4 is not limited to this, and is arranged in an arbitrary order. You can do it.

  16 to 18 are diagrams for explaining another example of the state of the power supply layout after the process in each step in the flowchart of FIG. 11 is completed. Hereinafter, FIGS. 16 to 18 will be described with reference to the flowchart of FIG.

  FIG. 16 shows step S30 (power supply line wiring layer selection step), step S32 (module placement step), step S34 (power supply ring recognition step), step S36 (power supply wiring candidate region setting step) and step S38 in the flowchart of FIG. The state of the power supply layout after the process in (power supply wiring prohibited area setting step) is completed is shown.

  The semiconductor integrated circuit device 200 is the same as the semiconductor integrated circuit 200 described with reference to FIG. 12, and it is assumed that there is a rule that power lines of different wiring layers are always connected by the stack VIA.

  First, by the process in step S30, for example, the fourth metal layer is designated as a wiring layer for wiring the power supply line in the first VDD power supply wiring direction (vertical direction), and the second VDD power supply wiring direction (horizontal direction) The first metal layer is designated as a wiring layer for wiring the power line in the direction.

  Next, the processing in steps S32 to S36 is the same as the processing in steps S32 to S36 described in FIG. 12 and FIG.

  Next, in step S38, when the power supply wiring candidate areas 230, 240, 250, and 260 overlap with the arrangement area of the VSS power supply ring 222 to which the VSS potential different from the VDD potential is supplied, the wiring designated in step S30. Based on the layer, it is determined whether or not to set the power supply wiring candidate areas 230, 240, 250, and 260 as power supply wiring prohibited areas. In step S30, the fourth metal layer is designated as the wiring layer for wiring the power line in the first VDD power wiring direction (vertical direction), and the power line in the second VDD power wiring direction (lateral direction) is wired. The first metal layer is designated as a wiring layer for this purpose. Therefore, when power supply wiring of the VDD power supply line is performed in the source wiring candidate region 240 in step S40, the VDD power supply line and the second VDD power supply of the fourth metal layer in the first VDD power supply wiring direction (vertical direction). The VSS power ring 222 (222-3 portion) of the second metal layer exists between the VDD power lines of the first metal layer in the wiring direction (lateral direction). Therefore, in the region where the wiring candidate region 240 and the VSS power supply ring 222 are arranged (portion 222-3), the VDD power supply line in the first VDD power supply wiring direction (vertical direction) and the second VDD power supply wiring direction When the VDD power supply line in the (horizontal direction) is connected by the stack VIA, VDD and VSS are short-circuited. Therefore, the power supply wiring candidate area 240 is set to the power supply wiring prohibited area 242.

  FIG. 17 shows the state of the power supply layout after the processing in step S40 (power supply line wiring step) in the flowchart of FIG. 11 is completed.

  In step S40, first, in the power supply wiring candidate region 230, the VDD power supply line 232 is wired with the fourth metal layer along the first VDD power supply wiring direction (vertical direction), and the VDD power supply ring 212 and the stack VIAs 232-1 and 232 are connected. -2 to connect. Next, in the power supply wiring candidate region 250, the VDD power supply line 252 is wired with the first metal layer along the second VDD power supply wiring direction (lateral direction), and the VDD power supply ring 212 and the stacks VIA 232-1 and 242-1 are connected. Connect. Next, in the power supply wiring candidate region 260, the VDD power supply line 262 is wired with the first metal layer along the second VDD power supply wiring direction (lateral direction), and the VDD power supply ring 212 and the stack VIAs 232-2 and 242-2 are connected. Connect. Power supply wiring is not performed in the power supply wiring prohibition region 242. Note that the order of wiring of the VDD power supply lines in the power supply wiring candidate regions 230, 250, and 260 is not limited to this, and wiring may be performed in an arbitrary order. Similarly, the arrangement order of the stack VIAs 232-1, 232-2, 242-1, and 242-2 is not limited to this, and the stack VIAs 232-1, 232-2, and 242-1 and 242-2 may be arranged in any order.

  FIG. 18 shows the state of the power supply layout after the processing in step S42 (power supply line automatic wiring step) in the flowchart of FIG.

  In step S42, first, the VDD power supply lines 234-1, 234-2, and 236-1 of the fourth metal layer along the first VDD power supply wiring direction (vertical direction) using a given automatic wiring tool. 236-2 and 238-1 and 238-2 are automatically wired to the VDD power ring 212 of the second metal layer and the stack VIA 234-3, 234-4, 236-3, 236-4 and 238-3, 238- 4 to connect.

  Next, the VDD power supply lines 254-1, 256-1 and 254-2, 256-2 of the first metal layer are automatically wired along the second VDD power supply wiring direction (lateral direction), and the fourth metal layer The VDD power supply lines 232 and 242 are connected to the stacks VIA 254-3, 256-3 and 254-4, 256-4.

  Next, VDD power supply lines 274-1 and 276-1 of the first metal layer are automatically wired along the second VDD power supply wiring direction (lateral direction), and the VDD power supply line 232 of the fourth metal layer and the stack VIA 274-. 3, 276-3. The VDD power supply lines 274-1 and 276-1 are used for supplying a VDD potential to other modules (not shown), for example.

  Here, it is possible to prevent the VDD power supply line from being routed in the power supply wiring prohibited area 244 by designating that the wiring in the power supply wiring prohibited area 244 is prohibited and causing the automatic wiring tool to perform automatic wiring.

  Note that the order of wiring of the VDD power supply lines 254-1, 254-2, 256-1, 256-2, 274-1, and 276-1 is not limited thereto, and wiring may be performed in an arbitrary order. Similarly, the arrangement order of the stacks VIA 254-3, 254-4, 256-3, 256-4, 274-3, 276-3 is not limited to this, and may be arranged in any order.

  According to the power supply wiring method of the semiconductor integrated circuit device of this embodiment, the power supply line can be wired by aligning with the position of the power supply ring of the IP module. Therefore, according to the power supply wiring method for the semiconductor integrated circuit device of the present embodiment, it is possible to reduce the correction work after the power supply wiring and to realize an efficient power supply wiring for facilitating the signal wiring in the subsequent process. it can.

  Further, according to the power supply wiring method of the semiconductor integrated circuit device of the present embodiment, it is not necessary to manually perform power supply wiring at the corner portion of the power supply ring, so that the occurrence of wiring mistakes can be suppressed and the number of work steps can be reduced. .

  Further, according to the power supply wiring method of the semiconductor integrated circuit device of this embodiment, the power supply wiring at the corner portion of the power supply ring is completed before the power supply wiring is performed by the automatic wiring tool. For this reason, even if other power supply wiring (power supply wiring for each side of the power supply ring) is automatically routed by the automatic wiring tool, it may cause significant correction work of power supply wiring and deterioration of wiring efficiency of signal wiring in the subsequent process. The possibility of efficient power supply wiring can be reduced.

  In addition, according to the power supply wiring method of the semiconductor integrated circuit device of the present embodiment, since power supply wiring is not performed in the power supply wiring prohibited area, it is possible to prevent a wiring short-circuit between different power supplies. Therefore, the man-hours required for the power line correction work can be reduced.

  In addition, according to the power supply wiring method of the semiconductor integrated circuit device of this embodiment, even if the power supply ring wiring layer and the power supply line wiring layer are different, a region where a short error or the like may occur during subsequent power supply wiring It is possible to prevent the power supply wiring from being provided. Therefore, the man-hours required for the power line correction work can be reduced.

2. Semiconductor Integrated Circuit Device Design Support System, Semiconductor Integrated Circuit Device Power Supply Wiring Program Next, the configuration of the semiconductor integrated circuit device design support system of this embodiment will be described with reference to FIG. The semiconductor integrated circuit device design support system 400 of this embodiment may have a configuration in which some of the components (each unit) are omitted.

  The design support system 400 for a semiconductor integrated circuit device according to the present embodiment is at least partially laid along a given first direction, and at least part of the other is in a second direction orthogonal to the first direction. 1 is a design support system for supporting the design of a semiconductor integrated circuit device including at least one module having a power supply ring laid along the line.

  The operation unit 440 is for inputting user operations and the like as data, and the function can be realized by hardware such as a keyboard and a mouse.

  The storage unit 450 is a work area such as the processing unit 420 and the communication unit 490, and the function thereof can be realized by hardware such as a RAM.

  The storage unit 450 includes a library information storage unit 452.

  The library information storage unit 452 stores library information (logic circuit information, layout information, connection information) obtained from design data, information on the generated netlist, and the like.

  An information storage medium 460 (a computer-readable medium) stores programs, data, and the like, and functions as an optical disk (CD, DVD, etc.), a magneto-optical disk (MO), a magnetic disk, a hard disk, and a magnetic disk. It can be realized by hardware such as a tape or memory (ROM).

  In addition, the information storage medium 460 stores a program for causing the computer to function as each unit of the present embodiment and auxiliary data (additional data).

  The processing unit 420 performs various processes of the present embodiment based on a program (power supply wiring program) stored in the information storage medium 460, data read from the information storage medium 460, and the like. That is, the information storage medium 460 stores a program for causing a computer to function as each unit of the present embodiment (a program for causing a computer to execute the process of each unit).

  The display unit 470 outputs an image generated according to the present embodiment, and functions thereof are a CRT display, an LCD (liquid crystal display), an OELD (organic EL display), a PDP (plasma display panel), and a touch panel display. It can be realized by hardware such as.

  The sound output unit 480 outputs the sound generated by the present embodiment, and its function can be realized by hardware such as a speaker or headphones.

  The communication unit 490 performs various controls for communicating with the outside (for example, a server device or another terminal), and functions thereof are hardware such as various processors or communication ASICs, It can be realized by a program.

  The processing unit 420 (processor) performs various types of processing based on operation data and programs from the operation unit 440. The processing unit 420 performs various processes using the storage unit 450 as a work area. The function of the processing unit 420 can be realized by hardware such as various processors (CPU, DSP, etc.), ASIC (gate array, etc.), application program, and OS (for example, general-purpose OS).

  The processing unit 420 includes module placement means 422, power supply wiring candidate area setting means 424, and power supply line wiring means 428. The processing unit 420 may further include a power supply wiring prohibited area setting unit 426 and a power supply line automatic wiring unit 430.

  The module arrangement means 422 arranges the modules so that at least one of the first direction and the second direction coincides with a power supply wiring direction in which a power supply line for supplying a predetermined potential to the power supply ring is wired. Process.

  The power supply wiring candidate area setting means 424 is provided along the power supply wiring direction including a portion laid along the first direction or the second direction of the power supply ring included in the arranged module, which coincides with the power supply wiring direction. A process of setting the area as a power supply wiring candidate area is performed.

  When the power supply wiring candidate area overlaps with the arrangement area of a given power supply ring to which a potential different from a predetermined potential is supplied, the power supply wiring prohibited area setting unit 426 sets the power supply wiring prohibited area as the power supply wiring prohibited area. Perform processing to set.

  Further, the power supply wiring prohibited area setting unit 426 may determine whether or not to set the power supply wiring candidate area as the power supply wiring prohibited area based on the wiring layer for wiring the power supply line.

  The power supply line wiring means 428 performs processing for wiring the power supply line along the power supply wiring direction and connecting it to the power supply ring in the power supply wiring candidate region.

  Further, the power supply line wiring means 428 may not perform power supply line wiring in the power supply wiring prohibited area.

  The power line automatic wiring means 430 performs a process of automatically wiring a predetermined power line along the power wiring direction with a given automatic wiring tool and connecting it to the power ring.

  Further, the power line automatic wiring means 430 may designate that the wiring in the power wiring prohibition area is prohibited and cause the automatic wiring tool to automatically perform wiring.

  According to the design support system or the power supply wiring program of the semiconductor integrated circuit device of this embodiment, the power supply line can be wired by aligning with the position of the power supply ring of each module. Therefore, according to the present embodiment, it is possible to reduce the correction work after the power supply wiring and to realize an efficient power supply wiring for facilitating the signal wiring in the subsequent process. Further, according to the present embodiment, since it is not necessary to manually perform the power supply wiring at the corner portion of the power supply ring of each module, it is possible to suppress the occurrence of wiring mistakes and reduce the work man-hours.

  Note that a program (power supply wiring program) for causing a computer to function as each unit of the present embodiment is transmitted from an information storage medium of a host device (server) to an information storage medium 460 (storage unit 450) via a network and communication unit 490. ). Use of the information storage medium of such a host device (server) can also be included in the scope of the present invention.

3. Semiconductor Integrated Circuit Device FIG. 20 is an example of a block diagram of the semiconductor integrated circuit device of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, a ROM 710, a RAM 720, an MMU 730, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DMA controller 570, an interrupt controller 580, a communication control circuit 590, and a bus. Controller 600, A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 660, prescaler 670, clock stop control circuit 740, and general purpose for connecting them A bus 680, a dedicated bus 750, etc., various pins 690, etc. are included.

  For example, the CPU 510, the RAM 720, the A / D converter 610, the D / A converter 620, and the like are configured as an IP module having a power supply ring, and the microcomputer 700 includes the power supply wiring method and the power supply wiring according to the present embodiment. A semiconductor integrated circuit device designed and manufactured using a program or a design support system.

4). Electronic Device FIG. 21 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (semiconductor integrated circuit device) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 22A illustrates an example of an external view of a mobile phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 22B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 22C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the semiconductor integrated circuit device of this embodiment into the electronic devices in FIGS. 22A to 22C, an electronic device with high cost performance can be provided in a short period of time.

  Note that electronic devices that can use this embodiment include, in addition to those shown in FIGS. 22A to 22C, portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, projectors, Various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, in FIGS. 2 to 10 and FIGS. 12 to 18, the example in which the VDD power supply line is connected to the VDD power supply ring has been described, but the present invention is not limited thereto. For example, the present invention can be applied to a case where a VSS power supply line is connected to the VSS power supply ring or a case where a VDD power supply line and a VSS power supply line are connected to the VDD power supply ring and the VSS power supply ring. The present invention can be similarly applied to a semiconductor integrated circuit device including an IP module including a VDD power supply ring and a VSS power supply ring.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

The figure which shows the 1st example of the flowchart of the power supply wiring method of this Embodiment. The figure which shows the example of the power supply layout by the 1st power supply wiring method. The figure which shows the example of the power supply layout by the 1st power supply wiring method. The figure which shows the example of the power supply layout by the 1st power supply wiring method. The figure which shows the example of the power supply layout by the 1st power supply wiring method. The figure which shows the other example of the power supply layout by a 1st power supply wiring method. The figure which shows the other example of the power supply layout by a 1st power supply wiring method. The figure which shows the other example of the power supply layout by a 1st power supply wiring method. The figure which shows the other example of the power supply layout by a 1st power supply wiring method. The figure which shows the other example of the power supply layout by a 1st power supply wiring method. The figure which shows the 2nd example of the flowchart of the power supply wiring method of this Embodiment. The figure which shows the example of the power supply layout by the 2nd power supply wiring method. The figure which shows the example of the power supply layout by the 2nd power supply wiring method. The figure which shows the example of the power supply layout by the 2nd power supply wiring method. The figure which shows the example of the power supply layout by the 2nd power supply wiring method. The figure which shows the other example of the power supply layout by the 2nd power supply wiring method. The figure which shows the other example of the power supply layout by the 2nd power supply wiring method. The figure which shows the other example of the power supply layout by the 2nd power supply wiring method. The figure for demonstrating the structure of the design support system of the integrated circuit device of this embodiment. 1 is an example of a block diagram of a semiconductor integrated circuit device of an embodiment. 1 is an example of a block diagram of an electronic device including a semiconductor integrated circuit device. 22A to 22C are examples of external views of various electronic devices. The figure for demonstrating an example of the conventional power supply wiring method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device, 10 IP module, 12 VDD power supply ring, 14 core part, 20 IP module, 22 VDD power supply ring, 24 core part, 30 Power supply wiring candidate area, 32-1-32-3 VDD power supply line, 34 -1 to 34-3 VDD power supply line, 36-1 to 36-3 VDD power supply line, 38-1 to 38-3 VDD power supply line, 40 power supply wiring candidate region, 42-1 to 42-3 VDD power supply line, 50 Power supply wiring candidate region, 52-1 to 52-2 VDD power supply line, 54-1 to 54-2 VDD power supply line, 56-1 to 56-2 VDD power supply line, 60 Power supply wiring candidate region, 62-1 to 62- 2 VDD power line, 70 power wiring candidate area, 72-1 to 72-2 VDD power line, 74-1 to 74-2 VDD power line , 76-1 to 76-2 VDD power supply line, 80 power supply wiring candidate region, 82-1 to 82-2 VDD power supply line, 100 semiconductor integrated circuit device, 110 IP module, 112 VDD power supply ring, 114 core portion, 120 IP module, 122 VSS power ring, 124 core portion, 130 power wiring candidate area, 132-1 to 132-2 VDD power line, 134-1 to 134-2 VDD power line, 136-1 to 136-2 VDD power line 138-1 to 138-2 VDD power supply line, 140 power supply wiring candidate area, 142 power supply wiring prohibition area, 150 power supply wiring candidate area, 152-1 to 152-2 VDD power supply line, 154-1 to 154-2 VDD power supply Line, 156-1 to 156-2 VDD power line, 160 power distribution Candidate area, 162-1 to 162-2 VDD power line, 174 VDD power line, 176 VDD power line, 200 semiconductor integrated circuit device, 210 IP module, 212 VDD power ring, 214 core part, 220 IP module, 222 VSS power source Ring, 224 core portion, 230 power supply wiring candidate area, 232 VDD power supply line, 232-1 to 232-2 stack VIA, 234-1 to 234-2 VDD power supply line, 234-3 to 234-4 stack VIA, 236- 1-236-2 VDD power supply line, 236-3 to 236-4 Stack VIA, 238-1 to 238-2 VDD power supply line, 238-3 to 238-4 stack VIA, 240 Power supply wiring candidate area, 242 VDD power supply line , 242-1 to 242-2 Stack VIA, 244 Power supply wiring prohibited area, 250 Power supply wiring candidate area, 252 VDD power supply line, 254-1 to 254-2 VDD power supply line, 254-3 to 254-4 Stack VIA, 256-1 to 256-2 VDD power supply Line, 256-3 to 256-6 Stack VIA, 260 Power supply wiring candidate area, 262 VDD power supply line, 274-1 to 274-2 VDD power supply line, 274-3 to 274-4 Stack VIA, 276-1 to 276- 2 VDD power line, 276-3 to 276-4 Stack VIA, 300 Semiconductor integrated circuit device, 310 IP module, 312 VDD power ring, 320 IP module, 322 VDD power ring, 332 VDD power line, 342 VDD power line, 400 Design support system 420 processing units, 422 module placement means, 424 power supply wiring candidate area setting means, 426 power supply wiring prohibited area setting means, 428 power supply line wiring means, 430 power supply line automatic wiring means, 440 operation part, 450 storage part, 452 library information storage Part, 460 information storage medium, 470 display part, 480 sound output part, 490 communication part, 510 CPU, 520 cache memory, 530 LCD controller, 540 reset circuit, 550 programmable timer, 560 real-time clock (RTC), 570 DMA controller, 580 interrupt controller, 590 communication control circuit, 600 bus controller, 610 A / D converter, 620 D / A converter, 630 input port, 640 output port, 650 I / O port, 66 Clock generator, 670 prescaler, 680 general-purpose bus, 690 various pins, 700 microcomputer (semiconductor integrated circuit device), 710 ROM, 720 RAM, 730 MMU, 740 clock stop control circuit, 750 dedicated bus, 800 electronic device, 810 micro Computer (semiconductor integrated circuit device), 820 input unit, 830 memory, 840 power generation unit, 850 LCD, 860 sound output unit, 950 mobile phone, 952 dial button, 954 LCD, 956 speaker, 960 portable game device, 962 operation Button, 964 Cross key, 966 LCD, 968 Speaker, 970 Personal computer, 972 Keyboard, 974 LCD, 976 Sound output section

Claims (9)

At least one module having a power ring with at least a portion laid along a given first direction and at least another portion laid along a second direction orthogonal to the first direction; A semiconductor integrated circuit device including a power supply wiring method for a semiconductor integrated circuit device, wherein a power supply line for supplying a predetermined potential to the power supply ring is provided,
A module placement step of placing the module such that at least one of the first direction or the second direction matches a power supply wiring direction in which the power supply line is wired;
An area along the power supply wiring direction including a portion laid along the first direction or the second direction of the power supply ring included in the arranged module is aligned with the power supply wiring direction. A power supply wiring candidate area setting step to be set in the wiring candidate area;
And a power line wiring step for wiring the power line along the power wiring direction in the power wiring candidate region and connecting the power line to the power ring. In claim 1,
When the power supply wiring candidate region overlaps with a given power supply ring arrangement region supplied with a potential different from the predetermined potential, the power supply wiring prohibition region sets the power supply wiring candidate region as a power supply wiring prohibition region Including configuration steps,
In the power line wiring step,
A power supply wiring method for a semiconductor integrated circuit device, wherein the power supply line is not wired in the power supply wiring prohibited area. In claim 2,
In the power supply wiring prohibited area setting step,
A power supply wiring method for a semiconductor integrated circuit device, comprising: determining whether to set the power supply wiring candidate area as the power supply wiring prohibited area based on a wiring layer for wiring the power supply line. In any one of Claims 1 thru | or 3,
The power line wiring step further includes a power line automatic wiring step for causing a predetermined automatic wiring tool to automatically wire a predetermined power line along the power wiring direction and to connect to the power ring after the power line wiring step. A power supply wiring method for a semiconductor integrated circuit device. In claim 4 dependent on claim 2 or 3,
In the automatic power line wiring step,
A power supply wiring method for a semiconductor integrated circuit device, wherein the automatic wiring tool is automatically wired by designating that wiring in the power supply wiring prohibited area is prohibited. At least one module having a power ring with at least a portion laid along a given first direction and at least another portion laid along a second direction orthogonal to the first direction; A semiconductor integrated circuit device includes a power supply wiring program for a semiconductor integrated circuit device for wiring a power supply line for supplying a predetermined potential to the power supply ring,
Module placement means for placing the module such that at least one of the first direction or the second direction matches a power supply wiring direction in which the power supply line is wired;
An area along the power supply wiring direction including a portion laid along the first direction or the second direction of the power supply ring included in the arranged module is aligned with the power supply wiring direction. Power wiring candidate area setting means for setting the wiring candidate area;
A power supply wiring program for a semiconductor integrated circuit device, wherein a computer functions as a power supply line wiring means for wiring the power supply line along the power supply wiring direction in the power supply wiring candidate region and connecting the power supply line to the power supply ring. At least one module having a power ring with at least a portion laid along a given first direction and at least another portion laid along a second direction orthogonal to the first direction; A design support system for supporting the design of a semiconductor integrated circuit device including:
Module arrangement in which the modules are arranged so that at least one of the first direction or the second direction matches a power supply wiring direction in which a power supply line for supplying a predetermined potential to the power supply ring is wired Means,
An area along the power supply wiring direction including a portion laid along the first direction or the second direction of the power supply ring included in the arranged module is aligned with the power supply wiring direction. Power wiring candidate area setting means for setting the wiring candidate area;
A design support system for a semiconductor integrated circuit device, comprising: power line wiring means for wiring the power line along the power wiring direction and connecting to the power ring in the power wiring candidate region.   A power supply wiring method for a semiconductor integrated circuit device according to any one of claims 1 to 5, a power supply wiring program for a semiconductor integrated circuit device according to claim 6, or a design of a semiconductor integrated circuit device according to claim 7. A semiconductor integrated circuit device designed and manufactured using a support system. A semiconductor integrated circuit device according to claim 8;
Data input means to be processed by the semiconductor integrated circuit device;
And an output means for outputting data processed by the semiconductor integrated circuit device.

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