JP2009168685A - Delay line test method and circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To test a delay line so as to eliminate an erroneous determination. <P>SOLUTION: When the delay line 2 comprising 256 delay cells 1 connected to an output terminal 3 in series is tested, two delay cells 1 separated from each other at a distance of 128 cells are selected, and a test pulse is simultaneously input to them. A time difference between two test pulses output from the output terminal 3 is detected. Selected locations of two delay cells separated from each other at the distance of 128 cells are sequentially and repetitively shifted. It determines whether the time difference is within a predetermined range or not, and determines whether the delay line is normal or abnormal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method and a circuit for testing normal / failure of a delay line configured by connecting delay cells in a plurality of stages in series.

  FIG. 11 shows a multi-input / 1-output type delay line 2 formed by connecting a plurality of delay cells 1 (for example, 256) in series. Each delay cell 1 includes an input terminal 1a, an output terminal 1b, a clock terminal 1c, and a select terminal 1d. By connecting the input terminal 1a of the delay cell 1 at the subsequent stage to the output terminal 1b of the delay cell 1 at the previous stage, A plurality of terminals 3 are connected in series. The clock terminal 1c of each delay cell 1 is connected in common to the input terminal 4. When the select terminal 1d is “H”, for example, the clock from the input terminal 4 can be input to the clock terminal 1c, and input when it is “L”. It becomes impossible.

  Therefore, the delay line 2 sets only the select terminal 1d of any one delay cell 1 to "H" and sets the other to "L", thereby setting the select terminal 1d set to "H". A test pulse input from the input terminal 4 is input to the delay cell 1 and is transmitted via the delay cell 1 at the subsequent stage, and is output from the output terminal 3 with a delay corresponding to the number of via stages.

  FIG. 12 is an explanatory diagram of the delay line 2 test. In the test, a test pulse of “H” or “L” is input from the input terminal 4 at one address (for example, 100 ns). Here, two addresses for inputting “H” and “L” test pulses per test are used for each delay cell. When testing the delay cell 1 in the foremost stage (right end) of the delay line 2, the select terminal 1d of the foremost delay cell 1 is set to “H” and the input terminal 4 is set to “H” at the first one address. For example, when 99 ns have elapsed, the level of the output terminal 3 is collated with an expected value (in this case, “H”). Subsequently, at the next one address, an “L” test pulse is input to the input terminal 4 and the level of the output terminal 3 is compared with an expected value (in this case, “L”) when 99 ns elapses, for example. Thereby, the presence or absence of a failure of the first delay cell 1 can be confirmed.

  When testing the delay cell 1 in the latter stage (second from the right end) of the foremost stage, the select terminal 1d of the delay cell 1 is set to “H” and the input terminal 4 is set to “H” at the first one address. For example, when 99 ns elapses after inputting a test pulse, the level of the output terminal 3 is collated with an expected value (in this case, “H”). Subsequently, at the next one address, an “L” test pulse is input to the input terminal 4 and the level of the output terminal 3 is compared with an expected value (in this case, “L”) when 99 ns elapses, for example. Thereby, it can be confirmed whether or not there is a failure in the second delay cell 1 from the right end. In the same manner, the delay cells 1 are sequentially tested, and the presence or absence of a failure in each delay cell 1 can be confirmed.

  However, in the above test, when the select terminal 1d of a specific delay cell 1 is fixed to “H” due to a failure, a test pulse is always input from the specific delay cell 1, but this cannot be determined as a failure. . This is because the determination of this test confirms that the output signal is “H” if the test pulse is “H”, and the output signal is “L” if the test pulse is “L”. This is because it has not been confirmed which delay cell 1 the test pulse input from the input terminal 4 has passed.

  If the select terminals 1d of the plurality of delay cells 1 are simultaneously fixed to “H” due to a failure, test pulses are simultaneously input from the plurality of delay cells 1, but this cannot be determined as a failure. In this case, when the expected value is collated, the selection terminal 1d is simultaneously input from a plurality of delay cells 1 fixed to “H” in order to determine normality / failure depending on whether or not the logic level is a desired level. If the same level as the level of the test pulse is output from the output terminal 3 at the collation timing, no failure occurs.

  It is an object of the present invention to select two delay cells that are separated by a predetermined number of stages from a plurality of delay cells connected in series so that the above-described erroneous determination does not occur. It is to provide a line testing method and apparatus.

To achieve the above object, the invention according to claim 1 is a delay line test method for testing a delay line constituted by connecting a plurality of delay cells to an output terminal in series. A plurality of delay cells are selected and test pulses are simultaneously input thereto, the time difference between the two test pulses output from the output terminal is detected, and the selected positions of the two delay cells separated by the predetermined number of stages are sequentially The normal / failure is determined based on whether or not the time difference is within a predetermined range.
According to a second aspect of the present invention, there is provided a delay line test method for testing a delay line configured by providing a selection circuit for connecting a plurality of delay cells in series to an input terminal and selecting and connecting each delay cell to an output terminal. , A test pulse is input to the input terminal, and the selection circuit selects a delay cell closer to the input terminal among the two delay cells separated by a predetermined number of stages in the first period, The delay cell far from the input terminal is selected from the two delay cells separated by the predetermined number of stages in the period of time, and the time difference between the two test pulses output from the output terminal is detected, and the predetermined number of stages is detected. The selection position of two separate delay cells is sequentially shifted, the same repetition is performed, and normality / failure is determined based on whether the time difference is within a predetermined range.
The invention according to claim 3 is a delay line test method for testing a delay line constituted by connecting a plurality of delay cells in series to an input terminal and providing a path selection circuit to the output terminal in each delay cell. A test pulse is input to the input terminal, and the path selection circuit of the delay cell closer to the input terminal among the two delay cells separated by a predetermined number of stages in the first period is enabled, and in the second period By enabling the path selection circuit of the delay cell far from the input terminal of the two delay cells, the time difference between the two test pulses output from the output terminal is detected, and 2 2 apart by the predetermined number of stages. The effective positions of the path selection circuits of the delay cells are sequentially shifted, the same repetition is performed, and normality / failure is determined based on whether or not the time difference is within a predetermined range.
According to a fourth aspect of the present invention, in the delay line test method according to the first, second, or third aspect, the time difference is a time difference between rising edges or a time difference between falling edges of the two test pulses, or a preceding point. This is a time difference from the rising edge or falling edge of the test pulse to the falling edge or rising edge of the subsequent test pulse.
The invention according to claim 5 selects two delay cells in the delay line according to claim 1, or controls the delay line selection circuit according to claim 2, or according to claim 3. The control means for selecting the effective position of the two path selection circuits of the delay line and the time difference between the two test pulses output from the output terminal of the delay line according to claim 1, 2 or 3 to detect normal / failure Test determination means for determining.
The delay line test circuit according to a sixth aspect is the delay line test circuit according to the fifth aspect, wherein the time difference is a time difference between rising edges of the two test pulses, a time difference between falling edges, or a previous test pulse. It is a time difference from a rising edge or a falling edge to a falling edge or a rising edge of a subsequent test pulse.
According to a seventh aspect of the present invention, in the delay line test circuit according to the fifth or sixth aspect, the test determination unit starts a pulse oscillation operation with the first test pulse of the two test pulses, and A reference oscillation source that stops the pulse oscillation operation with the test pulse, a counter that counts the oscillation pulse of the reference oscillation source, and a test determination circuit that determines normality / failure from the count value of the counter And

  According to the present invention, it is possible not only to determine whether or not the delay time of a delay cell is normal, but also to prevent erroneous determination due to a failure of a specific delay cell.

<Example 1>
FIG. 1 is a block diagram showing the configuration of a delay line test circuit 10 according to the first embodiment of the present invention. The delay line 2 includes a plurality of (for example, 256) delay cells 1 connected in series. The delay line test circuit 10 selects two delay cells 1 in the delay line 2 and simultaneously supplies a pulse signal of “H” to their select terminals 1d, a pulse count counter 12, and the counter 12 includes a reference oscillation source 13 for applying a pulse to 12, a control for starting / stopping the pulse oscillation operation of the reference oscillation source 13, and a test determination circuit 14 for taking in the count value of the counter 12 and determining normality / failure.

In this embodiment, two delay cells separated by a predetermined number of delay cells are selected within one address, and test pulses are simultaneously input to the two delay cells. For example,
Address 1: 1st (right end in FIG. 11) and 129th delay cells Address 2: 2nd and 130th delay cells Address 3: 3rd and 131st delay cells
:
:
Address 126: 126th and 254th delay cells Address 127: 127th and 255th delay cells Address 128: Two delay cells shifted by 128 stages, such as 128th and 256th (leftmost in FIG. 11) delay cells A test pulse is simultaneously input to the delay cells, and the two delay cells are sequentially shifted and repeated in the same manner.

  As a result, two test pulses are output from the output terminal 3 of the delay line 2. The two test pulses are output before the test pulse input to the delay cell closer to the output terminal 3 side of the delay line 2 than the test pulse input to the far delay cell. Operates based on the two test pulses that have passed through the delay line 2.

  First, the pulse oscillation operation of the reference oscillation source 13 is started by a test pulse output first from the delay line 2, and at the same time, the counter 12 that counts the number of oscillations also starts the operation. Thereafter, the pulse oscillation operation of the reference oscillation source 13 is stopped by a test pulse output later. The counter 12 automatically stops counting when the reference oscillation source 13 stops. Then, the count value counted by the counter 12 is taken into the test determination circuit 14, and whether the two selected delay cells 1 are normal or not depends on whether the count value is within a predetermined range (within the standard). Determine failure.

  The test operation of this embodiment is shown in FIG. A pulse that becomes “H” for a predetermined time is used as a test pulse. At the first address, test pulses (P1 is a test pulse input to the first stage and P129 is a test pulse input to the 129th stage) are simultaneously input to the first and 129th delay cells as described above. Therefore, the counter 12 counts the time difference Ta between the rising edges of the two test pulses P1 and P129 appearing at the output terminal 3 of the delay line 2, that is, the time difference Ta corresponding to the delay amount of the delay cells for 128 stages. The At the next one address, a test pulse (P2 is a test pulse input to the second stage and P130 is a test pulse input to the 130th stage) is simultaneously input to the delay cells of the second stage and the 130th stage and output 2 The time difference Ta of the rising edges of the test pulse pulses P2 and P130 is counted, and the same applies to the subsequent addresses.

  At this time, as a failure example, when the delay time of the delay cell is smaller than a value within a predetermined range, even if the selection position of the delay cell is normal and the operation of the reference oscillation source 13 is normal, the reference oscillation source Since the oscillation period of 13 is shortened, the count value deviates from the normal range and becomes small. When the delay time of the delay cell is larger than a predetermined value, the count value is out of the normal range and becomes large. Thereby, it can be determined whether or not the delay time of the delay cell is out of the predetermined range.

  On the other hand, even if the delay time of the delay cell is a value within a predetermined range, if any one of the delay cells fails and its select terminal 1d is fixed to “H”, the delay cell of the failure Since the test pulse is always input to the delay line 2 from when the address is sequentially switched and the test is repeated, the interval between the two test pulses appearing at the output terminal 3 at any address becomes narrow, and the count value becomes small.

  First, when the failed delay cell whose select terminal 1d is fixed at “H” is between the first stage and the 129th stage, as shown in FIG. Before the test pulse P129 input to the 129th delay cell is output from the delay line 2 after the input test pulse P1 is output from the delay line 2, the test pulse Pe input to the failed delay cell is the delay line. Therefore, the counter 12 counts the time Tb from the rising edge of the test pulse P1 to the rising edge of the test pulse Pe. Since this time Tb is shorter than the normal time Ta, the count value becomes smaller than the normal value range, and the failure delay cells whose select terminal 1d is fixed at “H” are the first and 129th delay cells. It can be confirmed that it exists between the delay cells in the stage. FIG. 3A shows a normal case.

  Further, when the failed delay cell in which the select terminal 1d is fixed to “H” is between the 129th stage (left side in FIG. 11), as shown in FIGS. 3 (c) to 3 (e). In addition, the count value of the counter 12 is within a normal value range from the beginning to the predetermined address, but by updating the address, the failed delay element is between two delay elements separated by 128 stages. As shown in FIG. 3 (f), the count value of the counter 12 becomes smaller than the normal value range, and the delay line 2 has a failure in which the select terminal 1d is fixed to “H”. It can be confirmed that there is a delay cell.

  Fig. 4 summarizes the failure cases. As a failure of a delay cell, the delay time is smaller / larger than the predetermined value and the position of the failed delay cell is within the 128th stage / after, but in any case, the count value is out of the predetermined range. Can be determined.

  As for the count value of the counter 12, the normal range is set to 1 or more and the number of selected two delay cell intervals. For example, when two locations are selected simultaneously at intervals of 128 stages of delay cells, and the pulse oscillation period (1 count value) of the reference oscillation source 13 is 5 stages of delay cells, 128 ÷ 5 = 25.6. The normal range of the count value may be set to “1 or more and 25 or less”.

  Further, if the reference oscillation source 13 is constituted by a ring oscillator or the like using a cell having the same MOS size and layout as the delay cell 1, the delay time of the delay cell changes due to a change in PVT (process, voltage, temperature). However, since the interval between the delay cells at which two locations are simultaneously selected for each address is constant, the determination can be made without changing the normal range of the count value according to the PVT. Therefore, the reference oscillation source 13 is preferably mounted on the same silicon as the delay line 2. However, when not affected by PVT fluctuation, another silicon or another reference oscillation source 13 may be used.

Further, by grasping the pulse oscillation cycle of the reference oscillation source 13, it becomes possible to indirectly measure the delay time of the delay cell from the count value of the counter 12, thereby selecting the delay cell by the absolute delay time. Also, a more AC-like test is possible. For example, if the normal range of the count value when the oscillation period of the reference oscillation source 13 is 1 ns and two delay cells are simultaneously selected at intervals of 128 delay cells is “10 or more and 15 or less”, the delay cell 1 When the delay time per stage is within the range calculated as follows, it can be determined to be normal.
Delay stage lower limit of one delay cell: (10 × 1 ns) ÷ 128 = 78 ps or more Upper limit of delay time of delay cell one stage: (15 × 1 ns) ÷ 128 = 117 ps or less

  The time difference between the two test pulses output from the output terminal 3 is measured not only between the rising edges of the test pulse but also between the falling edges, or between the rising edge and the falling edge, and between the falling edge and the rising edge. You may measure with. In particular, when two delay cells are selected, if the delay time of the delay cell is relatively small or the delay line is short, two test pulses appearing at the output terminal 3 of the delay line 2 may overlap. . In such a case, as shown in FIG. 5, the pulse oscillation operation of the reference oscillation source 13 is started at the rising edge of the test pulse P1 output earlier, and the reference oscillation source is output at the falling edge of the test pulse P129 output later. It is only necessary to stop the 13 oscillation operations. As a result, a test can be performed as in the case described with reference to FIG.

<Example 2>
In the first embodiment described with reference to FIG. 1, the multi-input / single-output type delay line 2 shown in FIG. 11 is used, but a single-input / multi-output type delay line 2A as shown in FIG. 6 is used. You can also. This delay line 2A has a plurality of (for example, 256) delay cells 1 connected in series to the input terminal 4, and the output side of each delay cell 1 is connected to a selection circuit 5. By controlling and selecting the output of a predetermined delay cell 1, the delay time can be selected. FIG. 7 shows a waveform appearing at the output of each delay cell 1 when a test pulse is input to the input terminal 4. If the delay time of one delay cell 1 is Tu, the test pulse output from the adjacent delay cell has a time difference by Tu.

  In the present embodiment, the selection circuit 5 is controlled by the control circuit 11 of the delay test circuit 10 (FIG. 1), so that first of the two delay cells separated by a predetermined number of delay cells within one address. The output of the delay cell on the front side (side closer to the input terminal 4) is selected in the first period, and the output of the delay cell on the rear side (the side far from the input terminal 4) is selected in the second period. Is input to the test determination circuit 14. For example, when selecting the output of two delay cells shifted by 128 stages, it is as shown in FIG. The start / stop of the pulse oscillation operation of the reference oscillation source 13 by these two test pulses, determination of whether or not the count value of the counter 12 is within a predetermined range, etc. are exactly the same as in the first embodiment.

<Example 3>
FIG. 9 is a diagram showing the configuration of the 1-input / 1-output type delay line 2B. The delay line 2B has a plurality of (for example, 256) delay cells 1 connected in series to the input terminal 4, and a selector (path selection circuit) 6 for selecting a signal path on the output side of each delay cell 1. The selector 6 is connected to the output terminal 3 in cascade. As a result, the test pulse input to the input terminal 4 can be folded back at the specific delay cell 1 and output to the output terminal 3, and the delay time can be selected by selecting the loop-back selector 6. For example, if the selector 6 at the foremost stage closest to the output terminal 3 selects “1” and all the other selectors 6 select “0”, the number of delay stages becomes one, and the last stage farthest from the output terminal 3 If the selector 6 of the first selector selects the “1” side and all the other selectors 6 select “0”, the number of delay stages is 256. However, in this embodiment, there are a plurality of selectors 6 between the input terminal 4 and the output terminal 3, and the number of selector stages varies depending on the number of delay stages.

  In this embodiment, the control circuit 11 of the delay line test circuit 10 (FIG. 1) firstly closes to the front side (close to the input terminal 4) of two delay cells separated by a predetermined number of delay cells within one address. The output of the delay cell on the side is turned back in the first period, the output of the delay cell on the rear side (the side far from the input terminal 4) is turned back in the second period, and these are input to the test determination circuit 14. For example, when selecting outputs of two delay cells shifted by 128 stages, first, the selector 6 in the first stage is set to “1” and all other selectors 6 are set to “0”. The test pulse is folded back at the first delay cell. Next, the selector 6 at the 129th stage is set to “1” and all other selectors 6 are set to “0”, and the test pulse is folded back at the delay cell at the 129th stage. The start / stop of the pulse oscillation operation of the reference oscillation source 13 by these two test pulses, determination of whether or not the count value of the counter 12 is within a predetermined range, etc. are exactly the same as in the first embodiment.

In this case, assuming that the delay time of one delay cell 1 is Tu, the “1” path passage time of one selector 6 is T1, and the “0” path passage time is T0, the delay time Ta of the 128-stage delay cell. Is
Ta = 128 (Tu + T0)
It becomes.

FIG. 3 is a block diagram illustrating a configuration of a delay line test circuit according to the first embodiment. 2 is an explanatory diagram of a test of Example 1. FIG. It is explanatory drawing of the failure detection of Example 1. FIG. FIG. 3 is an explanatory diagram of types of failures detected in the first embodiment. 6 is an explanatory diagram of another example of the test of Embodiment 1. FIG. FIG. 10 is an explanatory diagram of a delay line according to the second embodiment. It is explanatory drawing of the delay of the delay line of Example 2. FIG. 10 is an explanatory diagram of a test of Example 2. FIG. FIG. 10 is an explanatory diagram of a delay line according to the third embodiment. 10 is an explanatory diagram of a test of Example 3. FIG. It is a block diagram of a conventional delay line. It is explanatory drawing of the conventional test.

Explanation of symbols

  1: delay cell, 2, 2A, 2B: delay line, 3: output terminal, 4: input terminal, 5: selection circuit, 6: selector (path selection circuit), 10: delay line test circuit, 11: control circuit, 12: Counter, 13: Reference oscillation source, 14: Test determination circuit

Claims (7)

In a delay line test method for testing a delay line configured by connecting a plurality of delay cells in series to an output terminal,
Two delay cells separated by a predetermined number of stages are selected and a test pulse is simultaneously input thereto, and a time difference between the two test pulses output from the output terminal is detected.
The selected positions of the two delay cells separated by the predetermined number of stages are sequentially shifted, and the same repetition is performed.
A delay line test method, wherein normality / failure is determined based on whether or not the time difference is within a predetermined range. In a delay line test method for testing a delay line configured by connecting a plurality of delay cells to an input terminal in series and providing a selection circuit for selecting and connecting each delay cell to an output terminal,
A test pulse is input to the input terminal, and the selection circuit selects a delay cell closer to the input terminal among the two delay cells separated by a predetermined number of stages in the first period, and the second period. And selecting a delay cell far from the input terminal among the two delay cells separated by a predetermined number of stages, and detecting a time difference between the two test pulses output from the output terminal,
The selected positions of the two delay cells separated by the predetermined number of stages are sequentially shifted, and the same repetition is performed.
A delay line test method, wherein normality / failure is determined based on whether or not the time difference is within a predetermined range. In a delay line test method for testing a delay line configured by connecting a plurality of delay cells to an input terminal in series and providing a path selection circuit to the output terminal in each delay cell,
A test pulse is input to the input terminal, and the path selection circuit of the delay cell closer to the input terminal among the two delay cells separated by a predetermined number of stages in the first period is enabled, and in the second period Enabling a delay cell path selection circuit far from the input terminal of the two delay cells to detect a time difference between two test pulses output from the output terminal;
The same position is repeated by sequentially shifting the effective positions of the path selection circuits of two delay cells separated by the predetermined number of stages,
A delay line test method, wherein normality / failure is determined based on whether or not the time difference is within a predetermined range. The delay line test method according to claim 1, 2, or 3,
The time difference is the time difference between the rising edges of the two test pulses or the time difference between the falling edges, or the rising edge or falling edge of the previous test pulse to the falling edge or rising edge of the subsequent test pulse. A delay line test method characterized by being a time difference. 4. Select two delay cells in a delay line according to claim 1, or control a delay line selection circuit according to claim 2, or select two paths of a delay line according to claim 3. Control means for selecting an effective position of the circuit;
Test determination means for detecting normal / failure by detecting a time difference between two test pulses output from the output terminal of the delay line according to claim 1, 2 or 3;
A delay line test circuit comprising: The delay line test circuit according to claim 5, wherein
The time difference is the time difference between the rising edges of the two test pulses, the time difference between the falling edges, or the rising edge or falling edge of the previous test pulse to the falling edge or rising edge of the subsequent test pulse. A delay line test circuit characterized by a time difference. The delay line test circuit according to claim 5 or 6,
The test determination means includes
A reference oscillation source that starts a pulse oscillation operation with the first test pulse of the two test pulses and stops the pulse oscillation operation with a later test pulse;
A counter that counts oscillation pulses of the reference oscillation source;
A test determination circuit for determining normality / failure from the count value of the counter;
A delay line test circuit comprising:

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