JP2008304355A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of easily modifying the timing of a control signal inside the semiconductor device and an internal power supply. <P>SOLUTION: The semiconductor device has an on chip compare test function of comparing the internal signal generated inside with an expected value input from the outside and recognizing the operation. The semiconductor device comprises a counter for counting the order of test conditions used by every on chip test during on chip compare test mode, a test condition selection circuit for sequentially selecting different test conditions in response to the counted value of the counter, and an operation condition setting circuit for fixing the state of the internal connection to the test condition corresponding to the counted value of the counter. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an internal circuit timing test function.

In recent years, microfabrication has been promoted in order to reduce the cost of semiconductor devices such as semiconductor memories and logic circuits, that is, to manufacture more chips from a single wafer.
However, with the progress of microfabrication at the time of manufacturing a semiconductor device, production variations are likely to occur in a diffusion process in which fine adjustment is difficult as the pattern is formed.
Further, since the distance between adjacent wirings is reduced by miniaturization of the wiring pattern pitch, the influence from the adjacent wirings is increased due to variation in the distance between the wirings.

Variations in the manufacturing process described above cannot be avoided, and in order to achieve cost reduction, it is necessary to suppress a decrease in yield due to the manufacturing variations.
In addition, the production volume of semiconductor devices, particularly semiconductor memories, has increased, and it has become impossible to individually deal with defects caused by variations.
Therefore, for the purpose of improving the yield, the semiconductor device performs self-diagnosis, has two similar functional circuit units, tests these functional circuit units, and operates normally according to the results. There is a technique for switching to a functional circuit unit (for example, see Patent Document 1).
JP 2004-340877 A

However, since the conventional example has a plurality of functional circuit units that perform main operations, there is a problem that the circuit scale becomes large.
In particular, in the case of a semiconductor memory or the like, a technique for replacing a memory element with a redundant circuit already exists, and it is possible to cope with a defect in the memory element.
On the other hand, defects are often caused by variations in the manufacturing process due to deviations in internal signal timing and internal transistor threshold voltages from design values.

That is, due to variations in the manufacturing process, the order relationship and interval of internal signals for controlling the internal circuit are disrupted, resulting in malfunction and delay in operation speed (access time in the case of a semiconductor memory).
As described above, it occurs due to variations in characteristics of transistors and wiring resistance (or wiring capacitance) in the manufacturing process, and these variations are very difficult to avoid when manufacturing a semiconductor device.

In addition, it takes a lot of time to detect defects caused by variations in the above manufacturing process, that is, to improve the yield due to these defects, and to detect each defect by correcting it from the outside. And has a problem of reducing productivity due to complicated work.
Therefore, in order to bring the timing of the internal signal and the operation of the transistor closer to the design value, it is necessary to adjust the timing of the internal signal and the internal power source for operating the transistor.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device that can easily correct the timing of control signals and the internal power supply in the semiconductor device.

  The semiconductor device of the present invention is an on-chip compare test mode in a semiconductor device having an on-chip compare test function for comparing an internal signal generated internally and an expected value input from the outside and confirming an operation. Sometimes, for each on-chip test, a counter that counts the order of the test conditions used in the test, and a test in which the circuit constant or drive voltage, or the combination of the circuit constant and the power supply voltage sequentially differs depending on the count value of the counter A test condition selection circuit for selecting a condition; and an operation condition setting circuit for fixing a state of internal connection to a circuit constant or drive voltage of the test condition corresponding to a count value of the counter.

  When the semiconductor device of the present invention compares the internal signal with the expected value for each of the different test conditions, and outputs a pass signal when it is detected that they match, and detects that they do not match And an on-chip compare test circuit for outputting a fail signal.

  The semiconductor device of the present invention further includes a selector circuit that supplies the count value to the connection fixing circuit when the pass signal is input and supplies the count value to the connection fixing circuit when the fail signal is input. It is characterized by.

  The semiconductor device according to the present invention is characterized in that the connection fixing circuit is constituted by an antifuse circuit.

  As described above, according to the present invention, the variation in timing of the internal control signal due to the manufacturing process is performed by the self-diagnosis function built in the semiconductor device, so that a human compares the test results and corrects the timing. There is no need to perform the process, and the man-hours required for manpower can be reduced, and the circuit constant is corrected to a combination that operates using an antifuse, so that the process of correcting the circuit constant can also be reduced.

Further, according to the invention, by reading which circuit constant state (combination) is maintained in the internal latch circuit, which signal is shifted due to manufacturing variations without actually measuring the timing of the internal control signal. Can be verified.
In other words, the semiconductor device of the present invention is held in the latch while the timing at the time of normal operation is corrected when a defective product appears, so which signal from the operation at the design value, The degree of deviation can be verified without man-hours and without man-hours.

The semiconductor device of the present invention corrects the timing of the internal control signal used in the internal circuit to be within the design specifications by the self-diagnosis function provided inside without requiring an external process, Yield is improved.
That is, according to the present invention, an internal on-chip compare circuit (a circuit that compares an internal control signal with an expected value input from the outside) performs pass / fail judgment for each test mode sequentially entered. The determination result is output, and if it fails, the counter circuit is incremented.

Then, in response to the count value output from the counter circuit, the internal control signal timing change test mode (test mode to be entered) is selected, and the circuit constants (resistance value, capacitance value, voltage value, etc.) of the internal circuit are selected. If the result is another failure, the counter circuit is further incremented, the sequential timing change test mode is changed, and the on-chip compare circuit outputs the path determination result. Repeat the above process.
When the pass determination result is finally output, the count output from the counter circuit is held by the determination output, and the circuit constant of the internal circuit is set to the circuit constant corresponding to the count value. The wiring is changed by an antifuse or the like, and the timing of the internal control signal is corrected based on the self-diagnosis result so that the path determination operation state is obtained.

A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of the embodiment.
In this figure, the semiconductor device has a control circuit 1, an on-chip compare circuit 2, a counter circuit 3, a selector circuit 4, an operating condition setting circuit 5, a test condition setting circuit 6 and an internal circuit 7.

The internal circuit 7 is a circuit in which the operation of the semiconductor device is expected to vary due to variations in device parameters due to variations in process steps in the internal circuit provided in the semiconductor device.
For example, if this internal circuit 7 is a timing signal generation circuit or the like, it is considered that the internal circuit 7 is likely to deviate from a narrow design range due to wiring resistance, transistor threshold fluctuation, etc. This circuit is intended to be a non-defective product.
In addition, the internal circuit 7 has a plurality of operating conditions prepared in advance, and the corresponding antifuse is electrically connected, so that the resistance between the wiring, the capacitance, and the voltage (drive) supplied to the circuit are arbitrarily selected. Thus, the circuit configuration can be arbitrarily changed.
For example, in the above antifuse, an antifuse (SiO2) is deposited on a diode (Poly-Si) and connected to the upper metal wiring. When a predetermined write voltage is applied, the antifuse is destroyed, and the metal wiring and the diode A current flows between them.

In the present invention, in order to determine an internal control signal for controlling an internal circuit, a normally used on-chip compare test mode (the above-described timing change test mode) is used.
Therefore, in order to output the pass / fail judgment of the entire semiconductor device, the judgment result is reduced to one signal by the on-chip compare mode.
That is, the on-chip compare circuit 2 compresses a plurality of test results, degenerates the compressed signal into a 1-bit signal by a logical operation, and outputs it as a pass-fail signal.
Further, the compare test signal used below is a signal indicating whether or not the on-chip compare circuit is performing a test. For example, the test is at the “L” level and the result is being output at the “H” level. Signal.

The on-chip compare circuit 2 compares an internal control signal generated by the internal circuit 7 with an externally input signal or the like and an expected value input from the outside, and passes as a result indicating whether or not they match. Outputs a fail signal.
Here, the on-chip compare circuit 2 compares the internal control signal generated by the internal circuit 7 with the expected value input from the outside at the timing when the expected value is input. A compare signal indicating the timing for performing the comparison processing is supplied from the outside.
Therefore, the on-chip compare circuit 2 outputs a pass / fail signal in synchronization with the compare signal.

  When the control circuit 1 receives an enable signal that is a signal that enables processing for setting operating conditions, and the comparison test signal indicating that the on-chip compare circuit 2 is performing a compare test is not input, Depending on the state of the pass face signal output from the on-chip compare circuit 2 (either “H” level or “L” level), a control signal for performing a process for setting an operating condition is sent to either the contact 1 or the contact 2. Output to.

That is, when the enable signal is input as a state (for example, “H” level) in which the enable signal is set, and the on-chip compare signal is input at the “H” level, the on-chip compare circuit 2 When the pass-fail signal output from the state indicates a failure (for example, “L” level), a control signal (for example, “H” level) is output to the contact 1 and no output is output to the contact 2. No (for example, “H” level).
On the other hand, when the enable signal is input as a state (for example, “H” level) in which the enable signal is set, and the on-chip compare signal is input at the “H” level, the control circuit 1 When the pass / fail signal output from the state indicates a path (for example, “H” level), a control signal (for example, “H” level) is output to the contact 2, and no output is output to the contact 1. No (for example, “H” level).

Each time a control signal is output to the contact 1, the counter circuit 3 counts the control signal and outputs it to the selector circuit 4 as a count output.
The selector circuit 4 outputs a count output that is a count value of the control signal input from the counter circuit 3 to either the operation condition setting circuit 5 or the test condition setting circuit 6 by a pass-fail signal.
That is, when the pass fail signal is input at the “H” level indicating the pass, the selector circuit 4 outputs the count output to the operation condition setting circuit 5, while the pass fail signal is at the “L” level indicating the fail. When input, the count output is output to the test condition setting circuit 6.

The operation condition setting circuit 5 includes a latch circuit 51 and an antifuse circuit 52. The circuit condition or drive voltage in the internal circuit 7 is tested using the antifuse technology and a test condition (circuit constant or drive) that is passed. The connection of the circuit elements in the internal circuit 7 is fixed so that the circuit constant or drive voltage corresponding to the voltage or a combination of the circuit constant and the power supply voltage is obtained.
That is, when the on-chip compare circuit 2 outputs “H” level, the latch circuit 51 latches (holds) the count output output from the selector circuit 4 by the control signal output to the contact 2.
Further, the latch circuit 51 is configured to be able to read out the held bit string to the outside by a read signal, and to easily check the count value indicating the shorted combination of the antifuses from the outside. ing.

The antifuse circuit 52 has a correspondence table between count values of the count output and fuses to be connected corresponding to the count values, and a write signal is input from the outside or the control circuit 1. As a result, the fuse corresponding to the count value of the count output held in the latch circuit 51 is processed from the electrically insulated state to the connected state.
The write signal is output from the outside or the control circuit 1 in response to the case where the on-chip compare circuit 2 outputs the pass / fail signal at the “H” level.

The test condition setting circuit 6 includes a latch circuit 61 and a test condition selection circuit 62. The circuit constants in the internal circuit 7 correspond to the count value of the count output using switching means such as a MOS transistor. Connections of circuit elements in the internal circuit 7 are sequentially set so that the above combinations corresponding to the test conditions, circuit constants, or drive voltages are obtained.
That is, the latch circuit 61 latches (holds) the count output output from the selector circuit 4 by the control signal output to the contact 1 when the on-chip compare circuit 2 outputs the “H” level.
In addition, the latch circuit 61 is configured to be able to read the held bit string to the outside by a read signal, and to detect the current count value externally.

The test condition selection circuit 62 has a correspondence table between the count value of the count output and the switching means to be connected according to the count value, and is held in the latch circuit 61. Processing is performed to connect the switching means corresponding to the count value of the count output.
Therefore, the counter circuit 3 counts the control signal output to the contact 1 and outputs the count output until the on-chip compare circuit 2 outputs the “H” level pass fail signal indicating the path as the test result. It becomes.

The switching means is provided for each combination such as which of a plurality of driving voltages is supplied to an internal circuit, or which of a plurality of resistors is selected in order to adjust a delay amount between circuits. Yes. Each of the switching means is provided with the corresponding fuse.
Then, the selector circuit 4 outputs the count output to the test condition setting circuit 6, and the test condition setting circuit 6 sets the switching means corresponding to the count value of the input count output to the connection state and corresponds to the test condition. The connection state of the internal circuit 7 is repeatedly changed in order corresponding to the count value so as to be a circuit constant.

Next, the operation of the self-diagnosis function unit of the semiconductor device according to the embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a timing chart showing an operation example of the self-diagnosis function in the semiconductor device according to the present embodiment. Here, the self-diagnosis function unit includes a control circuit 1, an on-chip compare circuit 2, a counter circuit 3, a selector circuit 4, an operation condition setting circuit 5, and a test condition setting circuit 6.
At time t0, as an initial setting for operating the self-diagnosis function unit, a reset signal is input to initialize the counter circuit 3, the latch circuit 51, and the latch circuit 61, and the counter circuit 3, the latch circuit 51, and the latch circuit 61 are initialized. Are reset to “L” level.

At time t1, in order to operate the self-diagnosis function unit, an enable signal input from the outside changes from “L” level to “H” level, and an “H” level enable signal is input to the control circuit 1 This activates the self-diagnosis function unit.
Further, since the on-chip compare test is executed, a compare test signal is input from the outside as an “H” level pulse that is an output state of the test result.
At this time, since the test itself is not performed, all the count signals output from the selector circuit 4 are also at the “L” level, remain in the reset state, and the control signal is not output from the control circuit 1. The outputs of 51 and 61 do not change.
Here, since the on-chip compare circuit 2 has not been tested at all, the pass-fail signal is output at the “L” level indicating failure.

At time t2, the enable signal remains at “H” level, and the compare test signal changes from “H” level to “L” level (start of compare test).
The control circuit 1 outputs an “H” level control signal to the contact 1 because the pass fail signal is input at the “L” level.
As a result, the counter circuit 3 increments the count value (adds 1) to the initial count value {bit 0 (2 ⁰ ), bit 1 (2 ¹ ), bit 2 (2 ² )} = {0, From 0,0}, the count value {bit 0, bit 1, bit 2} = {1, 0, 0}.

At this time, the selector circuit 4 outputs the count value from the counter circuit 3 to the test condition setting circuit 6 because the “L” level pass-fail signal is input.
Since the control signal is input at the “H” level, the latch circuit 61 is in a data capture state and outputs the count value input from the selector circuit 4 to the test condition selection circuit 62. To do.
Thereby, the test condition selection circuit 62 outputs the combination of the switching means corresponding to the bit string {bit 0, bit 1, bit 2} = {1, 0, 0} output from the latch circuit 61 to the internal circuit 7, The circuit constants are set in the internal circuit 7.

Here, the on-chip compare circuit 2 performs a determination test of a plurality of internal control signals, degenerates the result, and outputs a pass-fail signal as 1-bit information.
At this time, an expected value and a compare signal are input from a test apparatus outside the semiconductor device, and the on-chip compare circuit 2 is supplied from the outside with an internal control signal output from the internal circuit 7 according to the set circuit constant. And a test for determining whether or not they match is started.

Next, at time t3, the compare test signal changes from the “L” level to the “H” level while the enable signal remains at the “H” level (end of the compare test).
Here, since the on-chip compare circuit 2 is in the output state of the determination result, the switching means is controlled by the bit string {bit 0, bit 1, bit 2} = {1, 0, 0} output from the latch circuit 61. The test result performed with the set circuit constant is output as a pass-fail signal.

The on-chip compare circuit 2 outputs a pass / fail signal at the “L” level because the determination result of any of the internal control signals is “fail”.
In addition, the control circuit 1 changes the control signal from the “H” level to the “L” level in synchronization with the rise of the compare test signal.
As a result, the latch circuit 61 holds the bit string {bit 0, bit 1, bit 2} = {1, 0, 0} output from the selector circuit 4 at the falling edge of the control signal.

At time t4, the enable signal remains at “H” level, and the compare test signal changes from “H” level to “L” level (start of compare test).
The control circuit 1 outputs an “H” level control signal to the contact 1 because the pass fail signal is input at the “L” level.
Thereby, the counter circuit 3 increments the count value, and the count value {bit 0, bit 1, bit 2 from the count value {bit 0, bit 1, bit 2} = {1, 0, 0} in the initial state. } = {0, 1, 0}.

At this time, the selector circuit 4 outputs the count value from the counter circuit 3 to the test condition setting circuit 6 because the “L” level pass-fail signal is input.
Since the control signal is input at the “H” level, the latch circuit 61 is in a data capture state and outputs the count value input from the selector circuit 4 to the test condition selection circuit 62. To do.
Thereby, the test condition selection circuit 62 outputs a combination of switching means corresponding to the bit string {bit 0, bit 1, bit 2} = {0, 1, 0} output from the latch circuit 61 to the internal circuit 7, The circuit constants are set in the internal circuit 7.

Here, the on-chip compare circuit 2 performs a determination test of a plurality of internal control signals, degenerates the result, and outputs a pass-fail signal as 1-bit information.
At this time, an expected value and a compare signal are input from a test apparatus outside the semiconductor device, and the on-chip compare circuit 2 is supplied from the outside with an internal control signal output from the internal circuit 7 according to the set circuit constant. And a test for determining whether or not they match is started.

Next, at time t5, the enable signal remains at “H” level, and the compare test signal changes from “L” level to “H” level (end of the compare test).
Here, since the on-chip compare circuit 2 is in the output state of the determination result, the switching means is controlled by the bit string {bit 0, bit 1, bit 2} = {0, 1, 0} output from the latch circuit 61. The test result performed with the set circuit constant is output as a pass-fail signal.

The on-chip compare circuit 2 outputs a pass / fail signal at the “L” level because the determination result of any of the internal control signals is “fail”.
In addition, the control circuit 1 changes the control signal from the “H” level to the “L” level in synchronization with the rise of the compare test signal.
As a result, the latch circuit 61 holds the bit string {bit 0, bit 1, bit 2} = {0, 1, 0} output from the selector circuit 4 at the falling edge of the control signal.

At time t6, the enable signal remains “H” level, and the compare test signal changes from “H” level to “L” level (start of compare test).
The control circuit 1 outputs an “H” level control signal to the contact 1 because the pass fail signal is input at the “L” level.
Thereby, the counter circuit 3 increments the count value, and the count value {bit 0, bit 1, bit 2 from the initial count value {bit 0, bit 1, bit 2} = {0, 1, 0}. } = {1,1,0}.

At this time, the selector circuit 4 outputs the count value from the counter circuit 3 to the test condition setting circuit 6 because the “L” level pass-fail signal is input.
Since the control signal is input at the “H” level, the latch circuit 61 is in a data capture state and outputs the count value input from the selector circuit 4 to the test condition selection circuit 62. To do.
Thereby, the test condition selection circuit 62 outputs the combination of the switching means corresponding to the bit string {bit 0, bit 1, bit 2} = {1, 1, 0} output from the latch circuit 61 to the internal circuit 7, The circuit constants are set in the internal circuit 7.

Here, the on-chip compare circuit 2 performs a determination test of a plurality of internal control signals, degenerates the result, and outputs a pass-fail signal as 1-bit information.
At this time, an expected value and a compare signal are input from a test apparatus outside the semiconductor device, and the on-chip compare circuit 2 is supplied from the outside with an internal control signal output from the internal circuit 7 according to the set circuit constant. And a test for determining whether or not they match is started.

Next, at time t7, the enable signal remains at “H” level, and the compare test signal changes from “L” level to “H” level (end of the compare test).
Here, since the on-chip compare circuit 2 is in the output state of the determination result, the switching means is controlled by the bit string {bit 0, bit 1, bit 2} = {1, 1, 0} output from the latch circuit 61. The test result performed with the set circuit constant is output as a pass-fail signal.

The on-chip compare circuit 2 outputs a pass / fail signal at the “H” level because the determination result of all the internal control signals is “pass”.
Therefore, the selector circuit 4 outputs the count value input from the counter circuit 3 to the operation condition setting circuit 5 because the pass-fail signal is input at the “H” level.
In addition, the control circuit 1 changes the control signal from the “H” level to the “L” level in synchronization with the rise of the compare test signal.
As a result, the latch circuit 61 holds the bit string {bit 0, bit 1, bit 2} = {1, 1, 0} output from the selector circuit 4 at the falling edge of the control signal.

Next, at time t8, the enable signal remains “H” level, and the compare test signal changes from “H” level to “L” level (start of compare test).
The control circuit 1 outputs an “H” level control signal to the contact 2 because the pass-fail signal is input at the “H” level.
As a result, the counter circuit 3 does not receive the control signal to be counted, and therefore does not increment the count value and does not change from the count value {bit 0, bit 1, bit 2} = {1, 1, 0}.

At this time, the selector circuit 4 outputs the count value from the counter circuit 3 to the operating condition setting circuit 5 because the “H” level pass-fail signal is input.
Since the control signal is input at the “H” level, the latch circuit 51 is in a data capturing state, and outputs the count value input from the selector circuit 4 to the antifuse circuit 52. .

Next, at time t9, the compare test signal changes from the “L” level to the “H” level while the enable signal remains at the “H” level (end of the compare test).
Thereby, the control circuit 1 changes the control signal from the “H” level to the “L” level in synchronization with the rising edge of the compare test signal.
As a result, the latch circuit 62 holds the bit string {bit 0, bit 1, bit 2} = {1, 1, 0} output from the selector circuit 4 at the falling edge of the control signal.
Thereafter, when a write signal is input from the outside, the fuse corresponding to the test condition set in the latch circuit 51 is short-circuited, and the circuit constants of the operating conditions (power supply voltage and delay circuit of the delay circuit) become a pass state. The wiring of the internal circuit 7 is fixed to the delay amount.

Similarly, by using a test mode other than internal timing (such as changing the transistor size) as the test mode type, the internal circuit can be corrected to the operating state by the semiconductor device itself without man-hours. it can.
For example, by changing the voltage created inside the semiconductor device in the test mode, the defective chip can be remedied, and the defect location can be specified by using the present invention at the time of defect analysis. It can be used for etc. As a result, the yield can be improved by correcting the defect so as to operate without taking much time for detection of a circuit constant that operates normally.

It is a block diagram which shows the structural example of the semiconductor device by one Embodiment of this invention. 2 is a timing chart showing an operation of a self-diagnosis function in the semiconductor device in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Control circuit 2 ... On-chip compare circuit 3 ... Counter circuit 4 ... Selector circuit 5 ... Operation condition setting circuit 6 ... Test condition setting circuit 7 ... Internal circuit 51, 61 ... Latch circuit 52 ... Antifuse circuit 62 ... Test condition selection circuit

Claims (4)

In a semiconductor device with an on-chip compare test function that compares an internal signal generated internally with an expected value input from the outside and confirms the operation,
A counter that counts the order of test conditions used in each on-chip test in the on-chip compare test mode;
A test condition selection circuit for sequentially selecting test conditions having different circuit constants according to the count value of the counter;
An operation condition setting circuit for fixing an internal connection state to a circuit constant of the test condition corresponding to the count value of the counter.   For each of the different test conditions, the internal signal is compared with the expected value, and when a match is detected, a pass signal is output, and when a mismatch is detected, a fail signal is output. 2. The semiconductor device according to claim 1, further comprising a chip compare test circuit.   3. A selector circuit for supplying the count value to the connection fixing circuit when the pass signal is input and further supplying the count value to the connection fixing circuit when the fail signal is input. The semiconductor device described.   4. The semiconductor device according to claim 1, wherein the connection fixing circuit is constituted by an antifuse circuit.

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