JP2009164456A - Semiconductor photodetector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor photodetector capable of reducing the number of dark carriers and also improving an S/N. <P>SOLUTION: The semiconductor photodetector 1 includes an n-type buffer layer 12, a first multiplication layer 13 provided on the buffer layer 12, an electric field adjustment layer 14 provided on the first multiplication layer 13, a second multiplication layer 15 provided on the electric field adjustment layer 14, an electric field mitigation layer 16 of opposite conductivity provided on the second multiplication layer 15, and an optical absorption layer 17 provided on the field mitigation layer 16. In the first multiplication layer 13 and the second multiplication layer 15, each of a p-type impurity concentration and an n-type impurity concentration is ≤5×10<SP>15</SP>cm<SP>-3</SP>. While applying an operation voltage, the field strength of the first multiplication layer 13 is made higher than the field strength of the second multiplication layer 15, by the electric field adjustment layer 14. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor light receiving element.

Various single photon detectors have been proposed due to differences in manufacturing methods and device configurations.
Single photon detectors using avalanche photodiodes (hereinafter referred to as APDs) made of silicon are well known, but there is no sensitivity in the 1.55 μm wavelength range often used for optical fiber communications, and quantum information is left as it is. Not suitable for communication applications.
Therefore, as a technique for detecting photons in the 1.55 μm wavelength band,
(1) Technique using InGaAs-based APD (2) Technique for performing detection using Si-APD after conversion to a visible light wavelength band using a wavelength conversion element or the like (3) Technique using a superconducting detection element Etc. have been proposed.

  Among these (1) to (3), not only the sensitivity of the detector but also the size, cost and power consumption are compared, and it seems that the InGaAs-based APD element of (1) seems to be promising for practical use. It is a method using. This is because wavelength conversion efficiency is a problem in (2), and the size and power consumption of the cooling device are problems in (3).

When an InGaAs-based APD is used for photon detection, in general, an operation method in which a normal DC bias is applied is insufficient to detect a single photon. In order to obtain higher sensitivity, a bias application technique called gated Geiger mode (hereinafter abbreviated as gate mode) is used.
In this method, a DC bias is applied in the vicinity of the breakdown in advance, and a gate pulse having a voltage exceeding the breakdown is added to the bias in synchronization with the timing when the photon reaches the APD, and then applied. This is a method for obtaining a high multiplication factor and detecting its output.

The gate mode applied voltage will be described with reference to the timing chart of FIG. In the gate mode, a DC bias voltage of V1 is applied in advance, the voltage is increased to a voltage V2 (> Vb) exceeding the breakdown voltage (Vb) in accordance with the photon detection timing, and photons are detected for a predetermined time (Δt1). After that, the time period (Δt2) until the next gate is returned to the bias of V1 with a small gain and waits.
On the other hand, a technique that has been used in conventional optical communication is a method of applying a bias voltage V0. In this method, the bias voltage is constant regardless of time, and the gain is generally 100 or less. In order to obtain a high S / N ratio, the multiplication factor M may be about 10.
In the gate mode, a higher multiplication factor and an S / N ratio can be obtained at the same time as compared with the method of keeping the bias voltage constant.
In addition, the following patent documents 1-3 are mention | raise | lifted as a gazette relevant to the background art of this invention.

JP 2002-324911 A JP 2003-347777 A JP 2006-302954 A

  When a single photon detector is applied to quantum information communication or the like, it is necessary to further improve the S / N ratio in order to improve the transmission characteristics (transmission speed and error rate). In the gate mode operation, it is possible to optimize the operating conditions by adjusting the gate width, pulse height, and gate interval. However, the limit of the optimization is determined by the characteristics of APD. Therefore, in order to improve the S / N ratio, it is necessary to develop an APD that can be optimized from the element structure and expected to have a higher S / N ratio.

  An object of the present invention is to provide a semiconductor light receiving element capable of improving the S / N ratio.

According to the present invention, a first multiplication layer, an electric field adjustment layer provided on the first multiplication layer, a second multiplication layer provided on the electric field adjustment layer, and the second multiplication layer An electric field relaxation layer provided on the layer; and a light absorption layer provided on the electric field relaxation layer, wherein each of the first multiplication layer and the second multiplication layer has a p-type impurity concentration and Each impurity concentration of the n-type impurity concentration is 5 × 10 ¹⁵ cm ⁻³ or less, and the electric field adjustment layer increases the electric field strength of the first multiplication layer by the electric field adjustment layer when an operating voltage is applied. A semiconductor light-receiving element having a larger electric field strength than the double layer is provided.

  According to the present invention, a semiconductor light receiving element capable of improving the S / N ratio is provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
3 and 4 show the semiconductor light receiving element 1 of the present embodiment.
FIG. 3 is a cross-sectional view of the semiconductor light-receiving element 1, and FIG. 4 is a diagram schematically showing the semiconductor light-receiving element 1.
First, an outline of the semiconductor light receiving element 1 will be described.
The semiconductor light receiving element 1 includes an n-type buffer layer (first layer) 12 provided on a semiconductor substrate 11, a first multiplication layer 13 provided on the buffer layer 12, and the first multiplication. An electric field adjustment layer 14 provided on the layer 13, a second multiplication layer 15 provided on the electric field adjustment layer 14, a p-type electric field relaxation layer 16 provided on the second multiplication layer 15, And a p-type light absorption layer 17 provided on the electric field relaxation layer 16.
Each of the first multiplication layer 13 and the second multiplication layer 15 has a p-type impurity concentration and an n-type impurity concentration of 5 × 10 ¹⁵ cm ⁻³ or less.
Further, the electric field adjustment layer 14 makes the electric field intensity of the first multiplication layer 13 larger than the electric field intensity of the second multiplication layer 15 in the state where the operating voltage is applied.

Next, the semiconductor light receiving element 1 will be described in detail.
In addition to the substrate 11, the buffer layer 12, the first multiplication layer 13, the electric field adjustment layer 14, the second multiplication layer 15, the electric field relaxation layer 16, and the light absorption layer 17, the semiconductor light receiving element 1 includes a light absorption layer. 17 includes a buffer layer 18 provided on the buffer layer 17 and a contact layer 19 provided on the buffer layer 18.
This semiconductor light-receiving element 1 is a III-V group semiconductor light-receiving element including a group III-V compound semiconductor layer. Examples of materials and the like of each layer are as shown in Table 1. The impurity concentration in Table 1 indicates the impurity concentration of the same conductivity type as that of the substrate 11 and the layers 12, 14, 16, 17, 18, and 19. In the first multiplication layer 13 and the second multiplication layer 15, the impurity concentrations of p-type impurity concentration and n-type impurity concentration are shown.

An AR coating 23 is applied to the back side of the semiconductor substrate 11. Further, each of the layers 12 to 19 is formed in a mesa shape, and the periphery thereof is covered with a passivation film (insulating film) 21. In the passivation film 21, an opening is formed in an upper portion of the contact layer 19, and a p-side electrode 20 is formed in the opening.
In addition, an n-side electrode 22 is formed in a portion adjacent to the mesa constituted by the layers 12 to 19 with the groove interposed therebetween.

The first multiplication layer 13 and the second multiplication layer 15 are layers that cause avalanche multiplication by applying a high electric field and generate a large amount of carriers.
The first multiplication layer 13 has a higher electric field than the second multiplication layer 15 and is provided directly on the buffer layer 12. The first multiplication layer 13 needs to be formed with a uniform electric field with a layer thickness of a certain level or more in order to reduce the generation of dark carriers. The first multiplication layer 13 preferably has a layer thickness of 0.2 μm or more. By doing in this way, the multiplication function of the 1st multiplication layer 13 can be ensured reliably.
Further, the n-type impurity concentration and the p-type impurity concentration of the first multiplication layer 13 are each 5 × 10 ¹⁵ cm ⁻³ or less. By adopting such an impurity concentration, the electric field strength of the first multiplication layer 13 can be made constant (uniform electric field) along the layer direction during the operation of the light receiving element 1.
When the layer thickness is 2.0 μm or more, the n-type impurity concentration and the p-type impurity concentration are 1 × 10 ¹⁵ cm ⁻³ or less in order to ensure the uniformity of the electric field strength. Is desirable.
Note that the lower limit values of the n-type impurity concentration and the p-type impurity concentration are not particularly limited, but may be less than the detection limits of an Auger spectrometer or a secondary ion mass spectrometer.

The first multiplication layer 13 desirably has a large band gap in order to obtain good multiplication characteristics. When the first multiplication layer 13 is formed on the InP substrate as the substrate 11, In _x Al _y Ga _{(1 -Xy)} As (0 <x <1, 0 <y <1, 0 <x + y ≦ 1) is desirable, and InAlAs, which is InAlGaAs having the largest band gap, is suitable.

In the second multiplication layer 15, the dark count is suppressed as compared with the first multiplication layer 13, and a multiplication function with a smaller gain than the first multiplication layer 13 is provided. For this purpose, a uniform electric field in which the electric field strength is constant along the layer direction during the operation of the light receiving element is desirable. Specifically, the n-type impurity concentration and the p-type impurity concentration are each 5 × 10 ¹⁵ cm ⁻³ or less.

In order to sufficiently suppress the dark count as compared with the first multiplication layer 13, the electric field strength of the second multiplication layer 15 is preferably 90% or less of the electric field strength of the first multiplication layer 13.
On the other hand, in order for the second multiplication layer 15 to have a multiplication function, a certain electric field strength is required. When the electric field strength decreases, the travel distance λ required for one multiplication process becomes longer, so that the layer thickness needs to be increased.
In order to increase the multiplication gain of carrier injection to about 10 times even when the electric field is the highest, a traveling distance for ionization is required about 5 times (the maximum value of the multiplication factor at that time is 2 ⁵ = 32 times). For this purpose, when considering an average ionization distance of 200 to 300 mm at the time of normal breakdown, a uniform electric field of 200 to 300 mm × 5 = 0.1 to 0.15 μm is required by calculating five times the average ionization distance. That is, the required thickness is at least 0.1 μm.

When the electric field intensity of the second multiplication layer 15 is about 20% of that of the first multiplication layer 13, and when the travel distance necessary for ionization is estimated to be about five times, 1000 to 1500 mm × 5 = 0.5 to The minimum layer thickness required for the second multiplication layer 15 is 0.5 μm.
When the electric field intensity of the second multiplication layer 15 is about 50% of that of the first multiplication layer 13 and the travel distance necessary for ionization is estimated to be about twice, 400 to 600 mm × 5 = 0.2 to The minimum layer thickness required for the second multiplication layer 15 is 0.2 μm.
When the electric field intensity of the second multiplication layer 15 is about 60% of that of the first multiplication layer 13 and the travel distance required for ionization is estimated to be about 1.66 times, 332 to 500 mm × 5 = 0. 16 to 0.25 μm, and the minimum layer thickness required for the second multiplication layer 15 is 0.16 μm.
When the electric field intensity of the second multiplication layer 15 is about 80% of that of the first multiplication layer 13 and the travel distance necessary for ionization is estimated to be about 1.25 times, 250 to 375 mm × 5 = 0. 13 to 0.19 μm, and the minimum layer thickness required for the second multiplication layer 15 is 0.13 μm.
FIG. 5 shows the relationship between the thickness of the second multiplication layer 15 and the relative electric field strength of the second multiplication layer 15 with respect to the first multiplication layer 13. It can be seen that the required layer thickness of the second multiplication layer 15 increases as the electric field strength of the second multiplication layer 15 is lowered.
In FIG. 5, the first multiplication layer 13 is a region A and the second multiplication layer 15 is a region B.

On the other hand, the maximum layer thickness of the second multiplication layer 15 is preferably within about 1.2 to 1.5 times the thickness of the first multiplication layer 13, and particularly preferably within one time.
By doing so, it is possible to reliably prevent the multiplication factor of the second multiplication layer 15 from exceeding the multiplication factor of the first multiplication layer 13.
In order to obtain good multiplication characteristics, the material used for the second multiplication layer 15 is desirably a band gap material equal to or greater than that of the first multiplication layer 13. Specifically, In _x Al _y Ga _(1-xy) As (0 <x <1, 0 <y <1, 0 <x + y ≦ 1) similar to the first multiplication layer 13, InAlAs is preferred. Furthermore, InGaAsP may be used. It is also possible to introduce a structure having a band offset such as a superlattice structure formed by alternately using these materials.

  The electric field adjustment layer 14 is a layer having a function of making a difference in electric field strength between the first multiplication layer 13 and the second multiplication layer 15 (see FIG. 6). The electric field adjustment layer 14 is in direct contact with the first multiplication layer 13 and the second multiplication layer 15. The first multiplication layer 13 and the second multiplication layer 15 are configured by a uniform electric field, and the average electric field strength and electric field strength of the multiplication layer are the same. Therefore, the electric field relaxation amount (impurity concentration × layer thickness) of the electric field adjustment layer 14 constitutes the difference in electric field strength between the first multiplication layer 13 and the second multiplication layer 15 (see FIG. 6). A calculation example of the electric field relaxation amount is shown in Table 2 below. Table 2 shows the relationship between the thickness of the electric field adjustment layer 14, the p-type impurity concentration, and the relaxation amount.

In order to reduce the multiplication effect inside the electric field adjustment layer 14, it is necessary to reduce ionization, and the thickness of the electric field adjustment layer 14 is desirably 0.1 μm or less. If it is 0.1 μm or less, the average ionization distance (200 mm) is less than 10 times, and the number of ionizations can be suppressed.
Furthermore, the ionization probability inside the electric field adjustment layer 14 can be reduced by setting the thickness of the electric field adjustment layer 14 to 500 mm (0.05 μm) or less. If it is 500 mm, it is within 3 times the average ionization distance, and ionization hardly occurs.
In addition, the thinner the electric field adjustment layer 14, the less ionization is preferable. However, when the electric field adjustment layer 14 is thin, it is necessary to increase the p-type impurity concentration in the electric field adjustment layer 14 to perform electric field adjustment. (See Table 2). However, if the p-type impurity concentration is too high, the crystallinity of the electric field adjustment layer 14 may be deteriorated.
Thus, by setting the thickness of the electric field adjustment layer 14 to 10 mm (0.001 μm) or more, the electric field adjustment layer can be formed with a reasonable doping concentration (there is less risk of deterioration due to crystallinity).
Furthermore, the thickness of the electric field adjustment layer 14 is desirably 1/5 or less of the first multiplication layer 13, and is preferably set to 1/10 or less.

Here, the film thickness and the p-type impurity concentration of the electric field adjustment layer 14 are EA-EB when the electric field strength of the first multiplication layer 13 is EA and the average electric field strength of the second multiplication layer 15 is EB. It is preferably set to be 100 kV / cm or more.
By doing in this way, generation | occurrence | production of the dark carrier in the 2nd multiplication layer 15 can be suppressed reliably.
The film thickness and the p-type impurity concentration of the electric field adjusting layer 14 are such that when the average electric field strength of the first multiplication layer 13 is EA and the average electric field strength of the second multiplication layer is EB, EB is EA × 0. .1 or more may be set. By doing in this way, the multiplication function in the 2nd multiplication layer 15 can be ensured reliably. When EB is EA × 0.1, the thickness of the second multiplication layer 15 is preferably 1 μm or more.
Furthermore, EB is preferably EA × 0.2 or more. By doing in this way, the multiplication function in the 2nd multiplication layer 15 can be ensured more reliably.

  The electric field relaxation layer 16 is a layer provided for relaxing the difference between the high electric field applied to the second multiplication layer 15 and the relatively low electric field applied to the light absorption layer 17. The electric field relaxation layer 16 is in direct contact with the second multiplication layer 15 and the light absorption layer 17. By providing the electric field relaxation layer 16, it is possible to stably apply a high electric field to the second multiplication layer 15. The electric field relaxation layer 16 contains a p-type impurity, and the same constituent material as that of the light absorption layer 17 and the second multiplication layer 15 can be used.

  The light absorption layer 17 is a layer that plays a role of converting incident light into electricity, and has a band gap that can absorb light to be received. The constituent material of the light absorption layer 17 is appropriately selected according to the wavelength of incident light.

Here, FIG. 6 shows an electric field strength distribution in a state where an operating voltage is applied to the semiconductor light receiving element 1. This electric field strength distribution is a distribution along the layer direction of the semiconductor light receiving element 1.
Also from FIG. 6, the electric field strength E1 of the first multiplication layer 13 is higher than the electric field strength E2 of the second multiplication layer 15, and these electric field strengths E1 and E2 are adjusted by the electric field adjustment layer 14. I understand that.

Such a semiconductor light receiving element 1 can be manufactured as follows.
The layers 12 to 19 are epitaxially grown on the semiconductor substrate 11 and then etched into a mesa shape.
Thereafter, the entire mesa is covered with a passivation film 21 to form the electrodes 20 and 22. Then, the AR coating 23 is applied to the back surface of the substrate on which the optical signal is incident.
The signal light is incident from the substrate side of the semiconductor light-receiving element 1, undergoes photoelectric conversion and multiplication inside the element in a bias applied state, and appears as current output at the electrodes at both ends.

Next, the effect of this embodiment is demonstrated.
When the multiplication layer of the APD is a uniform electric field in which the electric field intensity distribution at the time of multiplication is uniform, the ionization gain (= multiplication gain) and the generation probability of dark carriers are constant values in the layer thickness direction. For example, the dark carrier generation probability has a uniform distribution in the layer thickness direction as shown in FIG.
In FIG. 2, reference numeral 91 denotes a light absorption layer, reference numeral 92 denotes an electric field relaxation layer, and reference numeral 93 denotes a multiplication layer. Reference numeral 94 denotes dark carriers that are uniformly distributed in the multiplication layer.

However, it is known that the electron ionization rate and the hole ionization rate are not equal in a multiplication layer having a uniform electric field strength distribution, and this ratio is called an ionization rate ratio k. Due to the difference between the ionization probability of electrons and the ionization probability of holes, the dark carriers generated in the first multiplication layer 13 having a high electric field strength and the dark carriers generated in the second multiplication layer 15 having a low electric field strength have their multiplication characteristics. Makes a difference.
In the case of a multiplication layer composed of a material having an electron multiplication type characteristic (ionization rate ratio k <1), carriers in the first multiplication layer 13 having a high electric field strength cause multiplication similar to an electron injection type model. The average gain <M> is high and the excess noise F is small. On the other hand, since the carriers of the second multiplication layer 15 having a low electric field strength approach the hole injection model, the average gain <M> is small and the excess noise F is large.
In the present embodiment, the electric field strength of the first multiplication layer 13 out of the first multiplication layer 13 or the second multiplication layer 15 is made higher than the electric field strength of the second multiplication layer 15.
Thereby, when the semiconductor light receiving element 1 is operated in the gate mode, the dark count due to the application of the gate pulse is mainly generated in the first multiplication layer 13 having a high electric field.
On the other hand, since the electric field strength of the second multiplication layer 15 is lower than that of the first multiplication layer 13, dark carriers are hardly generated in the second multiplication layer 15. The electrons derived from the signal light are multiplied by the second multiplication layer 15 and proceed to the first multiplication layer 13. At this time, dark carriers are easily generated in the first multiplication layer 13 having a large electric field strength, but the second multiplication layer 15 has already been compared with the number of dark carriers generated in the first multiplication layer 13. Thus, since the number of multiplied electrons is very large, the S / N ratio is improved. FIG. 7 shows the number of appearances of carriers when the semiconductor light-receiving element 1 is operated in the gate mode and photons are detected. FIG. 7 also shows that the S / N ratio is improved.
In addition, since the first multiplication layer 13 and the second multiplication layer 15 have an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ or less, the electric field distribution during multiplication is uniform. Therefore, the amount of dark carriers generated when a certain voltage is applied is smaller than the number of carriers generated in the non-uniform electric field type multiplication layer.

In the gate mode, a gate pulse with a voltage exceeding the breakdown is applied in synchronization with the timing of electrons traveling in the first multiplication layer 13, and a high probability ionization state (continuous ionization state) peculiar to the gate mode. Will cause a breakdown. Thereafter, as the gate pulse passes, the bias decreases, the gain of the first multiplication layer 13 decreases, and the avalanche multiplication state is terminated.
Here, the high probability ionization state to be described is a multiplication process specific to the gate mode, and is different from a multiplication condition under a DC bias that is normally used.
Under normal multiplication conditions, a finite multiplication factor is obtained for a finite number of carriers.
On the other hand, under a bias condition equal to or higher than the breakdown used in the gate mode, the multiplication factor increases with the bias application time. Therefore, the multiplication factor when the application time is infinite is theoretically infinite. If an actual element is placed in this state, the element will fail due to overcurrent.
For this reason, the multiplication factor is converged to a finite value by setting a finite bias time by a pulse having a finite gate width. As a result of such an operation, the difference between the peak values of the signal and noise multiplication pulses becomes large, and the detection can be performed by providing an appropriate threshold to improve the S / N ratio.

  In the present embodiment, the buffer layer 12 is n-type, and the electric field relaxation layer 16 is p-type. Thus, by adopting a configuration in which the buffer layer 12 is n-type and the electric field relaxation layer 16 is p-type, an electron multiplication type multiplication process can be used. The electron multiplication type multiplication process uses electrons as carriers injected into the multiplication layer. Comparing the average travel distance of carriers (holes in the case of electrons) generated in pairs with injected carriers, injected carriers are longer, so if electrons with a high traveling speed are used as injected carriers, the multiplication process is generated at high speed. There are advantages that can be made.

By configuring the first multiplication layer 13 with InAlAs having the largest band gap among InAlGaAs lattice-matched on the substrate 11 which is an InP substrate, good multiplication characteristics can be obtained.
Further, the second multiplication layer 15 can also be made of InAlAs to obtain good multiplication characteristics.
Furthermore, by setting the thickness of the first multiplication layer 13 to 0.2 μm or more, the multiplication function of the first multiplication layer 13 can be reliably ensured.

It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
For example, in the above embodiment, the buffer layer 12 is n-type and the electric field relaxation layer 16 is p-type. However, the present invention is not limited to this, and the buffer layer may be p-type and the electric field relaxation layer may be n-type. Even in this case, the same effect as the above embodiment can be obtained. Since the electric field intensity of the second multiplication layer is lower than that of the first multiplication layer, dark carriers are hardly generated in the second multiplication layer. The hole derived from the signal light is multiplied by the second multiplication layer and proceeds to the first multiplication layer. At this time, in the first multiplication layer having a large electric field strength, dark carriers are easily generated, but compared with the number of dark carriers generated in the first multiplication layer, the second multiplication layer already has Since the number of multiplied holes is very large, the S / N ratio is improved.
The buffer layer may be n-type, the electric field relaxation layer may be p-type, and the light absorption layer may be i-type.
Furthermore, although the light receiving element is a mesa type in the embodiment, the present invention is not limited to this, and a planar type light receiving element may be used.
In the embodiment, the gate mode applied voltage is applied to the light receiving element. However, the present invention is not limited to this, and a bias voltage is applied to the light receiving element to operate the light receiving element as in the past. Also good.

Next, examples of the present invention will be described.
Example 1
A light receiving element similar to that of the above embodiment was formed. The thickness of each epitaxial layer is formed as shown in Table 3.

  A high-intensity uniform electric field type multiplication layer acts as the first multiplication layer 13, and a low-intensity uniform electric field type multiplication layer acts as the second multiplication layer 15. The amount of electric field relaxation in the electric field adjusting layer 14 is about 100 kV / cm 2, and the first multiplication layer 13 is the main multiplication during breakdown. By configuring the first multiplication layer 13 with InAlAs having the largest band gap among InAlGaAs lattice-matched on the InP substrate 11, a good multiplication characteristic could be obtained.

The second multiplication layer 15 and the electric field adjustment layer 14 were also made of InAlAs having the largest band gap among InAlGaAs lattice-matched on the InP substrate 11, and good multiplication characteristics could be obtained.
When the layer thickness and the p-type impurity concentration of the electric field adjustment layer 14 are defined as the electric field intensity EA of the first multiplication layer 13 and the electric field intensity EB of the second multiplication layer 15, EA-EB is 100 kV / cm or more. By setting as above, dark carriers generated in the second multiplication layer 15 could be suppressed.

A gate mode bias was applied to the light-receiving element thus fabricated.
Most of the gain for breakdown was obtained in the high-intensity uniform electric field type multiplication layer (first multiplication layer 13) in a state where a bias higher than breakdown by the gate was applied for a time Δt determined by the gate width. .
On the other hand, the optical carrier breaks down in the high-intensity multiplication layer (first multiplication layer 13) after traversing the low-intensity multiplication layer (second multiplication layer 15) in the carrier traveling. At that time, in order to obtain gain even in the low-intensity multiplication layer (second multiplication layer 15), the total gain was higher than the dark count. As a result, the difference in wave height distribution between the photon detection signal and the dark carrier, after-pulse carrier, etc. was emphasized, and a higher S / N ratio than that of the normal element could be obtained.

(Example 2)
The thickness of each epitaxial layer produced the light receiving element formed as shown in Table 4.

By configuring the first multiplication layer 13 with InAlAs having the largest band gap among the InAlGaAs lattice-matched on the InP substrate 11, good multiplication characteristics can be obtained.
The second multiplication layer 15 and the electric field adjustment layer 14 were also made of InAlAs having the largest band gap among InAlGaAs lattice-matched on the InP substrate 11, and good multiplication characteristics could be obtained.
When the combination of the layer thickness of the electric field adjustment layer 14 and the p-type impurity concentration is the electric field intensity EA of the first multiplication layer and the electric field intensity EB of the second multiplication layer 15, EB becomes EA × 0.2. By forming, a gain could be obtained in the second multiplication layer 15.
The amount of electric field relaxation in the electric field adjusting layer 14 is about 500 kV / cm, and the main multiplication occurs during breakdown in the high-strength uniform electric field type multiplication layer (first multiplication layer 13).
The average electric field strength of the low-strength uniform multiplication layer (second multiplication layer 15) was reduced to 20% or less of the average electric field strength of the high-strength uniform multiplication layer (first multiplication layer 13). For this reason, in order to obtain a gain in the second multiplication layer 15, the thickness of the second multiplication layer 15 is set to 0.5 μm.
A gate mode bias was applied to the light-receiving element thus fabricated.
In the state where a bias higher than the breakdown was applied for the gate width Δt by the gate pulse, most of the gain for breakdown was obtained in the high-intensity uniform electric field type multiplication layer (first multiplication layer 13). .
On the other hand, the optical carrier breaks down in the high-intensity multiplication layer (first multiplication layer 13) after traversing the low-intensity multiplication layer (second multiplication layer 15) in the carrier traveling. At this time, gain is obtained even in the low-intensity multiplication layer, so that the total gain is higher than the dark count. As a result, the difference in wave height distribution between the photon detection signal and the dark carrier, after-pulse carrier, etc. was emphasized, and a higher S / N ratio than that of the normal element could be obtained.

It is a figure which shows the timing of the applied bias at the time of gate mode and DC bias. It is a schematic diagram which shows the dark carrier generation | occurrence | production in a uniform electric field. It is sectional drawing of the semiconductor light receiving element in embodiment. It is the figure which showed the semiconductor light receiving element typically. It is a figure which shows the relationship between the relative electric field strength with respect to the 1st multiplication layer of a 2nd multiplication layer, and the minimum film thickness of a 2nd multiplication layer. It is a figure which shows electric field strength distribution at the time of operation | movement of a semiconductor light receiving element. It is a figure which shows the frequency | count of appearance of the carrier at the time of operating a semiconductor light receiving element by gate mode and detecting a photon.

Explanation of symbols

1 Semiconductor Photodetector 11 Semiconductor Substrate (Substrate)
12 buffer layer 13 first multiplication layer 14 electric field adjustment layer 15 second multiplication layer 16 electric field relaxation layer 17 light absorption layer 18 buffer layer 19 contact layer 20 p-side electrode 21 passivation film (insulating film)
22 n-side electrode 23 AR coating 91 light absorption layer 92 electric field relaxation layer 93 multiplication layer 94 dark carrier generated uniformly distributed in the multiplication layer

Claims (7)

The first multiplication layer,
An electric field adjustment layer provided on the first multiplication layer;
A second multiplication layer provided on the electric field adjustment layer;
An electric field relaxation layer provided on the second multiplication layer;
A light absorption layer provided on the electric field relaxation layer,
Each of the first multiplication layer and the second multiplication layer has a p-type impurity concentration and an n-type impurity concentration of 5 × 10 ¹⁵ cm ⁻³ or less,
A semiconductor light receiving element in which an electric field strength of the first multiplication layer is made larger than an electric field strength of the second multiplication layer by the electric field adjustment layer in a state where an operating voltage is applied. The semiconductor light receiving element according to claim 1,
Having a first layer on which the first multiplication layer is provided;
The first layer is n-type;
The electric field relaxation layer is a p-type semiconductor light receiving element. The semiconductor light-receiving element according to claim 1 or 2,
The thickness of the electric field adjustment layer and the p-type or n-type impurity concentration of the electric field adjustment layer are obtained when the electric field intensity EA of the first multiplication layer and the electric field intensity of the second multiplication layer are EB. , EA-EB is a semiconductor light receiving element set so as to be 100 kV / cm or more. In the semiconductor light receiving element according to any one of claims 1 to 3,
The thickness of the electric field adjustment layer and the p-type or n-type impurity concentration of the electric field adjustment layer are obtained when the electric field intensity EA of the first multiplication layer and the electric field intensity of the second multiplication layer are EB. , EB is set to EA × 0.1 or more. In the semiconductor light receiving element according to any one of claims 1 to 4,
A substrate on which the first multiplication layer, the electric field adjustment layer, the second multiplication layer, the electric field relaxation layer, and the light absorption layer are laminated;
The substrate is InP;
The first multiplication layer comprises InAlAs;
A semiconductor light-receiving element, wherein the first multiplication layer has a thickness of 0.2 μm or more. In the semiconductor light receiving element according to claim 5,
The semiconductor light receiving element in which said 2nd multiplication layer and said electric field adjustment layer contain InAlAs. In the semiconductor light receiving element according to any one of claims 1 to 6,
A semiconductor light-receiving element having a thickness of the electric field adjustment layer of 0.001 μm or more and 0.05 μm or less.

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