JP2009164372A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a wiring structure whose yield is not reduced and which can reduce inter-wiring capacitance practically sufficiently. <P>SOLUTION: The semiconductor device has a first interlayer insulating film 101 formed on a semiconductor substrate 100 and a plurality of lower wiring lines 105 made of conductive members buried in a plurality of groove portions formed on the first interlayer insulating film 101. A gap portion 101c formed by removing the first interlayer insulating film is selectively formed between adjacent wiring lines of the plurality of lower wiring lines 105 in the first interlayer insulating film 101. Further, the position of a lower end of the gap portion 101c is lower than the position of a lower end of each lower wiring line 105. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a multilayer wiring structure and a manufacturing method thereof.

  In recent years, with the miniaturization of a semiconductor device, the interval between a plurality of elements constituting the semiconductor device and the interval between wirings connecting the elements have been reduced. For this reason, the problem that the inter-wiring capacity | capacitance in wiring increases and the propagation speed of a signal falls has become obvious.

  Therefore, as shown in Patent Document 1, a method of reducing the capacitance between wirings by providing a gap (air gap) between the wirings has been studied.

  Hereinafter, a conventional wiring manufacturing method disclosed in Patent Document 1 will be described with reference to FIGS.

  First, as shown in FIG. 5A, a sacrificial film 2 is formed on an interlayer insulating film 1 formed on a semiconductor substrate (not shown). Subsequently, a plurality of wiring forming grooves are formed in the sacrificial film 2, and then a barrier film 4 and a copper film 5 are sequentially deposited in each wiring forming groove, whereby a plurality of barrier films 4 and copper films 5 are respectively formed. The wiring 6 is formed.

  Next, as shown in FIG. 5B, a porous film 7 is deposited on the entire surface of the sacrificial film 2 including the wirings 6.

Next, as shown in FIG. 5C, the sacrificial film 2 is decomposed and removed by heating or the like, thereby forming an air gap 8 between the wirings 6. With the above method, a wiring structure having the air gap 8 can be obtained.
JP 2004-266244 A

  However, the conventional wiring forming method has the following various problems.

  First, in the conventional forming method, the height of the lower end portion of the air gap 8 is substantially the same as the height of the lower end portion of each wiring 6. For this reason, as shown in FIG. 6, the lines of electric force between the wires pass not only through the air gap 8 but also through the interlayer insulating film 1 and the porous film 7. As a result, although the air gap 8 is formed, there is a problem that the inter-wiring capacity of the wiring 6 is not sufficiently reduced.

  Next, in the conventional forming method, as shown in FIG. 7, the structure for supporting the porous film 7 is lost in the region where the distance between the wirings is wide, so that the mechanical strength is lowered. That is, the porous film 7 having low mechanical strength is deformed and destroyed. As a result, there is a problem that the yield of the semiconductor device is lowered, such as foreign matters entering the air gap 8 and unintended conduction between the wirings.

  In the conventional manufacturing method, the porous film 7 is formed on the upper surface of each wiring 6. For this reason, as shown in FIG. 8, the oxidizing substance diffuses inside the porous film 7 and the wiring 6 is oxidized. As a result, the yield of the semiconductor device such as the resistance of the wiring 6 increases. There is also a problem that it falls.

  The present invention solves the above-described conventional problems, and an object of the present invention is to provide a semiconductor device having a wiring structure in which the yield can be reduced and the inter-wiring capacitance can be sufficiently reduced in practice.

  In order to achieve the above object, according to the present invention, a semiconductor device is configured such that a gap (air gap) formed between wirings in an insulating film is formed deeper than the bottom of the wiring.

  Specifically, a semiconductor device according to the present invention includes a first insulating film formed on a semiconductor substrate, and a plurality of conductive members formed in a plurality of grooves formed in the first insulating film. And a gap formed by removing the first insulating film is selectively formed between adjacent wirings of the plurality of wirings in the first insulating film, and a lower end of the gap is formed. The position of the part is lower than the position of the lower end part of each wiring.

  According to the semiconductor device of the present invention, the position of the lower end portion of the gap portion that is selectively formed between adjacent wires of the plurality of wires in the first insulating film is lower than the position of the lower end portion of each wire. For this reason, most of the lines of electric force between the adjacent wirings pass through the gap, so that the capacity between the wirings can be sufficiently reduced in practice.

  In the semiconductor device of the present invention, it is preferable that the width of the lower end portion and the width of the upper end portion in the gap portion are the same as the interval between wirings adjacent to the gap portion.

  In the semiconductor device of the present invention, it is preferable that the gap is formed in a region excluding a region where the interval between the plurality of wirings in the first insulating film is the largest.

  In the semiconductor device of the present invention, the dielectric constant of the lower portion of the gap in the first insulating film is preferably lower than the dielectric constant of the lower portion of the wiring in the first insulating film.

  In the semiconductor device of the present invention, it is preferable that a dummy via is formed in the first insulating film.

  The semiconductor device of the present invention preferably further includes a protective film formed on the first insulating film so as to cover each wiring and the gap.

  In the semiconductor device of the present invention, the protective film is preferably a single layer film made of SiCN or SiCO, or a laminated film of SiCN and SiCO.

  The semiconductor device of the present invention further includes a second insulating film formed on the protective film, and the second insulating film includes a via selectively connected to any of the plurality of wirings and the plurality of wirings. It is preferable that a dummy via that is not connected to any of the first and second layers is formed, and the dummy via reaches the first interlayer insulating film.

  In this case, it is preferable that the minimum value of the gap between the dummy via and the gap is set to a value that is a quarter of the sum of the minimum diameter of the dummy via and the minimum width of the gap.

  Further, in this case, the maximum value of the distance between the dummy via and the gap is preferably set to the sum of the minimum diameter of the dummy via and the minimum width of the gap.

  Further, in this case, it is preferable that the minimum value of the distance between the dummy via and the wiring is set to a value that is a quarter of the sum of the minimum diameter of the dummy via and the minimum width of the wiring.

  The semiconductor device of the present invention preferably further includes a cap film formed on and in contact with each wiring on the plurality of wirings.

  In this case, the cap film is made of Co, Mn, W, Ta, or Ru, or an alloy containing one or more metals selected from Co, Mn, W, Ta, and Ru, or Co, Mn, W, Ta, or Ru. The cap film is preferably made of Ru oxide or CuSiN and has conductivity.

  The method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first insulating film on a semiconductor substrate, and a plurality of wiring forming groove portions formed on the first insulating film, thereby forming the wiring A step (b) of forming a plurality of wirings by embedding a conductive film in the forming groove, and a step (c) of selectively forming a gap forming groove between the wirings in the first insulating film; A step (d) of forming a sacrificial film in the gap forming groove, a step (e) of forming a protective film on the first insulating film so as to cover each wiring and the sacrificial film, and a sacrifice from the gap forming groove A step (f) of forming a gap between the wirings in the first insulating film by removing the film, and in step (c), the position of the lower end of the gap forming groove is the lower end of the wiring The gap forming groove is formed so as to be lower than the position of the portion.

  According to the method for manufacturing a semiconductor device of the present invention, the gap forming groove is formed in the first insulating film so that the position of the lower end of the gap forming groove is lower than the position of the lower end of the wiring. Since most of the lines of electric force between the adjacent wirings pass through the gap, the capacity between the wirings can be sufficiently reduced in practical use.

  In the method for manufacturing a semiconductor device of the present invention, in the step (f), the sacrificial film is preferably decomposed and removed by heating.

  In the method for manufacturing a semiconductor device of the present invention, in the step (f), it is preferable that the width of the lower end portion and the width of the upper end portion in the gap portion are the same as the interval between the wiring adjacent to the gap portion. .

  In the method for manufacturing a semiconductor device of the present invention, in the step (c), the gap forming groove is preferably formed in a region excluding a region where the interval between the plurality of wirings in the first insulating film is the largest.

  In the method of manufacturing a semiconductor device according to the present invention, in step (f), the dielectric constant of the lower portion of the gap in the first insulating film is lower than the dielectric constant of the lower portion of the wiring in the first insulating film. It is preferable.

  The semiconductor device manufacturing method of the present invention includes a step (g) of forming a second insulating film on the protective film between the step (e) and the step (f), and after the step (g). The via is selectively formed so as to be connected to any of the plurality of wirings through the second insulating film and the protective film, and any of the plurality of wirings through the second insulating film and the protective film. And a step (h) of forming a dummy via so as not to be connected to each other, and the dummy via preferably reaches the first interlayer insulating film.

  The method for manufacturing a semiconductor device according to the present invention further includes a step (i) of forming a cap film on the plurality of wirings so as to be in contact with each wiring between the steps (b) and (c). It is preferable to provide.

  In this case, the cap film is made of Co, Mn, W, Ta, or Ru, or an alloy containing one or more metals selected from Co, Mn, W, Ta, and Ru, or Co, Mn, W, Ta, or Ru. The cap film is preferably made of Ru oxide or CuSiN and has conductivity.

  According to the semiconductor device and the method for manufacturing the same according to the present invention, it is possible to realize a semiconductor device having a wiring structure in which the yield is not lowered and the inter-wiring capacitance can be sufficiently reduced practically.

(One embodiment)
A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional configuration of a main part of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 1, for example, a first interlayer insulating film 101 made of SiOC having a dielectric constant lower than that of silicon oxide (SiO ₂ ) is formed on the main surface of a semiconductor substrate 100 made of silicon (Si). A plurality of lower wirings 105 are formed on the first interlayer insulating film 101 so as to be spaced apart from each other. Each lower wiring 105 includes a barrier film 103 in which, for example, tantalum (Ta) and tantalum nitride (TaN) are stacked in this order on a side surface and a bottom surface, and a copper film 104 formed inside thereof. Note that although SiOC is used for the first interlayer insulating film 101, it is not limited to SiOC, and a porous insulating film having a relatively low dielectric constant can be used. In addition, although not shown, a plurality of semiconductor elements such as transistors and resistors are formed on the semiconductor substrate 100.

  A gap (air gap) 101c formed by removing the first interlayer insulating film 101 is selectively formed between the lower wirings 105 which are part of the plurality of lower wirings 105 and are adjacent to each other. Has been. Here, as a feature of this embodiment, the position of the lower end of the gap 101c is lower than the position of the lower end of the lower wiring 105, and the width of the lower end and the upper end of the gap 101c are lower. The interval between the wirings 105 is the same. The first interlayer insulating film is formed on the side surface and the bottom surface of each gap portion 101c by etching a sacrificial film filling groove portion for forming the gap portion 101c in the first interlayer insulating film 101. A modified layer 101B is formed by modifying a damaged layer generated on the bottom surface and the wall surface of the groove portion in 101. The damage layer 101A and the modified layer 101B will be described later.

On the first interlayer insulating film 101, for example, SiCN and SiCO are laminated in this order so as to cover the respective lower wirings 105 and the respective gaps 101c, thereby preventing diffusion of copper into the insulating film. A liner film 110 as a protective film is formed. A second interlayer insulating film 111 made of SiOC is formed on the liner film 110. Here, the difference between SiOC and SiCO is that SiOC is based on the Si—O skeleton, and —CH ₃ group is bonded to the Si—O skeleton. On the other hand, SiCO is based on Si, and O is bonded to the base Si. SiOC in which —CH ₃ groups are bonded to the Si—O skeleton has a lower density than SiCO due to the difference in skeleton base.

  In the second interlayer insulating film 111, an upper wiring 118 made of a barrier film 116 and a copper film 117 having the same configuration as the lower wiring 105 is selectively formed. The lower wiring 105 and the upper wiring 118 are electrically connected through a through hole that selectively penetrates the second interlayer insulating film 111 and the liner film 110. The second interlayer insulating film 111, the liner film 110, and the first interlayer insulating film 101 are formed with dummy vias 118A that are not connected to any of the lower wirings 105. The dummy vias 118A are connected to the first interlayer insulating film. It has reached 101.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to the drawings.

  2 (a) to 2 (g) and FIGS. 3 (a) to 3 (e) show cross-sectional structures in order of steps of a method for manufacturing a main part of a semiconductor device according to an embodiment of the present invention. .

  First, as shown in FIG. 2A, a first SiOC layer is formed on a main surface of a semiconductor substrate (not shown) on which a plurality of semiconductor elements are formed by, for example, chemical vapor deposition (CVD). An interlayer insulating film 101 is deposited.

  Next, as shown in FIG. 2B, a plurality of wiring trenches 101a for forming a lower wiring spaced apart from each other are selectively formed in the first interlayer insulating film 101 by lithography and dry etching. .

  Next, as shown in FIG. 2C, the barrier film 103 and the copper film made of Ta / TaN are formed on the entire surface including the wiring trenches 101a on the first interlayer insulating film 101 by sputtering and plating. 104 are sequentially deposited. Thereafter, the barrier film 103 and the copper film 104 deposited in the region excluding the wiring trench 101a on the first interlayer insulating film 101 are removed by a chemical mechanical polishing (CMP) method, so that the side surface and the bottom surface are the barrier film. A lower wiring 105 covered with 103 and made of a copper film 104 is formed. In this embodiment, a stacked film of Ta and TaN is used for the barrier film 103, but either the Ta film or the TaN film may be used. Further, although copper (Cu) is used for the conductive film embedded in the wiring groove 101a, the conductive film is not limited to copper, and silver (Ag), aluminum (Al), an alloy thereof, or the like can be used.

  Next, as shown in FIG. 2D, the first interlayer insulating film 101 between some of the plurality of lower wirings 105 is selected on the first interlayer insulating film 101 by lithography. A resist pattern 106 having an opening pattern is formed. A preferable shape of the resist pattern 106 will be described later.

Next, as shown in FIG. 2E, a part of the first interlayer insulating film 101 is removed by dry etching using a fluorocarbon (CF) gas, using the resist pattern 106 as a mask. Then, the gap forming groove 101b is formed. At this time, dry etching conditions are set so that the height of the bottom surface of the gap forming groove 101b from the substrate surface is lower than the height of the bottom surface of the lower wiring 105 from the substrate surface. Note that the barrier film 103 and the copper film 104 remain without being etched because the vapor pressure of fluoride is low. Further, as a side effect of this etching, a part of the Si—CH ₃ bond included in the first interlayer insulating film 101 is replaced by the Si—OH bond, so that damage is caused on the bottom surface and the wall surface of the gap forming groove portion 101b. Layer 101A is formed.

  Next, as shown in FIG. 2F, a polymer sacrificial film 109 is applied on the first interlayer insulating film 101 over the entire surface including the lower wirings 105 and the gap forming grooves 101b. Thereafter, the sacrificial film 109 formed in a region on the first interlayer insulating film 101 except for the gap forming groove 101b is removed by CMP to bury the sacrificial film 109 in the gap forming groove 101b. Note that preferable characteristics (physical properties) and preferable materials of the sacrificial film 109 will be described later.

  Next, as shown in FIG. 2G, a SiCN film and a SiCO film are sequentially deposited on the entire surface including the lower wiring 105 and the sacrificial film 109 on the first interlayer insulating film 101 by the CVD method. A liner film 110 is formed.

  Next, as shown in FIG. 3A, a second interlayer insulating film 111 made of SiOC is deposited on the liner film 110 by a CVD method.

  Next, as shown in FIG. 3B, a plurality of wiring trenches 111a for forming an upper wiring spaced apart from each other are selectively formed in the second interlayer insulating film 111 by lithography and dry etching. To do. At this time, the liner film 110 is removed in a part of the wiring trench 111a, thereby exposing the lower wiring 105 thereunder to form a via hole 111b. Further, a dummy via hole 111c is also formed at a position where the lower wiring 105 is not exposed. Therefore, the dummy via formed by burying the conductive film in the dummy via hole 111 c is not connected to the lower wiring 105. That is, the dummy via does not function as an electric circuit. Further, the bottom of the dummy via hole 111 c reaches the first interlayer insulating film 101. A preferred arrangement method of the dummy via holes 111c will be described later.

Next, as shown in FIG. 3C, the semiconductor substrate is heated to decompose and remove the sacrificial film 109 embedded in the gap forming groove 101b. As a result, a gap 101 c is formed between the lower wirings 105. At this time, as a result of part of the Si—OH bonds included in the damaged layer 101A being replaced by Si—CH ₃ bonds, the damaged layer 101A changes to the modified layer 101B. The phenomenon that the damaged layer 101A changes to the modified layer 101B will be described in detail later. A part of the decomposition product of the sacrificial film 109 diffuses through the damaged layer 101A and the first interlayer insulating film 101 and is discharged to the outside through the dummy via hole 111c.

  Next, as shown in FIG. 3 (d), Ta / TaN is formed on the entire surface including the wiring trenches 111a, the via holes 111b and the dummy via holes 111c on the second interlayer insulating film 111 by sputtering and plating. A barrier film 116 and a copper film 117 are sequentially deposited. Thereafter, by removing the barrier film 116 and the copper film 117 deposited in a region excluding the wiring trench 111a, the via hole 111b, and the dummy via hole 111c on the second interlayer insulating film 111 by the CMP method, the side surface and the bottom surface are removed. An upper wiring 118 covered with the barrier film 116 and made of the copper film 117 is formed.

  Next, as shown in FIG. 3E, the multilayer wiring structure 120 can be formed by sequentially repeating the steps of FIGS. 2G to 3D.

  Thus, according to the semiconductor device and the manufacturing method thereof of the present embodiment, for example, the position of the bottom surface of the gap (air gap) 101 c is lower than the position of the bottom surface of the lower wiring 105. For this reason, since most of the electric lines of force between the lower wirings 105 pass through the gap 101c, there is a first effect that the inter-wiring capacitance between the lower wirings 105 can be made sufficiently low in practice.

  Further, according to the present embodiment, for example, in the region where the interval between the lower wirings 105 is wide, the gap 101c can be prevented from being formed. For this reason, there exists a 2nd effect that the deformation | transformation or destruction of the film | membrane formed so that the cavity part 101c may be block | closed, ie, the porous film of a prior art example, or the liner film | membrane 110 of this embodiment can be suppressed.

  Further, according to the present embodiment, since the liner film 110 is deposited instead of the porous film 7 on the upper surface of the lower wiring 105 and the like, the third wiring that can suppress the oxidation of the lower wiring 105 due to the diffusion of the oxidizing substance. It also has an effect.

  Note that a method for manufacturing a semiconductor device that selectively exhibits one of the first effect and the second effect may be used. That is, in this embodiment, a porous film may be used instead of the liner film 110 as the film formed so as to close the air gap. In this case, it is not necessary to form the dummy via hole 111c, but the third effect cannot be obtained. However, when giving priority to the first effect and the second effect, such a method of manufacturing a semiconductor device may be used. However, the third effect can be obtained by using the liner film 110 as a film formed so as to close the gap 101c and forming the gap 101c by forming the dummy via hole 111c. Needless to say, it is more desirable.

  Further, between the step shown in FIG. 2C and the step shown in FIG. 2D (between the step shown in FIG. 2E and the step shown in FIG. 2F, or FIG. 2F). It is desirable to form a cap film on the lower wiring 105 so as to be in contact with the lower wiring 105 between the process shown in FIG. 2 and the process shown in FIG. Thus, for example, by forming a cap film on the lower wiring 105, the lower wiring 105 is exposed to a severe situation caused by dry etching, and a situation can be prevented. Here, as the cap film, one or more selected from cobalt (Co), manganese (Mn), tungsten (W), tantalum (Ta) or ruthenium (Ru), or Co, Mn, W, Ta and Ru. It is necessary that the cap film be made of an alloy containing any of these metals, an oxide of Co, Mn, W, Ta, or Ru, or copper-added silicon nitride (CuSiN).

  In addition, the dummy via hole 111c is formed after the second interlayer insulating film 111 is formed, but the dummy via hole 111c is formed after the liner film (protective film) 110 is formed and before the second interlayer insulating film 111 is formed. Only 111 c may be formed on the first interlayer insulating film 101 and the liner film 110. Even in this case, after the dummy via hole 111c is formed and before the second interlayer insulating film 111 is formed, a part of the decomposition product of the sacrificial film 109 is removed from the damage layer 101A and the first interlayer insulating film. By diffusing to 101, it can be discharged to the outside through the dummy via hole 111c.

  Hereinafter, a specific method of forming the resist pattern 106 in the step shown in FIG. 2D will be described with reference to FIGS. 4A to 4D. The shape of the resist pattern 106 is preferably determined by the following procedure.

  First, as shown in FIG. 4A, an area where the interval between the lower wirings 105 is larger than Smax is extracted from the arrangement information of the lower wirings 105, and the extracted graphic set is A.

  Next, as shown in FIG. 4B, each side of each figure included in the figure set A is moved in the outward direction of the figure set A by ΔS. As a result, the area occupied by the graphic set A is enlarged, and the enlarged graphic set is designated as B.

  Next, as shown in FIG. 4C, via hole formation regions are extracted from the arrangement information of the via holes 111b, and each via hole formation region is moved by ΔΦ toward the outside of the extracted via hole formation region. A figure set C is created by enlarging the area occupied by the formation area.

  Next, as shown in FIG. 4D, the union of the graphic set B and the graphic set C is taken to obtain a graphic set D.

  By the above method, a resist pattern 106 having an opening pattern is formed in a region excluding the figure set D.

  Here, it is preferable to set Smax to be about three times the minimum value of the interval between adjacent wirings among the plurality of lower wirings 105. By setting Smax in this way, a gap (air gap) is formed between the wirings only in a region where the distance between the lower wirings 105 is narrow. For example, the capacitance between the wirings of the lower wiring 105 can be reliably reduced. it can. Further, in a region where the interval between the adjacent lower wirings 105 is larger than Smax, the first interlayer insulating film 101 remains without forming a gap between the wirings. As a result, the mechanical strength of the multilayer wiring structure 120 can be increased. That is, it is possible to realize a multilayer wiring structure in which the inter-wiring capacitance is sufficiently low in practical use and the mechanical strength is sufficiently high in practical use.

  Further, ΔS is preferably set to about half of the wiring having the smallest wiring width among the plurality of lower wirings 105. By setting ΔS in this way, the gap forming groove portion 101b can be formed in a self-aligning manner using the lower wiring 105 and the resist pattern 106 as a mask. For this reason, even if an error occurs in dimensions when performing the lithography method and the etching method, the shape of the multilayer wiring structure 120 is hardly affected. As a result, since the dimensional accuracy of lithography for forming the resist pattern 106 can be set low, the cost for manufacturing a semiconductor device can be kept low.

  ΔΦ is preferably set to a value of (minimum width of the gap forming groove portion 101b + minimum diameter of the via hole 111b) / 4. When ΔΦ becomes smaller than this set value, it is caused by variations in the finish of each process, that is, dimensional variation of the gap forming groove portion 101b, dimensional variation of the dummy via hole 111c, misalignment between the gap forming groove portion 101b and the via hole 111b, and the like. This is because the gap forming groove portion 101b and the via hole 111b may be connected to each other. When the gap forming groove 101b and the via hole 111b are connected, the barrier film 116 or the copper film 117 enters the inside of the gap 101c in the step shown in FIG. Since conduction is caused, the yield of the semiconductor device is reduced.

  Next, a preferred arrangement method of the dummy via holes 111c will be described.

  First, it is preferable that the dummy via hole 111 c is disposed not on the sacrificial film 109 but on the first interlayer insulating film 101, the liner film 110 formed on the upper side, and the second interlayer insulating film 111. This is because if the dummy via hole 111c is disposed on the upper side of the sacrificial film 109, the barrier film 116 or the copper film 117 enters the gap 101c in the step shown in FIG.

  Further, the lower limit of the distance X between the side of the dummy via hole 111c close to the gap forming groove 101b and the side of the gap forming groove 101b close to the dummy via hole 111c is (the minimum diameter of the dummy via hole 111c + the gap forming groove 101b). It is preferable to set a value of (minimum width) / 4.

  This is because when the distance X between the side of the dummy via hole 111c close to the gap forming groove 101b and the side of the gap forming groove 101b close to the dummy via hole 111c is smaller than the above set value, the variation in the finish of each process, That is, there is a risk that the dummy via hole 111c and the gap forming groove 101b may be connected due to a dimensional change of the dummy via hole 111c, a dimensional change of the gap forming groove 101b, and a misalignment between the dummy via hole 111c and the gap forming groove 101b. Because there is.

  Further, the upper limit of the distance X between the side of the dummy via hole 111c close to the gap forming groove 101b and the side of the gap forming groove 101b close to the dummy via hole 111c (the minimum diameter of the dummy via hole 111c + the gap forming groove 101b) It is preferable to set a value of (minimum width).

  This is because, when the distance X between the side of the dummy via hole 111c close to the gap forming groove 101b and the side of the gap forming groove 101b close to the dummy via hole 111c is larger than the set value, the gap forming groove 101b and the dummy The distance from the via hole 111c is too large. As a result, the decomposition product of the sacrificial film 109 is not easily discharged to the outside through the dummy via hole 111c, and the thermal decomposition of the sacrificial film 109 may not proceed sufficiently. That is, the dummy via hole 111c needs to be formed at such a distance that the thermal decomposition of the sacrificial film 109 proceeds sufficiently.

  The lower limit of the distance Y between the side of the dummy via hole 111c near the lower wiring 105 and the side of the lower wiring 105 near the dummy via hole 111c is (minimum diameter of the dummy via hole 111c + minimum width of the lower wiring 105) / A value of 4 is preferably set.

  This is because when the distance Y between the side of the dummy via hole 111c close to the gap forming groove 101b and the side of the lower wiring 105 close to the dummy via hole 111c becomes smaller than the above set value, the variation in the finish of each process, that is, the dummy Due to dimensional variation of the via hole 111c, dimensional variation of the lower wiring 105, misalignment between the dummy via hole 111c and the lower wiring 105, etc., the dummy via hole 111c and the lower wiring 105 are connected to each other, causing malfunction of the semiconductor device. Because there is a fear.

  The upper and lower limits of the distance X and the lower limit of the distance Y described above are desirable values, and are not limited to these due to design circumstances.

Next, the effect of changing the damaged layer 101A to the modified layer 101B will be described. As already described, in the damaged layer 101A, a part of Si—CH ₃ bonds contained in SiOC is replaced with Si—OH bonds. Accordingly, the damaged layer 101A has intermediate properties between SiOC and SiO _2, it is larger than the SiOC in terms of dielectric constant. For this reason, if the damaged layer 101A is left as it is, a problem arises in that the inter-wiring capacitance of the lower wiring 105 and the like increases. Therefore, as described above, the Si—OH bond contained in the damaged layer 101A is replaced with Si—CH ₃ again to be changed to the modified layer 101B closer to SiOC, so that the wiring between the lower wiring 105 and the like can be changed. It is preferable to keep the capacity low.

  In the above layout, the first interlayer insulating film 101 including the lower wiring 105 and the via hole 111b and the dummy via hole 111c formed in the second interlayer insulating film 111 on the first interlayer insulating film 101 have been described. The same applies to the upper wiring 118 formed in the second interlayer insulating film 111 and the upper via holes and dummy via holes connected to the upper wiring 118.

  Next, characteristics required for the sacrificial film 109 and preferable materials will be described. As is clear from the above description, the characteristics required for the sacrificial film 109 are the following two points. First, the void 101c can be formed by decomposition by heating, and secondly, the decomposition product can change the damaged layer 101A to the modified layer 101B.

Therefore, it is preferable to use a crosslinkable polymer having a functional group as shown in [Chemical Formula 1] or [Chemical Formula 2] as the material of the sacrificial film 109. Examples of [Chemical Formula 1] and [Chemical Formula 2] include hexamethyldisilazane {(CH ₃ ) ₃ Si—NH—Si (CH ₃ ) ₃ }.

  It is known that a crosslinkable polymer having an appropriately designed structure decomposes at a temperature of 300 ° C to 400 ° C. Moreover, when a functional group as shown in [Chemical Formula 1] or [Chemical Formula 2] is added, a substance such as [Chemical Formula 3] or [Chemical Formula 4] is generated by thermal decomposition.

This is because the substance having the structure shown in [Chemical Formula 3] has an action of substituting the Si—OH group for the Si—CH ₃ group by the reaction shown in [Chemical Formula 5]. This is because the substance having the structure shown has the effect of substituting the Si—OH group for the Si—CH ₃ group by the reaction shown in [Chemical Formula 6].

  In addition, (s) attached | subjected to the chemical formula of [Chemical Formula 5] and [Chemical Formula 6] represents a solid phase, and (g) represents a gas phase.

  The semiconductor device and the manufacturing method thereof according to the present invention can realize a semiconductor device having a wiring structure in which the yield is not lowered and the inter-wiring capacitance can be sufficiently reduced in practice, and in particular, a semiconductor device having a multilayer wiring structure and It is useful for its manufacturing method.

1 is a structural cross-sectional view showing a main part of a semiconductor device according to an embodiment of the present invention. (A)-(g) is the structure sectional drawing of the order of a process which shows the manufacturing method of the principal part of the semiconductor device which concerns on one Embodiment of this invention. (A)-(e) is the structure sectional drawing of the order of a process which shows the manufacturing method of the principal part of the semiconductor device which concerns on one Embodiment of this invention. It is a top view of the order of a process which shows the formation method of the mask pattern at the time of forming the groove part for space | gap formation in the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is the structure sectional drawing of the order of a process which shows the manufacturing method of the wiring of the conventional semiconductor device which has an air gap. It is typical sectional drawing which shows the electric force line between wiring at the time of using the formation method of the wiring in the conventional semiconductor device. It is typical sectional drawing explaining the problem at the time of using the formation method of the wiring in the conventional semiconductor device. It is typical sectional drawing explaining the other problem at the time of using the formation method of the wiring in the conventional semiconductor device.

Explanation of symbols

100 Semiconductor Substrate 101 First Interlayer Insulating Film 101a Wiring Groove 101b Gap Formation Groove 101c Gap (Air Gap)
101A Damaged layer 101B Modified layer 103 Barrier film 104 Copper film 105 Lower wiring 106 Resist pattern 107 Sacrificial film 110 Liner film (protective film)
111 Second interlayer insulating film 111a Wiring groove 111b Via hole 111c Dummy via hole 116 Barrier film 117 Copper film 118 Upper wiring 118A Dummy via 120 Multilayer wiring structure

Claims (21)

A first insulating film formed on the semiconductor substrate;
A plurality of wirings made of a conductive member formed in a plurality of grooves formed in the first insulating film,
A gap formed by removing the first insulating film is selectively formed between adjacent wirings of the plurality of wirings in the first insulating film,
The position of the lower end part of the said cavity part is lower than the position of the lower end part of each said wiring, The semiconductor device characterized by the above-mentioned.   2. The semiconductor device according to claim 1, wherein a width of a lower end portion and a width of an upper end portion in the gap portion are the same as an interval between wirings adjacent to the gap portion.   3. The semiconductor device according to claim 1, wherein the gap is formed in a region excluding a region where the interval between the plurality of wirings in the first insulating film is the largest.   4. The dielectric constant of the lower portion of the gap in the first insulating film is lower than the dielectric constant of the lower portion of the wiring in the first insulating film. 2. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein a dummy via is formed in the first insulating film.   5. The semiconductor device according to claim 1, further comprising a protective film formed on the first insulating film so as to cover the wirings and the gaps. 6. .   The semiconductor device according to claim 6, wherein the protective film is a single layer film made of SiCN or SiCO, or a laminated film of SiCN and SiCO. A second insulating film formed on the protective film;
The second insulating film is formed with a via that is selectively connected to any of the plurality of wirings and a dummy via that is not connected to any of the plurality of wirings. The semiconductor device according to claim 6, wherein the semiconductor device reaches the interlayer insulating film.   The minimum value of the gap between the dummy via and the gap is set to a value that is a quarter of the sum of the minimum diameter of the dummy via and the minimum width of the gap. 8. The semiconductor device according to 8.   9. The maximum value of the gap between the dummy via and the gap is set to a sum of the minimum diameter of the dummy via and the minimum width of the gap. Semiconductor device.   The minimum value of the interval between the dummy via and the wiring is set to a value that is a quarter of the sum of the minimum diameter of the dummy via and the minimum width of the wiring. 10. The semiconductor device according to any one of 9 above.   The semiconductor device according to claim 1, further comprising a cap film formed on the plurality of wirings in contact with the wirings.   The cap film is made of Co, Mn, W, Ta or Ru, or an alloy containing one or more metals selected from Co, Mn, W, Ta and Ru, or oxidation of Co, Mn, W, Ta or Ru. The semiconductor device according to claim 12, wherein the cap film is made of a material or CuSiN and has conductivity. Forming a first insulating film on the semiconductor substrate (a);
A step (b) of forming a plurality of wirings by forming a plurality of wiring forming groove portions on the first insulating film and embedding a conductive film in the formed wiring forming groove portions;
A step (c) of selectively forming a gap forming groove between the wirings in the first insulating film;
Forming a sacrificial film in the gap forming groove (d);
Forming a protective film on the first insulating film so as to cover the wirings and the sacrificial film (e);
A step (f) of forming a void portion between the wirings in the first insulating film by removing the sacrificial film from the void forming groove portion,
In the step (c), the gap forming groove is formed so that the position of the lower end of the gap forming groove is lower than the position of the lower end of the wiring.   15. The method of manufacturing a semiconductor device according to claim 14, wherein in the step (f), the sacrificial film is decomposed and removed by heating.   16. In the step (f), a width of a lower end portion and a width of an upper end portion in the gap portion are formed so as to be the same as an interval between wirings adjacent to the gap portion. The manufacturing method of the semiconductor device as described in any one of.   17. The method according to claim 14, wherein, in the step (c), the gap forming groove is formed in a region excluding a region where the interval between the plurality of wirings in the first insulating film is the largest. Semiconductor device manufacturing method.   In the step (f), the dielectric constant of the lower part of the gap in the first insulating film is lower than the dielectric constant of the lower part of the wiring in the first insulating film. The manufacturing method of the semiconductor device of any one of Claims 13-16. Between the step (e) and the step (f),
Forming a second insulating film on the protective film (g);
After the step (g), a via is selectively formed so as to pass through the second insulating film and the protective film and to be connected to any of the plurality of wirings, and the second insulating film and the protective film are formed. And a step (h) of forming a dummy via so as not to be connected to any of the plurality of wirings through the film, and the dummy via reaches the first interlayer insulating film. A method for manufacturing a semiconductor device according to any one of claims 14 to 18.   The method further includes a step (i) of forming a cap film on the plurality of wirings so as to be in contact with the wirings between the step (b) and the step (c). A method for manufacturing a semiconductor device according to claim 14.   The cap film is made of Co, Mn, W, Ta or Ru, or an alloy containing one or more metals selected from Co, Mn, W, Ta and Ru, or oxidation of Co, Mn, W, Ta or Ru. 21. The method of manufacturing a semiconductor device according to claim 20, wherein the cap film is made of a material or CuSiN, and has a conductivity.

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