JP2009158633A - Nonvolatile semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify the structure of a nonvolatile semiconductor memory device. <P>SOLUTION: A floating gate 40 made of polysilicon is provided on a semiconductor substrate 20 through the medium of a gate insulator 30. A sidewall insulating film 50 is provided on each sidewall of the floating gate 40. A first impurity diffusion layer 60 is provided in the semiconductor substrate 20 separately apart from the floating gate 40 by a predetermined distance. A second impurity diffusion layer 70 is provided in the semiconductor substrate 20 to overlap with the floating gate 40. Electrons are injected into the floating gate 40 by applying a high voltage to the second impurity diffusion layer 70 in capacitive coupling with the floating gate 40. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  In recent years, with the expansion of application fields such as mobile phones and digital still cameras, electrically-programmable and erasable read-only memory devices (EEPROMs) are rapidly becoming popular. Among these, an EEPROM that can be erased collectively is called a flash EEPROM.

The EEPROM stores binary digital information of two or more values depending on whether or not a predetermined charge amount is accumulated in the floating gate, and the digital information is changed by changing the conduction of the channel region according to the charge amount. Is a non-volatile semiconductor storage device.
JP-A-7-249701

  In the conventional EEPROM, it is necessary to apply a voltage to the control gate in order to put charges in and out of the floating gate. For this reason, since a wiring for a control gate is required for each memory cell, the structure of the memory cell is complicated.

  Further, when a conventional EEPROM is manufactured, there is a problem in that an affinity with a logic process cannot be obtained because a process of manufacturing a control gate is essential. In particular, when the EEPROM is used for storing data of a small capacity of several bytes, it is necessary to carry out the EEPROM manufacturing process separately from the logic process, resulting in an increase in manufacturing cost.

  The present invention has been made in view of these problems, and an object thereof is to provide a technique for simplifying the structure of a nonvolatile semiconductor memory device. Another object of the present invention is to provide a technique for improving the affinity between a manufacturing process of a nonvolatile semiconductor memory device and a logic process and reducing a manufacturing cost of the nonvolatile semiconductor memory device.

  One embodiment of the present invention is a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device is provided in a semiconductor substrate having a first conductivity type semiconductor substrate, a gate insulating film provided on the semiconductor substrate, a floating gate provided on the gate insulating film, A first impurity diffusion layer of a second conductivity type opposite to the first conductivity type separated from the floating gate, and a second conductivity type provided in the semiconductor substrate and overlapping the floating gate; And a second impurity diffusion layer. In this aspect, by applying a high voltage to the second impurity diffusion layer at the time of writing, the second impurity diffusion layer and the floating gate are coupled, and electrons emitted from the first impurity diffusion layer are coupled to the floating gate. May be injected.

  According to this aspect, since it is possible to inject electrons into the floating gate by applying a high voltage to the second impurity diffusion layer coupled to the floating gate without using the control gate, the nonvolatile semiconductor memory device Further simplification of the structure can be achieved.

  In the above aspect, the electrons accumulated in the floating gate may be emitted by applying a high voltage to the first impurity diffusion layer at the time of erasing.

  Another aspect of the present invention is a method for manufacturing a nonvolatile semiconductor memory device. The manufacturing method of the nonvolatile semiconductor memory device includes a step of forming a floating gate on a first conductivity type semiconductor substrate via an insulating film, and a reverse of the first conductivity type in the semiconductor substrate on one side of the floating gate. A step of implanting a first impurity of the second conductivity type, which is a first conductivity type, a step of forming side wall insulating films on both side walls of the floating gate, A step of implanting a second impurity of the second conductivity type having a lower diffusion rate than the impurity; and thermally diffusing the first impurity so that the diffusion region of the first impurity in the surface direction of the semiconductor substrate becomes a floating gate. And a superimposing step.

  In the method for manufacturing the nonvolatile semiconductor memory device according to this aspect, since the control gate manufacturing process is unnecessary, the compatibility with the logic process is increased. As a result, since the nonvolatile semiconductor memory device can be manufactured in parallel with the logic process, the manufacturing cost of the nonvolatile semiconductor memory device can be reduced.

  In the manufacturing method of the above aspect, a P-type Si substrate may be used as the semiconductor substrate, and P and As may be used as the first impurity and the second impurity, respectively.

  A combination of the above-described elements as appropriate can also be included in the scope of the invention for which patent protection is sought by this patent application.

  According to the present invention, since electrons can be injected into the floating gate without using the control gate, the structure of the nonvolatile semiconductor memory device can be further simplified. In addition, since the affinity with the logic process is increased, the nonvolatile semiconductor memory device can be manufactured in parallel with the logic process, and the manufacturing cost of the nonvolatile semiconductor memory device can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a cross-sectional view showing a structure of a nonvolatile semiconductor memory device 10 according to the embodiment. The nonvolatile semiconductor memory device 10 is a memory cell including a semiconductor substrate 20, a gate insulating film 30, a floating gate 40, a sidewall insulating film 50, a first impurity diffusion layer 60, and a second impurity diffusion layer 70.

  A gate insulating film 30 is provided on the semiconductor substrate 20. As the semiconductor substrate 20, for example, a P-type Si substrate can be used. For example, a silicon oxide film can be used as the gate insulating film 30.

  A floating gate 40 is provided on the semiconductor substrate 20 via a gate insulating film 30. As the floating gate 40, for example, polysilicon can be used. Side wall insulating films 50 are respectively provided on both side walls of the floating gate 40. As the sidewall insulating film 50, for example, a silicon oxide film can be used.

  The first impurity diffusion layer 60 and the second impurity diffusion layer 70 are N + type diffusion layers.

  The first impurity diffusion layer 60 is provided in the semiconductor substrate 20 and is separated from the floating gate 40 by a predetermined distance. The distance between the first impurity diffusion layer 60 and the floating gate 40 is equal to the thickness of the bottom of the sidewall insulating film 50.

  The second impurity diffusion layer 70 is provided in the semiconductor substrate 20 and overlaps (overlaps) with the floating gate 40. The depth of the second impurity diffusion layer 70 is deeper than the depth of the first impurity diffusion layer 60.

  Note that the length of the second impurity diffusion layer 70 overlapping the floating gate 40 is such a length that a coupling capacitance between the second impurity diffusion layer 70 and the floating gate 40 can be sufficiently obtained, as will be described later. I just need it. However, when the second impurity diffusion layer 70 and the floating gate 40 are overlapped, it is necessary to prevent punch-through from occurring between the first impurity diffusion layer 60 and the second impurity diffusion layer 70. is there.

  Next, the operation of the nonvolatile semiconductor memory device 10 will be described with reference to FIGS.

(Write operation)
The write operation is performed in a state where electrons (charges) are released from the floating gate 40 by an erase operation described later. Specifically, as shown in FIG. 2A, when the first impurity diffusion layer 60 is set to a low voltage (for example, 0 V) and the second impurity diffusion layer 70 is set to a high voltage (for example, 10 V), A depletion layer 72 is formed in the channel region from the second impurity diffusion layer 70 toward the first impurity diffusion layer 60, and the electric field between the depletion layer 72 and the first impurity diffusion layer 60 is strengthened. As a result, hot electrons having energy exceeding the energy barrier of the gate insulating film 30 are generated in the vicinity of the first impurity diffusion layer 60. The hot electrons are attracted to the voltage (for example, 8 V) of the floating gate 40 capacitively coupled to the second impurity diffusion layer 70 and injected into the floating gate 40. As a result, the memory cell enters a write state, and the potential of the floating gate drops. Specifically, when the second impurity diffusion layer 70 is set to a low voltage, the potential of the floating gate 40 is lowered to a potential at which the interface of the semiconductor substrate 20 under the floating gate cannot be inverted.

(Erase operation)
By applying a high voltage (for example, 10 V) to the first impurity diffusion layer 60 and setting the second impurity diffusion layer 70 to a low voltage (for example, 0 V), depletion is caused in the vicinity of the first impurity diffusion layer 60. A layer 62 is formed, and electrons accumulated in the floating gate 40 are emitted to the depletion layer 62 through the gate insulating film 30 by the Fowler-Nordheim tunnel effect. As a result, the memory cell is erased, and the potential of the floating gate rises. Specifically, when the second impurity diffusion layer 70 is set to a low voltage, the potential of the floating gate 40 rises and rises to a potential at which the interface of the semiconductor substrate 20 under the floating gate is inverted.

(Read operation)
An intermediate voltage (for example, 5V) is applied to the first impurity diffusion layer 60, and the second impurity diffusion layer 70 is set to a low voltage (for example, 0V). At this time, when the memory cell is in the erased state, a current flows between the first impurity diffusion layer 60 and the second impurity diffusion layer 70. On the other hand, when the memory cell is in a write state, no current flows between the first impurity diffusion layer 60 and the second impurity diffusion layer 70. Based on this current, information stored in the floating gate 40 is read out. Note that a depletion layer exceeding the distance between the first impurity diffusion layer 60 and the floating gate 40 needs to be formed in the semiconductor substrate 20 by the voltage applied to the first impurity diffusion layer 60.

  In the nonvolatile semiconductor memory device 10 described above, it is only necessary to apply a high voltage to the second impurity diffusion layer 70 capacitively coupled to the floating gate 40 without using a control gate during a write operation. The cell structure can be simplified and miniaturized.

(Production method)
Next, a method for manufacturing the nonvolatile semiconductor memory device 10 will be described with reference to FIGS. The nonvolatile semiconductor memory device 10 can be performed in parallel with the manufacture of the MOSFET as will be described later.

  First, as shown in FIG. 3A, a semiconductor substrate 20 made of a P-type Si substrate is prepared in which elements are separated by a silicon oxide film 22 formed by a known STI (Shallow Trench Isolation) technique or the like.

  Next, as shown in FIG. 3B, a gate insulating film 30 made of a silicon oxide film is formed on the surface layer of the semiconductor substrate 20 by using a thermal oxidation method.

  Next, as shown in FIG. 3C, a polycrystalline silicon film 32 is formed on the gate insulating film 30. Note that the resistance value may be controlled by adding impurities such as B (boron) and P to the polycrystalline silicon film 32 during or after the formation of the polycrystalline silicon film 32.

  Next, as shown in FIG. 3D, the floating gate 40 and the gate electrode 100 are formed by selectively removing a predetermined region of the polycrystalline silicon film 32 using a photolithography method and a dry etching method. .

  Next, as shown in FIG. 4A, the second is performed using a mask (not shown) having an opening on one side of the floating gate 40 (in this embodiment, the side opposite to the gate electrode 100). P is ion-implanted into the impurity diffusion layer 70 as an N-type impurity. Further, As is implanted shallowly into the source region 104 and the drain region 106 on both sides of the gate electrode 100 using a mask (not shown).

  Next, a silicon oxide film (not shown) is deposited on the entire surface of the semiconductor substrate 20. Subsequently, as shown in FIG. 4B, the silicon oxide film is etched back by anisotropic dry etching, leaving the silicon oxide film only on both side walls of the floating gate 40 and the gate electrode 100. Thus, sidewall insulating films (sidewalls) 50 and 102 are formed on both side walls of the floating gate 40 and the gate electrode 100, respectively.

  Next, as shown in FIG. 4C, As is ion-implanted into the surface of the semiconductor substrate 20. As a result, As is added to the first impurity diffusion layer 60 and the second impurity diffusion layer 70 in self-alignment with the sidewall insulating film 50. A source region 104 and a drain region 106 are formed in self-alignment with the sidewall insulating film 102.

  Next, as shown in FIG. 5, the second impurity diffusion layer 70 is thermally diffused. Since the diffusion rate of P is faster than the diffusion rate of As, P mainly diffuses. Thereby, the second impurity diffusion layer 70 overlaps with the floating gate 40 in the plane direction of the semiconductor substrate 20 while the offset between the first impurity diffusion layer 60 and the floating gate 40 is maintained. Further, the depth of the second impurity diffusion layer 70 is deeper than the depth of the first impurity diffusion layer 60.

  Through the above process, the nonvolatile semiconductor memory device 10 and the MOSFET 190 are manufactured. Since the manufacturing process of the nonvolatile semiconductor memory device 10 is highly compatible with the manufacturing process of the MOSFET 190, the nonvolatile semiconductor memory device 10 and the MOSFET 190 can be manufactured in parallel, and the number of manufacturing process steps can be reduced and simplified. Can be achieved. In particular, when the nonvolatile semiconductor memory device 10 is used for storing data of a small capacity of several bytes, it is not necessary to separately carry out a manufacturing process for the nonvolatile semiconductor memory device 10, which greatly contributes to a reduction in manufacturing cost.

  6A to 6C are circuit diagrams of nonvolatile semiconductor memory devices arranged in a matrix. The first impurity diffusion layer 60 of the nonvolatile semiconductor memory device 10 is connected to the source region 104 of the MOSFET 190. The second impurity diffusion layers 70 of the nonvolatile semiconductor memory devices 10 adjacent along the bit line 210 are each connected to the common source line 200. The drain region 106 of the MOSFET 190 is connected to the bit line 210, and the gate electrode 100 of the MOSFET 190 is connected to the word line 220.

  In the following description, the bit line 210 corresponding to the target cell 300 to which data is written or the like is referred to as a bit line 210a, and the bit line 210 not corresponding to the target cell 300 is referred to as a bit line 210b. Further, the word line 220 corresponding to the target cell 300 is called a word line 220a, and the word line 220 not corresponding to the target cell 300 is called a word line 220b.

  When a write operation is performed on the target cell 300, the bit line 210a is set to 0V, and the bit line 210b is set to 5V or open. Further, the word line 220a is set to 5V, and the word line 220b is set to 0V. The source line 200 is set to 10V. For the target cell 300, the MOSFET 190 is turned on, and the first impurity diffusion layer 60 of the nonvolatile semiconductor memory device 10 is set to 0V. On the other hand, the second impurity diffusion layer 70 of the nonvolatile semiconductor memory device 10 becomes 10V. Thereby, the state at the time of the write operation shown in FIG. 2A is obtained for the nonvolatile semiconductor memory device 10, and electrons are injected into the floating gate of the nonvolatile semiconductor memory device 10 of the cell 300 of interest.

  For cells other than the target cell 300, the MOSFET 190 is turned off, or a sufficient potential difference cannot be obtained between the first impurity diffusion layer 60 and the second impurity diffusion layer 70. Electron injection does not occur.

  When performing the erase operation on the target cell 300, the bit line 210a is set to 10V and the bit line 210b is opened. Further, the word line 220a is set to 12V, and the word line 220b is set to 0V. Further, the source line 200 is set to 0V. For the target cell 300, the MOSFET 190 is completely turned on, and 10 V is applied to the first impurity diffusion layer 60 of the nonvolatile semiconductor memory device 10. On the other hand, the second impurity diffusion layer 70 of the nonvolatile semiconductor memory device 10 becomes 0V. As a result, the state during the erase operation shown in FIG. 2B is obtained for the nonvolatile semiconductor memory device 10, and electrons are emitted from the floating gate of the nonvolatile semiconductor memory device 10 in the cell of interest 300.

  For cells other than the cell of interest 300, the MOSFET 190 is turned off or accumulated in the floating gate because a sufficient potential difference cannot be obtained between the first impurity diffusion layer 60 and the second impurity diffusion layer 70. Of emitted electrons does not occur.

  When a read operation is performed on the target cell 300, the bit line 210a is set to 5V and the bit line 210b is opened. Further, the word line 220a is set to 5V, and the word line 220b is set to 0V. Further, the source line 200 is set to 0V. For the target cell 300, the MOSFET 190 is turned on, and 5 V is applied to the first impurity diffusion layer 60 of the nonvolatile semiconductor memory device 10. On the other hand, the second impurity diffusion layer 70 of the nonvolatile semiconductor memory device 10 becomes 0V.

  Thereby, the state at the time of the read operation shown in FIG. 2C regarding the nonvolatile semiconductor memory device 10 is obtained. Therefore, when the accumulation of electrons in the floating gate of the nonvolatile semiconductor memory device 10 of the target cell 300 is insufficient, a current flows through the target cell 00. On the other hand, when the accumulation of electrons in the floating gate of the nonvolatile semiconductor memory device 10 of the target cell 300 is sufficient, no current flows through the target cell 300. By detecting this current, information stored in the target cell 300 can be read. Note that no current flows through other cells on the bit line 210a regardless of the presence or absence of electrons accumulated in the floating gate because the MOSFET 190 is in an off state.

  According to the arrangement of the nonvolatile semiconductor memory device described above, writing, erasing and reading can be performed only for the target cell.

  The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. The form can also be included in the scope of the present invention.

  In the above embodiment, the writing operation and the erasing operation can be repeated. However, the circuit can be simplified so that only the writing operation can be performed by setting the initial state to the erasing state by ultraviolet irradiation or the like. Thereby, it can be made to function as One-Time PROM (OTPROM).

It is sectional drawing which shows the structure of the non-volatile semiconductor memory device which concerns on embodiment. FIG. 2A illustrates a write operation of the nonvolatile semiconductor memory device according to the embodiment. FIG. 2B illustrates an erasing operation of the nonvolatile semiconductor memory device according to the embodiment. FIG. 2C illustrates a read operation of the nonvolatile semiconductor memory device according to the embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on embodiment. It is process sectional drawing which shows the manufacturing method of the non-volatile semiconductor memory device which concerns on embodiment. 6A to 6C are circuit diagrams of nonvolatile semiconductor memory devices arranged in a matrix.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Nonvolatile semiconductor memory device, 20 Semiconductor substrate, 30 Gate insulating film, 40 Floating gate, 50 Side wall insulating film, 60 1st impurity diffusion layer, 70 2nd impurity diffusion layer.

Claims (6)

A first conductivity type semiconductor substrate;
A gate insulating film provided on the semiconductor substrate;
A floating gate provided on the gate insulating film;
A first impurity diffusion layer of a second conductivity type provided in the semiconductor substrate and having a conductivity type opposite to the first conductivity type and spaced apart from the floating gate;
A second impurity diffusion layer of the second conductivity type provided in the semiconductor substrate and overlapping the floating gate;
A nonvolatile semiconductor memory device comprising:   At the time of writing, by applying a high voltage to the second impurity diffusion layer, the second impurity diffusion layer and the floating gate are coupled, and electrons emitted from the first impurity diffusion layer are floating. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is injected into a gate.   3. The nonvolatile semiconductor memory device according to claim 1, wherein electrons stored in the floating gate are emitted by applying a high voltage to the first impurity diffusion layer during erasing. 4. Side wall insulating films are further provided on both side walls of the floating gate,
4. The nonvolatile semiconductor memory according to claim 1, wherein a separation distance between the floating gate and the first impurity diffusion layer is equal to a thickness of a bottom portion of the sidewall insulating film. 5. apparatus. Forming a floating gate on the first conductivity type semiconductor substrate via an insulating film;
Injecting a first impurity of a second conductivity type, which is a conductivity type opposite to the first conductivity type, into the semiconductor substrate on one side of the floating gate;
Forming sidewall insulating films on both side walls of the floating gate;
Injecting a second impurity of the second conductivity type, which has a lower diffusion rate of thermal diffusion into the semiconductor substrate than the first impurity, in a region outside the sidewall insulating film;
Thermally diffusing the first impurity to overlap the diffusion region of the first impurity with the floating gate;
A method for manufacturing a nonvolatile semiconductor memory device.   6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 5, wherein a P-type Si substrate is used as the semiconductor substrate, and P and As are used as the first impurity and the second impurity, respectively. .

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