JP2009158607A - Semiconductor module and imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for facilitating operation test of individual semiconductor elements in a semiconductor module having a plurality of semiconductor elements. <P>SOLUTION: A semiconductor module 100 comprises a wiring board 110, and a first semiconductor element 120 and a fourth semiconductor element 170 mounted on the wiring board 110. A solder ball 160a is connected electrically with one of electrodes 122 for logic signal of the first semiconductor element 120. A solder ball 160b is connected electrically with one of electrodes for logic signal of the fourth semiconductor element 170. An electrode pad 210a corresponding to the solder ball 160a and an electrode pad 210b corresponding to the solder ball 160b are connected electrically by a third wiring layer 220 provided on a mounting board 200. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor module and an imaging device on which the semiconductor module is mounted.

  In recent years, with the downsizing and high functionality of electronic devices, there has been a demand for further downsizing and integration of semiconductor modules used in electronic devices. In order to meet such a demand, an MCM (multi-chip module) in which a plurality of semiconductor chips are mounted on a substrate has been developed.

  As a structure for mounting a semiconductor chip in the MCM, a multi-stage stack structure in which a plurality of semiconductor chips are stacked is known. In an MCM having a multi-stage stack structure, external electrodes are provided around each semiconductor chip, and each external electrode and an electrode pad on the substrate are electrically connected by a bonding wire.

Such an MCM is incorporated in, for example, a CCD camera, and each semiconductor chip is given a unique function. For example, a control circuit is incorporated in a semiconductor chip that functions as a logic element, and a circuit that supplies current to a motor that drives a CCD is incorporated in a semiconductor chip that functions as a driver element. In addition, the MCM is equipped with a memory element such as an EEPROM, and data necessary for camera shake correction control or the like is appropriately held in the memory element.
JP 2006-286824 A

  In an MCM on which a plurality of semiconductor chips and memory elements are mounted, the semiconductor chips or the semiconductor chips and the memory elements are electrically connected via a wiring layer provided on the mounting surface of the wiring board. For this reason, in order to perform an operation test of a semiconductor chip or a memory element in a state where the MCM is packaged, it is necessary to confirm the operation via another element connected to the target element. For example, when an operation test of a memory element is performed when a semiconductor chip (logic element) and a memory element are electrically connected on a wiring board, the semiconductor element must be operated. For this reason, the operation of the semiconductor chip has an influence on the result of the operation test of the memory element, and the process of the operation test needs to be corrected according to the semiconductor chip connected to the memory element.

  Further, the conventional MCM has a problem that once it is packaged, it becomes difficult to connect an external semiconductor chip to each semiconductor chip or memory element.

  The present invention has been made in view of such problems, and an object thereof is to provide a technique capable of easily performing an operation test of each semiconductor element in a semiconductor module having a plurality of semiconductor elements.

  One embodiment of the present invention is a semiconductor module. The semiconductor module includes a wiring board, a semiconductor element mounted on one main surface of the wiring board, another semiconductor element mounted on one main surface of the wiring board, and the other main surface of the wiring board. And when the external electrode is electrically connected to the mounting board on which the wiring board is mounted, the semiconductor element and other semiconductor elements are connected via the wiring provided on the mounting board. And electrically connected.

  According to this aspect, it is possible to connect an external semiconductor chip to the wiring provided on the mounting substrate. Thereby, for example, the operation test of the other semiconductor element can be performed without starting one semiconductor element at the time of product shipment.

  In the above aspect, when the external electrode is connected to the mounting substrate, the semiconductor element and another semiconductor element may be bus-connected. The semiconductor element may be a logic element, and the other semiconductor element may be a memory element.

  Another embodiment of the present invention is an imaging apparatus. The imaging apparatus includes the semiconductor module according to any one of the above-described aspects.

  ADVANTAGE OF THE INVENTION According to this invention, in the semiconductor module which has several semiconductor elements, the operation test of each semiconductor element can be performed easily.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same constituent elements are denoted by the same reference numerals, and detailed description thereof will be appropriately omitted in the following description.

  The semiconductor module according to the embodiment is suitably used for an imaging apparatus such as a digital camera having a camera shake correction function. FIG. 1 is a block diagram illustrating a circuit configuration of an imaging apparatus having a semiconductor module according to an embodiment. The digital camera includes a signal amplification unit 10 and a camera shake correction unit 20. The signal amplification unit 10 amplifies the input signal with a predetermined amplification factor and outputs the amplified signal to the camera shake correction unit 20. Based on the input angular velocity signal and lens position signal, the camera shake correction unit 20 controls the lens position and outputs a signal for performing camera shake correction to the signal amplification unit 10.

  Hereinafter, the circuit configuration of the digital camera will be described more specifically.

  The gyro sensor 50 detects the angular velocity in the XY biaxial directions of the digital camera. The analog angular velocity signal obtained by the gyro sensor 50 is amplified by the amplifier circuit 12 and then output to an ADC (analog / digital converter) 22. The ADC 22 converts the angular velocity signal amplified by the amplifier circuit 12 into a digital angular velocity signal. The angular velocity signal output from the ADC 22 is output to the gyro-equalizer 24.

  In the gyro-equalizer 24, first, a digital angular velocity signal output from the ADC 22 is input to an HPF (High Pass Filter) 26. The HPF 26 removes a frequency component lower than the frequency component due to camera shake from the angular velocity signal output from the gyro sensor 50. In general, since the frequency component due to camera shake is 1 to 20 Hz, for example, a frequency component of 0.7 Hz or less is removed from the angular velocity signal.

  The pan / tilt determination circuit 28 detects the pan operation and tilt operation of the imaging apparatus based on the angular velocity signal output from the HPF 26. When the imaging device is moved according to the movement of the subject, the gyro sensor 50 outputs an angular velocity signal corresponding to the movement. However, since the fluctuation of the angular velocity signal due to the pan operation or the tilt operation is not due to camera shake, it may not be necessary to correct the optical system such as the lens 60. The pan / tilt determination circuit 28 is provided to perform camera shake correction without depending on the fluctuation of the angular velocity signal due to the pan operation or the tilt operation. Specifically, the pan / tilt determination circuit 28 determines that the pan operation or the tilt operation is being performed when it is detected that the angular velocity signal becomes a predetermined value continuously for a certain period. Note that moving the imaging device in the horizontal direction in accordance with the movement of the subject is called a pan operation, and moving in the vertical direction is a tilt operation.

  The gain adjustment circuit 30 changes the amplification factor of the angular velocity signal output from the HPF 26 according to the determination result of the pan / tilt determination circuit 28. For example, when the pan operation or the tilt operation is not being performed, the gain adjustment circuit 30 adjusts the gain of the angular velocity signal output from the HPF 26. Further, during the pan operation or the tilt operation, the gain adjustment circuit 30 performs gain adjustment so that the intensity of the angular velocity signal output from the HPF 26 is attenuated and the output becomes zero.

  An LPF (low-pass filter) 32 serves as an integration circuit, and integrates the angular velocity signal output from the gain adjustment circuit 30 to generate an angle signal indicating the amount of movement of the imaging apparatus. For example, the LPF 32 obtains an angle signal, that is, an amount of movement of the imaging device by performing filter processing using a digital filter.

  The centering processing circuit 34 subtracts a predetermined value from the angle signal output from the LPF 32. When camera shake correction processing is performed in the imaging apparatus, the lens position gradually moves away from the reference position while the correction processing is continuously performed, and may reach the vicinity of the limit point of the movable range of the lens. At this time, if the camera shake correction process is continued, the lens can move in one direction but cannot move in the other direction. The centering processing circuit is provided to prevent this, and is controlled so as not to approach the limit point of the movable range of the lens by subtracting a predetermined value from the angle signal.

  The angle signal output from the centering processing circuit 34 is adjusted by the gain adjustment circuit 36 to the signal range of the Hall element 70. The angle signal adjusted by the gain adjustment circuit 36 is output to the hall equalizer 40.

  The Hall element 70 is a magnetic sensor that uses the Hall effect, and functions as a position detection unit of the lens 60 in the X and Y directions. The analog position signal including the position information of the lens 60 obtained by the Hall element 70 is amplified by the amplifier circuit 14 and then transmitted to the ADC 22. The ADC 22 converts the analog position signal amplified by the amplifier circuit 14 into a digital position signal. The ADC 22 converts the analog outputs of the amplifier circuit 12 and the amplifier circuit 14 into digital values in a time division manner.

  The position signal output from the ADC 22 is output to the hall equalizer 40. In the hall equalizer 40, first, the position signal output from the ADC 22 is input to the adder circuit 42. Further, the angle signal adjusted by the gain adjustment circuit 36 is input to the addition circuit 42. The adder circuit 42 adds the input position signal and angle signal. The signal output from the adder circuit 42 is output to the servo circuit 44. The servo circuit 44 generates a signal for controlling driving of a VCM (voice coil motor) 80 based on the signal output to the servo circuit 44. The current of the signal (VCM drive current) is generally 200 to 300 mA. In the servo circuit 44, filter processing using a digital filter for the servo circuit may be performed.

  The VCM drive signal output from the servo circuit 44 is converted from a digital signal to an analog signal by a DAC (digital analog converter) 46. The analog VCM drive signal is amplified by the amplifier circuit 16 and then output to the VCM 80. The VCM 80 moves the position of the lens 60 in the X and Y directions based on the VCM drive signal.

  Here, the operation of the circuit of the imaging device of this embodiment when there is no camera shake and when there is camera shake will be described.

(Operation when there is no camera shake)
When there is no camera shake, an angular velocity does not occur in the image pickup apparatus, so that the signal output from the gyro-equalizer 24 is “0”. The position of the lens 60 driven by the VCM 80 is such that its optical axis coincides with the center of an image pickup device (not shown) such as a CCD provided in the image pickup apparatus. , After being converted into a digital position signal indicating “0” by the ADC 22, it is output to the hall equalizer 40. When the value of the position signal is “0”, the servo circuit 44 outputs a signal for controlling the VCM 80 so as to maintain the current position of the lens 60.

  Further, when the position of the lens 60 and the center of the image sensor do not coincide, the analog position signal by the Hall element 70 and the amplifier circuit 14 is converted into a digital position signal indicating a value different from “0” by the ADC 22, It is output to the hall equalizer 40. The servo circuit 44 controls the VCM 80 so that the value of the position signal becomes “0” according to the value of the digital position signal output from the ADC 22.

  By repeating such an operation, the position of the lens 60 is controlled so that the position of the lens 60 and the center of the image sensor coincide with each other.

(Operation when there is camera shake)
Since the optical axis of the lens 60 driven by the VCM 80 coincides with the center of the image pickup device provided in the image pickup apparatus, the analog position signal from the Hall element 70 and the amplifier circuit 14 indicates “0” by the ADC 22. After being converted into a digital position signal, it is output to the hall equalizer 40.

  On the other hand, since the imaging apparatus moves due to camera shake, the LPF 32 and the centering processing circuit 34 output an angle signal indicating the movement amount of the imaging apparatus based on the angular velocity signal detected by the gyro sensor 50.

  The servo circuit 44 generates a VCM drive signal according to a signal obtained by adding the position signal indicating “0” output from the ADC 22 and the angle signal output from the centering processing circuit. At this time, although the position signal is “0”, since the angle signal that is not “0” is added, the servo circuit 44 generates a correction signal for moving the lens 60.

  The camera shake correction according to the present embodiment is not so-called electronic camera shake correction in which an image of a CCD is once read into a memory and an element of camera shake is excluded from comparison with the next image. Optical camera shake correction, such as a lens shift method for shifting the lens to a CCD or a CCD shift method for shifting a CCD.

  Therefore, there is a problem that arises when the electronic image stabilization mechanism is adopted, that is, there is a limit in the correction range and the imaging magnification due to the degradation of the image quality caused by trimming a large image in advance, or the limitation of the CCD size. The optical hand-shake correction can solve the problem and the problem that the touch of a still image of one frame cannot be corrected. In particular, when a still image is extracted from a high-definition video image, optical camera shake correction is effective.

  Since the VCM 80 moves the lens 60 based on the correction signal output from the servo circuit 44, the image pickup device provided in the image pickup apparatus can obtain a signal in which blurring of the subject due to camera shake is suppressed. By repeating such control, camera shake correction control is realized.

  FIG. 2 is a plan view showing a schematic configuration of the semiconductor module according to the embodiment. FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2, showing a schematic configuration of the semiconductor module according to the embodiment. In FIG. 2, a sealing resin 150 described later is omitted.

  The semiconductor module according to the embodiment will be described below with reference to FIGS. The semiconductor module 100 includes a wiring substrate 110, a first semiconductor element 120, a second semiconductor element 130, a third semiconductor element 140, a fourth semiconductor element 170, a sealing resin 150, and solder balls 160.

  The wiring board 110 has a first wiring layer 114 and a second wiring layer 116 with an insulating resin layer 112 interposed therebetween. The first wiring layer 114 and the second wiring layer 116 are electrically connected by a via 117 that penetrates the insulating resin layer 112. Solder balls 160 are connected to the second wiring layer 116.

  Examples of the material constituting the insulating resin layer 112 include thermosetting resins such as melamine derivatives such as BT resin, liquid crystal polymers, epoxy resins, PPE resins, polyimide resins, fluororesins, phenol resins, and polyamide bismaleimides. The From the viewpoint of improving the heat dissipation of the semiconductor module 100, the insulating resin layer 112 desirably has high thermal conductivity. For this reason, it is preferable that the insulating resin layer 112 contains silver, bismuth, copper, aluminum, magnesium, tin, zinc, alloys thereof, and the like as a high thermal conductive filler.

  An example of a material constituting the first wiring layer 114 and the second wiring layer 116 is copper.

  On the main surface S1 of the wiring board 110, the first semiconductor element 120 and the second semiconductor element 130 are mounted side by side. In addition, a third semiconductor element 140 is mounted so as to be stacked on the first semiconductor element 120. The first semiconductor element 120 is a logic element and corresponds to the camera shake correction unit 20 shown in FIG. The second semiconductor element 130 is a driver element or a power element, and corresponds to the signal amplification unit 10 shown in FIG. The third semiconductor element 140 is a flash memory. The third semiconductor element 140 assumes a part of the function of the first semiconductor element 120 or substitutes for the function of the first semiconductor element 120 as necessary. The fourth semiconductor element 170 is a memory element such as an EEPROM. The fourth semiconductor element 170 holds data or parameters necessary for camera shake correction control. The first semiconductor element 120, the second semiconductor element 130, the third semiconductor element 140, and the fourth semiconductor element 170 are sealed with a sealing resin 150 and packaged. The sealing resin 150 is formed by, for example, a transfer mold method.

  The first semiconductor element 120 is provided with a logic signal electrode 122 for inputting or outputting a logic signal. Examples of the logic signal input to the first semiconductor element 120 include the above-described angular velocity signal and position signal. The current of the logic signal is typically 2 mA. An example of the logic signal output from the first semiconductor element 120 is a camera shake correction signal. The logic signal electrode 122 is electrically connected to a substrate electrode 118a provided on the first wiring layer 114 via a bonding wire 124 such as a gold wire.

  The second semiconductor element 130 is provided with a current output electrode 132 for outputting a large current. A large current output from the second semiconductor element 130 includes a current (200 to 300 mA) for driving the VCM. The current output electrode 132 is electrically connected to the substrate electrode 118b provided on the first wiring layer 114 via a bonding wire 134 such as a gold wire. In addition to the current output electrode 132, the second semiconductor element 130 is provided with a chip electrode 136 used for input / output of signals with other semiconductor elements. The chip electrode 136 is electrically connected to the substrate electrode 118c provided on the first wiring layer 114 via a bonding wire 137 such as a gold wire. The connection by the bonding wires 124, 134, and 137 is performed after the first semiconductor element 120 is mounted on the wiring substrate 110 and the third semiconductor element 140 is mounted on the first semiconductor element 120. be able to.

  As shown in FIG. 2, when viewed from the main surface S1 side of the wiring substrate 110, the bonding wire 124 connected to the first semiconductor element 120 excludes the side F1 facing the side E1 of the second semiconductor element 130. , Crossing sides F2, F3 and F4, respectively. The logic signal electrode 122 is provided along the sides F2, F3, and F4.

  With respect to the second semiconductor element 130, the bonding wire 134 crosses the side other than the side E1 facing the side F1 of the first semiconductor element 120, that is, the side E2 adjacent to the side E1 in this embodiment. The current output electrode 132 is provided along the side E2.

  The chip electrode 136 is provided along each of the sides E1, E3, and E4, and the bonding wire 137 crosses the sides E1, E3, and E4.

  Note that the first semiconductor element 120 and the second semiconductor element 130 are installed at positions shifted from each other in the y-axis direction shown in FIG. In the present embodiment, the center position of the first semiconductor element 120 in the y-axis direction is closer to the center position of the wiring board 110. For this reason, the distance between the side E3 of the second semiconductor element 130 and the side G3 of the wiring board 110 is longer than the distance between the side E2 of the second semiconductor element 130 and the side G2 of the wiring board 110. ing. On the other hand, the distance between the side F2 of the first semiconductor element 120 and the side G2 of the wiring board 110 is equal to the distance between the side F3 of the first semiconductor element 120 and the side G3 of the wiring board 110.

  The third semiconductor element 140 is provided with an external electrode 142 that is electrically connected to the electrode pad 125 provided on the first semiconductor element 120 via a bonding wire 144. Thereby, the third semiconductor element 140 can transmit and receive signals to and from the first semiconductor element 120. In addition, the third semiconductor element 140 is provided with an external electrode 148 that is electrically connected to the substrate electrode 118 d provided on the first wiring layer 114 via the bonding wire 146.

  The fourth semiconductor element 170 is mounted side by side on the side E3 opposite to the side E2 on which the current output electrode 132 and the bonding wire 134 are provided. In other words, the current output electrode 132 and the bonding wire 134 of the second semiconductor element 130 cross the side of the second semiconductor element 130 different from the side on which the fourth semiconductor element 170 is provided. More preferably, the fourth semiconductor element 170 is provided in the vicinity of the corner of the wiring substrate 110 on the side opposite to the current output electrode 132 and the bonding wire 134 of the second semiconductor element 130.

  The fourth semiconductor element 170 is provided with a logic signal electrode 172 for inputting or outputting a logic signal. The logic signal electrode 172 is electrically connected to the substrate electrode 118e provided in the first wiring layer 114 via a bonding wire 174 such as a gold wire.

  According to the semiconductor module 100 described above, since the fourth semiconductor element 170 is provided at a position away from the current output electrode 132 and the bonding wire 134, the large current output from the second semiconductor element 130 is used. Generation of noise in the fourth semiconductor element 170 is suppressed. As a result, the operational reliability of the fourth semiconductor element 170 can be improved, and as a result, the operational reliability of the semiconductor module 100 can be improved.

  Further, the distance between the side E3 of the second semiconductor element 130 and the side G3 of the wiring board 110 is longer than the distance between the side E2 of the second semiconductor element 130 and the side G2 of the wiring board 110. Therefore, a region for installing the fourth semiconductor element 170 can be secured.

  In addition, with respect to the second semiconductor element 130, a current output electrode 132 is provided along a side other than the side E1 facing or adjacent to the side F1 of the first semiconductor element 120, and the bonding wire 134 is a side other than the side E1. Across. As a result, the current output electrode 132 and the bonding wire 134 are provided at positions away from the first semiconductor element 120, and therefore noise due to a large current output from the second semiconductor element 130 is generated in the first semiconductor element 120. It is suppressed.

  Further, regarding the first semiconductor element 120, the logic signal electrode 122 and the bonding wire 124 are not provided on the side F1 facing or adjacent to the side E1 of the second semiconductor element 130 that outputs a large current. As a result, generation of noise in the first semiconductor element 120 due to a large current output from the second semiconductor element 130 is suppressed.

  4 is a cross-sectional view taken along the line B-B ′ of FIG. 2, showing a state where the semiconductor module according to the embodiment is mounted on the mounting substrate.

  The solder ball 160a and the second wiring layer 116a are electrically connected to one of the logic signal electrodes 122 of the first semiconductor element 120 through the via 117a, the first wiring layer 114, and the bonding wire 124. . The solder ball 160b and the second wiring layer 116b are connected to one of the logic signal electrodes 172 of the fourth semiconductor element 170 shown in FIG. 2 via the via 117b, the first wiring layer 114, and the bonding wire 174. Electrically connected.

  On the other hand, electrode pads 210 corresponding to the solder balls 160 are provided on the surface of the mounting substrate 200. The solder ball 160 is soldered to the corresponding electrode pad 210. The electrode pads 210a corresponding to the solder balls 160a and the electrode pads 210b corresponding to the solder balls 160b are electrically connected by the third wiring layer 220. Thus, in a state where the semiconductor module 100 is mounted on the mounting substrate 200, the first semiconductor element 120 and the fourth semiconductor element 170 are electrically connected via the third wiring layer 220 provided on the mounting substrate 200. Connected. Thereby, for example, the first semiconductor element 120 can read out the parameter related to camera shake correction from the fourth semiconductor element 170 and execute the process related to camera shake correction as described above.

  Note that the connection method between the first semiconductor element 120 and the fourth semiconductor element 170 is preferably bus connection. In a state where the first semiconductor element 120 and the fourth semiconductor element 170 are connected by bus, data input / output to / from the first semiconductor element 120 and the fourth semiconductor element 170 is allocated to each semiconductor element. Differentiated by address.

  An external terminal 230 is provided on the back surface of the mounting substrate 200. The external terminal 230 is electrically connected to the third wiring layer 220 by a conductor 240 that penetrates the mounting substrate 200.

  When the operation test of the fourth semiconductor element 170 is performed, the external CPU 300 is connected to the external terminal 230, and the operation test of the fourth semiconductor element 170 is performed using the CPU 300. In addition, the CPU 300 can rewrite parameters relating to camera shake correction stored in the fourth semiconductor element 170.

  According to this, the fourth semiconductor element 170 can be directly accessed from the external CPU 300 via the external terminal 230. Therefore, for example, the operation of the first semiconductor element 120 (semiconductor chip) affects the result of the operation test of the fourth semiconductor element 170 (memory element), or the process of the operation test is changed to the fourth semiconductor element 170. Therefore, it is possible to prevent the necessity of making a correction in accordance with the first semiconductor element 120 connected to the. Further, the operation test of the fourth semiconductor element 170 can be performed without starting the first semiconductor element 120 at the time of product shipment.

  Further, the first semiconductor element 120 and the fourth semiconductor element 170 are electrically connected via the third wiring layer 220 provided on the mounting substrate 200, so that the main surface S 1 of the wiring substrate 110 is formed. Even when there is a layout restriction, the first semiconductor element 120 and the fourth semiconductor element 170 can be connected.

  In addition, the first semiconductor element 120 and the fourth semiconductor element 170 are electrically connected to each other through the third wiring layer 220 provided on the mounting substrate 200, whereby the first semiconductor element 120 and the fourth semiconductor element 120 are connected to each other. The conductor connecting the semiconductor element 170 can be separated from the second semiconductor element 130 serving as a noise source. Thereby, it is possible to suppress the generation of noise from the second semiconductor element 130 in the conductor portion that connects the first semiconductor element 120 and the fourth semiconductor element 170.

  FIG. 5 is a transparent perspective view of a digital camera having the semiconductor module according to the above-described embodiment. The digital camera includes a gyro sensor 50, a lens 60, a hall element 70, a VCM 80, and a semiconductor module 100. As shown in FIGS. 2 and 3, the semiconductor module 100 has the first semiconductor element 120, the second semiconductor element 130, and the fourth semiconductor element 170 mounted in parallel. In addition, a third semiconductor element 140 is mounted so as to be stacked on the first semiconductor element 120. In the semiconductor module 100 illustrated in FIG. 4, the configuration other than the first semiconductor element 120, the second semiconductor element 130, the third semiconductor element 140, and the fourth semiconductor element 170 is simplified and appropriately omitted. Yes.

  According to this, even when the first semiconductor element 120 and the second semiconductor element 130 are close to each other, it is possible to further reduce the size of the digital camera without deteriorating the operation reliability. . Further, since the semiconductor module 100 can be mounted on a digital camera after performing an operation test of each semiconductor element, the operation reliability of the digital camera can be improved. In addition, the semiconductor module 100 mounted on the digital camera can be easily tested for operation of individual semiconductor elements.

  The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. Embodiments to which such modifications are added Can also be included in the scope of the present invention.

  In the present application, the imaging device is not limited to the above-described digital camera, and may be a video camera, a camera mounted on a mobile phone, a surveillance camera, or the like, and has the same effect as the digital camera.

It is a block diagram which shows the circuit structure of the imaging device which has the semiconductor module which concerns on embodiment. It is a top view which shows schematic structure of the semiconductor module which concerns on embodiment. FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2 showing a schematic configuration of the semiconductor module according to the embodiment. FIG. 3 is a cross-sectional view taken along line B-B ′ of FIG. 2, showing a state where the semiconductor module according to the embodiment is mounted on a mounting substrate. 1 is a transparent perspective view of a digital camera having a semiconductor module according to an embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Signal amplification part, 12, 14, 16 Amplification circuit, 20 Camera shake correction part, 22 ADC, 24 Gyroscope, 26 HPF, 28 Pan / tilt determination circuit, 30 Gain adjustment circuit, 32 LPF, 34 Centering processing circuit, 36 gain Adjustment circuit, 40 hall equalizer, 42 adder circuit, 44 servo circuit, 46 DAC, 50 gyro sensor, 60 lens, 70 hall element, 80 VCM, 100 semiconductor module, 110 wiring board, 120 first semiconductor element, 130 second A semiconductor element, 140 a third semiconductor element, 150 sealing resin, 160 solder balls.

Claims (4)

A wiring board;
A semiconductor element mounted on one main surface of the wiring board;
Another semiconductor element mounted on one main surface of the wiring board;
An external electrode provided on the other main surface of the wiring board;
With
When the external electrode is electrically connected to a mounting board on which the wiring board is mounted, the semiconductor element and the other semiconductor element are electrically connected via wiring provided on the mounting board. A semiconductor module characterized by that.   The semiconductor module according to claim 1, wherein when the external electrode is connected to the mounting substrate, the semiconductor element and the other semiconductor element are bus-connected.   The semiconductor module according to claim 1, wherein the semiconductor element is a logic element, and the other semiconductor element is a memory element.   An imaging apparatus comprising the semiconductor module according to claim 1.

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