JP2009153960A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine giving a report of an opening state of a door body to a predetermined apparatus even if the power of the game machine is turned off. <P>SOLUTION: The inner frame input/output port output circuit 290b outputs a signal to the input/output port 205 if it detects an opening of an inner frame 12 when the power supply to a Pachinko game machine 500 is turned on. Then, the opening state of the inner frame 12 is reported by a third image pattern display a device 81, a voice output device 226 and a lamp display device 227. Meanwhile, the inner frame terminal board output circuit 290a outputs a pulse signal from an inner frame external output terminal board 291 to a hall computer 262 if it detects an opening state of the inner frame 12 not only when the power supply to the Pachinko game machine 500 is turned on but also when the power supply to the Pachinko game machine 500 is turned off. Such being the case, a pulse signal output to the hall computer 262 can be carried out using an inner frame frame-opening detection circuit 290, which is a circuit 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a gaming machine represented by a pachinko machine, a spinning machine (for example, a slot machine), or a spinning machine using a game ball.

  In the pachinko machine, when a ball that has been driven into the game area enters the symbol operating port, a lottery is performed at the timing of the entry. In addition, in a spinning type gaming machine using a slot machine or a game ball, when a start lever is operated, a lottery is performed at the timing of the operation. As a result of the lottery, for example, when a big hit is made, a large amount of prize balls and coins can be paid out. Since the control for determining the lottery and the jackpot is performed by the main control device, the main control device is likely to be a target of fraud.

  Specifically, for example, the main control device may be replaced with an unauthorized one that frequently generates jackpots, or an illegal board (for example, a “hanging board”) may be connected to the main control apparatus. There are things that illegally generate. In addition, in the case of a pachinko machine, there is also a fraudulent act that makes it easier for a ball to enter a winning port or a symbol operating port by illegally bending a nail that has been driven onto the game board surface.

In the case of a pachinko machine, the main controller is mounted on the back of the game board. A frame body is provided on the back surface of the game board, and an inner frame on which the game board is mounted is provided on the front surface of the frame body. The inner frame can be opened and closed with respect to the frame. A glass frame is provided on the front surface of the inner frame, and the glass frame can be opened and closed with respect to the inner frame. Therefore, when a fraudulent person cheats against the game board surface or the main control device, the inner frame or the glass frame must be opened, but when the inner frame or the glass frame is opened, Opening is detected by a sensor and notified to the hall computer that manages the amusement hall, as well as to which pachinko machine by informing the outside that the inner frame or glass frame has been opened by lighting the lamp or outputting sound. It is possible to easily grasp whether cheating has been done.
JP 2001-198332 A

  However, if, for example, late at night after the amusement hall is closed, a fraudulent person enters, and the intruder opens the inner frame or the glass frame and conducts a fraudulent action, the pachinko machine is turned off at that time. Since the pachinko machine is stopped, the opening of the inner frame or the glass frame cannot be detected, and the opening cannot be reported to the hall computer.

  The present invention has been made in order to solve the above-described problems and the like, and allows the opening to be grasped when the door is opened while the power of the gaming machine is turned off. It aims to provide a gaming machine that can.

  In order to achieve this object, a gaming machine according to claim 1 is provided in a space formed by a main body, a door body that opens and closes the front surface of the main body, and the door body and the main body, and controls the game. Control means for performing and notification means for performing notification by control of the control means, door opening detection means for detecting the opening of the door body with respect to the main body, and the door body by the door opening detection means Output of the detection result is output to the control means, the notification means is executed, and the detection result is output to a specific device, the output means, the output means, When the gaming machine is turned on and controlled by the control means, the detection result by the door opening detection means is output to the specific device, and the gaming machine is turned off and the control means System Even if it is not performed, and the detection result by the door opening detection means is configured to output to the specified device.

  The gaming machine according to claim 2 is the gaming machine according to claim 1, wherein when the gaming machine is powered on, the power supply means that operates by supplying power to the output means, and the power supply means A separate off-state operating means for operating the gaming machine by supplying power to the output means when the gaming machine is powered off, wherein the output means operates with the power supplied by the power supply means; The control output means for outputting the detection result by the door opening detection means to the control means, and the detection result by the door opening detection means by operating with the power supplied from the power supply means or the off-operation means. Specific output means for outputting to the apparatus.

  A gaming machine according to a third aspect is the gaming machine according to the second aspect, further comprising output period limiting means for keeping one output period by the specifying output means within a predetermined period, and the off-operation means is the In addition to the specifying output means, the output period limiting means is also configured to operate by supplying power.

  A gaming machine according to a fourth aspect of the present invention is the gaming machine according to the second or third aspect, wherein the off-operation means is configured to be rechargeable by electric power supplied from a power source of the gaming machine.

  The gaming machine according to claim 5 is the gaming machine according to any one of claims 2 to 4, further comprising a diode that flows a current supplied from the power supply means in one direction, wherein the operating means during off is a capacitor or The door opening detection means is configured to be turned on when the door body is opened, and blocked when the door body is closed. The power supply means is connected to the anode terminal of the diode, the cathode terminal of the diode is connected to one end of the off-state operation means, and the other end of the off-state operation means is grounded The control output means is connected to the power supply means and the anode terminal of the diode via the door opening detection means, and the specifying output means is the cathode of the diode. Wherein one end of the child and the OFF operating means are connected via a door opening detection means.

  According to the gaming machine of the first aspect, when the opening of the door body is detected by the door opening detecting means when the power of the gaming machine is turned on and the control means is controlled, the detection result is Output to the control means by the output means and notification by the notification means are executed, and the detection result is output to the specific device by the output means. Therefore, for example, when the door is opened by an unauthorized act by someone while the game machine is turned on, it is possible to determine the gaming machine whose door has been opened by notification by the notification means. At the same time, it is possible to determine the gaming machine whose door is opened by the specific device. On the other hand, when the power of the gaming machine is turned off, control of the control means is stopped. In this case as well, when the door opening detection means detects the opening of the door body, the detection result is output. Is output to the specific device by the means. Therefore, even if the door is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door opened by the specific device can be determined. Therefore, regardless of whether the gaming machine is powered on or off, if the door is opened by an unauthorized act by somebody, the detection result is output to the specific device by one output means, and the game in which the door is opened There is an effect that the machine can be identified by a specific device.

  According to the gaming machine according to claim 2, in addition to the effect of the gaming machine according to claim 1, when the power of the gaming machine is turned on, the control output means and the specifying output means are connected to the power supply means. Power is supplied. Thus, when the door opening detection means detects the opening of the door body, the detection result is output to the control means by the control output means, the notification by the notification means is executed, and the detection result is output for specification. Is output to the specific device by the means. Therefore, for example, when the door is opened by an unauthorized act by someone while the game machine is turned on, it is possible to determine the gaming machine whose door has been opened by notification by the notification means. At the same time, it is possible to determine the gaming machine whose door is opened by the specific device. On the other hand, when the power of the gaming machine is turned off, power is supplied to the specifying output means by the off-operation means. Thus, when the door opening detection means detects the opening of the door body, the detection result is output to the specifying device by the specifying output means. Therefore, even if the door is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door opened by the specific device can be determined. Therefore, regardless of whether the gaming machine is powered on or off, when a door is opened by an unauthorized act by somebody, a detection result is output to the specific device by the specifying output means, and the game in which the door is opened There is an effect that the machine can be identified by a specific device.

  According to the gaming machine of the third aspect, in addition to the effect produced by the gaming machine of the second aspect, the one output period by the specifying output means is kept within a predetermined period by the output period limiting means. Similarly to the specifying output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operating period of the specifying output means by one opening of the door body Can be kept within a predetermined period, and consumption of the off-operation means during the power-off of the gaming machine can be suppressed. Therefore, there is an effect that it is possible to increase the number of times that the output means for specifying can be operated and to increase the number of times that the opening of the door body can be detected.

  According to the gaming machine of the fourth aspect, in addition to the effect achieved by the gaming machine according to the second or third aspect, the off-time operation means is operated by electric power supplied to the gaming machine while the gaming machine is powered on. Since it is charged, the off-operation means can be charged simply by turning on the power supply of the gaming machine in accordance with the game hall business hours. Therefore, when the door is opened while the power of the gaming machine is turned off after the game hall is closed, the output means for specifying and the output period limiting means are operated by the off-operation means, and the door There is an effect that the detection result by the opening detection means can be reported to the specific device.

  According to the gaming machine of the fifth aspect, in addition to the effect achieved by the gaming machine according to any one of the second to fourth aspects, the control output means is connected to the power supply means and the anode terminal of the diode. When the door is opened while the power of the gaming machine is turned on, the door opening detection means is turned on, and power is supplied from the power supply means to the control output means, and the operation state is established. On the other hand, when the power of the gaming machine is turned off, the supply of power by the power supply means is stopped, so even if the door body is opened and the door opening detection means is conducted, the control output means The electric power is not supplied from the power supply means and the vehicle is stopped. On the other hand, because the specifying output means is connected to the off-state operating means and the cathode terminal of the diode, when the door body is opened when the power of the gaming machine is turned on, the door opening detection means The power supply means is supplied to the specifying output means from the power supply means, and the operation state is set. When the power source of the gaming machine is turned off, the power supply by the power supply means to the specifying output means is stopped, but when the door body is opened and the door opening detecting means is turned on, the specifying operation is performed by the off-operation means. Since electric power is supplied to the output means, the specifying output means is in an operating state. Here, when the power source of the gaming machine is turned off and power is supplied from the off-operation means to the specifying output means, the power supply to the control output means can be cut off by the diode. Thereby, the consumption of the off-operation means during the power-off of the gaming machine can be suppressed. Therefore, there is an effect that it is possible to increase the number of times that the output means for specifying can be operated and to increase the number of times that the opening of the door body can be detected.

  Hereinafter, an embodiment of a pachinko gaming machine (hereinafter simply referred to as “pachinko machine”) will be described with reference to the drawings. 1 is a front view of the pachinko machine 10, FIG. 2 is a front view of the game board 13 of the pachinko machine 10, and FIG. 3 is a rear view of the pachinko machine 10.

  As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 having an outer shell formed of a wooden frame combined in a substantially rectangular shape, and an outer frame 11 having substantially the same outer shape as the outer frame 11. And an inner frame 12 supported to be openable and closable. In order to support the inner frame 12, metal hinges 18 are attached to the outer frame 11 at two upper and lower portions on the left side when viewed from the front (see FIG. 1), and the side on which the hinge 18 is provided is used as an opening / closing axis. The frame 12 is supported so as to be openable and closable to the front front side.

  A game board 13 (see FIG. 2) having a large number of nails, winning holes 63, 64, and the like is detachably mounted on the inner frame 12 from the back side. A ball ball game is performed when the ball flows down the front surface of the game board 13. The inner frame 12 has a ball launch unit 112a (see FIG. 5) that launches a ball to the front area of the game board 13 and a launch that guides the ball launched from the ball launch unit 112a to the front area of the game board 13. A rail (not shown) or the like is attached.

  On the front side of the inner frame 12, a front frame 14 that covers the upper side of the front surface and a lower dish unit 15 that covers the lower side of the front frame 14 are provided. In order to support the front frame 14 and the lower dish unit 15, metal hinges 19 are attached to two upper and lower portions on the left side when viewed from the front (see FIG. 1), and the side on which the hinges 19 are provided is used as an opening / closing axis. 14 and the lower pan unit 15 are supported so as to be openable and closable toward the front front side. The locking of the inner frame 12 and the locking of the front frame 14 are respectively released by inserting a dedicated key into the key hole 21 of the cylinder lock 20 and performing a predetermined operation.

  The front frame 14 is assembled with decorative resin parts, electrical parts, and the like, and a window part 14c that is formed in an approximately elliptical shape is provided at a substantially central part thereof. A glass unit 16 having two plate glasses is disposed on the back side of the front frame 14, and the front surface of the game board 13 can be seen on the front side of the pachinko machine 10 through the glass unit 16. On the front frame 14, an upper plate 17 that stores balls is formed in a substantially box shape that protrudes forward and the upper surface is opened, and prize balls and rental balls are discharged to the upper plate 17. The bottom surface of the upper plate 17 is formed to be inclined downward to the right when viewed from the front (see FIG. 1), and the sphere thrown into the upper plate 17 is guided to the ball launch unit 112a by the inclination. A frame button 22 is provided on the upper surface of the upper plate 17. This frame button 22 is operated by the player, for example, when changing the effect pattern of the variable display displayed on the third symbol display device 81 or changing the effect content at the reach effect.

  In addition, the front frame 14 is provided with light emitting means such as various lamps around the periphery (for example, a corner portion). These light-emitting means play a role of enhancing the effect of the game during the game by changing or controlling the light-emitting mode by turning on or flashing according to the change in the gaming state at the time of big hit or predetermined reach. On the peripheral edge of the window portion 14c, there are provided electric decoration portions 29 to 33 incorporating light emitting means such as LEDs. In the pachinko machine 10, these lighting parts 29 to 33 function as effect lamps such as jackpot lamps, and the lighting parts 29 to 33 are turned on by lighting or blinking of the built-in LEDs at the time of jackpot or reach effects. Alternatively, it blinks to notify that the jackpot is being hit or that the reach is one step before the jackpot.

  Further, in the upper left part of the front frame 14 as viewed from the front (see FIG. 1), there is provided a display lamp 34 which has built-in light emitting means such as LEDs and can display the payout of a prize ball and when an error occurs. Further, a small window 35 is formed by attaching a transparent resin from the back side so that the back side of the front frame 14 can be visually recognized, on the lower side of the right illumination part 32, and a sticking space K1 on the front side of the game board 13 (FIG. 2) is visible from the front surface of the pachinko machine 10. In addition, in the pachinko machine 10, a plated member 36 made of ABS resin that is chrome-plated is attached to an area around the electric decoration parts 29 to 33 in order to bring out more gorgeousness.

  A ball rental operation unit 40 is disposed below the window 14c. The ball lending operation unit 40 is provided with a frequency display unit 41, a ball lending button 42, and a return button 43. When the ball lending operation unit 40 is operated in a state where a bill or a card is inserted into a card unit (ball lending unit) (not shown) arranged on the side of the pachinko machine 10, Loans are made. Specifically, the frequency display unit 41 is an area in which the remaining amount information such as a card is displayed, and the built-in LED is lit to display the remaining amount as the remaining amount information. The ball lending button 42 is operated to obtain a lending ball based on information recorded on a card or the like (recording medium), and the lending ball is supplied to the upper plate 17 as long as there is a remaining amount on the card or the like. Is done. The return button 43 is operated when requesting the return of a card or the like inserted into the card unit. In addition, in a pachinko machine in which a ball is lent directly to the upper plate 17 from a ball lending device or the like without using a card unit, a so-called cash machine does not require the ball lending operation unit 40. In this case, the ball lending operation unit 40 It is also possible to add a decorative seal or the like to the installation portion of the parts so that the component configuration is common. A pachinko machine using a card unit and a cash machine can be shared.

  In the lower plate unit 15 located on the lower side of the upper plate 17, a lower plate 50 for storing a ball that could not be stored in the upper plate 17 is formed in a substantially box shape having an open upper surface. Yes. On the right side of the lower plate 50, an operation handle 51 that is operated by a player to drive a ball into the front surface of the game board 13 is disposed, and the operation of the ball launching unit 112a is permitted inside the operation handle 51. Touch sensor 51a, a push button-type stop switch 51b for stopping the launch of the ball during the pressing operation, and a variable resistor for detecting the amount of rotation of the operating handle 51 by a change in electric resistance (Not shown). When the operation handle 51 is rotated clockwise by the player, the touch sensor is turned on and the resistance value of the variable resistor changes corresponding to the operation amount, and according to the rotation operation amount of the operation handle 51. A ball is fired with a strength corresponding to the resistance value of the variable resistor that changes, and the ball is driven into the front surface of the game board 13 with a jump amount corresponding to the player's operation. Further, when the operation handle 51 is not operated by the player, the touch sensor 51a and the stop switch 51b are off.

  In the lower part of the front of the lower plate 50, a ball removal lever 52 is provided for operating when the balls stored in the lower plate 50 are discharged downward. The ball removal lever 52 is always urged in the right direction. By sliding the ball release lever 52 in the left direction against the urge, the bottom opening formed in the bottom surface of the lower plate 50 is opened. A ball naturally falls from the bottom opening and is discharged. The operation of the ball removal lever 52 is normally performed in a state where a box (generally referred to as “a thousand box”) for receiving the balls discharged from the lower plate 50 is placed below the lower plate 50. As described above, the operation handle 51 is disposed on the right side of the lower plate 50, and the ashtray 53 is attached on the left side of the lower plate 50.

  As shown in FIG. 2, the game board 13 includes a wooden base plate 60 cut into a substantially square shape when viewed from the front, a large number of ball nails, windmills and rails 61 and 62, a general winning opening 63, The ball entrance 64, the variable winning device 65, the variable display device unit 80, and the like are assembled, and the peripheral edge thereof is attached to the back side of the inner frame 12. The general winning port 63, the first winning port 64, the variable winning device 65, and the variable display device unit 80 are arranged in a through hole formed in the base plate 60 by router processing, and the wood screw is provided from the front side of the game board 13. It is fixed by etc. Further, the front center portion of the game board 13 can be viewed from the front side of the inner frame 13 through the window portion 14c (see FIG. 1) of the front frame 14. Below, the structure of the game board 13 is demonstrated.

  An outer rail 62 formed by bending a strip-shaped metal plate into a substantially arc shape is planted on the front surface of the game board 13, and the strip-shaped metal plate is located on the inner side of the outer rail 62 in the same manner as the outer rail 62. The arc-shaped inner rail 61 formed by the above is planted. The inner rail 61 and the outer rail 62 surround the outer periphery of the front surface of the game board 13, and the game board 13 and the glass unit 16 (see FIG. 1) surround the front and rear. A game area in which a game is played is formed by the behavior of. The game area is a front surface of the game board 13 and is a substantially circular area formed by dividing the two rails 61 and 62 and the arc member 70 (a winning hole or the like is provided, Area).

  The two rails 61 and 62 are provided to guide the ball fired from the ball launching unit 112a to the upper part of the game board 13. A return ball preventing member 68 is attached to the front end portion of the inner rail 61 (upper left portion in FIG. 2) to prevent the ball once guided to the upper portion of the game board 13 from returning to the ball guide path again. Is done. A return rubber 69 is attached to the tip of the outer rail 62 (upper right part in FIG. 2) at a position corresponding to the maximum flying portion of the sphere, and the ball launched at a predetermined momentum or more hits the return rubber 69 and gains momentum. Is bounced back to the center while being attenuated. A resin arc member 70 formed by providing an arc connecting the rails on the inner surface side between the lower right end of the inner rail 61 and the upper right end of the outer rail 62 is a base. The plate 60 is driven and fixed.

  A first symbol display device 37 provided with a plurality of LEDs 37a, which are light emitting means, and a 7-segment display 37b is disposed in the upper right portion of the game area as viewed from the front (upper right portion in FIG. 2). The first symbol display device 37 displays information corresponding to each control performed by the main control device 110, and mainly displays the gaming state of the pachinko machine 10. The plurality of LEDs 37a indicate whether the pachinko machine 10 is in the process of being probabilistically changing, operating in a short time, or in a normal state, indicating whether the pachinko machine 10 is changing or not by a lighting state, and the symbols corresponding to the probable big hit. Whether the symbol is a symbol corresponding to a normal jackpot or an out-of-game symbol is indicated by a lighting state, or the number of reserved balls is indicated by a lighting state. The 7-segment display device 37b displays the number of rounds that are a big hit and an error display. Note that the LEDs 37a are configured so that the emission colors (for example, red, green, and blue) of the respective LEDs are different, and the combination of the emission colors can suggest various gaming states of the pachinko machine 10 with fewer LEDs. .

  In addition, the above-mentioned pachinko machine 10 being probable is a game state in which the jackpot probability is increased and it is easy to shift to the special game state. Further, during the probability change in the present embodiment, the game is in a state where the hit probability of the second symbol is increased and the ball easily enters the first entrance 64. In addition, when the pachinko machine 10 is short-running, it is a game state in which the hit probability of the second symbol is increased without changing the jackpot probability and the ball easily enters the first entrance 64. In addition, when the pachinko machine 10 is in a normal state, it is a game state in which neither the probability change nor the time is short (the state where neither the big hit probability nor the second symbol hit probability is increased). It should be noted that, depending on the gaming state of the pachinko machine 10, the time for opening the electric accessory (not shown) associated with the first entrance 64 and the number of times the electric accessory is released per hit are changed. It is good as a thing.

  The game area is provided with a plurality of general winning openings 63 through which 5 to 15 balls are paid out as winning balls when the balls win. In addition, a variable display device unit 80 is disposed in the central portion of the game area. The variable display device unit 80 includes a third symbol display device 81 configured with a liquid crystal display (hereinafter simply referred to as “display device”) that displays the third symbol in a variable manner with a winning at the first entrance 64 as a trigger. And a second symbol display device 82 composed of a light emitting diode (hereinafter abbreviated as “LED”) that variably displays the second symbol with the passage of the ball of the second entrance 67 as a trigger. .

  The display content of the third symbol display device 81 is controlled by a display control device 114, which will be described later, and for example, three symbol sequences of left, middle, and right are displayed. Each symbol row is composed of a plurality of symbols, and these symbols are vertically scrolled for each symbol row so that the third symbol is variably displayed on the display screen of the third symbol display device 81. Further, in the present embodiment, the third symbol display device 81 is constituted by a large liquid crystal display of 8 inch size, and the variable display device unit 80 surrounds the outer periphery of the third symbol display device 81 so as to surround the center frame. 86 is arranged. In the third symbol display device 81 of the present embodiment, the display of the gaming state accompanying the control of the main control device 110 is performed by the first symbol display device 37, whereas the display of the first symbol display device 37 is performed. The decorative display according to is performed. Instead of the display device, for example, the third symbol display device 81 may be configured using a reel or the like.

  In addition, when the ball enters the first entrance 64 until the stop symbol (any one of the probable jackpot symbol, the normal jackpot symbol, or the off symbol) is displayed on the first symbol display device 37. The number of entered balls is held up to 4 times, and the number of held times is indicated by the first symbol display device 37 and the number of lights of the holding lamp 85. Four hold lamps 85 are provided corresponding to the maximum number of holds, and are arranged symmetrically above the third symbol display device 81. In the present embodiment, the winning at the first entrance 64 is configured to be held up to 4 times, but the maximum holding number is not limited to 4 times, but 3 times or less. Alternatively, the number may be set to 5 times or more (for example, 8 times). In addition, the hold lamp 85 is deleted, and the number of times the variable display is held based on the winning at the first entrance 64 is numerically held in a part of the third symbol display device 81, or the area divided into four is held. You may make it display in a different aspect (for example, a color and a lighting pattern) by the frequency | count. In addition, since the number of times of holding is indicated by the first symbol display device 37, the holding lamp 85 may not perform lighting display.

  The second symbol display device 82 includes a second symbol display unit 83 and a holding lamp 84, and each time the ball passes through the second entrance 67, the display unit 83 displays a display symbol (second symbol). The “○” symbol and the “×” symbol are alternately lit and displayed in a variable manner. When the fluctuation display stops at a predetermined symbol (in this embodiment, the symbol “O”) The 1 entrance 64 is configured to be activated (opened) for a predetermined time. The number of passes through the second entrance 67 of the sphere is suspended up to a maximum of 4 times, and the number of suspensions is displayed by the above-described first symbol display device 37 and is also lit on the hold lamp 84. The second symbol variation display is performed by switching on and off of a plurality of lamps in the display unit 83 as in the present embodiment, as well as the first symbol display device 37 and the third symbol display device. A part of 81 may be used. Similarly, the hold lamp 84 may be turned on by a part of the third symbol display device 81. In addition, the passage of the second entrance 67 is not limited to 4 times as in the case of the 1st entrance 64, and is not limited to 4 times, or 3 times or less (for example, (8 times). In addition, since the number of times of holding is indicated by the first symbol display device 37, the holding lamp 84 may not perform lighting display.

  Below the variable display device unit 80, a first entrance 64 into which a sphere can enter is disposed. When a ball enters the first entrance 64, a first entrance switch (not shown) provided on the back side of the game board 13 is turned on, and the first entrance switch is turned on. The main controller 110 performs a lottery lottery, and a display corresponding to the lottery result is indicated by the LED 37 a of the first symbol display device 37. The first entrance 64 is also one of the entrances through which 5 balls are paid out as prize balls when a ball enters.

  A variable winning device 65 is disposed below the first ball opening 64, and a horizontally-long rectangular specific winning port (large opening) 65a is provided at a substantially central portion thereof. In the pachinko machine 10, when the lottery in the main controller 110 is a big hit, after a predetermined time (fluctuation time) has elapsed, the LED 37a of the first symbol display device 37 is turned on so as to become a big hit stop symbol. The stop symbol corresponding to the jackpot is displayed on the third symbol display device 81 to indicate the occurrence of the jackpot. Thereafter, the gaming state transitions to a special gaming state (big hit) where the ball is easy to win. In this special gaming state, the special winning opening 65a that is normally closed is opened for a predetermined time (for example, until 30 seconds have elapsed or ten balls have been won).

  The specific winning opening 65a is closed when a predetermined time elapses, and after the closing, the specific winning opening 65a is opened again for a predetermined time. The opening / closing operation of the specific winning opening 65a can be repeated up to 16 times (16 rounds), for example. The state in which the opening / closing operation is performed is a form of a special gaming state advantageous to the player, and the player is given out a larger amount of prize balls than usual in order to give a gaming value (game value). Is done.

  Specifically, the variable winning device 65 is a horizontally long rectangular opening / closing plate covering the specific winning opening 65a, and a large opening opening solenoid (not shown) for driving to open / close forward with the lower side of the opening / closing plate as an axis. And. The special winning opening 65a is normally closed so that the ball cannot win or is difficult to win. In the case of a big hit, the large opening opening solenoid is driven to tilt the opening / closing plate to the lower front side to temporarily form an open state in which the ball is likely to win the specific winning opening 65a. It operates to repeat the state and the state alternately.

  Note that the special gaming state is not limited to the above-described form. When the game area is provided with a large opening that is opened and closed separately from the specific winning opening 65a, and the LED 37a corresponding to the jackpot is turned on in the first symbol display device 37, the specific winning opening 65a is opened for a predetermined time, and the specific winning opening A special gaming state is defined as a game state in which a large opening provided separately from the specific winning port 65a is opened for a predetermined time and a predetermined number of times when the ball 65 is opened into the specific winning port 65a. You may make it form.

  Adhesive spaces K1, K2 for adhering certificate papers, identification labels, etc. are provided at the left and right corners on the lower side of the game board 13, and the certificate paper, etc., adhered to the adhesive space K1, is a front frame 14. It can be visually recognized through the small window 35 (see FIG. 1).

  Further, the game board 13 is provided with an out port 66. A ball that has not entered any of the winning openings 63, 64, 65a is guided through an out port 66 to a ball discharge path (not shown). A number of nails are planted on the game board 13 in order to appropriately disperse and adjust the falling direction of the ball, and various members (instruments) such as a windmill are arranged.

  As shown in FIG. 3, control board units 90 and 91 and a back pack unit 94 are mainly provided on the back side of the pachinko machine 10. The control board unit 90 is unitized by mounting a main board (main control apparatus 110), an audio lamp control board (audio lamp control apparatus 113), and a display control board (display control apparatus 114). The control board unit 91 is unitized by mounting a payout control board (payout control apparatus 111), a firing control board (launching control apparatus 112), a power supply board (power supply apparatus 115), and a card unit connection board 116.

  The back pack unit 94 includes a back pack 92 and a dispensing unit 93 that form a protective cover. In addition, each control board is used for MPU as a one-chip microcomputer that controls each control, a port for communicating with various devices, a random number generator used for various lotteries, time counting and synchronization. A clock pulse generation circuit or the like is mounted as necessary.

  The main control device 110, the sound lamp control device 113 and the display control device 114, the payout control device 111 and the firing control device 112, the power supply device 115, and the card unit connection board 116 are housed in the board boxes 100 to 104, respectively. . The board boxes 100 to 104 include a box base and a box cover that covers the opening of the box base. The box base and the box cover are connected to each other, and each control device and each board are accommodated.

  Further, the substrate box 100 (main control device 110) and the substrate box 102 (dispensing control device 111 and launch control device 112) connect the box base and the box cover so that they cannot be opened by a sealing unit (not shown) (caulking structure). Consolidated). In addition, a seal (not shown) is attached to the connecting portion between the box base and the box cover so as to cover the box base and the box cover. This seal seal is made of a brittle material. If the seal is to be peeled off in order to open the substrate boxes 100, 102, or if the substrate boxes 100, 102 are forcibly opened, the box base side and the box cover are removed. Cut to the side. Therefore, it is possible to know whether or not the substrate boxes 100 and 102 have been opened by checking the sealing unit or the sealing seal.

  The payout unit 93 includes a tank 130 that is located at the top of the back pack unit 94 and opens upward, a tank rail 131 that is connected to the lower side of the tank 130 and is gently inclined toward the downstream side, and downstream of the tank rail 131. A case rail 132 that is vertically connected to the side, and a payout device 133 that is provided at the most downstream portion of the case rail 132 and that pays out a ball by a predetermined electrical configuration of the payout motor 216 (see FIG. 5). ing. The tank 130 is successively replenished with balls supplied from the island equipment of the game hall, and a required number of balls are paid out by the payout device 133 as appropriate. A vibrator 134 for applying vibration to the tank rail 131 is attached to the tank rail 131.

  The payout control device 111 is provided with a state return switch 120, the firing control device 112 is provided with a variable resistor operation knob 121, and the power supply device 115 is provided with a RAM erase switch 122. The state return switch 120 is operated, for example, to eliminate ball clogging (return to a normal state) when a payout error occurs, such as ball clogging in the payout motor 216 (see FIG. 4). The operation knob 121 is operated to adjust the firing force of the firing solenoid. The RAM erase switch 122 is operated when the power is turned on to return the pachinko machine 10 to the initial state.

  Next, the internal configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 4 is a perspective view of the pachinko machine 10 in a state where the inner frame 12, the front frame 14, and the lower dish unit 15 are opened.

  The pachinko machine 10 is provided with an outer frame 11 that forms an outer shell thereof, and an inner frame 12 is supported to the outer frame 11 so as to be opened and closed. In the game hall, the outer peripheral surface of the outer frame 11 is fixed to an installation location called an island of the game hall. Since the inner frame 12, the front frame 14, and the lower dish unit 15 are configured to be openable to the front side with respect to the outer frame 11, the inner frame 12, the front frame 14, and the lower dish unit 15 are not touched from the front side of the pachinko machine 10. Inspection and adjustment are performed with the inner frame 12 and the like open to the front side with respect to the outer frame 11.

  In order to support the inner frame 12, metal upper hinges (not shown) and lower hinges (not shown) are attached to the outer frame 11 at two upper and lower positions on the left side when viewed from the front. The inner frame 12 is supported so as to be openable and closable with the side on which the upper and lower hinges are provided as an opening / closing axis.

  The inner frame 12 is mainly composed of an ABS resin-made inner frame base 55 formed in a rectangular shape, and a substantially circular central window 55 a is formed at the center of the inner frame base 55. An attachment portion for the game board 13 is provided on the back side of the inner frame base 55, and the game board 13 is detachably attached.

  The lower side of the central window 55a of the inner frame base 55 is formed in a concave shape with the front side open, and a flat mounting surface 52b is formed on the back side. The mounting surface 52b is attached with a launch unit 140 for launching a ball to the front surface of the game board 13, a passage forming member 54 that forms a passage for discharging the ball to the upper plate 17 and the lower plate 50, and the like.

  Between the outer frame 11 and the inner frame 12, switches SW1 (SW1a, SW1b) for detecting opening and closing of the inner frame 12 are provided, and between the inner frame 12 and the front frame 14, a front surface is provided. Switches SW2 (SW2a, SW2b) for detecting opening and closing of the frame 14 are provided. The switch SW1 is composed of a female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12, and a male switch SW1b disposed on the surface of the inner frame 12 facing the outer frame 11. The The switch SW2 includes a female switch SW2a disposed on the surface of the inner frame 12 facing the front frame 14, and a male switch SW2b disposed on the surface of the front frame 14 facing the inner frame 12. Composed.

  Here, the structure of the switch SW1 and the switch SW2 will be described with reference to FIG. Since the switch SW1 and the switch SW2 have the same structure, the structure of the switch SW1 will be described, and the description of the switch SW2 will be omitted.

  FIG. 5 is a diagram showing the structure of the switch SW1. FIG. 5A is a diagram showing a state (cut-off state) of the switch SW1 in a state where the inner frame 12 is closed. FIG. 5B is a diagram showing the state (conducting state) of the switch SW1 in a state where the inner frame 12 is opened.

  As shown in FIG. 5A, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 incorporates a pair of terminal pairs SW1c made of metal as a conductive member. ing. When the inner frame 12 is closed, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 is connected to the male switch SW1a disposed on the surface of the inner frame 12 facing the outer frame 11. The mold switch SW1b is inserted, and contact between the terminal pairs SW1c is prevented. Therefore, in a state where the inner frame 12 is closed, the switch SW1 is in a state where conduction is cut off.

  On the other hand, as shown in FIG. 5B, in a state where the inner frame 12 is opened, the female switch SW1a disposed on the surface of the outer frame 11 facing the inner frame 12 is connected to the outside of the inner frame 12. The male switch SW1b disposed on the surface facing the frame 11 is pulled out. Since the terminal pair SW1c built in the female switch SW1a has a structure in which an urging force is generated in the opposite direction, the terminal pair SW1c is in contact with each other when the male switch SW1b is pulled out from the female switch SW1a. To do. Therefore, in a state where the inner frame 12 is opened, the switch SW1 is in a conductive state.

  As described above, the switch SW1 is in a cut-off state when the inner frame 12 is closed, and is in a conductive state when the inner frame 12 is opened. However, the structure of the switch SW1 is not limited to the shape shown in FIG. 5, and when the inner frame 12 is closed, the switch SW1 is in a cut-off state, while in the state where the inner frame 12 is opened, Any structure may be used as long as the switch SW1 is in a conductive state. The same applies to the structure of the switch SW2.

  Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 6 is a block diagram showing an electrical configuration of the pachinko machine 10.

  The main controller 110 is equipped with an MPU 201 as a one-chip microcomputer that is an arithmetic unit. The MPU 201 includes a ROM 202 that stores various control programs executed by the MPU 201 and fixed value data, and a memory that temporarily stores various data when the control program stored in the ROM 202 is executed. A certain RAM 203 and various other circuits such as an interrupt circuit, a timer circuit, and a data transmission / reception circuit are incorporated. Various commands are transmitted from the main control device 110 to the sub control device by the data transmission / reception circuit in order to instruct the sub control device such as the payout control device 111 and the sound lamp control device 113 to operate. Such a command is transmitted from the main controller 110 to the sub controller only in one direction.

  The RAM 203 stores the contents of the internal registers of the MPU 201, the return address of the control program executed by the MPU 201, and the work area (work area for storing various flags and counters, I / O values, etc. Area). The RAM 203 is configured to hold (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is shut off, and all data stored in the RAM 203 is backed up.

  When the power is shut down due to the occurrence of a power failure or the like, the stack pointer and the value of each register when the power is shut off (including when the power failure occurs, the same applies hereinafter) are stored in RAM 203. On the other hand, at the time of power-on (including power-on due to power failure cancellation, the same applies hereinafter), the state of the pachinko machine 10 is restored to the state before power-off based on information stored in the RAM 203. Writing to the RAM 203 is executed when the power is shut off by the main process (see FIG. 12), and restoration of each value written in the RAM 203 is executed in a startup process (see FIG. 11) when the power is turned on. Note that the power failure signal SG1 from the power failure monitoring circuit 252 is input to the NMI terminal (non-maskable interrupt terminal) of the MPU 201 when the power is interrupted due to the occurrence of a power failure or the like. Is input immediately, the NMI interrupt process (see FIG. 17) as a power failure process is immediately executed.

  An input / output port 205 is connected to the MPU 201 of the main control device 110 via a bus line 204 composed of an address bus and a data bus. The input / output port 205 includes a payout control device 111, a sound lamp control device 113, a first symbol display device 37, a second symbol display device 82, various switches 208 including a switch group and a sensor group (not shown), and a specific prize. A solenoid 209 comprising a large opening solenoid for opening and closing the front side with the lower side of the opening and closing plate of the opening 65a as an axis, a solenoid for driving an electric accessory, and the like is connected.

  The main controller 110 is also provided with a frame opening detection circuit 260 that detects opening of the inner frame 12 when the switch SW1 is turned on and detects opening of the front frame 14 when the switch SW2 is turned on. Yes. Connected to the frame opening detection circuit 260 are a switch SW1 for detecting the opening of the inner frame 12, a switch SW2 for detecting the opening of the front frame 14, and an external output terminal plate 261 configured to be connectable to the hall computer 262. Has been. It should be noted that an input / output unit (input / output port 205 and an input / output port) that inputs and outputs signals is used to connect the switches SW1 and SW2 to the frame opening detection circuit 260 and to connect the frame opening detection circuit 260 and the external output terminal plate 261. Are connected via different input / output ports (not shown). When the switch SW1 is turned on and the opening of the inner frame 12 is detected, or when the switch SW2 is turned on and the opening of the front frame 14 is detected, the frame opening detection circuit 260 is switched from the external output terminal board 261 to the hall computer 262. A pulse signal having a pulse width of 10 milliseconds is output. The pulse signal output from the external output terminal plate 261 is stored in the hall computer 262. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected by analyzing the pulse signal stored in the hall computer 262.

  The frame opening detection circuit 260 is configured not to be connected to the MPU 201 or the input / output port 205 (input / output port of the MPU 201) of the main controller 110. Therefore, the frame opening detection circuit 260 may be configured to be mounted on a device (circuit board) other than the main control device 110. For example, it may be mounted on a device (circuit board) on which an arithmetic device such as an MPU or CPU is not mounted, or a dedicated substrate for the frame opening detection circuit 260 may be provided and mounted thereon. More preferably, like the main control device 110, the payout control device 111, and the launch control device 112, the frame opening detection circuit 260 is accommodated in the substrate box, and the box base and the box cover provided in the substrate box are sealed. (Not shown) is connected so that it cannot be opened (connection by caulking structure). A sealing seal (not shown) may be attached to the connecting portion between the box base and the box cover so as to extend over the box cover and the box base.

  The payout control device 111 drives the payout motor 216 to perform payout control of prize balls and rental balls. The MPU 211, which is an arithmetic unit, includes a ROM 212 that stores a control program executed by the MPU 211, fixed value data, and the like, and a RAM 213 that is used as a work memory or the like.

  The RAM 213 of the payout control device 111, like the RAM 203 of the main control device 110, has a stack area for storing the contents of the internal registers of the MPU 211, the return address of the control program executed by the MPU 211, and various flags and counters. And a work area (work area) in which values such as I / O are stored. The RAM 213 is configured to be able to retain (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is cut off, and all data stored in the RAM 213 is backed up. As with the MPU 201 of the main controller 110, the power failure signal SG1 is also input to the NMI terminal of the MPU 211 from the power failure monitoring circuit 252 when the power is interrupted due to the occurrence of a power failure or the like. When input to the MPU 211, an NMI interrupt process (see FIG. 17) is immediately executed as a power failure process.

  An input / output port 215 is connected to the MPU 211 of the payout control device 111 via a bus line 214 composed of an address bus and a data bus. The main control device 110, the payout motor 216, the firing control device 112, and the like are connected to the input / output port 215, respectively. Although not shown, the payout control device 111 is connected to a prize ball detection switch for detecting a prize ball that has been paid out. The prize ball detection switch is connected to the payout control device 111 but is not connected to the main control device 110.

  The launch control device 112 controls the ball launch unit 112a so that the launch strength of the ball according to the rotational operation amount of the operation handle 51 is obtained when the main control device 110 gives an instruction to launch a ball. The ball launching unit 112a includes a launching solenoid and an electromagnet (not shown), and the firing solenoid and the electromagnet are permitted to be driven when predetermined conditions are met. Specifically, the operation handle 51 is detected on the condition that the touch sensor 51a detects that the player is touching the operation handle 51 and the stop switch 51b for stopping the ball firing is turned off (not operated). The firing solenoid is excited in accordance with the amount of rotation 51, and a ball is launched with a strength corresponding to the amount of operation of the operation handle 51.

  The voice lamp control device 113 is a voice output in a voice output device (such as a speaker not shown) 226, an output of lighting and extinguishing in a lamp display device (such as the illumination units 29 to 33 and the display lamp 34), and the display control device 114. The setting of the display mode of the 3rd symbol display apparatus 81 performed etc. is controlled. The MPU 221 that is an arithmetic unit includes a ROM 222 that stores a control program executed by the MPU 221, fixed value data, and the like, and a RAM 223 that is used as a work memory or the like.

  An input / output port 225 is connected to the MPU 221 of the sound lamp control device 113 via a bus line 224 including an address bus and a data bus. The main control device 110, the display control device 114, the audio output device 226, the lamp display device 227, and the like are connected to the input / output port 225, respectively.

  The display control device 114 controls the change display of the third symbol on the third symbol display device (LCD) 81. The display control device 114 includes an MPU 231, a ROM (program ROM) 232, a work RAM 233, a video RAM 234, a character ROM 235, an image controller 236, an input port 237, an output port 238, and bus lines 239 and 240. have. The input side of the input port 237 is connected to the output side of the sound lamp control device 113, and the output side of the input port 237 is connected to the MPU 231, ROM 232, work RAM 233, and image controller 236. A video RAM 234 and a character ROM 235 are connected to the image controller 236, and an output port 238 is connected via a bus line 240. A third symbol display device 81 is connected to the output side of the output port 238. Even if the pachinko machine 10 is a different model with different winning probability for winning the jackpot and the number of prize balls to be paid out in one jackpot, there is a model having the same specifications as the symbols displayed on the third symbol display device 81. Therefore, the display control device 114 is made into a common part to reduce the cost.

  The MPU 231 of the display control device 114 controls the display content of the third symbol display device 81 based on the symbol display command input from the sound lamp control device 113. The ROM 232 is a memory for storing various control programs executed by the MPU 231 and fixed value data. The work RAM 233 is a memory for temporarily storing work data and flags used when the MPU 231 executes various programs. The character ROM 235 is a memory that stores data for effects such as symbols (background symbols and third symbols) displayed on the third symbol display device 81. The video RAM 234 is a memory for storing effect data displayed on the third symbol display device 81, and the display content of the third symbol display device 81 is changed by rewriting the contents of the video RAM 234.

  The image controller 236 adjusts the timing of the MPU 231, the video RAM 234, and the output port 238 to intervene in reading and writing data, and reads display data stored in the video RAM 234 at a predetermined timing to read the third symbol display device 81. Is displayed.

  The power supply device 115 includes a power supply unit 251 for supplying power to each unit of the pachinko machine 10, a power failure monitoring circuit 252 for monitoring power interruption due to a power failure, and a RAM deletion switch 122 (see FIG. 3). And an erasing switch circuit 253. The power supply unit 251 is a device that supplies a necessary operating voltage to each of the control devices 110 to 114 through a power supply path (not shown). As its outline, the power supply unit 251 takes in the voltage of AC 24 volts supplied from the outside, and drives various switches such as various switches 208, solenoids such as the solenoid 209, motors, etc. A 5 volt voltage for logic, a backup voltage for RAM backup, and the like are generated, and the 12 volt voltage, the 5 volt voltage, and the backup voltage are supplied to the control devices 110 to 114 as necessary voltages.

  The power failure monitoring circuit 252 is a circuit for outputting a power failure signal SG1 to each NMI terminal of the MPU 201 of the main control device 110 and the MPU 211 of the payout control device 111 when the power is cut off due to the occurrence of a power failure or the like. The power failure monitoring circuit 252 monitors the DC stable voltage of 24 volts, which is the maximum voltage output from the power supply unit 251, and determines that a power failure (power interruption, power interruption) occurs when this voltage falls below 22 volts. Then, the power failure signal SG1 is output to the main controller 110 and the payout controller 111. Based on the output of the power failure signal SG1, the main controller 110 and the payout controller 111 recognize the occurrence of the power failure and execute the NMI interrupt process. Note that the power supply unit 251 outputs a voltage of 5 volts, which is a drive voltage of the control system, for a time sufficient to execute the NMI interrupt processing even after the DC stable voltage of 24 volts becomes less than 22 volts. Is maintained at a normal value. Therefore, main controller 110 and payout controller 111 can normally execute and complete the NMI interrupt process (see FIG. 17).

  The RAM erase switch circuit 253 is a circuit for outputting a RAM erase signal SG2 for clearing backup data to the main controller 110 when the RAM erase switch 122 is pressed. When the RAM erase signal SG2 is input when the pachinko machine 10 is turned on, the main control device 110 and the payout control device 111 clear the respective backup data and the payout control device 111 for clearing the backup data. A payout initialization command is transmitted to the payout control device 111.

  Next, the frame opening detection circuit 260 and the external output terminal plate 261 will be described with reference to FIG. FIG. 7 is a block diagram showing the electrical configuration of the frame opening detection circuit 260 and the external output terminal plate 261. In FIG. 7, the frame opening detection circuit 260 is described first, and then the external output terminal plate 261 is described.

  A frame opening detection circuit 260 that detects opening of the inner frame 12 or opening of the front frame 14 includes a DC power source DC1 that supplies a DC voltage of 12 volts, a diode D1, capacitors CD1 to CD5, resistors R1 to R4, It mainly includes a timer IC1 (LMC555 manufactured by National Semiconductor) that is a C-MOS timer and a transistor TR1 provided with an internal resistor R5 and an internal resistor R6.

  In order to detect the opening of the inner frame 12 when the switch SW1 is turned on and to detect the opening of the front frame 14 when the switch SW2 is turned on, the frame opening detection circuit 260 has the above components shown in FIG. Connected according to block diagram. Since the switch SW1 and the switch SW2 are connected in parallel and connected to the frame opening detection circuit 260, the frame opening detection circuit 260 is connected to the inner frame 12 or the front frame if either switch is turned on. 14 can be detected.

  The DC power source DC1 is a power source that supplies a DC voltage of 12 volts to the open frame detection circuit 260 and the external output terminal board 261. Power (power) to the DC power supply DC1 is supplied from a power supply unit 251 provided in the power supply device 115 through a power supply path (not shown). This DC power supply DC1 is connected to the anode terminal of the diode D1. One end of a 0.1F (farad) capacitor CD1 is connected to the cathode terminal of the diode D1. The other end of the capacitor CD1 is grounded. One end of the capacitor CD1 is connected to one end of the switch SW1, one end of the switch SW2, and the VDD terminal and the RES terminal of the timer IC1.

  The capacitor CD1 is a charge that supplies a DC voltage to the frame open detection circuit 260 and the external output terminal plate 261 when the power supply to the pachinko machine 10 is cut off and a DC voltage of 12 volts is not supplied from the DC power supply DC1. It is a part that demonstrates the function of the battery.

  This is because when the capacitor CD1 is supplied with power to the pachinko machine 10 and a DC voltage of 12 volts is supplied from the DC power source DC1, the capacitor CD1 has a capacitance of 0.1 F (farad) and the capacitor CD1. Charges obtained by the product of the applied DC voltage (about 11.3 volts obtained by subtracting about 0.7 volts from the diode D1 from 12 volts supplied from the DC power supply DC1) are stored.

  On the other hand, the capacitor CD1 is stored in the capacitor CD1, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is cut off and no DC voltage of 12 volts is supplied from the DC power supply DC1. A DC voltage (about 11.3 volts) based on the generated charge is supplied to the open frame detection circuit 260 and the external output terminal board 261.

  Therefore, the frame opening detection circuit 260 operates naturally when power is supplied to the pachinko machine 10 and a DC voltage of 12 volts is supplied from the DC power supply DC1, and further, for example, a game hall business Even if the power supply to the pachinko machine 10 is cut off after the time is over and the DC voltage of 12 volts is not supplied from the DC power supply DC1, the internal power supply operates by the DC voltage supplied by the capacitor CD1, The opening of the frame 12 and the opening of the front frame 14 can be detected. In the present embodiment, the capacitor CD1 is used as a component for supplying a DC voltage to the open frame detection circuit 260 and the external output terminal plate 261 when a DC voltage of 12 volts is not supplied from the DC power source DC1. . However, the present invention is not limited to this, and the capacitor CD1 may be a secondary battery (rechargeable battery) with a larger amount of stored electricity or a primary battery that does not require charging.

  In addition, a cathode terminal of a diode D1 is connected to one end of the capacitor CD1, and this diode D1 serves to prevent a backflow of current. Therefore, a direct current is passed from the capacitor CD1 to the open frame detection circuit 260 and the external output terminal plate 261. Even when a voltage (about 11.3 volts) is supplied, the DC voltage is not applied to the DC power source DC1, and the DC power source DC1 is not damaged.

  The timer IC1 is a C-MOS timer and detects the opening of the inner frame 12 or the opening of the front frame 14 by connecting the resistors R1 and R2 of 100 kΩ and the capacitors CD3 to CD5 of 0.1 μF, and external output terminals It functions as a circuit for energizing the photocoupler PR1 of the plate 261 for about 10 milliseconds.

  The operating voltage range of the timer IC 1 is that of the MPU 201 mounted on the main control device 110, the MPU 211 mounted on the payout control device 111, the MPU 221 mounted on the sound lamp control device 113, and the MPU 231 mounted on the display control device 114. It is set in a wider range than each operating voltage range. Specifically, the operating voltage range of the timer IC 1 is about 1.5 volts to about 12.0 volts, while the operating voltage ranges of the MPUs 201, 211, 2221, and 231 are about 4.5 volts. It is about 5.5 volts (each operating voltage in this embodiment is about 5.0 volts). Therefore, the timer IC 1 can operate at a voltage lower than the operating voltages of the MPUs 201, 211, 211, and 231. Therefore, even if the charge stored in the capacitor CD1 decreases and the voltage supplied by the capacitor CD1 drops below about 4.5 volts, the timer IC1 can operate sufficiently. Further, the timer IC1 is, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is cut off and no DC voltage of 12 volts is supplied from the DC power supply DC1, that is, the capacitor CD1 is connected to the timer IC1. The case where the voltage is supplied and the case where the power supply to the pachinko machine 10 is performed and the DC voltage of 12 volts is supplied from the DC power source DC1 are combined. Therefore, of course, the timer IC 1 can operate at a DC voltage of 12 volts or less supplied to the frame opening detection circuit 260 when power is supplied to the pachinko machine 10. Furthermore, since the timer IC1 is a timer composed of a C-MOS semiconductor, power consumption during operation can be suppressed and operation can be performed for a long time.

  The VDD terminal of the timer IC1 is a terminal for inputting a DC voltage supplied to the timer IC1, and is connected to one end of the capacitor CD1. The VDD terminal of the timer IC1 is connected to one end of a 0.1 μF capacitor CD4, and the other end of the capacitor CD4 is connected to the GND terminal of the grounded timer IC1. The capacitor CD4 reduces noise generated at the VDD terminal of the timer IC1 when the switch SW1 and the switch SW2 are turned on or off (when the inner frame 12 and the front frame 14 are opened or closed). .

  The RES terminal of the timer IC 1 is a terminal for operating a reset function for forcibly stopping the voltage output from the OUT terminal (zero volts) when a pulse signal is input to the RES terminal. However, since the reset function is not used in the open frame detection circuit 260, the RES terminal of the timer IC1 is connected to one end of the capacitor CD1 so that the reset function is not activated. Since the VDD terminal of timer IC1 and the RES terminal of timer IC1 are connected to one end of capacitor CD1 as described above, a DC voltage of about 11.3 volts is applied to the VDD terminal and RES terminal of timer IC1. Applied.

  When the switch SW1 and the switch SW2 are cut off (when the inner frame 12 and the front frame 14 are closed), the TRG terminal of the timer IC1 reduces the voltage output from the OUT terminal of the timer IC1. When one of the switches SW1 and SW2 or both of the switches SW1 and SW2 is in a conductive state (either the inner frame 12 or the front frame 14, Or the terminal for setting the voltage output from the OUT terminal of the timer IC 1 from about 10.6 volts to zero volts in about 10 milliseconds after the inner frame 12 and the front frame 14 are both open. is there. The TRG terminal of the timer IC1 is connected to one end of the resistor R2, one end of the capacitor CD5, the other end of the switch SW1, the other end of the switch SW2, one end of the resistor R1, and one end of the resistor R7 of the external output terminal plate 261. The other end of the resistor R2 and the other end of the capacitor CD5 are grounded.

  The resistor R2 connected to the TRG terminal of the timer IC1 is connected to the timer R1 when the inner frame 12 and the front frame 14 are in an open state and the switch SW1 and the switch SW2 are in a conductive state (see FIG. 5B). This is a resistor for applying a DC voltage (about 11.3 volts) to the TRG terminal of IC1. The capacitor CD5 is a capacitor for reducing noise generated in the resistor R2 when the switch SW1 and the switch SW2 are turned on or off (when the inner frame 12 and the front frame 14 are opened or closed). It is.

  With the above connection, when the switch SW1 and the switch SW2 are in the cut-off state (when the inner frame 12 and the front frame 14 are in the closed state), no voltage is supplied to the resistor R2 and the capacitor CD5. The applied voltage (the voltage applied to the TRG terminal of the timer IC1) is zero volts. At this time, the voltage output from the OUT terminal of the timer IC 1 is about 10.6 volts.

  On the other hand, when either the switch SW1 or the switch SW2 or both the switch SW1 and the switch SW2 are in a conductive state (either the inner frame 12 or the front frame 14 or both the inner frame 12 and the front frame 14 are Since the voltage is supplied to the resistor R2 and the capacitor CD5 (when in the open state), the voltage applied to the resistor R2 and the capacitor CD5 (the voltage applied to the TRG terminal of the timer IC1) is applied to one end of the capacitor CD1. It is about 11.3 volts which is the same as the applied voltage. At this time, the voltage output from the OUT terminal of the timer IC1 is about 10.6 for about 10 milliseconds after either the switch SW1 or the switch SW2 or both the switch SW1 and the switch SW2 are turned on. It becomes a bolt, and then it becomes zero volts.

  In this way, the voltage output from the OUT terminal of the timer IC 1 can be set to about 10.6 volts or zero volts by the voltage applied to the TRG terminal of the timer IC 1. Note that the switch SW1 or the switch SW2 is turned on (the inner frame 12 or the front frame 14 is opened), and the voltage applied to the TRG terminal of the timer IC1 (voltage applied to the resistor R2) is from zero volts to about 11.3 volts. As described above, the voltage of about 10.6 volts output from the OUT terminal of the timer IC1 falls to zero volts with a delay of about 10 milliseconds from the rise of the voltage as described above. As will be described in detail later, the time difference between the rise of the voltage applied to the TRG terminal of the timer IC1 (voltage applied to the resistor R2) and the fall of the voltage output from the OUT terminal of the timer IC1 ( About 10 msec), a current is supplied to one end of the resistor R7 of the external output terminal plate 261 for about 10 msec, and the photocoupler PR1 of the external output terminal plate 261 is energized for about 10 msec.

  When the switch SW1 and the switch SW2 are cut off (the inner frame 12 and the front frame 14 are closed) and the voltage applied to the TRG terminal of the timer IC1 becomes zero volts, the OUT terminal of the timer IC1 has a voltage of about 10.6 volts. On the other hand, when the switch SW1 or the switch SW2 is turned on (the inner frame 12 or the front frame 14 is opened) and the voltage applied to the TRG terminal of the timer IC1 rises to about 11.3 volts, This is a terminal for setting the output voltage of about 10.6 volts to zero volts with a delay of about 10 milliseconds. This OUT terminal is connected to one end of a 10 kΩ resistor R3. The other end of the resistor R3 is connected to one end of a capacitor CD2 and one end of a 10 kΩ resistor R4, and the other end of the capacitor CD2 and the other end of the resistor R4 are grounded.

  The resistors R3 and R4 are voltage dividing resistors for dividing the voltage output from the OUT terminal of the timer IC1. Therefore, the voltage output from the OUT terminal of the timer IC1 is divided into the resistor R3 and the resistor R4 according to the ratio of the resistance value of the resistor R3 and the resistance value of the resistor R4. Since both the resistor R3 and the resistor R4 are 10 kΩ, the voltage of about 10.6 volts output from the OUT terminal of the timer IC1 is divided into a maximum value of about 5.3 volts by the resistors R3 and R4, respectively. Pressed.

  The 10 μF capacitor CD2 connected in parallel with the resistor R4 is a capacitor for stabilizing the voltage applied to the resistor R4. One end of the capacitor CD2 is connected to one end of the resistor R4, and the other end of the capacitor CD2 is connected to the other end of the resistor R4 and grounded. The capacitor CD2 stabilizes the voltage applied to the resistor R4, thereby stabilizing the bias voltage applied between the base terminal b of the transistor TR1 and the emitter terminal e of the transistor TR1. The operation can be stabilized.

  The transistor TR1 is a switching element that switches between the conduction terminal and the interruption terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 based on the voltage applied to the resistor R4. The transistor TR1 is provided with an internal resistance R5 of 10 kΩ. One end of the internal resistor R5 is connected to one end of the resistor R4, and the other end of the internal resistor R5 is connected to the base terminal b. The transistor TR1 is provided with an internal resistance R6 of 10 kΩ. The other end of the internal resistor R5 is connected to one end of the internal resistor R6, and the emitter terminal e is connected to the other end of the internal resistor R6.

  Therefore, when a voltage of about 10.6 volts is output from the OUT terminal of the timer IC 1 (when the inner frame 12 and the front frame 14 are closed, the inner frame 12 or the front frame 14 is opened). The voltage is divided by the resistor R3 and the resistor R4, and the voltage (about 5.3 volts) applied to the resistor R4 is one end of the internal resistor R5 of the transistor TR1. And the emitter terminal e of the transistor TR1. As a result, the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 are electrically connected. At this time, if the switch SW1 or the switch SW2 is in a conductive state (the inner frame 12 or the front frame 14 is in an open state), the voltage of about 10.6 volts output from the OUT terminal of the timer IC1 is switched to zero volts. That is, a current is supplied to one end of the resistor R7 of the external output terminal board 261 for about 10 milliseconds after the inner frame 12 or the front frame 14 is opened. If a current is supplied to one end of the resistor R7, the photocoupler PR1 of the external output terminal plate 261 can be energized for about 10 milliseconds, and a pulse signal having a pulse width of about 10 milliseconds can be output to the hall computer 262. However, when the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are cut off, the connection between one end of the capacitor CD1 and the resistor R7 provided on the external output terminal plate 261 is cut off. Therefore, no current is supplied to one end of the resistor R7 of the external output terminal plate 261. Accordingly, the photocoupler PR1 of the external output terminal plate 261 is not energized, and no pulse signal is output to the hall computer 262.

  On the other hand, when the OUT terminal voltage of the timer IC1 is zero volts (when about 10 milliseconds have elapsed since the inner frame 12 or the front frame 14 is opened), no voltage is applied to the resistor R4, so that the internal resistance of the transistor TR1. No voltage is applied between one end of R5 and the emitter terminal e of the transistor TR1. Thereby, the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is cut off. Therefore, even if the switch SW1 or the switch SW2 is in a conductive state (the inner frame 12 or the front frame 14 is in an open state), no current is supplied to one end of the resistor R7 of the external output terminal plate 261. Accordingly, the photocoupler PR1 of the external output terminal plate 261 is not energized, and no pulse signal is output to the hall computer 262.

  As described above, when the inner frame 12 or the front frame 14 is in an open state, the photocoupler PR1 of the external output terminal plate 261 can be energized for about 10 milliseconds. Therefore, when the inner frame 12 or the front frame 14 is opened, a pulse signal having a pulse width of about 10 msec can be output from the external output terminal plate 261 to the hall computer 262.

  The TH terminal of the timer IC1 is a terminal that measures a voltage applied to the TH terminal, and is connected to the other end of the resistor R1, one end of the capacitor CD3, and the DCH terminal of the timer IC1. The DCH terminal of the timer IC1 has a voltage (about 7.5 volts) that is 2/3 of the direct current voltage (about 11.3 volts) applied to the VDD terminal of the timer IC1. In this case, the terminal switches the impedance of the DCH terminal from an infinite state to a zero state. When the impedance of the DCH terminal becomes zero (ground state), a voltage cannot be applied to the capacitor CD3. On the other hand, when the impedance of the DCH terminal is infinite, a voltage can be applied to the capacitor CD3.

  The resistor R1 and the capacitor CD3 connected to the TH terminal of the timer IC1 and the DCH terminal of the timer IC1 open the inner frame 12 or the front frame 14 based on the time constant that is the product of the resistance value of the resistor R1 and the capacitor CD3. In this case, it is a part for determining the period until the voltage of about 10.6 volts output from the OUT terminal of the timer IC 1 is switched to zero volts to about 10 milliseconds. One end of the resistor R1 is connected to the other end of the switch SW1, the other end of the switch SW2, and one end of the resistor R7 of the external output terminal board 261. The other end of the resistor R1 is connected to the TH terminal of the timer IC1, the DCH terminal of the timer IC1, and one end of the capacitor CD3. The other end of the capacitor CD3 is grounded.

  Here, the resistor R1 and the capacitor CD3 will be described together with the TRG terminal of the timer IC1, the TH terminal of the timer IC1, the DCH terminal of the timer IC1, and the OUT terminal of the timer IC1.

  When the inner frame 12 and the front frame 14 are in the closed state (when the switch SW1 and the switch SW2 are in the cut-off state), no voltage is supplied to the resistor R1, so the voltage applied to the TH terminal of the timer IC1 is zero volts (about 7.5 volts). Thus, the impedance of the DCH terminal of the timer IC 1 is set to an infinite state. Therefore, a voltage can be applied to the capacitor CD3, and the capacitor CD3 is in a chargeable state (a state in which charge can be stored). However, when the switch SW1 and the switch SW2 are cut off, the connection between one end of the capacitor CD1 and the resistor R1 is cut off, so that no voltage is applied to the capacitor CD3, and the voltage applied to the capacitor CD3 is zero volts. It becomes. Thus, the capacitor CD3 is in a chargeable state, but is not charged. At this time, the voltage at the OUT terminal of the timer IC1 is about 10.6 volts, and the collector terminal c and the emitter terminal e of the transistor TR1 are electrically connected. However, since the switch SW1 and the switch SW2 are in the cut-off state, no current is supplied to one end of the resistor R7 of the external output terminal plate 261. Accordingly, the energization of the external output terminal plate 261 to the photocoupler PR1 is not performed, and no pulse signal is output from the external output terminal plate 261 to the hall computer 262.

  Next, when the inner frame 12 or the front frame 14 is opened (see FIG. 5B) and the switch SW1 or the switch SW2 is turned on, the voltage applied to the TRG terminal of the timer IC1 (resistor R7) The applied voltage) switches from zero volts to about 11.3 volts. At this time, the voltage at the OUT terminal of the timer IC1 is about 10.6 volts, and the collector terminal c and the emitter terminal e of the transistor TR1 are conducted. Therefore, current supply to one end of the resistor R7 is started, and the photocoupler PR1 of the external output terminal plate 261 is energized. As a result, output of a signal to the hall computer 262 is started.

  At the same time that the voltage applied to the TRG terminal of the timer IC1 (the voltage applied to the resistor R7) switches from zero volts to about 11.3 volts, the voltage is applied to the capacitor CD3, and the capacitor CD3 is charged. Be started. At this time, the voltage applied to the TH terminal of the timer IC1 starts to rise.

  The voltage at the OUT terminal of the timer IC1 is 2 / of the voltage (about 11.3 volts) applied to the VDD terminal of the timer IC1 (the voltage applied to the capacitor CD3) applied to the TH terminal of the timer IC1. Continue to maintain about 10.6 volts until equal to a voltage of 3, ie, about 7.5 volts. When the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD2) rises and becomes equal to about 7.5 volts, the impedance of the DCH terminal of the timer IC1 is changed from an infinite state to a zero state (ground To the ( Then, the voltage applied to the capacitor CD3 becomes a zero volt state, and the electric charge stored in the capacitor CD3 is discharged. As a result, the voltage applied to the TH terminal of the timer IC 1 is switched from about 7.5 volts to zero volts. By switching the voltage applied to the TH terminal of the timer IC1, the voltage of the OUT terminal of the timer IC1 is switched from about 10.6 volts to zero volts. Then, the conduction between the collector terminal c and the emitter terminal e of the transistor TR1 is cut off, and the current supply to one end of the resistor R7 is stopped. As a result, energization of the external output terminal plate 261 to the photocoupler PR1 is stopped, and signal output to the hall computer 262 is stopped.

  As described above, when the inner frame 12 or the front frame 14 is in an open state and the switch SW1 or the switch SW2 is in a conductive state (see FIG. 5B), the signal is output from the OUT terminal of the timer IC1. A period until the voltage of about 10.6 volts is switched to zero volts, that is, a period until the voltage applied to the TH terminal of the timer IC1 (voltage applied to the capacitor CD3) is changed from zero volts to about 7.5 volts. Based on the time constant, which is the product of the resistance value of the resistor R1 and the capacitance of the capacitor CD3, it is determined to be about 10 milliseconds. Then, when the inner frame 12 or the front frame 14 is in an open state, supply of current is started to one end of the resistor R7 of the photocoupler PR1 of the external output terminal plate 261. Then, after about 10 msec from the start of current supply to one end of the resistor R7, the voltage of about 10.6 volts output from the OUT terminal of the timer IC1 is switched to zero volts, and the collector terminal c and the emitter of the transistor TR1 The conduction with the terminal e is cut off, and the current supply to one end of the resistor R7 is stopped. As a result, when the inner frame 12 or the front frame 14 is opened, a current is supplied to one end of the resistor R7 of the external output terminal plate 261 for about 10 milliseconds, and the photocoupler PR1 of the external output terminal plate 261 is reduced by about It can be energized only for 10 milliseconds. Therefore, when the inner frame 12 or the front frame 14 is opened, a pulse signal having a pulse width of about 10 milliseconds can be output from the external output terminal plate 261 to the hall computer 262.

  When the inner frame 12 and the front frame 14 are changed from the open state to the closed state (the switch SW1 and the switch SW2 are cut off from the conductive state), that is, the voltage applied to the TRG terminal of the timer IC1 (applied to the resistor R7). When the voltage is switched from about 11.3 volts to zero volts, the voltage at the OUT terminal of the timer IC 1 is switched from zero volts to about 10.6 volts. In this state, as described above, the collector terminal c and the emitter terminal e of the transistor TR1 are in conduction, but the switch SW1 and the switch SW2 are in the cut-off state, so that one end of the resistor R7 of the external output terminal plate 261 is connected. Is not supplied with current. Therefore, the external output terminal plate 261 is not energized to the photocoupler PR1, and no pulse signal is output from the external output terminal plate 261 to the hall computer 262.

  As described above, when the inner frame 12 or the front frame 14 is in an open state, one end of the resistor R7 of the external output terminal plate 261 is based on the time constant that is the product of the resistance value of the resistor R1 and the capacitor CD3. A current is supplied for about 10 milliseconds, and the photocoupler PR1 of the external output terminal plate 261 can be energized for about 10 milliseconds. As a result, when the inner frame 12 or the front frame 14 is opened, a pulse signal having a pulse width of about 10 milliseconds can be output from the external output terminal plate 261 to the hall computer 262.

  Returning to the description of FIG. The CNT terminal of the timer IC 1 is a terminal that adjusts the output period of the voltage output from the OUT terminal of the timer IC 1 by a signal input to the CNT terminal. However, since the open-frame detection circuit 260 does not adjust the output period of the voltage output from the OUT terminal of the timer IC1 (the output period of the voltage output from the OUT terminal of the timer IC1 is fixed to 10 milliseconds), the timer IC1 The CNT terminal is not connected to any part of the frame open detection circuit 260 and the external output terminal plate 261 and is open.

  As described above, when the inner frame 12 or the front frame 14 is in an open state and the switch SW1 or the switch SW2 is in a conductive state (see FIG. 5B), the frame open detection circuit 260 has an external output terminal plate 261. The current supply to one end of the resistor R7 is started. On the other hand, the frame open detection circuit 260 causes the terminal between the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 to be in a conductive state after approximately 10 milliseconds have elapsed since the inner frame 12 or the front frame 14 has been opened. Switching to the cut-off state stops the current supply to one end of the resistor R7 of the external output terminal plate 261. As a result, the photocoupler PR1 of the external output terminal plate 261 is energized for about 10 milliseconds, and a pulse signal having a pulse width of about 10 milliseconds is output from the external output terminal plate 261 to the hall computer 262.

  The door opening detection circuit 260 uses the LMC 555 as the timer IC 1 to detect the opening of the inner frame 12 or the opening of the front frame 14 and realizes a circuit that energizes the photocoupler PR1 for about 10 milliseconds. It is not limited to. That is, a circuit that generates one pulse signal for one opening of the inner frame 12 or one opening of the front frame 14 by using another integrated circuit or the like for the timer IC 1 is realized. Any device may be used as long as the photocoupler PR1 is energized for a predetermined period based on the pulse signal.

  Next, the external output terminal board 261 connected to the frame opening detection circuit 260 and connected to the hall computer 262 will be described. The external output terminal plate 261 has a function of outputting a pulse signal having a pulse width of about 10 milliseconds to the hall computer 262, and is mainly composed of a 1 kΩ resistor R7 and a photocoupler PR1.

  The resistor R7 is a resistor that limits the current supplied to the photocoupler PR1, and one end of the resistor R7 is connected to one end of the resistor R1 of the frame opening detection circuit 260, the other end of the switch SW1, and the other end of the switch SW2. The other end of the resistor R7 is connected to the primary side of the photocoupler PR1 (the anode terminal of the light emitting diode). The photocoupler PR1 is a current switch including a light emitting diode and a light receiving element (phototransistor) that receives light emitted from the light emitting diode. As described above, the light emitting diode which is the primary side of the photocoupler PR1 has an anode terminal connected to one end of the resistor R7 and a cathode terminal connected to the collector terminal c of the transistor TR1 of the frame open detection circuit 260. The light receiving element (phototransistor) that is the secondary side of the photocoupler PR1 is connected to the hall computer 262.

  Accordingly, between the terminal of the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 is approximately 10 milliseconds after the inner frame 12 or the front frame 14 is opened (the switch SW1 or the switch SW2 is in a conductive state). When conducting, current is supplied to the primary light emitting diode of the photocoupler PR1 through the resistor R7, and the light emitting diode emits light for about 10 milliseconds. Then, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 receives the emitted light, and converts the received light of about 10 milliseconds into a pulse signal (electric signal) having a pulse width of about 10 milliseconds. The pulse signal is output to the hall computer 262. The hall computer 262 can store the pulse signal output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1. Therefore, the hall computer 262 can store that the inner frame 12 has been opened or the front frame 14 has been opened.

  On the other hand, when the inner frame 12 and the front frame 14 are closed (when the switch SW1 and the switch SW2 are shut off), no voltage is supplied to one end of the resistor R7, so that the light emitting diode that is the primary side of the photocoupler PR1 Is not supplied with current. Therefore, no pulse signal is output to the hall computer 262 from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1.

  Here, an advantage of using the photocoupler PR1 for the external output terminal plate 261 that outputs a pulse signal to the hall computer 262 will be described. The photocoupler PR1 is configured to convert a current supplied to the light emitting diode on the primary side into light, receive the light in a light receiving element (phototransistor) on the secondary side, and output a pulse signal (electric signal) (light emission) A configuration in which a signal is transmitted in one direction from the diode to the light receiving element). Therefore, an electrical signal such as a pulse signal cannot be transmitted from the secondary side light receiving element (phototransistor) to the primary side light emitting diode. Thereby, even if the open frame detection circuit 260 is connected to the light emitting diode on the primary side of the photocoupler PR1, and the hall computer 262 is connected to the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, the hall computer 262 is connected. It is impossible to transmit an electrical signal such as a pulse signal from the main controller 110 or the like provided with the frame opening detection circuit 260 or the frame opening detection circuit 260. Therefore, the use of the photocoupler PR1 prevents the transmission of an electrical signal such as an illegal pulse signal from the hall computer 262 to the frame opening detection circuit 260, the main controller 110, and the like, and prevents the hall computer from the external output terminal plate 261. 262 has an advantage that a pulse signal can be transmitted.

  Further, in the photocoupler PR1, the primary side light emitting diode and the secondary side light receiving element (phototransistor) are electrically insulated. Therefore, for example, even if electric current is included in the current supplied to the light emitting diode of the photocoupler PR1, the electric noise is not transmitted to the secondary side phototransistor. Therefore, by using the photocoupler PR1, the external output terminal plate 261 has an advantage that it can output an accurate pulse signal to the hall computer 262.

  As described above, the frame opening detection circuit 260 is provided with the 0.1-F capacitor CD1, so that the frame opening detection circuit 260 is supplied with power to the pachinko machine 10 and is supplied with 12 volts from the DC power supply DC1. When the DC voltage is supplied, the operation is naturally performed. Further, for example, the business hours of the amusement hall are terminated, the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is supplied from the DC power supply DC1. Even if it is not done, the opening of the inner frame 12 and the opening of the front frame 14 can be detected. When the frame opening detection circuit 260 detects the opening of the inner frame 12 or the opening of the front frame 14, a pulse signal having a pulse width of about 10 milliseconds can be output from the external output terminal plate 261 to the hall computer 262. . The pulse signal output from the external output terminal board 261 to the hall computer 262 is stored in the hall computer 262 that continues to operate for 24 hours.

  Here, in general, the amusement hall has a security contract with a private security company, and if there is an intruder into the amusement hall, the security company's guards immediately rush to the amusement hall. However, since the cheating is carried out in a short time, when the security guard rushes, in most cases, the intruder has already escaped from the playground, and it is impossible to determine which pachinko machine 10 has been cheated. There was a problem. The pachinko machine 10 that has been cheated must return to a normal state, but if it is not known which pachinko machine 10 has been cheated, the inner frame 12 and the front frame 14 of all the pachinko machines 10 are Opening them and inspecting them one by one, and performing this work at the amusement hall where a large number of pachinko machines 10 are installed, was a heavy labor.

  However, according to the pachinko machine 10 of the present embodiment, when the opening of the inner frame 12 or the opening of the front frame 14 is detected by the frame opening detection circuit 260, a pulse width of approximately from the external output terminal board 261 to the hall computer 262 is detected. A 10 ms pulse signal is output. The outputted pulse signal is stored in the hall computer 262. Therefore, the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened can be specified by the pulse signal stored in the hall computer 262. Further, the hall computer 262 outputs a pulse signal from the external output terminal plate 261 and stores the output time of the output pulse signal, thereby enabling the specified opening time of the inner frame 12 of the pachinko machine 10 or The opening time of the front frame 14 can be detected.

  For example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is shut off, and a DC voltage is supplied from the capacitor CD1 to the frame opening detection circuit 260 and the external output terminal plate 261, the internal When the total supply period of the current from the capacitor CD1 to the photocoupler PR1 due to the opening of the frame 12 or the front frame 14 is increased or the number of times of detecting the opening of the inner frame 12 or the front frame 14 is increased, the capacitor The capacity of CD1 may be increased (for example, the capacity of the capacitor CD1 is set to 1F), or the capacitor CD1 may be changed to a secondary battery with a large storage amount.

  Next, referring to FIG. 8, the TRG terminal voltage (external output terminal plate) of timer IC1 that changes in accordance with the state of switch SW1 (the state of inner frame 12) and the state of switch SW2 (the state of front frame 14). The relationship between the voltage applied to one end of the resistor R7 of 261), the OUT terminal voltage of the timer IC1, and the output of the external output terminal plate 261 (input of the hall computer 262) will be described. 8 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the TRG terminal voltage of the timer IC1 (the voltage applied to one end of the resistor R7 of the external output terminal plate 261). ), A timing chart showing the relationship between the OUT terminal voltage of the timer IC1 and the output of the external output terminal plate 261 (input of the hall computer 262).

  As shown in FIG. 8A, when the switch SW1 becomes conductive (the inner frame 12 is open) at t1, the TRG terminal voltage (external output terminal plate) of the timer IC 1 is shown in FIG. The voltage applied to one end of the resistor R7 of 261) switches from zero volts to about 11.3 volts at t1. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 milliseconds elapse from t1. As a result, current supply to the light emitting diode on the primary side of the photocoupler PR1 of the external output terminal plate 261 (see FIG. 7) is started (at time t1). Then, as shown in FIG. 8E, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 is switched from the low state to the high state at t1. Change. Thereby, output of a pulse signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  When about 10 milliseconds elapse from t1, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts to zero volts as shown in FIG. 8 (d). Then, the current supply to one end of the resistor R7 of the external output terminal plate 261 stops. Therefore, the output of the external output terminal plate 261 switches from the high state to the low state after 10 milliseconds have elapsed since t1. In this way, by switching the output of the external output terminal plate 261, the pulse width of the pulse signal output from the external output terminal plate 261 to the hall computer 262 can be kept at about 10 milliseconds.

  As shown in FIG. 8A, when the switch SW1 is in a cut-off state (inner frame 12 is closed) at t2, the TRG terminal voltage (external output) of the timer IC 1 is shown in FIG. The voltage applied to one end of the resistor R7 of the terminal board 261 is switched from about 11.3 volts to zero volts, and the OUT terminal voltage of the timer IC1 is switched from zero volts to about 10.6 volts (at time t2). As a result, the frame opening detection circuit 260 is set to a state in which the inner frame 12 and the front frame 14 can be detected again.

  Next, as shown in FIG. 8 (a), when the switch SW2 becomes conductive (the front frame 14 is in the open state) at t3, as shown in FIG. 8 (c), the TRG terminal voltage of the timer IC1 (external) The voltage applied to one end of the resistor R7 of the output terminal board 261 is switched from zero volts to about 11.3 volts at t3. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 milliseconds elapse from t3. As a result, the current supply to the light emitting diode on the primary side of the photocoupler PR1 of the external output terminal plate 261 (see FIG. 7) is started (at time t3). Then, as shown in FIG. 8E, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 is switched from the low state to the high state at t3. Change. Thereby, output of a pulse signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  When about 10 milliseconds elapse from t3, as shown in FIG. 8D, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts to zero volts. Then, the current supply to one end of the resistor R7 of the external output terminal plate 261 stops. Therefore, the output of the external output terminal plate 261 switches from the high state to the low state after 10 milliseconds have elapsed since t3. In this way, by switching the output of the external output terminal plate 261, the pulse width of the pulse signal output from the external output terminal plate 261 to the hall computer 262 can be kept at about 10 milliseconds.

  As shown in FIG. 8A, when the switch SW2 is cut off (the front frame 14 is closed), as shown in FIG. 8C, the TRG terminal voltage (external output terminal plate 261) of the timer IC1 is obtained. The voltage applied to one end of the resistor R7 is switched from about 11.3 volts to zero volts, and the OUT terminal voltage of the timer IC1 is switched from zero volts to about 10.6 volts (at time t4). As a result, the frame opening detection circuit 260 is set to a state in which the inner frame 12 and the front frame 14 can be detected again.

  Finally, a case will be described where the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 8A, at time t5, the switch SW1 becomes conductive (inner frame 12 is open), and as shown in FIG. 8B, at time t6, switch SW2 becomes conductive (front surface). When the frame 14 is in the open state), as shown in FIG. 8C, the TRG terminal voltage of the timer IC 1 (the voltage applied to one end of the resistor R7 of the external output terminal plate 261) is about zero volts at t5. Switch to 11.3 volts. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 10 milliseconds elapse from t5. As a result, current supply to the light emitting diode on the primary side of the photocoupler PR1 of the external output terminal plate 261 (see FIG. 7) is started (at time t5). Then, as shown in FIG. 8E, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 is switched from the low state to the high state at t5. Change. Thereby, output of a pulse signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  When about 10 milliseconds elapse from t5, as shown in FIG. 8D, the timer IC1 switches the voltage at the OUT terminal from about 10.6 volts to zero volts. Then, the current supply to one end of the resistor R7 of the external output terminal plate 261 stops. Therefore, the output of the external output terminal plate 261 switches from the high state to the low state after 10 milliseconds have elapsed since t5. In this way, by switching the output of the external output terminal plate 261, the pulse width of the pulse signal output from the external output terminal plate 261 to the hall computer 262 can be kept at about 10 milliseconds.

  As shown in FIG. 8A, at time t7, the switch SW1 is in a cut-off state (the inner frame 12 is closed), and as shown in FIG. 8B, at time t8, the switch SW2 is in a cut-off state. When the front frame 14 is closed, as shown in FIG. 8C, the TRG terminal voltage of the timer IC 1 (the voltage applied to one end of the resistor R7 of the external output terminal plate 261) is about 11.3 volts. From 0 to 0 volt, and the OUT terminal voltage of the timer IC 1 is switched from zero volt to about 10.6 volt (at t8). As a result, the frame opening detection circuit 260 is set to a state in which the inner frame 12 and the front frame 14 can be detected again.

  As described above, even when the switch SW1 is in the conductive state (the inner frame 12 is in the open state) and the switch SW2 is in the conductive state (the front frame 14 is in the open state), the timer IC1 is in the conductive period of the switch SW1. Regardless of the length of the inner frame 12 (the length of the opening period of the inner frame 12) and the length of the conduction period of the switch SW2 (the length of the opening period of the front frame 14), either the switch SW1 or the switch SW2 is in the conductive state. When about 10 milliseconds elapse from when either the inner frame 12 or the front frame 14 is open, the voltage at the OUT terminal is switched from about 10.6 volts to zero volts. As a result, the supply period of the current supplied to the photocoupler PR1 of the external output terminal plate 261 is about 10 milliseconds.

  Therefore, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is cut off, and a DC voltage of 12 volts is not supplied from the DC power supply DC1 to the frame opening detection circuit 260 and the external output terminal plate 261. That is, when a DC voltage of about 11.3 volts is supplied from the capacitor CD1 to the frame open detection circuit 260 and the external output terminal plate 261, the supply period of the current supplied from the capacitor CD1 to the photocoupler PR1 is set as follows. 12 or the front frame 14 can be opened for about 10 milliseconds per opening. Therefore, power consumption due to the opening of the inner frame 12 or the front frame 14 can be reduced.

  Here, since the capacitor CD1 has a capacitance of 0.1 F and the voltage applied to the capacitor CD1 is approximately 11.3 volts, the electric charge stored in the capacitor CD1 is the capacitance of the capacitor CD1 and the applied voltage of the capacitor CD1. From the product of this, it becomes about 1.13C (Coulomb). The electric charge of about 1.13C stored in the capacitor CD1 is about 500 times in terms of the number of times the current is supplied when the single supply period of the current supplied from the capacitor CD1 to the photocoupler PR1 is about 10 milliseconds. Equivalent to. Therefore, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is shut off and a DC voltage of 12 volts is not supplied from the DC power supply DC1, the inner frame 12 is opened (the switch SW1 is turned off). Continuity) or the opening of the front frame 14 (conduction of the switch SW2) is performed a number of times, the frame opening detection circuit 260 opens the inner frame 12 or the front frame 14 (conduction or conduction of the switch SW1). The conduction of the switch SW2) can be reliably detected every time up to about 500 times, and a pulse signal can be output from the external output terminal board 261 to the hall computer 262. At this time, when the opening of the inner frame 12 or the opening of the front frame 14 is about 500 times, the electric charge stored in the capacitor CD1 decreases, and the current value supplied from the capacitor CD1 to the photocoupler PR1 decreases. By increasing the detection sensitivity of the pulse signal of the computer 262 (by reducing the threshold for the amplitude of the pulse signal), the pulse signal can be stored in the hall computer 262.

  In this embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, a pulse signal is output from the external output terminal plate 261 to the hall computer 262. It is not limited to this. That is, when the connection of each part of the main frame opening detection circuit 260 is changed, the inner frame 12 or the front frame 14 is opened, and the opened inner frame 12 or front frame 14 is closed, the photocoupler PR1 is connected. A current may be supplied for about 10 milliseconds to output a pulse signal from the external output terminal board 261 to the hall computer 262.

  However, in the frame open detection circuit 260 of this embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, a pulse signal is sent from the external output terminal board 261 to the hall computer 262. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected quickly. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected before the inner frame 12 or the front frame 14 is opened and an illegal act is performed on the main controller 110 or the game board 13. Accordingly, it is possible to prevent an abnormal operation due to an illegal act occurring when power is supplied to the pachinko machine 10.

  The pulse signal output from the external output terminal board 261 to the hall computer 262 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened can be specified by the pulse signal stored in the hall computer 262. Further, the hall computer 262 outputs a pulse signal from the external output terminal plate 261 and stores the output time of the output pulse signal, thereby enabling the specified opening time of the inner frame 12 of the pachinko machine 10 or The opening time of the front frame 14 can be detected.

  When the inner frame 12 and the front frame 14 are closed (when the switch SW1 and the switch SW2 are shut off), the OUT terminal voltage of the timer IC1 is about 10.6 volts. The terminal between the collector terminal c of the transistor TR1 and the emitter terminal e (see FIG. 7) of the transistor TR1 is brought into conduction. However, at this time, the current flowing through the transistor TR1 is only the base current. The resistors R3 and R5 that determine the current value of the base current both have a resistance value of 10 kΩ, which is sufficiently larger than the resistance value (1 kΩ) of the resistor R7 that limits the current supplied to the photocoupler PR1. Therefore, the current value of the base current can be kept at about 100 μA (note that the current value supplied to the photocoupler PR1 when the switch SW1 and the switch SW2 are turned on is about 11.3 mA). Therefore, the consumption of the electric charge stored in the capacitor CD1 due to the conduction state of the transistor TR1 can be stopped very slightly.

  When the inner frame 12 and the front frame 14 are closed (when the switch SW1 and the switch SW2 are shut off), the OUT terminal voltage of the timer IC1 is about 10.6 volts, so that the OUT terminal of the timer IC1 Current is consumed via the resistor R3 and the resistor R4 connected in series between the resistor and the ground. However, both the resistance R3 and the resistance R4 have a resistance value of 10 kΩ, which is sufficiently larger than the resistance value (1 kΩ) of the resistance R7 that limits the current supplied to the photocoupler PR1. Therefore, when the inner frame 12 and the front frame 14 are closed, the current value flowing from the OUT terminal of the timer IC1 to the ground via the resistor R3 and the resistor R4 can be kept at about 530 μA. Therefore, the consumption of the electric charge stored in the capacitor CD1 by the resistors R3 and R4 can be stopped very slightly.

  When the inner frame 12 and the front frame 14 are closed (when the switch SW1 and the switch SW2 are cut off), the consumption of the charge stored in the capacitor CD1 due to the base current of the transistor TR1 and the resistance R3 and In order to further suppress the consumption of the electric charge stored in the capacitor CD1 by the resistor R4, the resistance values of the resistors R3, R4, and R5 may be made larger than 10 kΩ.

  Further, when the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are cut off, the consumption of charge stored in the capacitor CD1 due to the base current of the transistor TR1 and the capacitor CD1 due to the resistors R3 and R4 In order to reduce the consumption of the electric charge stored in the battery, the following configuration may be used. The switch SW1 and the switch SW2 are further provided with a male switch SW1b and a male switch SW2b, respectively, so that the male switch SW1b and the male switch SW2b disposed in the switch SW1 and the switch SW2 are respectively two. Correspondingly, the female switch SW1a and the female switch SW2a are further provided in the switch SW1 and the switch SW2, respectively, and the female switch SW1a and the female switch SW2a provided in the switch SW1 and the switch SW2 are respectively 2 One by one. Accordingly, one new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1. Similarly to the switch SW1, one combination of the male switch SW2b and the female switch SW2a is also added to the switch SW2. Then, the connection between the OUT terminal of the timer IC1 in the frame opening detection circuit 260 and one end of the resistor R3 is disconnected, and the female switch SW1a newly added to the OUT terminal of the timer IC1 after the disconnection is built in. One end of the pair of terminal pairs SW1c is connected. Then, the other end of the pair of terminal pairs SW1c incorporated in the newly added female switch SW1a is connected to one end of the resistor R3 after the disconnection. Similarly, one end of a pair of terminal pairs SW2c incorporated in the newly added female switch SW2a is connected to the OUT terminal of the timer IC1 after disconnection. Then, the other end of the pair of terminal pairs SW2c incorporated in the newly added female switch SW2a is connected to one end of the resistor R3 after the disconnection. With this configuration, when the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are shut off, about 10.6 volts, which is the OUT terminal voltage of the timer IC1, is set to the resistor R3, It is not applied to the resistor R4 and the resistor R5, and the consumption of the charge stored in the capacitor CD1 by the base current of the transistor TR1 and the consumption of the charge stored in the capacitor CD1 by the resistor R3 and the resistor R4 can be made zero. it can. On the other hand, when either the inner frame 12 or the front frame 14 or both the inner frame 12 and the front frame 14 are open (one of the switches SW1 or SW2, or both the switches SW1 and SW2). Is supplied), the OUT terminal voltage of the timer IC1 is divided and applied to the resistor R3, the resistor R4, the resistor R5, the resistor R6, and the capacitor CD2, thereby supplying the current to the photocoupler PR1. This can be done normally via the resistor R7.

  Note that the connection between the terminal pair SW1c and the terminal pair SW2c by cutting the connection with the OUT terminal of the timer IC1 is not limited to the above. For example, the other end of the resistor R3 and one end of the resistor R4, the resistor R5, and the capacitor CD2 are disconnected, and the other end of the resistor R3 after the disconnection is paired with a female switch SW1a newly added. One end of the terminal pair SW1c is connected. Then, the other ends of the pair of terminals SW1c built in the newly added female switch SW1a are connected to one ends of the resistor R4, the resistor R5 and the capacitor CD2 after the disconnection. Similarly, one end of a pair of terminal pairs SW2c incorporated in the newly added female switch SW2a is connected to the other end of the resistor R3 after disconnection. Then, the other ends of the pair of terminals SW2c incorporated in the newly added female switch SW2a may be connected to one ends of the resistors R4, R5, and the capacitor CD2 after the disconnection. That is, when the inner frame 12 and the front frame 14 are closed by the newly added male switch SW1b and female switch SW1a and the newly added male switch SW2b and female switch SW2a. (When the switch SW1 and the switch SW2 are cut off), the conduction between the OUT terminal of the timer IC 1 and the ground is cut off, while one of the inner frame 12 or the front frame 14 or the inner frame 12 and the front frame 14 Are open (when either switch SW1 or switch SW2 or both switch SW1 and switch SW2 are conductive), resistor R3, resistor R4, resistor R5, resistor R6 and What is necessary is just to comprise so that the OUT terminal voltage of timer IC1 may be divided and applied to the capacitor CD2.

  Further, when it is desired to separately store in the hall computer 262 which of the inner frame 12 and the front frame 14 is opened, the following configuration may be used. First, the frame opening detection circuit 260 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. It may be connected to the provided frame opening detection circuit 260. Specifically, one end of the disconnected switch SW2 is connected to one end of the capacitor CD1 of the newly provided frame opening detection circuit 260, the VDD terminal of the timer IC1, one end of the capacitor CD4, and the RES terminal of the timer IC1 and disconnected. The other end of the switch SW2 may be connected to one end of the capacitor CD5 of the newly provided frame opening detection circuit 260, one end of the resistor R1, and one end of the resistor R7 of the external output terminal board 261. Thus, the frame opening detection circuit 260 and the external output terminal board 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch By connecting only SW1, when the switch SW1 is conductive (the inner frame 12 is opened), the pulse signal output from the existing external output terminal plate 261 and the switch SW2 are conductive (the front frame 14 is opened). ), The pulse signal output from the newly provided external output terminal board 261 can be output separately to the hall computer 262. Here, the hall computer 262 includes an input terminal for a pulse signal output from the existing external output terminal board 261 (for detecting conduction of the switch SW1 (for detecting opening of the inner frame 12)), and a newly provided external output terminal. Input terminals for pulse signals output from the plate 261 (for detecting conduction of the switch SW2 (for detecting opening of the front frame 14)) are separately provided. With this configuration, the conduction of the switch SW1 (opening of the inner frame 12) and the conduction of the switch SW2 (opening of the front frame 14) can be distinguished and stored in the hall computer 262. Therefore, according to the pulse signal stored in the hall computer 262, there was conduction of the switch SW1 (opening of the inner frame 12), conduction of the switch SW2 (opening of the front frame 14), or both. Is accurately detected.

  In addition, when power is supplied to the pachinko machine 10, the hall computer 262 separately stores which of the inner frame 12 and the front frame 14 is opened, and between the inner frame 12 and the front frame 14. When it is desired to notify the pachinko machine 10 when one of them is opened, the following configuration may be used. First, the frame opening detection circuit 260 and the external output terminal plate 261 used in this embodiment are newly provided one by one, the switch SW2 connected in parallel to the switch SW1 is disconnected, and the disconnected switch SW2 is newly installed. Connected to the provided frame opening detection circuit 260. Next, the male switches SW1b and SW2b and the female switches SW1a and SW2a are newly provided for the switch SW1 and the switch SW2, respectively. Then, when the inner frame 12 or the front frame 14 is opened using the newly provided male switches SW1b and SW2b and the female switches SW1a and SW2a and the switch SW1 or the switch SW2 is turned on, a signal is sent to the MPU 201. What is necessary is just to comprise so that it may be input.

  Specifically, one end of the disconnected switch SW2 is connected to one end of the capacitor CD1 of the newly provided frame opening detection circuit 260, the VDD terminal of the timer IC1, one end of the capacitor CD4, and the RES terminal of the timer IC1 and disconnected. The other end of the switch SW2 may be connected to one end of the capacitor CD5 of the newly provided frame opening detection circuit 260, one end of the resistor R1, and one end of the resistor R7 of the external output terminal board 261. Thus, the frame opening detection circuit 260 and the external output terminal board 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch By connecting only SW1, when the switch SW1 is conductive (the inner frame 12 is opened), the pulse signal output from the existing external output terminal plate 261 and the switch SW2 are conductive (the front frame 14 is opened). ), The pulse signal output from the newly provided external output terminal board 261 can be output separately to the hall computer 262.

  Next, male switch SW1b and male switch SW2b are further provided for switch SW1 and switch SW2, respectively, and male switch SW1b and male switch SW2b disposed in switch SW1 and switch SW2 are respectively provided in two. To do. Correspondingly, the female switch SW1a and the female switch SW2a are further provided in the switch SW1 and the switch SW2, respectively, and the female switch SW1a and the female switch SW2a provided in the switch SW1 and the switch SW2 are respectively 2 One by one. As a result, one new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1. Similarly to the switch SW1, one combination of the male switch SW2b and the female switch SW2a is added to the switch SW2. Then, one end of a pair of terminal pairs SW1c built in the newly added female switch SW1a is connected to the DC power source DC1 of the existing frame opening detection circuit 260, and built into the newly added female switch SW1a. The other end of the paired terminal pair SW1c is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by a resistor. Similarly, one end of a pair of terminal pairs SW2c incorporated in the newly added female switch SW2a is connected to the DC power source DC1 of the newly provided frame opening detection circuit 260, and the newly added female type The other end of the pair of terminals SW2c built in the switch SW2a is connected to the input / output port 205 of the MPU 201 via a voltage dividing circuit constituted by a resistor and to a port different from the other end of the terminal pair SW1c. Further, the MPU 201 is supplied from the DC power source DC1 by a voltage of 5 volts (the voltage dividing circuit detects the opening of the inner frame 12 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on. 12 volt voltage is reduced to 5 volts) or 5 volt voltage to detect the opening of the inner frame 14 (12 volt voltage supplied from the DC power supply DC1 is lowered to 5 volt by the voltage dividing circuit) ) Is input to the input / output port 205, a command indicating that the opening of the inner frame 12 or the front frame 14 is detected is transmitted to the audio lamp control device 113 and the display control device 114. At this time, the command transmitted from the MPU 201 includes a command when the opening of the inner frame 12 is detected (hereinafter referred to as “inner frame command”) and a command when the front frame 14 is released (hereinafter referred to as “ This is referred to as “front frame command”. Then, the audio lamp control device 113 that has received these commands performs different notifications depending on whether the inner frame command is received or the front frame command is received. For example, a different warning sound is emitted from the audio output device 226 or the lighting mode of the lamp display device 227 is changed. Further, the display control device 114 that has received each command displays different modes depending on whether the inner frame command is received or the front frame command is received. For example, when the display control device 114 receives an inner frame command, the third symbol display device 81 displays “the inner frame is open” or the display control device 114 receives a front frame command. May be configured to display “front frame is open” on the third symbol display device 81.

  Thus, one new combination of the male switch SW1b and the female switch SW1a is added to the switch SW1, and the new combination of the male switch SW2b and the female switch SW2a is added to the switch SW2 as well as the switch SW1. When one switch is used and the switch SW1 is turned on (when the inner frame 12 is opened), the MPU 201 sends an inner frame command to the audio lamp control device 113 and the display control device 114. Configure to send. Further, when the switch SW2 is turned on (when the front frame 14 is opened), the MPU 201 is configured to transmit a front frame command to the audio lamp control device 113 and the display control device 114. By configuring in this way, notification of a different aspect between when the inner frame 12 is opened and when the front frame 14 is opened is performed using the audio lamp control device 113 and the display control device 114. Can do. As a result, the pachinko machine 10 can be used to accurately determine whether the switch SW1 is conductive (the inner frame 12 is opened), the switch SW2 is conductive (the front frame 14 is opened), or both. Can be detected.

  Further, a frame opening detection circuit 260 and an external output terminal plate 261 are newly provided, and only the switch SW2 is connected to the newly provided frame opening detection circuit 260, and the existing frame opening detection circuit 260 has a switch SW1. Only when the switch SW1 is conductive (the inner frame 12 is opened), the pulse signal output from the existing external output terminal plate 261 and the switch SW2 are conductive (the front frame 14 is opened). In the case where there is, the pulse signal output from the newly provided external output terminal board 261 can be separately output to the hall computer 262. Therefore, according to the pulse signal stored in the hall computer 262, there was conduction of the switch SW1 (opening of the inner frame 12), conduction of the switch SW2 (opening of the front frame 14), or both. Is accurately detected.

  In the present embodiment, the pulse signal output from the external output terminal plate 261 is output to the hall computer 262 having a different installation location from the pachinko machine 10, but the present invention is not limited to this. A dedicated storage device having the function of the hall computer 262 may be provided for each pachinko machine 10, and the dedicated storage device may be provided on the back side of each pachinko machine 10 provided with the main control device 110 and the like. In this case, more preferably, a dedicated storage device such as the main control device 110, the payout control device 111, and the launch control device 112 is stored in the substrate box, and the box base and the box cover provided in the substrate box are stored. Are connected by a sealing unit (not shown) so that they cannot be opened (connection by caulking structure). Then, a seal seal (not shown) is attached to the connecting portion between the box base and the box cover so as to cover the box cover and the box base.

  Next, the display content of the third symbol display device 81 will be described with reference to FIG. FIG. 9 is a diagram for explaining the display screen of the third symbol display device 81, and FIG. 9A is a diagram schematically showing the area division setting and the effective line setting of the display screen, FIG. 9B is a diagram illustrating an actual display screen.

  The third symbol is composed of ten types of main symbols with numbers from “0” to “9” and one type of sub-shaped petal shape formed smaller than this main symbol. Each main symbol is composed of numbers from “0” to “9” on the rear symbol consisting of a wooden box, of which the main symbols with odd numbers (1, 3, 5, 7, 9) are A large number is added to almost the front of the wooden box. On the other hand, the main symbols with even numbers (0, 2, 4, 6, 8) are attached to the front of the wooden box almost fully, and attached symbols imitating characters such as furoshiki and helmets are added. An even number is small in green on the lower right side of the attached symbol and is added so as to be displayed on the front side of the attached symbol.

  Further, in the pachinko machine 10 according to the present embodiment, when the lottery result by the main control device 110 is a big win, a variable display in which the same main symbols are arranged is performed, and a big hit occurs after the variable display is finished. It is configured to When shifting to the high probability state (probability variation state) after the big hit, the variable display in which the main symbols (corresponding to “high probability symbols”) to which odd numbers are added is arranged. On the other hand, when shifting to the low probability state after the big hit, the variable display is performed in which the main symbols to which the even numbers are added (corresponding to “low probability symbols”) are arranged. Here, the high probability state refers to a state in which the subsequent jackpot probability is increased as an added value after the jackpot ends, that is, a so-called probability fluctuation (probability change). Further, the normal state (low probability state) refers to a time when the probability of hitting is not probable, and refers to a state where the probability of jackpot is normal, that is, a state where the probability of jackpot is lower than that during probability change.

  As shown in FIG. 9 (a), the display screen of the third symbol display device 81 is roughly divided into two vertically, and the lower 2/3 is the main display area Dm in which the third symbol is variably displayed, and the others. The upper third is a sub display area Ds for displaying a notice effect and a character.

  In the main display area Dm, three symbol rows Z1, Z2, and Z3 of left, middle, and right are displayed. In each symbol row Z1 to Z3, the above-described third symbols are displayed in a prescribed order. That is, in each symbol row Z1 to Z3, main symbols are arranged in ascending or descending numerical order, and one sub symbol is arranged between each main symbol. For this reason, a total of 20 third symbols of 10 main symbols and 10 sub-designs are set in each symbol row, and each symbol row Z1 to Z3 scrolls from top to bottom with periodicity. The display is changed. In particular, the left symbol row Z1 is arranged so that the numbers of the main symbols appear in descending order, and the middle symbol row Z2 and the right symbol row Z3 are arranged so that the numbers of the main symbols appear in ascending order.

  In the main display area Dm, the third symbols are displayed in the upper, middle, and lower three rows for each symbol row Z1 to Z3. Accordingly, the third symbol display device 81 displays a total of nine third symbols of 3 rows × 3 columns. In the main display area Dm, five effective lines, that is, an upper line L1, a middle line L2, a lower line L3, a right rising line L4, and a left rising line L5 are set. In each game, the variable display stops in the order of the left symbol row Z1 → the right symbol row Z3 → the middle symbol row Z2, and the combination of jackpot symbols on any active line at the time of the stop (in this embodiment, A jackpot video is displayed as a jackpot if the same combination of main symbols) is arranged.

  The sub display area Ds is horizontally long above the main display area Dm, and is further equally divided into three notice areas Ds1 to Ds3 in the left-right direction. Here, the left and right notice areas Ds1, Ds3 are usually covered with double-open opaque doors that are electrically opened and closed by solenoids (not shown), and sometimes the solenoids are excited and the doors are on the front side. It is a display area that is visible to the player when it is opened. The center notice area Ds2 is a display area that is always visible without being covered by the door.

  As shown in FIG. 9B, on the actual display screen, a total of nine main symbols and sub-designs of the third symbol are displayed in the main display area Dm. In the sub display area Ds, the left and right doors are closed, and the left and right notice areas Ds1, Ds3 are covered and the display screen cannot be visually recognized. If either one of the left and right doors or both doors are opened during the variable display, a video is displayed in the left and right notice areas Ds1 and Ds3, and it is easy for the player to change to a big hit than usual. It is suggested. In the notice area Ds2 in the center, a predetermined character (a boy with a bee in this embodiment) usually performs a predetermined action, sometimes performs a special action different from the predetermined action, or another character A notice effect is performed by appearing. The display screen of the third symbol display device 81 is divided into upper and lower display areas Dm and Ds in principle, but the third symbol and characters are displayed larger across the display areas Dm and Ds. A display effect can be performed.

  Next, a counter and the like provided in the RAM 203 of the main controller 110 will be described with reference to FIG. These counters and the like are used by the MPU 201 of the main control device 110 to perform jackpot lottery, display setting of the first symbol display device 37, lottery of display results of the second symbol display device 82, and the like.

  For the jackpot lottery or display setting of the first symbol display device 37, the first hit random number counter C1 used for the jackpot lottery, the first hit type symbol counter C2 used for the jackpot symbol selection, and the stop pattern selection counter C3, a first initial value random number counter CINI1 used for setting an initial value of the first per-random number counter C1, and variation type counters CS1, CS2, CS3 used for variation pattern selection are used. The second symbol random number counter C4 is used for the lottery of the second symbol display device 82, and the second initial random number counter CINI2 is used for setting the initial value of the second random number counter C4. Each of these counters is a loop counter that adds 1 to the previous value every time it is updated and returns to 0 after reaching the maximum value.

  Each counter is updated at an interval of 4 milliseconds, which is the execution interval of the main process (see FIG. 12), or at an interval of 2 milliseconds, which is the execution interval of the timer interrupt process (see FIG. 15). Are stored in the counter buffer set as follows. The RAM 203 is provided with a holding ball storage area composed of one execution area and four holding areas (holding first to fourth areas). The values of the first per-random number counter C1, the first per-type counter C2, and the stop pattern selection counter C3 are stored in accordance with the ball winning timing.

  Each counter will be described in detail. The first random number counter C1 is configured so that, for example, 1 is added in order within a range of 0 to 738, and after reaching the maximum value (that is, 738), it returns to 0. In particular, when the first random number counter C1 makes one round, the value of the first initial value random number counter CINI1 at that time is read as the initial value of the first random number counter C1. The first initial value random number counter CINI1 is configured as a loop counter that is updated in the same range as the first per-random number counter C1 (value = 0 to 738), and each time the timer interrupt process (see FIG. 15) is executed. It is updated once and updated repeatedly within the remaining time of the main process (see FIG. 12). The value of the first per-random number counter C1 is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the stored ball is stored in the RAM 203 at the timing when the ball wins the first entrance 64. Stored in the area. The number of random number values that are jackpots is set at low probability and high probability, and the number of random numbers that are jackpots at low probability is 2, and the value is “373, 727” There are 14 random numbers that are big hits at high probability, and the values are "59, 109, 163, 211, 263, 317, 367, 421, 479, 523, 631, 683, 733".

  The first hit type counter C2 determines the display mode of the first symbol display device 37 at the time of the big hit. In the present embodiment, the first hit type counter C2 is incremented one by one within the range of 0 to 4, and the maximum value ( That is, it is configured to return to 0 after reaching 4). The value of the first hit type counter C2 is updated, for example, periodically (once every timer interruption process in this embodiment), and the stored ball is stored in the RAM 203 at the timing when the ball wins the first entrance 64. Stored in the area. In addition, the value of the random number that becomes a high probability state after the jackpot is “1, 2, 3”, the value of the random number that becomes the low probability state after the jackpot is “0, 4”, and two types of hits are determined. The Therefore, the display mode corresponding to the stop symbol displayed on the first symbol display device 37 is a display mode corresponding to two types of jackpots of a high probability state and a low probability state, and one type of display mode corresponding to a deviation. Any one of the three display modes is selected.

  The stop pattern selection counter C3 is, for example, incremented by 1 in the range of 0 to 238, and returns to 0 after reaching the maximum value (that is, 238). In the present embodiment, after the stop pattern selection counter C3 selects the effect pattern displayed on the third symbol display device 81 and the reach occurs, the final stop symbol is shifted by one before and after the reach symbol. “Stop before and after detachment reach” (for example, a range of 0 to 8) and “Leach other than detachment before and after detachment” (for example, a range of 9 to 38) after the reach has occurred and the final stop symbol stops at other than before and after the reach design. The three stop (effect) patterns are selected as “completely out” (for example, a range of 39 to 238) that does not cause reach. The value of the stop pattern selection counter C3 is updated, for example, periodically (once every timer interrupt process in the present embodiment), and the reserved ball storage area of the RAM 203 at the timing when the ball wins the first entrance 64. Stored in

  Further, the stop pattern selection counter C3 is provided with a plurality of tables having different ranges of random number values from which the stop pattern is selected. This is based on whether the current state of the pachinko machine 10 is a high probability state or a low probability state, in which area of the reserved ball storage area each random number value is stored (that is, the number of reservations), etc. This is to change the stop pattern selection ratio.

  For example, in a high probability state, a table with a wide random value range of 10 to 238 corresponding to the stop pattern of “completely out” is selected so that a jackpot is likely to occur and a reach effect is not selected more than necessary. It becomes easy to select “completely off”. In this table, “front / rear out of reach” is narrowed to 0-5, and “reach other than front / rear out of reach” is also narrowed to 6-9, making it difficult to select “rear out of front / rear out of reach” or “reach out of front / rear out of reach”. Further, if each random number value is not stored in the holding ball storage area in a low probability state, a disturbance corresponding to the stop pattern of “completely off” in order to secure the time for the ball to enter the first entrance 64. A table with a narrow numerical value range of 51 to 238 is selected, and “completely out” is difficult to select. In this table, the range of random numbers corresponding to the stop pattern of “reach other than front / rear deviation” is as wide as 9 to 50, and “reach other than front / rear deviation” is easily selected. Therefore, in the low probability state, the ball entry time to the first entrance 64 can be secured, and therefore, the variable display by the third symbol display device 81 is easily performed continuously.

  Of the two variation type counters CS1 and CS2, one variation type counter CS1 is incremented one by one in the range of 0 to 198, for example, and reaches a maximum value (that is, 198) and then returns to 0. On the other hand, the other variation type counter CS2 is, for example, incremented by 1 in order within a range of 0 to 240, and returns to 0 after reaching the maximum value (that is, 240). In the following description, CS1 is also referred to as “first variation type counter”, and CS2 is also referred to as “second variation type counter”.

  Rough display modes such as so-called normal reach, super reach, and premium reach are determined by the first variation type counter CS1. Specifically, the display mode is determined by determining the variation time of the symbol variation. Further, the second variation type counter CS2 determines a variation time (in other words, the number of variation symbols) until the final stop symbol (in this embodiment, the middle symbol) stops after the occurrence of reach. Based on the variation time determined by the variation type counters CS1 and CS2, the display control device 114 determines the reach type of the third symbol displayed on the third display device 81 and the detailed symbol variation mode. Therefore, a variety of variation patterns can be easily realized by combining these variation type counters CS1 and CS2. It is also possible to determine the symbol variation mode only by the first variation type counter CS1, or to determine the symbol variation mode similarly by the combination of the first variation type counter CS1 and the stop symbol. The values of the variation type counters CS1 and CS2 are updated once every time a main process (see FIG. 12) described later is executed once, and are repeatedly updated within the remaining time in the main process.

  For example, the value of the variation type counter CS3 is sequentially incremented by 1 within a range of 0 to 162, and returns to 0 after reaching the maximum value (that is, 162). In the following description, CS3 is also referred to as a “third variation type counter”. The 3rd symbol display device 81 of this Embodiment performs the decorative production according to the display mode of the 1st symbol display device 37, and can slide the symbol which is changing in addition to the variation of a symbol. A notice effect such as passing a notice character for notifying the occurrence of the reach effect is performed. The effect pattern of the notice effect is selected by the variation type counter CS3. Specifically, the time required for the notice effect is added to the variable time, or on the contrary, the variable time is subtracted to shorten the variable display time, or an effect pattern that does not add or subtract the variable time is selected. . As with the stop pattern selection counter C3, the variation type counter CS3 is provided with a plurality of tables with different ranges of random values from which the production pattern is selected, and whether the current state of the pachinko machine 10 is in a high probability state. Depending on the low probability state or in which area of the reserved ball storage area each random value is stored, the selection ratio of each effect pattern is different.

  As described above, the variation time of the symbol variation is determined by the variation type counters CS1 and CS2, and the time to be added to or subtracted from the variation time is determined by the variation type counter CS3. Therefore, the final fluctuation time until the final stop symbol stops is determined by the fluctuation type counters CS1, CS2, CS3.

  The second random number counter C4 is configured as a loop counter that is incremented one by one within a range of 0 to 250, for example, and returns to 0 after reaching the maximum value (that is, 250). In the present embodiment, the value of the second random number counter C4 is updated periodically, for example, every timer interrupt process, and the ball has passed through the second entrance (through gate) 67 on either the left or right side. Obtained when detected. The number of random number values to be won is 149, and the range is “5 to 153”. The second initial value random number counter CINI2 is configured as a loop counter that is updated within the same range as the second per-random number counter C4 (value = 0 to 250), and is once per timer interrupt process (see FIG. 15). In addition to being updated, it is repeatedly updated within the remaining time of the main process (see FIG. 12).

  Next, each control process executed by the MPU 201 in the main controller 110 will be described with reference to the flowcharts of FIGS. 11 to 17. The processing of the MPU 201 is roughly divided into a startup process that is started when the power is turned on, a main process that is executed after the startup process, and a startup process periodically (in this embodiment, at a cycle of 2 milliseconds). There are a timer interrupt process and an NMI interrupt process activated by the input of the power failure signal SG1 to the NMI terminal. For convenience of explanation, the timer interrupt process and the NMI interrupt process are described first, and then the startup process And the main process will be described.

  FIG. 15 is a flowchart showing the timer interrupt process. The timer interrupt process is executed by the MPU 201 of the main control device 110, for example, every 2 milliseconds. In the timer interrupt process, first, a process for reading various winning switches is executed (S501). That is, the state of various switches connected to the main controller 110 is read, and the state of the switch is determined and the detection information (winning detection information) is stored.

  Next, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S502). Specifically, the first initial value random number counter CINI1 is incremented by 1 and cleared to 0 when the counter value reaches the maximum value (738 in the present embodiment). Then, the updated value of the first initial value random number counter CINI 1 is stored in the corresponding buffer area of the RAM 203. Similarly, 1 is added to the second initial value random number counter CINI2, and when the counter value reaches the maximum value (250 in the present embodiment), it is cleared to 0, and the second initial value random number counter CINI2 is updated. The value is stored in the corresponding buffer area of the RAM 203.

  Further, the first per-random number counter C1, the first per-type counter C2, the stop pattern selection counter C3, and the second per-random number counter C4 are updated (S503). Specifically, the first per-random number counter C1, the first per-type counter C2, the stop pattern selection counter C3, and the second per-random number counter C4 are each incremented by 1 and their counter values are the maximum values (this embodiment) Then, when they reach 738, 4, 238, 250), they are cleared to 0. Then, the updated values of the counters C1 to C4 are stored in the corresponding buffer area of the RAM 203.

  Thereafter, a start winning process (see FIG. 16) associated with winning in the first entrance 64 is executed (S504), a firing control process is executed (S505), and the timer interrupt process is terminated. Note that the launch control process detects that the player is touching the operation handle 51 with the touch sensor 51a and turns on the launch of the ball on the condition that the stop switch 51b for stopping the launch is not operated. This is a process of determining / off. The main controller 110 instructs the launch controller 112 to launch a sphere when the launch of the sphere is on.

  Here, the start winning process executed in the process of S504 will be described with reference to the flowchart of FIG. FIG. 16 is a flowchart showing the start winning process (S504) executed in the timer interruption process (see FIG. 15).

  When this start winning process is executed, first, it is determined whether or not the ball has won a first winning opening 64 (start winning) (S601). If it is determined that the ball has won the first entrance 64 (S601: Yes), whether or not the number N of the operation reserved balls of the first symbol display device 37 is less than the upper limit (4 in the present embodiment). Is determined (S602). If there is a winning at the first entrance 64 and the number of reserved balls N <4 (S602: Yes), the number of reserved balls N is incremented by 1 (S603), and further updated in step S503. The values of the first per-random number counter C1, the first per-type counter C2, and the stop pattern selection counter C3 are stored in the first area among the free reserved areas in the reserved ball storage area of the RAM 203 (S604). On the other hand, if there is no winning at the first entrance 64 (S601: No), or even if there is a winning at the first entrance 64, if the number N of operational balls is not less than 4 (S602: No) , S603 and S604 are skipped, the start winning process is terminated, and the process returns to the timer interrupt process.

  FIG. 17 is a flowchart showing the NMI interrupt process. The NMI interrupt process is a process executed by the MPU 201 of the main controller 110 when the power of the pachinko machine 10 is shut off due to the occurrence of a power failure or the like. By this NMI interrupt processing, information on occurrence of power interruption is stored in the RAM 203. That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, the power failure signal SG1 is output from the power failure monitoring circuit 252 to the NMI terminal of the MPU 201 in the main controller 110. Then, the MPU 201 interrupts the control being executed and starts the NMI interrupt process, stores the power-off occurrence information in the RAM 203 as a setting of the power-off occurrence information (S651), and ends the NMI interrupt process. To do.

  The above NMI interrupt process is executed in the same manner in the payout and emission control device 111, and information on the occurrence of power interruption is stored in the RAM 213 by the NMI interrupt process. That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, the power failure signal SG1 is output from the power failure monitoring circuit 252 to the NMI terminal of the MPU 211 in the payout and emission control device 111, and the MPU 211 interrupts the control being executed. Then, the NMI interrupt process is started.

  Next, referring to FIG. 11, a startup process when the main controller 110 is powered on will be described. FIG. 11 is a flowchart showing start-up processing executed by the MPU 201 in the main controller 110. This start-up process is activated by a reset at power-on. In the start-up process, first, an initial setting process associated with power-on is executed (S101). Specifically, a predetermined value set in advance in the stack pointer is set, and the sub-side control devices (peripheral control devices such as the audio lamp control device 113 and the payout control device 111) become operable. In order to wait, a wait process (1 second in this embodiment) is executed. Next, access to the RAM 203 is permitted (S103).

  Thereafter, it is determined whether or not the RAM erase switch 122 (see FIG. 3) provided in the power supply device 115 is turned on (S104). If it is turned on (S104: Yes), the process proceeds to S110. On the other hand, if the RAM erasure switch 122 is not turned on (S104: No), it is further determined whether or not the power-off occurrence information is stored in the RAM 203 (S105), and if not stored (S105: No). Since there is a possibility that the process at the time of the previous power shutdown has not been completed normally, the process proceeds to S110 also in this case.

  If power failure occurrence information is stored in the RAM 203 (S105: Yes), a RAM determination value is calculated (S106). If the calculated RAM determination value is not normal (S107: No), that is, the calculated RAM If the determination value does not match the RAM determination value stored at the time of power-off, the backed up data has been destroyed. In such a case as well, the process proceeds to S110. Note that the RAM determination value is, for example, a checksum value at the work area address of the RAM 203, as will be described later in the processing of S213 in FIG. Instead of the RAM determination value, the validity of the backup may be determined based on whether or not the keyword written in a predetermined area of the RAM 203 is correctly stored.

  In the process of S111, a payout initialization command is transmitted in order to initialize the payout control device 111 as a sub-side control device (peripheral control device) (S111). Upon receiving this payout initialization command, the payout control device 111 clears an area (work area) other than the stack area of the RAM 213, sets an initial value, and enters a state in which game ball payout control can be started. After transmitting the payout initialization command, main controller 110 executes initialization processing (S112, S113) of RAM 203.

  As described above, in the pachinko machine 10, when RAM data is initialized when the power is turned on, for example, when the hall starts business, the power is turned on while the RAM erase switch 122 is pressed. Therefore, if the RAM erase switch 122 is pressed during the start-up process, the RAM initialization process (S112, S113) is executed. Similarly, initialization processing (S112, S113) of the RAM 203 is executed even when the information on occurrence of power interruption is not set or when a backup abnormality is confirmed by the RAM determination value (checksum value or the like). . In the RAM initialization process (S112, S113), the used area of the RAM 203 is cleared to 0 (S112), and then the initial value of the RAM 203 is set (S113). After executing the initialization process of the RAM 203, the process proceeds to S110.

  On the other hand, if the RAM erasure switch 122 is not turned on (S104: No), the information on occurrence of power interruption is stored (S105: Yes), and the RAM judgment value (checksum value etc.) is normal ( S107: Yes), the information on the occurrence of power interruption is cleared while the backed up data is held in the RAM 203 (S108). Next, a payout return command at the time of power recovery for returning the sub-side control device (peripheral control device) to the gaming state at the time of driving power interruption is transmitted (S109), and the process proceeds to S110. When the payout control device 111 receives this payout return command, the payout control device 111 is in a state where the payout control of the game ball can be started while holding the data stored in the RAM 213. In the process of S110, the interruption is permitted and the process proceeds to a main process described later.

  Next, with reference to FIG. 12, the main process executed after the above-described startup process will be described. FIG. 12 is a flowchart showing main processing executed by the MPU 201 in the main controller 110. In this main process, the main process of the game is executed. As an outline, each process of S201 to S206 is executed as a periodic process with a period of 4 milliseconds, and the counter update process of S209 and S210 is executed in the remaining time.

  In the main process, first, output data such as a command updated in the previous process is transmitted to each control device (peripheral control device) on the sub-side (S201). Specifically, the presence / absence of winning detection information detected in the switch reading process of S501 is determined, and if there is winning detection information, a winning ball command corresponding to the number of acquired balls is transmitted to the payout control device 111. In addition, by this external output process, a variation pattern command, a stop symbol command, a stop command, an effect time addition command, etc. necessary for the third symbol variation display by the third symbol display device 81 are transmitted to the sound lamp control device 113. Further, when launching a sphere, a sphere launch signal is transmitted to the launch controller 112.

  Next, each value of the variation type counters CS1, CS2, CS3 is updated (S202). Specifically, the variation type counters CS1, CS2, CS3 are incremented by 1, and are cleared to 0 when their counter values reach the maximum value (198, 240, 162 in this embodiment). Then, the update values of the variation type counters CS 1, CS 2 and CS 3 are stored in the corresponding buffer area of the RAM 203.

  When the update of the variation type counters CS1, CS2 and CS3 is completed, the winning ball counting signal and the payout abnormality signal received from the payout control device 111 are read (S203), and the process for displaying on the first symbol display device 37 is performed. A variation process for setting a variation pattern of the third symbol and the like by the three symbol display device 81 is executed (S204). Details of the variation process will be described later with reference to FIG.

  After the end of the variation process, a large opening opening / closing process for opening or closing the specific winning opening (large opening) 65a of the variable winning device 65 is executed in the case of the big win state (S205). That is, the specific winning opening 65a is opened for each round of the big hit state, and it is determined whether the maximum opening time of the specific winning opening 65a has elapsed or whether a specified number of balls have won the specific winning opening 65a. When any of these conditions is met, the specific winning opening 65a is closed. The opening and closing of the specific winning opening 65a is repeated for a predetermined number of rounds.

  Next, a display control process of the second symbol (for example, the symbol “◯” or “x”) by the second symbol display device 82 is executed (S206). Briefly, on the condition that the ball has passed through the second entrance (through gate) 67, the value of the second random number counter C4 is acquired at the timing of the passage, and the second symbol display device 82 is obtained. In the display unit 83, the second symbol variation display is performed. Then, the lottery of the second symbol is performed according to the value of the second winning random number counter C4, and when the winning state of the second symbol is reached, the electric accessory attached to the first entrance 64 is released for a predetermined time.

  Thereafter, it is determined whether or not the power failure occurrence information is stored in the RAM 203 (S207). If the power failure occurrence information is not stored in the RAM 203 (S207: No), a power failure signal is output from the power failure monitoring circuit 252. SG1 is not output and the power supply is not shut off. Therefore, in such a case, it is determined whether or not the execution timing of the next main process has been reached, that is, whether or not a predetermined time (4 ms in the present embodiment) has elapsed since the start of the previous main process (S208). If the predetermined time has already passed (S208: Yes), the process proceeds to S201, and the above-described processes after S201 are repeatedly executed.

  On the other hand, if the predetermined time has not yet elapsed since the start of the previous main process (S208: No), the first time is reached until the predetermined time, that is, within the remaining time until the next main process execution timing. The updating of the initial value random number counter CINI1, the second initial value random number counter CINI2, and the variation type counters CS1, CS2, and CS3 is repeatedly executed (S209, S210).

  First, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S209). Specifically, 1 is added to the first initial value random number counter CINI1 and the second initial value random number counter CINI2, and when the counter value reaches the maximum value (738, 250 in this embodiment), it is cleared to 0. To do. Then, the updated values of the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are stored in the corresponding buffer areas of the RAM 203, respectively.

  Next, the fluctuation type counters CS1, CS2, and CS3 are updated (S210). Specifically, the variation type counters CS1, CS2, CS3 are incremented by 1, and are cleared to 0 when their counter values reach the maximum value (198, 240, 162 in this embodiment). Then, the update values of the variation type counters CS1, CS2, and CS3 are stored in the corresponding buffer areas of the RAM 203, respectively.

  Here, since the execution time of each process of S201-S206 changes according to the state of the game, the remaining time until the next main process execution timing is not constant and varies. Therefore, by repeatedly performing the update of the first initial value random number counter CINI1 and the second initial value random number counter CINI2 using the remaining time, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 (that is, , The initial value of the first per-random number counter C1 and the initial value of the second per-random number counter C4) can be updated at random. Similarly, the variation type counters CS1, CS2, and CS3 can be updated at random.

  In the process of S207, if the power failure occurrence information is stored in the RAM 203 (S207: Yes), the power failure is caused by the occurrence of a power failure or the power is turned off, and the power failure monitoring circuit 252 outputs the power failure signal SG1. As a result, since the NMI interrupt process of FIG. 17 has been executed, the power-off process after S211 is executed. First, the generation of each interrupt process is prohibited (S211), and a power-off command indicating that the power has been cut off is sent to other control devices (peripheral control devices such as the payout control device 111 and the voice lamp control device 113). (S212). Then, the RAM determination value is calculated and stored (S213), access to the RAM 203 is prohibited (S214), and the infinite loop is continued until the power supply is completely shut down and the process cannot be executed. Here, the RAM determination value is, for example, a checksum value in the stack area and work area to be backed up in the RAM 203.

  Note that the processing of S207 is performed at the timing when the series of processing corresponding to the game state change performed in S201 to S206 is completed, or at the end of one cycle of the processing of S209 and S210 performed within the remaining time. It is running. Therefore, in the main process of the main controller 110, the occurrence information of the power supply interruption is confirmed at the timing when each setting is completed. Therefore, when returning from the power interruption state, the process is performed after the start-up process is completed. It can start from the process of S201. That is, the process can be started from the process of S201 as in the case where the process is initialized in the startup process. Therefore, in the process at power-off, the stack pointer is not stored in the initial setting process (S101) without saving the contents of each register used by the MPU 201 to the stack area or saving the value of the stack pointer. By setting to a predetermined value (initial value), it is possible to start from the process of S201. Therefore, it is possible to reduce the control burden on the main control device 110 and to perform accurate control without causing the main control device 110 to malfunction or run away.

  Next, the variation process (S204) will be described with reference to FIG. FIG. 13 is a flowchart showing the variation process (S204) executed in the main process (see FIG. 12). In this variation process, first, it is determined whether or not a big hit is currently being made (S301). The jackpot includes the jackpot game displayed on the third symbol display device 81 and the first symbol display device 37 in the jackpot and the middle of a predetermined time after the jackpot game ends. As a result of the determination, if it is a big hit (S301: Yes), this processing is terminated as it is.

  If it is not a big hit (S301: No), it is determined whether or not the display mode of the first symbol display device 37 is changing (S302), and if the display mode of the first symbol display device 37 is not changing. (S302: No), it is determined whether or not the number N of active suspension balls is greater than 0 (S303). If the number N of active balls is 0 (S303: No), this process is terminated as it is. If the number of the operation hold balls N> 0 (S303: Yes), the operation hold ball number N is decremented by 1 (S304), and the data stored in the hold ball storage area is shifted (S305). This data shift process is a process of sequentially shifting the data stored in the reserved first to fourth areas of the reserved ball storage area to the execution area side, and the reserved first area → execution area, reserved second area → The data in each area is shifted such as the first hold area, the third hold area → the second hold area, the fourth hold area → the third hold area. After the data shift process, the fluctuation start process of the first symbol display device 37 is executed (S306). The variation start process will be described later with reference to FIG.

  In the process of S302, if it is determined that the display mode of the first symbol display device 37 is changing (S302: Yes), it is determined whether or not the change time has elapsed (S307). The display time during fluctuation of the first symbol display device 37 is determined according to the fluctuation pattern selected by the fluctuation type counters CS1 and CS2 and the addition time selected by the fluctuation type counter CS3. If it has not elapsed (S307: No), the display of the first symbol display device 37 is updated (S308).

  In the present embodiment, among the LEDs 37a of the first symbol display device 37, for example, if the currently lit LED is red until the variation time elapses after the variation starts, the red LED is Turn off and turn on the green LED. If the green LED is on, turn off the green LED and turn on the blue LED. If the blue LED is on, turn on the blue LED. A display mode is set for turning off the red LED and turning on the red LED.

  The variation process is executed every 4 milliseconds, but if the LED lighting color is changed every time the variation process is executed, the player cannot confirm the change in the LED lighting color. Therefore, a counter (not shown) is counted once each time the variation process is executed so that the player can confirm the change in the lighting color of the LED. Change the lighting color of. That is, the lighting color of the LED is changed every 0.4 s. The counter value is reset to 0 when the lighting color of the LED is changed.

  On the other hand, if the variation time of the first symbol display device 37 has elapsed (S307: Yes), a display mode corresponding to the stop symbol of the first symbol display device 37 is set (S309). Whether or not the stop symbol is set is determined according to the value of the first random number counter C1, and if it is a big hit, the symbol that becomes a high probability state after the big hit by the value of the first hit type counter C2 Or a symbol that is in a low probability state is determined. In this embodiment, a red LED is turned on when a high probability state is reached after a big hit, a green LED is turned on when a low probability state is reached, and a blue LED is turned on when it is out of place. . In addition, although the lighting of each LED is released when the next fluctuation display is started, it may be turned on only for a few seconds after the fluctuation stops.

  When the display mode of the first symbol display device 37 corresponding to the stop symbol is set in the processing of S309, the variation stop of the third symbol display device 81 is stopped to synchronize with the lighting of the LED in the first symbol display device 37. A command is set (S310). When the sound lamp control device 113 receives this stop command, it instructs the display control device 114 to stop. When the variation time elapses, the third symbol display device 81 stops the variation, and receives the stop command, whereby one variation effect in the third symbol display device 81 ends.

  Next, the variation start process will be described with reference to FIG. FIG. 14 is a flowchart showing the change start process (S306) executed in the change process (see FIG. 13). In the variation start process (S306), first, it is determined whether or not a big hit is made based on the value of the first hit random number counter C1 stored in the execution area of the reserved ball storage area (S401). Whether or not it is a big hit is determined based on the relationship between the value of the first random number counter C1 and the mode at that time. As described above, “373,727” is a winning value among the numerical values 0 to 738 of the first random number counter C1 at the normal low probability, and “59, 109, 163, 211, 263, 317, 367, "421,479,523,631,683,733" is the winning value.

  When it is determined that it is a big hit (S401: Yes), the value of the first hit type counter C2 stored in the execution area of the reserved ball storage area is confirmed, and the display mode for the big hit is set (S402). ). In the process of S402, based on the value of the first hit type counter C2, whether to shift to the high probability state or shift to the low probability state after the big hit is set. When the transition state after the big hit is set, the display mode of the first symbol display device 37 (the lighting state of the LED 37a) is set. Further, based on the transition state after the jackpot, the jackpot stop symbol stopped and displayed on the third symbol display device 81 is set by the sound lamp control device 113 and the display control device 114. That is, the stop symbol in the third symbol display device 81 is set by setting the transition state after the big hit by the process of S402. Of the numerical values 0 to 4 of the first hit type counter C2, when “0, 4”, the state shifts to the low probability state, and when “1, 2, 3”, the state shifts to the high probability state. .

  Next, a variation pattern at the time of jackpot is determined (S403). When the variation pattern is set in the process of S403, the display time of the first symbol display device 37 is set and the variation time of the third symbol until the third symbol display device 81 stops at the jackpot symbol is determined. The At this time, the values of the fluctuation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and rough symbol fluctuations such as normal reach, super reach, premium reach, etc. are determined based on the value of the first fluctuation type counter CS1. In addition to determining the variation time, the variation time (in other words, the number of variation symbols) until the last stop symbol (in this embodiment, the middle symbol Z2) stops after the occurrence of reach is determined based on the value of the second variation type counter CS2. decide.

  The relationship between the numerical value of the first variation type counter CS1 and the variation time, and the relationship between the numerical value of the second variation type counter CS2 and the variation time are respectively defined in advance by a table or the like. However, the fluctuation time can be set using only the value of the first fluctuation type counter CS1 without using the value of the second fluctuation type counter CS2, and can be set only with the value of the first fluctuation type counter CS1. Whether or not to set with both values of both variation type counters CS1 and CS2 is appropriately determined according to the value of the first variation type counter CS1 and the game conditions each time.

  If it is determined in the process of S401 that it is not a big hit (S401: No), the display mode at the time of disconnection is set (S404). In the process of S404, the display mode of the first symbol display device 37 is set to the display mode corresponding to the off symbol, and based on the value of the stop pattern selection counter C3 stored in the execution area of the reserved ball storage area, An effect to be displayed on the third symbol display device 81 is set to indicate whether the reach is front / rear out of reach, reach other than front / rear out, or complete out. In the present embodiment, as described above, the range of values corresponding to each stop pattern of the stop pattern selection counter C3 depends on whether the state is a high probability state, a low probability state, and the operation suspension number N. Different tables are set up.

  Next, the variation pattern at the time of detachment is determined (S405), the display time of the first symbol display device 37 is set, and the variation time of the third symbol until the third symbol display device 81 stops at the detachment symbol. Is determined. At this time, as in the process of S403, the values of the variation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and the normal reach, super reach, and premium reach are determined based on the value of the first variation type counter CS1. In addition, the fluctuation time (in other words, the middle symbol Z2 in the present embodiment) is stopped after the reach has occurred based on the value of the second fluctuation type counter CS2 For example, the number of fluctuation symbols) is determined.

  When the process of S403 or the process of S405 is completed, the effect time to be added to or subtracted from the variation time determined by the first and second type counters CS1 and CS2 is determined (S406). At this time, the addition / subtraction of effect time is determined based on the value of the third type counter CS3 stored in the counter buffer of the RAM 203, the display time of the first symbol display device 37 is set, and the third symbol display The variation time of the device 81 is set. In the present embodiment, the effect time addition / subtraction is determined according to the value of the third variation type counter CS3 when the variation display time is not changed and when the variation display time is added for one second, the variation display time is set to 2 In the case of adding seconds, four types of addition values are determined for the case of subtracting 1 second from the variable display time.

  In addition, when the variable display time is added or subtracted, a notice effect that increases the expected value of the jackpot on the third symbol display device 81 (for example, a slip effect that causes the change time of the variable symbol to be longer than usual and is accompanied by a slip) An effect of displaying a notice character is produced, for example, an effect of making the change time of one change symbol shorter than usual and stopping it immediately). In addition, when the value of the first random number counter C1 is a big hit, the probability that an added value of 2 seconds is selected is set high, so that the player expects a big hit by confirming the notice effect. Can do.

  Next, a variation pattern command is set according to the variation pattern (variation time) determined in S403 or S405 (S407), and a stop symbol command is set according to the stop symbol set in S402 or S404. (S408). Then, an effect time addition command is set according to the added value of the effect time determined in the process of S406 (S409), and the process returns to the variation process.

  As described above, according to the pachinko machine 10, when the inner frame 12 or the front frame 14 is in the open state and the switch SW1 or the switch SW2 is in the conductive state (see FIG. 5B), the frame open detection is performed. The circuit 260 supplies a current to one end of the resistor R7 of the external output terminal board 261 until about 10 milliseconds have elapsed (for about 10 milliseconds) after the inner frame 12 or the front frame 14 is opened. Then, current is supplied to the light emitting diode on the primary side of the photocoupler PR1 provided on the external output terminal plate 261 via the resistor R7, and the light emitting diode emits light for about 10 milliseconds. When the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 receives the light from the light emitting diode, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 pulses the received light for about 10 milliseconds. The pulse signal is changed to a pulse signal (electric signal) having a width of about 10 milliseconds, and the pulse signal is output to the hall computer 262. The output pulse signal is stored in the hall computer 262. Therefore, by using the frame opening detection circuit 260 and the external output terminal board 261, the hall computer 262 can memorize that the inner frame 12 has been opened or the front frame 14 has been opened. The hall computer 262 continues to operate for 24 hours. Therefore, the frame opening detection circuit 260 detects the time when the pulse signal is output from the external output terminal board 261 and the time when the pulse signal is output, that is, the time when the inner frame 12 is opened and the front frame 14 is opened. 262 can be stored.

  In addition, since the frame opening detection circuit 260 is provided with the 0.1-F capacitor CD1, the frame opening detection circuit 260 is supplied with power to the pachinko machine 10, and the DC voltage of 12 volts from the DC power supply DC1. Of course, for example, the business hours of the amusement hall are over, the power supply to the pachinko machine 10 is cut off, and a DC voltage of 12 volts is supplied from the DC power supply DC1. Even if it is not, the opening of the inner frame 12 and the opening of the front frame 14 can be detected. Therefore, for example, even when the game hall is closed and power supply to the pachinko machine 10 is interrupted, a pulse signal with a pulse width of about 10 milliseconds is sent from the external output terminal board 261 to the hall computer 262. Can be output.

  Next, a pachinko machine according to a second embodiment will be described with reference to FIGS. 18 and 19. The pachinko machine of the second embodiment is obtained by changing the frame opening detection circuit 260 of the pachinko machine 10 of the first embodiment to a frame opening detection circuit 270 having another configuration. The frame opening detection circuit 270 of the second embodiment has a simplified circuit configuration compared to the frame opening detection circuit 260 of the first embodiment. Specifically, the frame opening detection circuit 270 of the second embodiment removes the timer IC1, resistors R1 to R3, and capacitors CD3 to CD5 from the frame opening detection circuit 260 of the first embodiment, and the capacitor CD1 has a different capacity. The circuit configuration is simplified by changing to the capacitor CD6 and changing the connection of each component.

  According to the frame open detection circuit 270 of the second embodiment, a high signal whose output period varies according to the open period of the inner frame 12 or the front frame 14 can be output to the hall computer 262. Alternatively, in addition to being able to detect the opening of the front frame 14, it is also possible to detect the opening period of the inner frame 12 or the front frame 14.

  FIG. 18 is a block diagram showing an electrical configuration of the frame opening detection circuit 270 of the second embodiment. In addition, the same number is attached | subjected to the part same as the frame open | release detection circuit 260 of 1st Embodiment mentioned above in FIG. 7, the description is abbreviate | omitted, and only a different part is demonstrated.

  The capacitor CD6 is obtained by changing the capacitance of the capacitor CD1 used in the frame opening detection circuit 260 of the first embodiment from 0.1 F (Farad) to 1F (Farad). The capacitor CD6 is a component that functions as a rechargeable battery like the capacitor CD1 of the frame open detection circuit 260 of the first embodiment. One end of the capacitor CD6 is connected to the cathode of the diode D1, and the other end of the capacitor CD6 is grounded. Yes.

  Similarly to the capacitor CD1 (see FIG. 7), the capacitor CD6 is supplied with power to the pachinko machine according to the second embodiment, and when a DC voltage of 12 volts is supplied from the DC power source DC1, It is obtained by the product of the capacitance 1F of the capacitor CD6 and the DC voltage applied to the capacitor CD6 (approximately 11.3 volts obtained by subtracting 0.7 volts from the diode D1 from 12 volts supplied from the DC power supply DC1). Stores charge.

  On the other hand, for example, when the business hours of the amusement hall are over, the power supply to the pachinko machine of the second embodiment is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1, the capacitor CD6 is Then, a DC voltage (about 11.3 volts) based on the electric charge stored in the capacitor CD6 is supplied to the frame open detection circuit 270 and the external output terminal plate 261.

  Specifically, the capacitor CD6 has a capacitance of 1F (farad), and the voltage applied to the capacitor CD6 is approximately 11.3 volts. Therefore, the charge stored in the capacitor CD6 is equal to the capacitance of the capacitor CD6 and the capacitance of the capacitor CD6. It becomes about 11.3 C (coulomb) from the product of the applied voltage. The charge of about 11.3 C stored in the capacitor CD6 is about 10 minutes in the output period of the high signal output from the external output terminal plate 261 to the hall computer 262. Therefore, for example, even when the business hours of the amusement hall are over, the power supply to the pachinko machine of the second embodiment is shut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1, Until the total output period of the high signal output from the output terminal plate 261 reaches about 10 minutes, the frame opening detection circuit 270 can detect the opening of the inner frame 12 or the front frame 14. The frame opening detection circuit 270 can also detect the opening period of the inner frame 12 or the front frame 14. When the total output period of opening the inner frame 12 or opening the front frame 14 approaches about 10 minutes, the charge stored in the capacitor CD6 decreases, and the current value supplied from the capacitor CD6 to the photocoupler PR1 decreases. However, the high signal can be stored in the hall computer 262 by increasing the detection sensitivity of the high signal of the hall computer 262 (by lowering the threshold for the amplitude of the high signal).

  In this way, when the power is supplied to the pachinko machine of the second embodiment and a DC voltage of 12 volts is supplied from the DC power supply DC1, it operates as a matter of course. Even when the power supply to the pachinko machine of the second embodiment is shut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, the frame opening detection circuit 270 has 1F ( Since the Farad capacitor CD6 is provided, the frame opening detection circuit 270 can detect the opening of the inner frame 12 and the opening of the front frame 14. Note that the cathode terminal of the diode D1 is connected to one end of the capacitor CD6, and this diode D1 performs a function of preventing the backflow of current. Therefore, a direct current is passed from the capacitor CD6 to the open frame detection circuit 270 and the external output terminal plate 261. Even when a voltage (about 11.3 volts) is supplied, the DC voltage is not applied to the DC power source DC1, and the DC power source DC1 is not damaged. In the present embodiment, the capacitor CD6 is used as a component for supplying a DC voltage to the open frame detection circuit 270 and the external output terminal plate 261 when a DC voltage of 12 volts is not supplied from the DC power source DC1. . However, the present invention is not limited to this, and the capacitor CD6 may be a secondary battery (rechargeable battery) with a larger amount of stored electricity or a primary battery that does not require charging.

  One end of the capacitor CD6 is connected to one ends of the switch SW1 and the switch SW2, and is also connected to one end of the resistor R7 of the external output terminal plate 261. One end of a resistor R9 is connected to the other ends of the switch SW1 and the switch SW2. The other end of the resistor R9 is connected to one end of the capacitor CD2, one end of the resistor R4, and one end of the internal resistor R5 of the transistor TR1.

  With this connection, either the switch SW1 or the switch SW2 (one of the inner frame 12 or the front frame 14) or both the switch SW1 and the switch SW2 are in a conductive state (both the inner frame 12 and the front frame 14 are open). During a certain period, since a DC voltage is supplied to the resistor R4, the collector terminal c of the transistor TR1 and the emitter terminal e of the transistor TR1 are electrically connected. Then, during this period, current is supplied to the light emitting diode on the primary side of the photocoupler PR1 through the resistor R7 of the external output terminal plate 261. Thereby, one of the switch SW1 or the switch SW2 (one of the inner frame 12 or the front frame 14) or both the switch SW1 and the switch SW2 are in a conductive state (both the inner frame 12 and the front frame 14 are in an open state). ) During the period, a high signal is output from the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 to the hall computer 262. Therefore, according to the frame opening detection circuit 270 of the second embodiment, since the frame opening detection circuit 270 is provided with the 1F (Farad) capacitor CD6, the power supply to the pachinko machine of the second embodiment can be performed. Even when the DC voltage of 12 volts is not supplied from the DC power source DC1, the high output signal whose output period varies according to the open period of the inner frame 12 or the front frame 14 is output to the external output terminal plate 261. To the hall computer 262. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14, it is also possible to detect the opening period of the inner frame 12 or the front frame 14. The hall computer 262 continues to operate for 24 hours. Accordingly, the frame opening detection circuit 270 is configured to output the high signal from the external output terminal board 261 and the time at which the high signal is output, that is, the opening time of the inner frame 12 and the opening time of the front frame 14 is also the hall computer. 262 can be stored.

  Furthermore, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10 is interrupted, and the DC voltage of 12 volts is not supplied from the DC power supply DC1 to the frame opening detection circuit 270 and the external output terminal plate 261. That is, when a DC voltage of about 11.3 volts is supplied from the capacitor CD6 to the frame open detection circuit 270 and the external output terminal plate 261, the supply period of the current supplied from the capacitor CD6 to the photocoupler PR1 is set as follows. 12 or the period when the front frame 14 is opened. Therefore, power consumption due to the opening of the inner frame 12 or the front frame 14 can be reduced.

  For example, when the business hours of the amusement hall are over and the power supply to the pachinko machine is cut off, and the DC voltage is supplied from the capacitor CD6 to the frame opening detection circuit 270 and the external output terminal plate 261, the inner frame 12 or when the total supply period of the current from the capacitor CD6 to the photocoupler PR1 due to the opening of the front frame 14 is increased or the number of times of detecting the opening of the inner frame 12 or the front frame 14 is increased. (For example, the capacity of the capacitor CD6 is set to 10F), or the capacitor CD6 may be changed to a secondary battery with a large amount of charge.

  Next, referring to FIG. 19, the voltage (A) of the frame open detection circuit 270 changes according to the state of the switch SW1 (the state of the inner frame 12) and the state of the switch SW2 (the state of the front frame 14). 18) and the output of the external output terminal board 261 (input of the hall computer 262) will be described. FIG. 19 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the voltage A of the frame open detection circuit 270, and the output of the external output terminal plate 261 (of the hall computer 262). 6 is a timing chart showing the relationship of input). Each time from t1 to t8 shown in FIG. 19 is the same as each time from t1 to t8 shown in the timing chart of the frame opening detection circuit 260 of the first embodiment shown in FIG. is there.

  As shown in FIG. 19A, when the switch SW1 is in a conductive state (the inner frame 12 is in an open state) at t1, the frame open detection circuit 270 follows this, as shown in FIG. 19C. The voltage of A (see FIG. 18) switches from zero volts to about 11.3 volts (at time t1). Then, as shown in FIG. 19 (d), the output of the secondary light receiving element (phototransistor) of the photocoupler PR1, that is, the output of the external output terminal plate 261 switches from the low state to the high state (t1). Time). As a result, output of a high signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  Then, as shown in FIG. 19A, when the switch SW1 is in the cut-off state (the inner frame 12 is closed) at t2, as shown in FIG. 19C, the voltage of A of the frame open detection circuit 270 is obtained. Switches from about 11.3 volts to zero volts (at t2). Then, following this, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the high state to the low state (at time t2).

  The switching of the output of the external output terminal plate 261 becomes a high signal, and the high signal is output from the external output terminal plate 261 to the hall computer 262 from time t1 to time t2. That is, a high signal that is an output period from t1 to t2 is output from the external output terminal board 261 to the hall computer 262.

  Next, as shown in FIG. 19 (a), when the switch SW1 becomes conductive (the inner frame 12 is in the open state) at t3, the frame opens as shown in FIG. 19 (c). The voltage of A in the detection circuit 270 (see FIG. 18) switches from zero volts to about 11.3 volts (at time t3). Then, as shown in FIG. 19D, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 switches from the low state to the high state (t3). Time). As a result, output of a high signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  Then, as shown in FIG. 19A, when the switch SW1 is in the cut-off state (the inner frame 12 is closed) at t4, as shown in FIG. Switches from about 11.3 volts to zero volts (at t4). Then, following this, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the high state to the low state (at time t4).

  The switching of the output of the external output terminal plate 261 becomes a high signal, and the high signal is output from the external output terminal plate 261 to the hall computer 262 from t3 to t4. That is, a high signal having an output period from t3 to t4 is output from the external output terminal board 261 to the hall computer 262.

  Finally, a case will be described where the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 19A, at time t5, the switch SW1 becomes conductive (inner frame 12 is open), and as shown in FIG. 19B, at time t6, switch SW2 becomes conductive (front surface). When the frame 14 is in the open state), as shown in FIG. 19C, the voltage A (see FIG. 18) of the frame open detection circuit 270 switches from zero volts to about 11.3 volts at t5. Then, following this, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the low state to the high state as shown in FIG. 19D (at time t5). As a result, output of a high signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  As shown in FIG. 19 (a), at time t7, the switch SW1 is in the cut-off state (the inner frame 12 is closed), and as shown in FIG. 19 (b), at time t8, the switch SW2 is in the cut-off state. When the front frame 14 is in the closed state, as shown in FIG. 19C, the voltage of A in the frame open detection circuit 270 switches from zero volts to about 11.3 volts at t8. Then, following this, as shown in FIG. 19D, the output of the external output terminal plate 261 switches from the high state to the low state (at time t8).

  The switching of the output of the external output terminal plate 261 becomes a high signal, and the high signal is output from the external output terminal plate 261 to the hall computer 262 from t5 to t8. That is, a high signal having an output period from t5 to t8 is output from the external output terminal board 261 to the hall computer 262.

  As described above, when the switch SW1 and the switch SW2 are in the conductive state (the inner frame 12 and the front frame 14 are in the open state), the frame open detection circuit 270 has either the switch SW1 or the switch SW2 in the conductive state (the inner frame 12). 12 until the switch SW1 and the switch SW2 are both shut off (both the inner frame 12 and the front frame 14 are closed). A high signal can be output from the output terminal board 261 to the hall computer 262. Therefore, in addition to being able to detect the opening of the inner frame 12 or the front frame 14, both the inner frame 12 and the front frame 14 from when either the inner frame 12 or the front frame 14 is opened. It is possible to detect the open period until the closed state.

  As described above, according to the pachinko machine of the second embodiment, the frame opening detection circuit 270 is provided with the 1F (farad) capacitor CD6, so that the power supply to the pachinko machine of the second embodiment is cut off. Even when a DC voltage of 12 volts is not supplied from the DC power source DC1, the frame open detection circuit 270 generates a high signal whose output period varies depending on the open period of the inner frame 12 or the front frame 14. The data can be output to the hall computer 262. In addition, when the high signal is output from the external output terminal board 261 to the hall computer 262 and the output period of the output high signal is stored, the opening of the inner frame 12 or the front frame 14 can be detected. In addition to being able to detect, the opening period of the inner frame 12 or the front frame 14 can also be detected. The high signal output from the external output terminal board 261 to the hall computer 262 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be specified by the high signal stored in the hall computer 262. Further, the hall computer 262 outputs a high signal from the external output terminal board 261 and stores the output time of the output high signal, thereby enabling the opening time or front surface of the specified inner frame 12 of the pachinko machine to be stored. The opening time of the frame 14 can also be detected.

  Next, a pachinko machine according to a third embodiment will be described with reference to FIGS. The pachinko machine of the third embodiment is obtained by changing the frame opening detection circuit 260 of the pachinko machine 10 of the first embodiment to a frame opening detection circuit 280 having another configuration. The frame opening detection circuit 280 of the third embodiment has a simplified circuit configuration compared to the frame opening detection circuit 260 of the first embodiment. Specifically, the frame opening detection circuit 280 according to the third embodiment removes the resistor R2, the capacitors CD4 and CD5 from the frame opening detection circuit 260 according to the first embodiment, and the resistor R1, the capacitor CD3, the resistor R7, and the switch SW1. And the connection of the switch SW2, the timer IC1 is made to function as a monostable multivibrator, and the integrating circuit 281 including the resistor 10 and the capacitor CD7 is connected to the preceding stage of the TRG terminal of the timer IC1 to thereby form a circuit configuration. Is simplified. Then, the frame open detection circuit 280 of the third embodiment is outputted from the frame open detection circuit 260 of the first embodiment from the mode of the voltage applied to the TRG terminal of the timer IC1 and the OUT terminal of the timer IC1. The mode of voltage is changed.

  According to the frame open detection circuit 280 of the third embodiment, the integration circuit 281 makes the falling period of the voltage applied to the TRG terminal of the timer IC 1 constant regardless of the open period of the inner frame 12 or the front frame 14. By setting the period (about 2 msec), the fall of the voltage applied to the TRG terminal of the timer IC1 is shorter than the period (about 10 msec) in which a voltage of about 9.6 volts is output from the OUT terminal of the timer IC1. The period can be adjusted short. Therefore, regardless of the opening period of the inner frame 12 or the front frame 14, the supply period of the current supplied from the capacitor CD1 to the photocoupler PR1 is about 10 milliseconds per opening of the inner frame 12 or the front frame 14. Can be fastened. Therefore, the frame opening detection circuit 280 can simplify the circuit configuration as compared with the frame opening detection circuit 260, and also keeps the period during which a voltage of about 9.6 volts is output from the OUT terminal of the timer IC1 to about 10 milliseconds. As a result, the power consumption due to the opening of the inner frame 12 or the front frame 14 can be further reduced compared to the frame opening detection circuit 260.

  FIG. 20 is a block diagram showing an electrical configuration of the frame opening detection circuit 280 of the third embodiment. In addition, the same number is attached | subjected to the part same as the frame open | release detection circuit 260 of 1st Embodiment mentioned above in FIG. 7, the description is abbreviate | omitted, and only a different part is demonstrated.

  When the power supply to the pachinko machine is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, one end of the capacitor CD1 that supplies the DC voltage to the frame open detection circuit 280 and the external output terminal plate 261 is: It is connected to one end of a 100 kΩ resistor R10, and is connected to the VDD terminal of the timer IC1, one end of a 100 KΩ resistor R1a, the RES terminal of the timer IC1, and one end of a 1 KΩ resistor R7a.

  The other end of the resistor R1a is connected to one end of a 0.1 μF capacitor CD3a and to the DCH terminal of the timer IC1 and the TH terminal of the timer IC1. The other end of the capacitor CD3a is grounded. Due to the connection between the capacitor CD3a and the resistor R1a, the timer IC1 opens the inner frame 12 or the front frame 14, whereby the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC1 is increased. When it falls to zero volts, it functions as a monostable multivibrator that raises the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts for about 10 milliseconds. Note that about 10 milliseconds, which is a period for raising the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts, is the product of the resistance value of the resistor R1a (100 kΩ) and the capacitance value of the capacitor CD3a (0.1 μF). Is determined by a time constant.

  The resistor R10 is a resistor that stabilizes the voltage applied to the TRG terminal of the timer IC1, and that constitutes the integrating circuit 281 with the capacitor CD7. The other end of the resistor R10 is connected to the anode terminal of the diode D2, the cathode terminal of the diode D2 is connected to the TRG terminal of the timer IC1, and a Zener whose limiting voltage (zener voltage) is about 10.5 volts. The cathode terminal of the diode D3 is connected to one end of each of the switch SW1 and the switch SW2 connected in parallel. Therefore, when the inner frame 12 and the front frame 14 are closed and the switches SW1 and SW2 are cut off, the voltage applied to the TRG terminal of the timer IC1 is about 11.3 volts supplied from the capacitor CD1. Is approximately 10.3 volts obtained by subtracting approximately 0.3 volts of the voltage drop at the resistor R10 and approximately 0.7 volts of the voltage drop at the diode D2.

  The 0.02 μF capacitor CD7 constitutes an integration circuit 281 with the resistor R10, and controls the voltage applied to the TRG terminal of the timer IC1. One end of the capacitor CD7 is connected to the other end of each of the switch SW1 and the switch SW2, and the other end of the capacitor CD7 is grounded. The integrating circuit 281 composed of the capacitor CD7 and the resistor R10 is applied to the TRG terminal of the timer IC1 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or SW2 is turned on. This is a circuit that lowers the voltage of about 10.3 volts to zero volts and returns the TRG terminal voltage of the timer IC1 to about 10.3 volts again after about 2 milliseconds from the fall.

  Specifically, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on in response to the opening, a voltage of about 10.3 volts supplied from the capacitor CD1 is applied to the capacitor CD7. Application is started, and charging of the capacitor CD7 is started. At the start of charging, the voltage applied to the capacitor CD7 instantaneously becomes zero volts, so that the voltage applied to the TRG terminal of the timer IC1 instantaneously becomes zero volts. As the capacitor CD7 is charged, the capacitor CD7 increases the voltage applied to the TRG terminal of the timer IC1, and finally controls the voltage applied to the TRG terminal of the timer IC1 to about 10.3 volts. It is.

  Note that the period until the capacitor CD7 is fully charged, that is, the voltage of about 10.3 volts applied to the TRG terminal of the timer IC1 falls to zero volts, and from the fall, the voltage of the TRG terminal of the timer IC1 becomes Again, about 2 milliseconds, which is a period until it returns to about 10.3 volts, is determined by a time constant which is the product of the resistance value of the resistor R10 (100 kΩ) and the capacitance value of the capacitor CD7 (0.02 μF).

  Thus, the voltage applied to the TRG terminal of the timer IC1 falls, and the period (about 2 milliseconds) from the fall to the time when the TRG terminal voltage of the timer IC1 returns to about 10.3 volts is an integration circuit. Regardless of the opening period of the inner frame 12 and the front frame 14, the voltage of the OUT terminal of the timer IC 1 is adjusted to a period shorter than the period (about 10 msec) rising from zero volts to about 9.6 volts. Note that the voltage applied to the TRG terminal of the timer IC1 falls after changing the resistance value of the resistor R10 and the capacitance value of the capacitor CD7, and then the voltage of the TRG terminal of the timer IC1 is about 10.3 volts. It is possible to freely change the period until returning to (5) within about 10 milliseconds, which is the period until the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts.

  Here, the monostable multivibrator does not normally output a signal from the output terminal unless the input period of the signal input to the input terminal is shorter than the output period of the signal output from the output terminal (from the output terminal). Signal continues to be output). For this reason, when the timer IC1 is made to function as a monostable multivibrator without using the integration circuit 281, the timer IC1 is more effective than the period in which the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts. The period until the TRG terminal voltage returns to about 10.3 volts again from zero volts, that is, the open period of the inner frame 12 and the front frame 14 (the conduction period of the switches SW1 and SW2) must be short. However, since the open period of the inner frame 12 and the front frame 14 is completely unpredictable, the inner frame 12 and the inner frame 12 and the front frame 14 are longer than the period in which the voltage at the OUT terminal of the timer IC 1 rises from zero volts to about 9.6 volts. In order to always shorten the opening period of the front frame 14, it is necessary to set a period in which the voltage at the OUT terminal of the timer IC 1 rises from zero volts to about 9.6 volts with a sufficient margin. For example, if the opening period of the inner frame 12 and the front frame 14 is predicted to be several tens of seconds to several minutes, the period during which the voltage at the OUT terminal of the timer IC 1 rises from zero volts to about 9.6 volts is sufficient. It must be set from several minutes to several tens of minutes. Then, since the DC voltage is continuously supplied from the capacitor CD1 to the frame opening detection circuit 280 and the external output terminal plate 261 during the set period, the consumption of the capacitor CD1 becomes significant. Therefore, a special circuit configuration is required to make the timer IC1 function as a monostable multivibrator without using the integration circuit 281 and to further suppress the consumption of the electric charge stored in the capacitor CD1. there were.

  However, by providing the integration circuit 281 in front of the TRG terminal of the timer IC1, when the inner frame 12 or the front frame 14 is opened, the timer IC1 regardless of the open period (the conduction period of the switch SW1 and the switch SW2). The period until the voltage applied to the TRG terminal of the timer IC1 falls to zero volts again and returns to about 10.3 volts is adjusted to be shorter than the period when the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts can do. In this way, the integration circuit 281 makes the timer IC1 normal by setting the falling period of the TRG terminal voltage of the timer IC1 to a fixed period (about 2 milliseconds) regardless of the opening period of the inner frame 12 and the front frame 14. The period when the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts can be kept at about 10 milliseconds.

  When the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts for about 10 milliseconds, the collector terminal and the emitter terminal of the transistor TR1 conduct for about 10 milliseconds and pass through the resistor R7a. Thus, a current is supplied from the capacitor CD1 to the photocoupler PR1 for about 10 milliseconds. Thus, a pulse signal having a pulse width of about 10 milliseconds is output from the external output terminal board 261 to the hall computer 262 for each opening of the inner frame 12 or the front frame 14. As described above, even if the timer IC1 is made to function as a monostable multivibrator, by providing the integration circuit 281 in the previous stage of the TRG terminal of the timer IC1, the consumption of the electric charge stored in the capacitor CD1 is suppressed. Without adopting a simple circuit configuration, the output period of the pulse signal output from the external output terminal board 261 to the hall computer 262 can be limited to about 10 milliseconds.

  The TRG terminal of the timer IC1 is connected to the cathode terminal of a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts, and the ground is connected to the anode terminal of the Zener diode D3. In the Zener diode D3, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the charge stored in the capacitor CD7 and the voltage supplied from the capacitor CD1 are superimposed. This is an element that prevents an overvoltage (for example, a voltage of 12.3 volts) that can break the timer IC1 from being applied to the TRG terminal of the timer IC1. Specifically, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the charge stored in the capacitor CD7 is regained again within a relatively short period of time. 14 is opened, and when the switch SW1 or SW2 is turned on, the switch SW1 or the switch SW2 is discharged from the other end side to the one end side. The voltage of about 10.3 volts discharged from the capacitor CD7 and the voltage of about 10.3 volts supplied from the capacitor CD1 are superimposed, and an overvoltage large enough to destroy the timer IC1 is applied to the TRG terminal of the timer IC1. Can be applied. However, since a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts is connected between the TRG terminal of the timer IC1 and the ground, the voltage applied to the TRG terminal of the timer IC1 The maximum value is about 10.5 volts, and an overvoltage that destroys the timer IC1 is not applied to the TRG terminal of the timer IC1. In this way, by using the Zener diode D3 that has a simple configuration and is inexpensive, it is possible to prevent an overvoltage large enough to destroy the timer IC1 from being applied to the TRG terminal of the timer IC1, and to prevent damage to the timer IC1. it can.

  As described above, the limit pressure reduction (zener voltage) of the Zener diode D3 is about 10.5 volts, so that the inner frame 12 and the front frame 14 are closed and the switch SW1 and the switch SW2 are shut off. In this case, the current supplied from the capacitor CD1 does not flow to the ground via the Zener diode D3, and the charge of the capacitor CD1 is not consumed. In addition, the cathode terminal of the diode D2 is connected to one end of the switch SW1 and the switch SW2, and this diode D2 exhibits a function of preventing the backflow of current. Is applied to the VDD terminal of the capacitor CD1 and the timer IC1, and they are not damaged.

  As described above, in the timer IC1 of the frame open detection circuit 280, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the voltage applied to the TRG terminal of the timer IC1 falls to zero volts. Then, it functions as a monostable multivibrator that raises the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts for about 10 milliseconds after the fall. Further, by providing an integration circuit 281 in front of the TRG terminal of the timer IC1, when the inner frame 12 or the front frame 14 is opened, the timer IC1 is connected regardless of the opening period of the inner frame 12 and the front frame 14. Adjust the period from when the voltage applied to the TRG terminal falls to zero volts until it returns to about 10.3 volts, shorter than the period when the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts Can do. As described above, the integration circuit 281 sets the falling period of the TRG terminal voltage of the timer IC 1 to a fixed period (about 2 milliseconds) regardless of the opening period of the inner frame 12 and the front frame 14, thereby providing a monostable multivibrator. The timer IC1 functioning as a normal operation can be normally operated, and the period during which the voltage at the OUT terminal of the timer IC1 rises from zero volts to about 9.6 volts can be kept to about 10 milliseconds. As a result, the period during which current is supplied from the capacitor CD1 to the photocoupler PR1 can be kept at about 10 milliseconds, and the output period of the pulse signal output from the external output terminal plate 261 to the hall computer 262 is kept at about 10 milliseconds. be able to.

  Further, since the frame opening detection circuit 280 is provided with a 0.1-F capacitor CD1, the frame opening detection circuit 280 is supplied with power to the pachinko machine, and a DC voltage of 12 volts is supplied from the DC power supply DC1. If it is supplied, it will naturally operate. Further, for example, when the business hours of the amusement hall are over, the power supply to the pachinko machine is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1. Even so, the opening of the inner frame 12 and the opening of the front frame 14 can be detected. When the opening of the inner frame 12 or the opening of the front frame 14 is detected by the frame opening detection circuit 280, a pulse having a pulse width of about 10 milliseconds is sent from the external output terminal board 261 to the hall computer 262 for each detection. A signal can be output. The pulse signal output from the external output terminal board 261 to the hall computer 262 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 or the front frame 14 is opened can be specified by the pulse signal stored in the hall computer 262. Further, the hall computer 262 outputs a pulse signal from the external output terminal plate 261 and stores the output time of the output pulse signal so that the opening time of the identified inner frame 12 of the pachinko machine or the front surface The opening time of the frame 14 can be detected.

  The door opening detection circuit 280 uses the LMC 555 for the timer IC 1 to detect the opening of the inner frame 12 or the opening of the front frame 14, and realizes a circuit for energizing the photocoupler PR1 for about 10 milliseconds. It is not limited to. That is, a circuit that generates one pulse signal for one opening of the inner frame 12 or one opening of the front frame 14 by using another integrated circuit or the like for the timer IC 1 is realized. Any device may be used as long as the photocoupler PR1 is energized for a predetermined period based on the pulse signal.

  Further, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine is cut off and the DC voltage is supplied from the capacitor CD1 to the frame opening detection circuit 280 and the external output terminal plate 261, the inner frame 12 or when the total supply period of the current from the capacitor CD1 to the photocoupler PR1 due to the opening of the front frame 14 is increased or the number of times of detecting the opening of the inner frame 12 or the front frame 14 is increased. (For example, the capacity of the capacitor CD1 is set to 1F), or the capacitor CD1 may be changed to a secondary battery with a large amount of charge.

  Next, referring to FIG. 21, the TRG terminal voltage of timer IC1 that changes according to the state of switch SW1 (the state of inner frame 12) and the state of switch SW2 (the state of front frame 14), The relationship between the OUT terminal voltage and the output of the external output terminal plate 261 (input of the hall computer 262) will be described. FIG. 21 shows the state of the switch SW1 (the state of the inner frame 12), the state of the switch SW2 (the state of the front frame 14), the TRG terminal voltage of the timer IC1, the OUT terminal voltage of the timer IC1, and the output of the external output terminal plate 261 ( 6 is a timing chart showing a relationship of inputs of the hall computer 262. Note that the times from t1 to t8 shown in FIG. 21 are the same as the times from t1 to t8 shown in the timing chart of the frame opening detection circuit 260 of the first embodiment shown in FIG. is there.

  As shown in FIG. 21A, when the switch SW1 is in a conductive state (inner frame 12 is in an open state) at time t1, charging of the capacitor CD7 is started, and as shown in FIG. The TRG terminal voltage falls from about 10.3 volts to zero volts (at time t1). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t1). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the open frame detection circuit 280 are made conductive, and current supply is started to the light emitting diode on the primary side of the photocoupler PR1 of the external output terminal plate 261 (see FIG. 20). (At t1). Then, as shown in FIG. 21 (e), the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 is switched from the low state to the high state at t1. Change. Thereby, output of a pulse signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  Next, as shown in FIG. 21 (c), when about 2 milliseconds have elapsed from time t1, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage of the OUT terminal of the timer IC1 has risen from zero volts to about 9.6 volts (from t1), about 10 milliseconds have not elapsed, the OUT terminal voltage of the timer IC1 is about 9.6 volts. Is maintained.

  Thereafter, when about 10 milliseconds elapse from t1, the timer IC1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts as shown in FIG. Then, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, the output of the external output terminal plate 261 switches from the high state to the low state as shown in FIG. 21 (e) when about 10 milliseconds elapse from t1. Thereby, the output of the pulse signal output to the hall computer 262 is stopped. In this way, by switching the output of the external output terminal plate 261, the pulse width of the pulse signal output from the external output terminal plate 261 to the hall computer 262 can be kept at about 10 milliseconds.

  As shown in FIG. 21A, when the switch SW1 is in the cut-off state (the inner frame 12 is closed) at t2, the frame opening detection circuit 280 detects the inner frame 12 and the front frame 14 again. Set to possible state.

  Next, as shown in FIG. 21B, at time t3, when the switch SW2 is in a conductive state (the front frame 14 is in an open state), charging of the capacitor CD7 is started, and as shown in FIG. The TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts (at time t3). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t3). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the open frame detection circuit 280 are made conductive, and current supply is started to the light emitting diode on the primary side of the photocoupler PR1 of the external output terminal plate 261 (see FIG. 20). (At t3). Then, as shown in FIG. 21 (e), the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 is switched from the low state to the high state at t3. Change. Thereby, output of a pulse signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  The electric charge stored in the capacitor CD7 between time t1 and time t2 is instantaneously discharged through the zener diode D3 at time t3. The discharge period of the capacitor CD7 is a period that is much shorter than about 2 milliseconds, in which the voltage at the TRG terminal of the timer IC1 is changed from about 10.3 volts to zero volts and is again about 10.3 volts. It does not significantly affect the voltage applied to the TRG terminal. In addition to this discharge, the electric charge stored in the capacitor CD7 from t1 to t2 is also discharged by self-discharge of the capacitor CD7.

  At time t3, a voltage of about 10.3 volts supplied from the capacitor CD1 and a voltage of about 10.3 volts associated with the charge stored in the capacitor CD7 are superimposed on the TRG terminal of the timer IC1. An overvoltage large enough to destroy the timer IC1 may be applied. However, since a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts is connected to the preceding stage of the TRG terminal of the timer IC1, the maximum value of the voltage applied to the TRG terminal of the timer IC1 is The overvoltage which is about 10.5 volts and destroys the timer IC1 is not applied to the TRG terminal of the timer IC1.

  Next, as shown in FIG. 21 (c), when about 2 milliseconds elapse from t3, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage of the OUT terminal of the timer IC1 has risen from zero volts to about 9.6 volts (from t3), about 10 milliseconds have not elapsed, the OUT terminal voltage of the timer IC1 is about 9.6 volts. Is maintained.

  Thereafter, when about 10 milliseconds elapse from t3, as shown in FIG. 21D, the timer IC1 switches the voltage of the OUT terminal from about 9.6 volts to zero volts. Then, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, the output of the external output terminal plate 261 switches from the high state to the low state as shown in FIG. 21 (e) when about 10 milliseconds elapse from t3. Thereby, the output of the pulse signal output to the hall computer 262 is stopped. In this way, by switching the output of the external output terminal plate 261, the pulse width of the pulse signal output from the external output terminal plate 261 to the hall computer 262 can be kept at about 10 milliseconds.

  As shown in FIG. 21 (b), when the switch SW2 is in a cut-off state (the front frame 14 is closed) at t4, the frame open detection circuit 280 detects the inner frame 12 and the front frame 14 again. Set to possible state.

  Finally, a case will be described where the switch SW2 is in a conductive state (the front frame 14 is in an open state) when the switch SW1 is in a conductive state (the inner frame 12 is in an open state). As shown in FIG. 21 (a), at time t5, the switch SW1 becomes conductive (inner frame 12 is open), and as shown in FIG. 21 (b), at time t6, switch SW2 becomes conductive (front surface). When the frame 14 is in an open state), at time t5, charging of the capacitor CD7 is started, and as shown in FIG. 21C, the TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts (t5). Time). Then, following this, as shown in FIG. 21 (d), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at time t5). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the open frame detection circuit 280 are made conductive, and current supply is started to the light emitting diode on the primary side of the photocoupler PR1 of the external output terminal plate 261 (see FIG. 20). (At t5). Then, as shown in FIG. 21E, the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the external output terminal plate 261 is switched from the low state to the high state at t5. Change. Thereby, output of a pulse signal indicating opening of the inner frame 12 or the front frame 14 to the hall computer 262 is started.

  The charge stored in the capacitor CD7 between t3 and t4 has a significant effect on the voltage applied to the TRG terminal of the timer IC1, since the discharge is instantaneously completed through the zener diode D3 at t5. is not. In addition to this discharge, the charge stored in the capacitor CD7 from t3 to t4 is also discharged by self-discharge of the capacitor CD7.

  At t5, a voltage of about 10.3 volts supplied from the capacitor CD1 and a voltage of about 10.3 volts associated with the electric charge stored in the capacitor CD7 are superimposed on the TRG terminal of the timer IC1, An overvoltage large enough to destroy the timer IC1 may be applied. However, since the maximum value of the voltage applied to the TRG terminal of the timer IC1 is about 10.5 volts due to the Zener diode D3, an overvoltage large enough to destroy the timer IC1 is applied to the TRG terminal of the timer IC1. There is no.

  Next, as shown in FIG. 21 (c), when about 2 milliseconds elapse from t5, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since about 10 milliseconds have not elapsed since the voltage of the OUT terminal of the timer IC1 rose from zero volts to about 9.6 volts (from t5), the OUT terminal voltage of the timer IC1 is about 9.6 volts. Is maintained.

  Thereafter, when about 10 milliseconds elapse from t5, as shown in FIG. 21D, the timer IC1 switches the voltage of the OUT terminal from about 9.6 volts to zero volts. Then, the collector terminal and the emitter terminal of the transistor TR1 of the frame opening detection circuit 280 are cut off, and the current supply to one end of the resistor R7a of the external output terminal plate 261 is stopped. Therefore, the output of the external output terminal plate 261 switches from the high state to the low state as shown in FIG. 21 (e) when about 10 milliseconds elapse from t5. Thereby, the output of the pulse signal output to the hall computer 262 is stopped. In this way, by switching the output of the external output terminal plate 261, the pulse width of the pulse signal output from the external output terminal plate 261 to the hall computer 262 can be kept at about 10 milliseconds.

  As shown in FIG. 21 (a), at time t7, the switch SW1 is turned off (the inner frame 12 is closed), and as shown in FIG. 21 (b), at time t8, the switch SW2 is turned off. When the front frame 14 is in the closed state, the frame open detection circuit 280 is set again to a state in which the inner frame 12 and the front frame 14 can be detected.

  As described above, even when the switch SW1 is in the conductive state (the inner frame 12 is in the open state) and the switch SW2 is in the conductive state (the front frame 14 is in the open state), the timer IC1 is in the conductive period of the switch SW1. Regardless of the (opening period of the inner frame 12) and the conduction period of the switch SW2 (opening period of the front frame 14), either the switch SW1 or the switch SW2 is in the conductive state (either the inner frame 12 or the front frame 14). When the TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts and about 10 msec elapses, the voltage at the OUT terminal of the timer IC1 is switched from about 9.6 volts to zero volts. As a result, the supply period of the current supplied to the photocoupler PR1 of the external output terminal plate 261 is about 10 milliseconds.

  Thus, for example, when the game hall is closed and the power supply to the pachinko machine is shut off, and the DC power supply DC1 does not supply the DC voltage of 12 volts to the frame opening detection circuit 280 and the external output terminal plate 261. When a DC voltage of about 10.3 volts is supplied from the capacitor CD1 to the frame open detection circuit 280 and the external output terminal plate 261, the supply period of the current supplied from the capacitor CD1 to the photocoupler PR1 is set as follows. Alternatively, the opening of the front frame 14 can be stopped for about 10 milliseconds. Therefore, power consumption due to the opening of the inner frame 12 or the front frame 14 can be reduced.

  Here, since the capacitor CD1 has a capacitance of 0.1 F and the voltage applied to the capacitor CD1 is approximately 11.3 volts, the electric charge stored in the capacitor CD1 is the capacitance of the capacitor CD1 and the applied voltage of the capacitor CD1. From the product of this, it becomes about 1.13C (Coulomb). The electric charge of about 1.13C stored in the capacitor CD1 is about 500 times in terms of the number of times the current is supplied when the single supply period of the current supplied from the capacitor CD1 to the photocoupler PR1 is about 10 milliseconds. Equivalent to. Therefore, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1, the inner frame 12 is opened (the switch SW1 is turned on). ) Or the opening of the front frame 14 (the conduction of the switch SW2) is performed many times, the frame opening detection circuit 280 opens the inner frame 12 or the opening of the front frame 14 (the conduction or switching of the switch SW1). SW2 conduction) can be reliably detected every time up to about 500 times, and a pulse signal can be output from the external output terminal board 261 to the hall computer 262. At this time, when the opening of the inner frame 12 or the opening of the front frame 14 is about 500 times, the electric charge stored in the capacitor CD1 decreases, and the current value supplied from the capacitor CD1 to the photocoupler PR1 decreases. By increasing the detection sensitivity of the pulse signal of the computer 262 (by reducing the threshold for the amplitude of the pulse signal), the pulse signal can be stored in the hall computer 262.

  As described above, according to the pachinko machine of the third embodiment, when the inner frame 12 or the front frame 14 is in the open state and the switch SW1 or the switch SW2 is in the conductive state, the integrating circuit 281 Regardless of the opening period of 12 or the front frame 14, the falling period of the voltage applied to the TRG terminal of the timer IC 1 is set to a certain period (about 2 milliseconds). Then, the timer IC1 functioning as a monostable multivibrator operates normally, and the voltage of the OUT terminal of the timer IC1 is changed from zero volts until about 10 milliseconds after the TRG terminal voltage of the timer IC1 falls to zero volts. Raise to about 9.6 volts. As a result, current is supplied to the primary light emitting diode of the photocoupler PR1 provided on the external output terminal plate 261 via the resistor R7a, and the light emitting diode emits light for about 10 milliseconds. When the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 receives the light from the light emitting diode, the light receiving element (phototransistor) on the secondary side of the photocoupler PR1 pulses the received light for about 10 milliseconds. The pulse signal is changed to a pulse signal (electric signal) having a width of about 10 milliseconds, and the pulse signal is output to the hall computer 262. The output pulse signal is stored in the hall computer 262. Therefore, by using the frame opening detection circuit 280 provided with the integration circuit 281 and the external output terminal board 261, the hall computer 262 can memorize that the inner frame 12 has been opened or the front frame 14 has been opened. it can. The hall computer 262 continues to operate for 24 hours. Therefore, the frame opening detection circuit 280 is configured so that the pulse signal is output from the external output terminal board 261, and the time when the pulse signal is output, that is, the opening time of the inner frame 12 and the opening time of the front frame 14 is also the hall computer. 262 can be stored.

  Further, since the frame opening detection circuit 280 is provided with a 0.1-F capacitor CD1, the frame opening detection circuit 280 is supplied with power to the pachinko machine, and a DC voltage of 12 volts is supplied from the DC power supply DC1. If it is supplied, it will naturally operate. Further, for example, when the business hours of the amusement hall are over, the power supply to the pachinko machine is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1. Even so, the opening of the inner frame 12 and the opening of the front frame 14 can be detected. Therefore, for example, even when the game hall is closed and the power supply to the pachinko machine is cut off, a pulse signal with a pulse width of about 10 milliseconds is output from the external output terminal board 261 to the hall computer 262. can do.

  In this embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, a pulse signal is output from the external output terminal plate 261 to the hall computer 262. It is not limited to this. That is, when the connection of each component of the frame opening detection circuit 280 is changed, the inner frame 12 or the front frame 14 is opened, and the opened inner frame 12 or the front frame 14 is closed, the photocoupler PR1 is connected. A current may be supplied for about 10 milliseconds to output a pulse signal from the external output terminal board 261 to the hall computer 262.

  However, in the frame open detection circuit 280 of this embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, a pulse signal is sent from the external output terminal plate 261 to the hall computer 262. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected quickly. Therefore, the opening of the inner frame 12 or the front frame 14 can be detected before the inner frame 12 or the front frame 14 is opened and an illegal act is performed on the main controller 110 or the game board 13. Therefore, it is possible to prevent an abnormal operation due to an illegal act that occurs when power is supplied to the pachinko machine.

  Next, a pachinko machine 500 according to the fourth embodiment will be described with reference to FIGS. 22 to 32. In the pachinko machine 500 according to the fourth embodiment, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power supply DC1, either the inner frame 12 or the front frame 14 is When opened, the pachinko machine 500 is used to separately notify which one is opened, and the other is output to the hall computer 262 separately. On the other hand, the pachinko machine 500 according to the fourth embodiment is, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine is shut off and a DC voltage of 12 volts is not supplied from the DC power supply DC1. Even if the control of the main control device 110 is stopped, when any of the inner frame 12 and the front frame 14 is opened, whichever is opened is separately output to the hall computer 262.

  Therefore, according to the pachinko machine 500 of the fourth embodiment, when a DC voltage of 12 volts is supplied from the DC power supply DC1, if either the inner frame 12 or the front frame 14 is opened, the inner frame The pachinko machine 500 can be used to separately notify whether there is 12 open, the front frame 14 open, or both open. Furthermore, according to the pachinko machine 500 of the fourth embodiment, in addition to the case where a DC voltage of 12 volts is supplied from the DC power supply DC1, there is a case where a DC voltage of 12 volts is not supplied from the DC power supply DC1. However, when either the inner frame 12 or the front frame 14 is opened, pulse signals can be separately output to the hall computer 262. Therefore, it is possible to identify whether the inner frame 12 has been opened, the front frame 14 has been opened, or both have been opened by the pulse signal stored in the hall computer 262.

  With reference to FIG. 22, the internal structure of the pachinko machine 500 of the fourth embodiment will be described. FIG. 22 is a perspective view of the pachinko machine 500 in a state where the inner frame 12, the front frame 14, and the lower dish unit 15 are opened. In the description of FIG. 22, the pachinko machine 500 according to the fourth embodiment includes the switches SW1 (SW1a, SW1b) and SW2 (SW2a, SW2b) provided in the pachinko machine 10 according to the first embodiment described above with reference to FIG. ) Is changed to switch SW3 and switch SW4. Therefore, the same parts as those of the pachinko machine 10 described above with reference to FIG. 4 are denoted by the same reference numerals, description thereof is omitted, and only different parts will be described.

  A switch SW3 for detecting opening and closing of the inner frame 12 is provided between the outer frame 11 and the inner frame 12, and between the inner frame 12 and the front frame 14, the opening of the front frame 14 and A switch SW4 for detecting closing is provided. With the switch SW3 and the switch SW4, the opening and closing of the inner frame 12 and the opening and closing of the front frame 14 can be detected separately.

  Next, the structure of the switch SW3 and the switch SW4 will be described with reference to FIG. Since the switch SW3 and the switch SW4 have the same structure, the structure of the switch SW3 will be described, and the description of the switch SW4 will be omitted.

  FIG. 23 is a cross-sectional view of the switch SW3. FIG. 23A is a cross-sectional view showing a state (cut-off state) of the switch SW3 in a state where the inner frame 12 is closed. FIG. 23B is a cross-sectional view showing a state (conductive state) of the switch SW3 in a state where the inner frame 12 is opened.

  As shown in FIG. 23 (a), the switch SW3 disposed on the surface of the outer frame 11 facing the inner frame 12 includes a movable shaft SW3a that contacts the closed state of the inner frame 12, and its movable shaft. Constructed from conductive plates SW3-1a and SW3-2a made of metal, which is a conductive member arranged in SW3a, and metals arranged in opposing positions of the conductive plates SW3-1a and SW3-2a. A pair of terminal plates SW3-1b, SW3-2b, a pair of terminal plates SW3-1b, SW3-2b, support plates SW3-1c, SW3-2c, and a conductor plate SW3, respectively. -2a is disposed on a surface opposite to the surface opposite to the pair of terminal plates SW3-2b, and generates a biasing force in the direction toward the pair of terminal plates SW3-2b with respect to the conductor plate SW3-2a. Spring SW3c It is provided. The conductor plate SW3-1a and the pair of terminal plates SW3-1b constitute a switch SW3-1, and the conductor plate SW3-2a and the pair of terminal plates SW3-2b constitute a switch SW3-2. Therefore, the switch SW3 includes two switches, a switch SW3-1 and a switch SW3-2.

  As shown in FIG. 23A, in a state where the inner frame 12 is closed, the movable shaft SW3a abuts on the inner frame 12, and the movable shaft SW3a is pushed into the housing SW3b. Therefore, the contact between the conductor plate SW3-1a and the pair of terminal plates SW3-1b is prevented, and the contact between the conductor plate SW3-2a and the pair of terminal plates SW3-2b is prevented. Therefore, when the inner frame 12 is closed, both the switch SW3-1 and the switch SW3-2 are disconnected.

  On the other hand, as shown in FIG. 23B, in a state where the inner frame 12 is opened, the contact of the movable shaft SW3a with the inner frame 12 is released. The plate SW3-1a and the pair of terminal plates SW3-1b are in contact with each other, and the conductor plate SW3-2a and the pair of terminal plates SW3-2b are in contact with each other. Therefore, when the inner frame 12 is opened, both the switch SW3-1 and the switch SW3-2 are in a conductive state.

  As described above, the switch SW3-1 and the switch SW3-2 built in the housing SW3b are both in a cut-off state when the inner frame 12 is closed, and are in a conductive state when the inner frame 12 is opened. It becomes. That is, the switch SW3-1 and the switch SW3-2 have a structure in which the conduction state and the cutoff state operate in conjunction with each other. However, the structure of the switch SW3 is not limited to the shape shown in FIG. 23. When the inner frame 12 is closed, the switch SW3-1 and the switch SW3-2 are cut off, while the inner frame 12 If the switch SW3-1 and the switch SW3-2 are in a conductive state in a state in which is opened. The same applies to the structure of the switch SW4.

  Next, the electrical configuration of the pachinko machine 500 will be described with reference to FIG. FIG. 24 is a block diagram showing an electrical configuration of the pachinko machine 500. Note that the pachinko machine 500 according to the fourth embodiment is the same as the frame opening detection circuit 260 provided in the main controller 110 of the pachinko machine 10 according to the first embodiment described above with reference to FIG. It is changed to the frame opening detection circuit 290, and the electrical connection of the inner frame frame opening detection circuit 290 is changed. And the pachinko machine 500 of 4th Embodiment changes the external output terminal board 261 mentioned above in FIG. 6 to the external output terminal board 291 for inner frames. In addition to this, the pachinko machine 500 of the fourth embodiment is provided with a front frame open frame detection circuit 292 in the main controller 110 of the pachinko machine 10 of the first embodiment described above with reference to FIG. is there. The pachinko machine 500 according to the fourth embodiment newly has a front frame external output terminal plate 293 corresponding to the front frame open frame detection circuit 292 newly provided in the main controller 110. It is. Therefore, the same parts as those of the pachinko machine 10 described above with reference to FIG.

  Main controller 110 is provided with an inner frame opening detection circuit 290 that detects opening of inner frame 12 when switch SW3 (switch SW3-1 and switch SW3-2) is turned on. The inner frame opening detection circuit 290 includes an input / output port 205 that is an input / output port of the MPU 201, a switch SW3 that detects opening of the inner frame 12, and an external output for the inner frame configured to be connectable to the hall computer 262. Connected to terminal plate 291. The connection between the switch SW3 and the inner frame opening detection circuit 290 and the connection between the inner frame opening detection circuit 290 and the inner frame external output terminal plate 291 include an input / output unit (input / output unit) for inputting and outputting signals. The connection is made through an input / output port (not shown) different from the input / output port 205.

  The inner frame open frame detection circuit 290 is supplied with power to the pachinko machine 500, and when a DC voltage of 12 volts is supplied from the DC power source DC1, the switch SW3 (switch SW3-1 and switch SW3-2). ) Is conducted and the opening of the inner frame 12 is detected, a signal having a DC voltage of 5 volts is output to the input / output port 205. When this signal is input to the input / output port 205, the pachinko machine 500 turns on an inner frame release flag 203a, which will be described later, and sends an inner frame release command indicating the release of the inner frame 12 via the input / output port 205. Output to the sound lamp controller 113. Then, the voice lamp control device 113 that has received this inner frame release command turns on an inner frame release command reception flag 223a, which will be described later, and outputs the inner frame release command to the display control device 114, as well as the voice output device 226 and The lamp display device 227 is used to notify the opening of the inner frame 12. In addition, the display control device 114 that has received the inner frame release command output from the sound lamp control device 113 turns on a display inner frame release command reception flag 233c, which will be described later, and displays a message indicating that the inner frame 12 is released. It is displayed on the 3 symbol display device 81. In addition to this, when the switch SW3 (switch SW3-1 and switch SW3-2) is turned on and the opening of the inner frame 12 is detected, the inner frame opening detection circuit 290 detects a hole from the inner frame external output terminal plate 291. A pulse signal having a pulse width of 10 milliseconds is output to the computer 262.

  On the other hand, the frame opening detection circuit 290 for the inner frame, for example, when the business hours of the amusement hall are over, the power supply to the pachinko machine 500 is cut off, and a DC voltage of 12 volts is not supplied from the DC power supply DC1. When the switch SW3 (the switch SW3-1 and the switch SW3-2) is turned on to detect the opening of the inner frame 12, no signal is output to the input port 205, and a hole is output from the outer output terminal plate 291 for the inner frame. A pulse signal having a pulse width of 10 milliseconds is output to the computer 262. The pulse signal output from the inner frame external output terminal plate 291 is stored in the hall computer 262. Therefore, the opening of the inner frame 12 can be detected by analyzing the pulse signal stored in the hall computer 262.

  Further, the main controller 110 is provided with a front frame opening detection circuit 292 for detecting the opening of the front frame 14 when the switch SW4 (switch SW4-1 and switch SW4-2) is turned on. The front frame opening detection circuit 292 includes an input / output port 205 that is an input / output port of the MPU 201, a switch SW4 that detects opening of the front frame 14, and a front frame external output configured to be connectable to the hall computer 262. Connected to terminal plate 293. The connection between the switch SW4 and the front frame opening detection circuit 292 and the connection between the front frame opening detection circuit 292 and the front frame external output terminal plate 293 include an input / output unit (input / output) for inputting and outputting signals. The connection is made via an input / output port (not shown) different from the port 205.

  The front frame open frame detection circuit 292 has the same function as the inner frame open frame detection circuit 290 described above. That is, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, the switch SW4 (switch SW4-1 and switch SW4-2) is turned on and the front frame 14 is turned on. Is detected, a signal with a DC voltage of 5 volts is output to the input / output port 205. When this signal is input to the input / output port 205, the pachinko machine 500 turns on a front frame opening flag 203b described later, and issues a front frame opening command indicating opening of the front frame 14 via the input / output port 205. Output to the sound lamp controller 113. Then, the voice lamp control device 113 that has received this front frame release command turns on a front frame release command reception flag 223b, which will be described later, and outputs the front frame release command to the display control device 114, as well as the voice output device 226 and The lamp display device 227 is used to notify the opening of the front frame 14. In addition, the display control device 114 that has received the front frame release command output from the sound lamp control device 113 turns on the display front frame release command reception flag 233d and displays a message indicating that the front frame 14 is released as the third symbol. It is displayed on the display device 81. In addition to this, when the switch SW4 (switch SW4-1 and switch SW4-2) conducts and detects the opening of the front frame 14, the front frame open detection circuit 292 detects a hole from the front frame external output terminal plate 293. A pulse signal having a pulse width of 10 milliseconds is output to the computer 262.

  On the other hand, the front frame opening detection circuit 292 is, for example, when the business hours of the amusement hall are over, the power supply to the pachinko machine 500 is cut off, and a DC voltage of 12 volts is not supplied from the DC power supply DC1. When the switch SW4 (switch SW4-1 and switch SW4-2) is turned on to detect the opening of the front frame 14, no signal is output to the input port 205, and a hole is generated from the external output terminal plate 293 for the front frame. A pulse signal having a pulse width of 10 milliseconds is output to the computer 262. The pulse signal output from the front frame external output terminal plate 293 is stored in the hall computer 262. Therefore, the opening of the front frame 14 can be detected by analyzing the pulse signal stored in the hall computer 262.

  Here, the front frame open frame detection circuit 292 and the inner frame open frame detection circuit 290 are connected to different input ports of the input / output port 205, respectively. Therefore, the signal output from the front frame opening detection circuit 292 and the signal output from the inner frame opening detection circuit 290 are individually input to the input / output port 205. Therefore, the MPU 201 mounted on the main controller 110 outputs the signal input to the input / output port 205 from the front frame opening detection circuit 292 or the inner frame opening detection circuit 290. Can be discriminated.

  The front frame external output terminal plate 293 and the inner frame external output terminal plate 291 are connected to different input terminals of the hall computer 262, respectively. Therefore, the pulse signal output from the front frame external output terminal plate 293 and the pulse signal output from the inner frame external output terminal plate 291 are individually input to the hall computer 262. As a result, the pulse signal output from the front frame external output terminal plate 293 and the pulse signal output from the inner frame external output terminal plate 291 can be individually stored in the hall computer 262. Accordingly, by analyzing the pulse signals individually stored in the hall computer 262, it is possible to detect whether the inner frame 12 is opened or the front frame 14 is opened.

  As described above, the main controller 110 includes the inner frame opening detection circuit 290 that operates when the inner frame 12 is opened and the front frame opening detection circuit 292 that operates when the front frame 14 is opened. Are provided separately. Therefore, when either or both of the inner frame 12 and the front frame 14 are opened, it is possible to determine which has been opened by the notification performed by the pachinko machine 500, in addition to the hall computer. The determination can also be made based on the pulse signal stored in H.262.

  The RAM 203 of the main controller 110 is provided with an inner frame release flag 203a and a front frame release flag 203b. The inner frame opening flag 203a is a flag indicating the opened state or the closed state of the inner frame 12. As described above, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power supply DC1, the inner frame 12 is opened, and the switch SW3 (switch SW3-1 and switch SW3 When -2) is turned on, a signal having a DC voltage of 5 volts is output from the inner frame opening detection circuit 290 to the input / output port 205. When this 5-volt signal is detected by the MPU 201 via the input / output port 205, the inner frame release flag 203a is turned on. When the inner frame release flag 203a is turned on, the MPU 201 transmits an inner frame release command that notifies the sound lamp control device 113 that the inner frame 12 has been released.

  On the other hand, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, the inner frame 12 is closed, and the switch SW3 (switch SW3-1 and switch SW3-2) is closed. ) Is cut off, the signal output of DC voltage 5 volts from the inner frame opening detection circuit 290 to the input / output port 205 is stopped (the output from the inner frame opening detection circuit 290 to the input / output port 205 is zero volts). Become). When this stop of signal output is detected by the MPU 201 via the input / output port 205, the inner frame release flag 203a is turned off. When the inner frame opening flag 203a is turned off, the MPU 201 transmits an inner frame closing command that informs the sound lamp control device 113 that the inner frame 12 has been closed. Thus, when the inner frame 12 is opened, the inner frame release flag 203a is turned on, while when the inner frame 12 is closed, the inner frame release flag 203a is turned off.

  The front frame opening flag 203b is a flag indicating whether the front frame 14 is open or closed. When power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, the front frame 14 is opened and the switch SW4 (switch SW4-1 and switch SW4-2) is turned on. When conducting, a signal with a DC voltage of 5 volts is output from the front frame opening detection circuit 292 to the input / output port 205. When this 5-volt signal is detected by the MPU 201 via the input / output port 205, the front frame opening flag 203b is turned on. When the front frame release flag 203b is turned on, the MPU 201 transmits a front frame release command that informs the audio lamp control device 113 that the front frame 14 has been opened.

  On the other hand, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, the front frame 14 is closed, and the switch SW4 (switch SW4-1 and switch SW4-2) is closed. ) Is stopped, the signal output of DC voltage 5 volts from the front frame opening detection circuit 292 to the input / output port 205 is stopped (the output from the front frame opening detection circuit 292 to the input / output port 205 is zero volts). Becomes). When this stop of signal output is detected by the MPU 201 via the input / output port 205, the front frame opening flag 203b is turned off. When the front frame opening flag 203b is turned off, the MPU 201 transmits a front frame closing command that informs the audio lamp control device 113 that the front frame 14 has been closed. Thus, when the front frame 14 is opened, the front frame opening flag 203b is turned on, while when the front frame 14 is closed, the front frame opening flag 203b is turned off.

  The RAM 223 of the sound lamp control device 113 is provided with an inner frame opening command reception flag 223a and a front frame opening command reception flag 223b. The inner frame opening command reception flag 223a is a flag indicating whether the command received by the sound lamp control device 113 is an inner frame opening command or an inner frame closing command. As described above, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, when the inner frame 12 is opened, the inner frame release flag 203a is turned on. The MPU 201 transmits an inner frame release command to the audio lamp control device 113. When this inner frame release command is detected by the MPU 221 via the input / output port 225, the inner frame release command reception flag 223a is turned on. When the inner frame release command reception flag 223a is turned on, the MPU 221 transmits an inner frame release command that notifies the display control device 114 that the inner frame 12 has been released. In addition, the MPU 221 notifies the opening of the inner frame 12 using the audio output device 226 and the lamp display device 227.

  On the other hand, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, if the inner frame 12 is closed, the inner frame open flag 203a is turned off, and the voice The MPU 201 transmits an inner frame closing command to the lamp control device 113. When this inner frame closing command is detected by the MPU 221 via the input / output port 225, the inner frame opening command reception flag 223a is turned off. When the inner frame open command reception flag 223a is turned off, the MPU 221 transmits an inner frame closing command that notifies the display control device 114 that the inner frame 12 has been closed. In addition, the MPU 221 stops the notification that has been performed using the audio output device 226 and the lamp display device 227. Thus, when the inner frame 12 is opened and the inner frame opening command is detected by the MPU 221, the inner frame opening command reception flag 223a is turned on, while the inner frame 12 is closed and the inner frame closing command is sent to the MPU 221. When detected, the inner frame release command reception flag 223a is turned off.

  The front frame open command reception flag 223b is a flag indicating whether the command received by the sound lamp control device 113 is a front frame open command or a front frame close command. When power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, when the front frame 14 is opened, the front frame open flag 203b is turned on and the sound lamp control is performed. The MPU 201 transmits a front frame release command to the device 113. When the front frame release command is detected by the MPU 221 via the input / output port 225, the front frame release command reception flag 223b is turned on. When the front frame opening command reception flag 223b is turned on, the MPU 221 transmits a front frame opening command that notifies the display control device 114 that the front frame 14 has been opened. In addition, the MPU 221 notifies the opening of the front frame 14 using the audio output device 226 and the lamp display device 227.

  On the other hand, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, if the front frame 14 is closed, the front frame opening flag 203b is turned off, and the voice A front frame closing command is transmitted from the MPU 201 to the lamp control device 113. When this front frame close command is detected by the MPU 221 via the input / output port 225, the front frame open command reception flag 223b is turned off. When the front frame opening command reception flag 223b is turned off, the MPU 221 transmits a front frame closing command that notifies the display control device 114 that the front frame 14 has been closed. In addition, the MPU 221 stops the notification that has been performed using the audio output device 226 and the lamp display device 227. Thus, when the front frame 14 is opened and the front frame open command is detected by the MPU 221, the front frame open command reception flag 223b is turned on, while the front frame 14 is closed and the front frame close command is sent to the MPU 221. When detected, the front frame open command reception flag 223b is turned off.

  The RAM 233 of the display control device 114 is provided with an effect permission flag 233a, a change start flag 233b, a display inner frame release command reception flag 233c, and a display front frame release command reception flag 233d. The effect permission flag 233a is a flag for permitting the start of display on the third symbol display device 81, and an effect permission command transmitted after the initial setting process of the main control device 110 is sent via the sound lamp control device 113. When the display control device 114 receives it (when an effect permission command is detected by the MPU 231 via the input port 237), it is turned on. In addition, once the effect permission flag 233a is turned on, the on-state is continued.

  The variation start flag 233b is a flag for permitting the start of variation display in the third symbol display device 81, and the display control device 114 sends the variation pattern command output from the main control device 110 to the voice lamp control device 113. (When the MPU 231 detects the variation pattern command output from the main control device 110 via the input port 237). The variation start flag 233b is turned off when variation display is started in the third symbol display device 81. Here, the fluctuation start flag 233b is turned off because, in the present embodiment, when the fluctuation start flag 233b is turned on, the third symbol display device 81 starts the fluctuation display. This is because, unless the fluctuation start flag 233b is turned off, a fluctuation start process (the process of S1010 in FIG. 31) described later is repeatedly executed, and a normal process is not executed.

  Next, the display inner frame release command reception flag 233c will be described. The display inner frame opening command reception flag 233c is a flag indicating whether the command received by the display control device 114 is an inner frame opening command or an inner frame closing command. As described above, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, when the inner frame 12 is opened, the main controller 110 is an audio lamp controller. An inner frame release command is transmitted to the display control device 114 via 113, indicating that the inner frame 12 has been released. When this inner frame release command is detected by the MPU 231 via the input port 237, the display inner frame release command reception flag 233c is turned on. When the display inner frame release command reception flag 233c is turned on, the MPU 231 displays a message indicating the release of the inner frame 12 on the third symbol display device 81.

  On the other hand, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power supply DC1, when the inner frame 12 is closed, the main controller 110 switches the sound lamp controller 113. Through this, an inner frame closing command for transmitting that the inner frame 12 has been closed is transmitted to the display control device 114. When this inner frame closing command is detected by the MPU 231 via the input port 237, the display inner frame opening command reception flag 233c is turned off. When the display inner frame release command reception flag 233c is turned off, the MPU 231 deletes the message indicating the release of the inner frame 12 displayed on the third symbol display device 81.

  Finally, the display front frame opening command reception flag 233d will be described. The display front frame opening command reception flag 233d is a flag indicating whether the command received by the display control device 114 is a front frame opening command or a front frame closing command. When power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power supply DC1, when the front frame 14 is opened, the main controller 110 passes through the sound lamp controller 113. Then, a front frame opening command is transmitted to the display control device 114 to notify that the front frame 14 has been opened. When this front frame release command is detected by the MPU 231 via the input port 237, the display front frame release command reception flag 233d is turned on. When the display front frame opening command reception flag 233d is turned on, the MPU 231 displays a message indicating the opening of the front frame 14 on the third symbol display device 81.

  On the other hand, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power supply DC1, when the front frame 14 is closed, the main controller 110 switches the sound lamp controller 113. The front frame closing command is transmitted to the display control device 114 to notify that the front frame 14 has been closed. When this front frame close command is detected by the MPU 231 via the input port 237, the display front frame open command reception flag 233d is turned off. When the display front frame opening command reception flag 233d is turned off, the MPU 231 deletes the message indicating the opening of the front frame 14 displayed on the third symbol display device 81.

  Next, with reference to FIG. 25, the inner frame open frame detection circuit 290 and the inner frame external output terminal plate 291 used in the pachinko machine 500 of the fourth embodiment will be described. FIG. 25 is a block diagram showing an electrical configuration of the inner frame opening detection circuit 290 and the inner frame external output terminal plate 291. Note that the inner frame open frame detection circuit 290 removes the switch SW2 connected in parallel to the switch SW1 of the frame open detection circuit 280 of the third embodiment described above with reference to FIG. 20, and switches the switch SW1 to the switch SW3-1. The inner frame terminal board output circuit 290a is changed, and the inner frame input / output port output circuit 290b having a switch SW3-2 operating in conjunction with the switch SW3-1. The inner frame terminal board output circuit 290a has the same configuration as the frame open detection circuit 280 of the third embodiment described above with reference to FIG. 20 except that the switch SW2 is removed and the switch SW1 is changed to the switch SW3-1. It is. Further, the inner frame external output terminal plate 291 has the same configuration as the external output terminal plate 261 of the third embodiment described above with reference to FIG. Therefore, for the inner frame frame opening detection circuit 290 and the inner frame external output terminal plate 291, the same parts as those of the frame opening detection circuit 280 and the external output terminal plate 261 described above with reference to FIG. The description thereof will be omitted, and only different parts will be described.

  Similarly to the configuration of the inner frame open frame detection circuit 290, the front frame open frame detection circuit 292 includes a front frame terminal board output circuit 292a (not shown) and a front frame input / output port output circuit 292b. (Not shown). The front frame terminal board output circuit 292a differs from the inner frame terminal board output circuit 290a only in that the connected switch is changed from the switch SW3-1 to the switch SW4-1. This is the same configuration as the frame terminal board output circuit 290a. That is, the front frame terminal board output circuit 292a has the same function as the inner frame open frame detection circuit 290 except that the switch to be connected is different from the inner frame open frame detection circuit 290. Similarly, the front frame input / output port output circuit 292b is different from the inner frame input / output port output circuit 290b only in that the connected switch is changed from the switch SW3-2 to the switch SW4-2. Other configurations are the same as those of the inner frame input / output port output circuit 290b. That is, the front frame input / output port output circuit 292b has the same function as the inner frame input / output port output circuit 290b except that the switch to be connected is different from the inner frame input / output port output circuit 290b. Further, the front frame external output terminal plate 293 has the same configuration as the inner frame external output terminal plate 291, that is, the same configuration as the external output terminal plate 261 of the third embodiment described above with reference to FIG. 20. is there. Therefore, description of the front frame open frame detection circuit 292 (front frame terminal board output circuit 292a and front frame input / output port output circuit 292b) and front frame external output terminal board 293 is omitted.

  As shown in FIG. 25, the switch SW3-2 used in the inner frame input / output port output circuit 290b has one end of the switch SW3-2 (one end of the terminal board 3-2b) as the anode of the DC power source DC1 and the diode D1. The other end of the switch SW3-2 (the other end of the terminal plate 3-2b) is connected to one end of the resistor R11 having a resistance value of 140 kΩ while being connected to the terminal.

  The other end of the resistor R11 is connected to one end of the resistor R12 having a resistance value of 100 kΩ and the input / output port 205, and the other end of the resistor R12 is grounded. The resistor R11 and the resistor R12 constitute a voltage dividing circuit that divides a 12-volt DC voltage supplied from the DC power source DC1. Therefore, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power supply DC1, when the inner frame 12 is opened and the switch SW3-2 is turned on, the DC power supply DC1 The supplied 12-volt DC voltage is divided by the resistors R11 and R12. At this time, the DC voltage applied to the resistor R12 is about 5 volts. Therefore, when the inner frame 12 is opened and the switch SW3-2 is turned on, a signal of 5 volts is input from the inner frame input / output port output circuit 290b to the input / output port 205. In addition, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, the inner frame 12 is opened and provided in the inner frame terminal board output circuit 290a. When the switch SW3-1 is turned on, the inner frame terminal plate output circuit 290a performs the same operation as that described in the frame open detection circuit 280 of the third embodiment in FIG. To the hall computer 262, a pulse signal having a pulse width of 10 milliseconds is output.

  On the other hand, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, the inner frame 12 is closed and provided in the input / output port output circuit 290b for the inner frame. When the switch SW3-2 is cut off, no DC voltage is applied to the resistors R11 and R12. Therefore, when the switch SW3 is cut off and the switch SW3-2 is cut off, no signal is input from the inner frame input / output port output circuit 290b to the input / output port 205 (input / output from the inner frame input / output port output circuit 290b). DC voltage input to port 205 is zero volts). In addition, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, the inner frame 12 is closed and provided in the inner frame terminal board output circuit 290a. When the switch SW3-1 is cut off, the inner frame terminal board output circuit 290a performs the same operation as that described in the frame open detection circuit 280 of the third embodiment in FIG. 20, and the detection of the inner frame 12 is performed again. Set to possible state.

  In addition, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 500 is cut off, the DC voltage of 12 volts is not supplied from the DC power supply DC1, so the switch SW3-2 is turned on. However, no signal is input from the inner frame input / output port output circuit 290b to the input / output port 205 (the DC voltage input from the inner frame input / output port output circuit 290b to the input / output port 205 is zero volts).

  However, the power is supplied from the capacitor CD1 to the inner frame terminal board output circuit 290a as described in the frame open detection circuit 280 of the third embodiment in FIG. Therefore, for example, even when the business hours of the game hall are over and the power supply to the pachinko machine 500 is cut off, the inner frame 12 is opened and provided in the inner frame terminal board output circuit 290a. When the switch SW3-1 is turned on, the inner frame terminal board output circuit 290a outputs a pulse signal having a pulse width of 10 milliseconds from the inner frame external output terminal board 291 to the hall computer 262.

  As described above, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power source DC1, the inner frame 12 is opened and the input / output port output circuit 290b for the inner frame is opened. When the provided switch SW3-2 is turned on, a signal of 5 volts is input from the inner frame input / output port output circuit 290b to the input / output port 205. When a 5 volt signal is input to the input / output port 205, the pachinko machine 500 notifies the opening of the inner frame 12 using the audio output device 226 and the lamp display device 227. In addition, the pachinko machine 500 displays a message indicating the opening of the inner frame 12 on the third symbol display device 81. Further, when the inner frame 12 is opened and the switch SW3-1 provided in the inner frame terminal plate output circuit 290a is turned on, the inner frame terminal plate output circuit 290a opens from the inner frame external output terminal plate 291 to the hole. A pulse signal having a pulse width of 10 milliseconds is output to the computer 262.

  On the other hand, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 500 is cut off, a DC voltage of 12 volts is not supplied from the DC power supply DC1, so the inner frame 12 is opened. Even when the switch SW3-2 provided in the inner frame input / output port output circuit 290b is turned on, no signal is input from the inner frame input / output port output circuit 290b to the input / output port 205 (input / output for the inner frame). The DC voltage input from the port output circuit 290b to the input / output port 205 becomes zero volts). However, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine 500 is interrupted, power is supplied from the capacitor CD1 to the inner frame terminal board output circuit 290a. Therefore, when the inner frame 12 is opened and the switch SW3-1 provided in the inner frame terminal plate output circuit 290a is turned on, the inner frame terminal plate output circuit 290a is connected to the inner frame external output terminal plate 291. A pulse signal having a pulse width of 10 milliseconds is output to the hall computer 262.

  The pulse signal output from the inner frame external output terminal plate 291 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 is opened can be specified by the pulse signal stored in the hall computer 262. Furthermore, the pulse signal is output from the external output terminal board 291 for the inner frame to the hall computer 262, and the output time of the output pulse signal is stored, so that the specified inner frame 12 of the pachinko machine is opened. The time can be detected.

  As described above, when the inner frame 12 is opened when power is supplied to the pachinko machine 500, the function of outputting a pulse signal to the hall computer 262 and the power supply to the pachinko machine 500 are cut off. When the inner frame 12 is opened, the function of outputting a pulse signal to the hall computer 262 can be exhibited by the inner frame terminal board output circuit 290a which is one circuit.

  One end of the switch SW3-2 of the inner frame input / output port output circuit 290b is connected to the DC power source DC1 and the anode terminal of the diode D1. Therefore, when the inner frame 12 is opened when the power of the pachinko machine 500 is turned on, the switch SW3-2 is turned on, and power is supplied from the DC power source DC1 to the inner frame input / output port output circuit 290b. Thus, the inner frame input / output port output circuit 290b is in an operating state. On the other hand, when the power of the pachinko machine 500 is off, no power is supplied from the DC power source DC1 to the input / output port output circuit 290b for the inner frame, so the inner frame 12 is opened and the switch SW3-2 is opened. Even so, the inner frame input / output port output circuit 290b is stopped.

  On the other hand, one end of the switch SW3-1 of the inner frame terminal board output circuit 290a is connected to one end of the capacitor CD1 via the diode D2 and the resistor R10. Therefore, when the inner frame 12 is opened while the power of the pachinko machine 500 is turned on, the switch SW3-1 becomes conductive, and power is supplied from the DC power source DC1 to the inner frame terminal board output circuit 290a. The inner frame terminal board output circuit 290a is in an operating state. On the other hand, when the power of the pachinko machine 500 is turned off, the power supply from the DC power source DC1 to the inner frame terminal board output circuit 290a is stopped, but the inner frame 12 is opened and the switch SW3-1 is turned on. Then, since electric power is supplied from the capacitor CD1 to the inner frame terminal board output circuit 290a, the inner frame terminal board output circuit 290a enters an operating state. Here, when the power of the pachinko machine 500 is turned off and power is supplied from the capacitor CD1 to the inner frame terminal board output circuit 290a, the power supply to the inner frame input / output port output circuit 290b is performed. It can be blocked by a diode D1 that exhibits a backflow prevention function. Therefore, when the power of the pachinko machine 500 is turned off, the number of times that the inner frame terminal board output circuit 290a can be operated can be increased, and the number of times that the inner frame 12 can be detected can be increased.

  Further, the timer IC1 of the inner frame terminal board output circuit 290a is activated when the inner frame 12 is opened, the switch SW3-1 is turned on, and the voltage applied to the TRG terminal of the timer IC1 falls to zero volts. It functions as a monostable multivibrator that raises the voltage of the OUT terminal of the timer IC 1 from zero volts to about 9.6 volts for about 10 milliseconds after the fall. By providing the integration circuit 281 in front of the TRG terminal of the timer IC1, when the inner frame 12 is opened, the voltage applied to the TRG terminal of the timer IC1 can be increased regardless of the opening period of the inner frame 12. The period from falling to zero volts until returning to about 10.3 volts can be adjusted to be shorter than the period in which the voltage at the OUT terminal of the timer IC 1 rises from zero volts to about 9.6 volts. In this way, the integration circuit 281 makes the timer functioning as a monostable multivibrator by setting the falling period of the TRG terminal voltage of the timer IC 1 to a fixed period (about 2 milliseconds) regardless of the opening period of the inner frame 12. It is possible to keep IC1 operating normally and to keep the voltage at the OUT terminal of timer IC1 rising from zero volts to about 9.6 volts to about 10 milliseconds. As a result, the period during which current is supplied from the capacitor CD1 to the photocoupler PR1 can be kept at about 10 milliseconds, and the output period of the pulse signal output from the inner frame external output terminal plate 291 to the hall computer 262 is about 10 m. You can stay in seconds.

  Next, referring to FIG. 26, regardless of whether the power of pachinko machine 500 is on or off, the inner frame terminal board output changes according to the conduction cut-off state of switch SW3-1 (open state of inner frame 12). The TRG terminal voltage of the timer IC1 of the circuit 290a, the OUT terminal voltage of the timer IC1 of the inner frame terminal board output circuit 290a, the output of the inner frame external output terminal board 291 (input of the hall computer 262), and the pachinko machine 500 The relationship between the switch SW3-2 and the output of the inner frame input / output port output circuit 290b that changes in accordance with the continuity cut-off state of the switch SW3-2 (the opened state of the inner frame 12) will be described. FIG. 26 shows an on / off state of the power source of the pachinko machine 500 (a state of a direct current voltage supplied from the direct current power source DC1), a conduction cutoff state of the switch SW3-1 and the switch SW3-2 (an open state of the inner frame 12), The TRG terminal voltage of the timer IC1 of the terminal board output circuit 290a for the inner frame, the OUT terminal voltage of the timer IC1 of the terminal board output circuit 290a for the inner frame, the output of the external output terminal board 291 for the inner frame (the input of the hall computer 262) And the output of the inner frame input / output port output circuit 290b.

  As described above, the front frame terminal board output circuit 292a provided in the front frame frame open detection circuit 292 is different from the inner frame terminal board output circuit 290a in that the switch to be connected is changed from the switch SW3-1. It is only the place changed to switch SW4-1, and others are the same structures as the terminal board output circuit 290a for inner frames. Therefore, the operation of the front frame terminal board output circuit 292a is the same as the operation of the inner frame terminal board output circuit 290a. Also, the front frame input / output port output circuit 292b is different from the inner frame input / output port output circuit 290b only in that the connected switch is changed from the switch SW3-2 to the switch SW4-2. The other configuration is the same as that of the inner frame input / output port output circuit 290b. Therefore, the operation of the front frame input / output port output circuit 292b is the same as the operation of the inner frame input / output port output circuit 290b. Further, since the front frame external output terminal plate 293 has the same configuration as the inner frame external output terminal plate 291, the operation of the front frame external output terminal plate 293 is the same as that of the inner frame external output terminal plate 291. It is. Therefore, description of the operations of the front frame terminal board output circuit 292a, the front frame input / output port output circuit 292b, and the front frame external output terminal board 293 is omitted.

  As shown in FIG. 26 (a), the power supply of the pachinko machine 500 is in an on state until t11 (the DC voltage supplied by the DC power supply DC1 is 12 volts until t11). The power supply of the machine 500 is turned off (the DC voltage supplied from the DC power supply DC1 is zero volts). Therefore, the power from the DC power supply DC1 is supplied to the inner frame terminal board output circuit 290a and the inner frame input / output port output circuit 290b until time t11. Then, after time t11, the supply of power by the DC power source DC1 to the inner frame terminal board output circuit 290a and the inner frame input / output port output circuit 290b is stopped. However, since the capacitor CD1 is provided in the inner frame terminal board output circuit 290a, power is supplied from the capacitor CD1 to the inner frame terminal board output circuit 290a after t11. Therefore, the inner frame terminal board output circuit 290a is operable even after t11.

  As shown in FIG. 26 (b), at time t9, when the switch SW3-1 becomes conductive (inner frame 12 is open), charging of the capacitor CD7 is started, and as shown in FIG. 26 (c), the timer The TRG terminal voltage of IC1 falls from about 10.3 volts to zero volts (at time t9). Then, following this, as shown in FIG. 26D, the OUT terminal voltage of the timer IC 1 rises from zero volts to about 9.6 volts (at time t9). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the inner frame terminal plate output circuit 290a are conducted, and the light emitting diode on the primary side of the photocoupler PR1 of the outer output terminal plate 291 for the inner frame (see FIG. 25), Current supply is started (at time t9). Then, as shown in FIG. 26 (e), the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the inner frame external output terminal plate 291 is changed from the low state to the high state at t9. Switch to state. Thereby, output of a pulse signal indicating opening of the inner frame 12 to the hall computer 262 is started. Further, as shown in FIG. 26B, when the switch SW3-2 is in a conductive state (the inner frame 12 is in an open state) at t9, a direct current is applied to the resistors R11 and R12 of the inner frame input / output port output circuit 290b. The power from the power source DC1 is supplied, and the voltage applied to the resistor R12 is 5 volts (at time t9). Therefore, as shown in FIG. 26 (f), a signal having a DC voltage of 5 volts is output from the inner frame input / output port output circuit 290b to the input / output port 205 (at time t9).

  Next, as shown in FIG. 26 (c), when about 2 milliseconds elapse from t9, the charging of the capacitor CD7 is completed, and the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again. However, since the voltage of the OUT terminal of the timer IC1 has risen from zero volts to about 9.6 volts (from t9), about 10 milliseconds have not elapsed, the OUT terminal voltage of the timer IC1 is about 9.6 volts. Is maintained.

  Thereafter, when about 10 milliseconds elapse from t9, as shown in FIG. 26D, the timer IC1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts. Then, the collector terminal and the emitter terminal of the transistor TR1 of the inner frame terminal plate output circuit 290a are cut off, and the current supply to one end of the resistor R7a of the inner frame external output terminal plate 291 is stopped. Therefore, the output of the inner frame external output terminal plate 291 switches from the high state to the low state as shown in FIG. 26 (e) when about 10 milliseconds elapse from t9. Thereby, the output of the pulse signal output to the hall computer 262 is stopped. Thus, by switching the output of the inner frame external output terminal plate 291, the pulse width of the pulse signal output from the inner frame external output terminal plate 291 to the hall computer 262 can be kept at about 10 milliseconds. .

  As shown in FIG. 26B, when the switch SW3-1 is in a cut-off state (the inner frame 12 is closed) at t10, the inner frame terminal board output circuit 290a again detects the inner frame 12. Is set to a possible state. As shown in FIG. 26 (b), when the switch SW3-2 is in a cut-off state (the inner frame 12 is closed) at time t10, the resistance R11 and the resistance R12 of the inner frame input / output port output circuit 290b are connected to each other. The power supply from the DC power supply DC1 is stopped, and the voltage applied to the resistor R12 becomes zero volts (at time t10). Therefore, as shown in FIG. 26 (f), the DC voltage 5 volt signal output from the inner frame input / output port output circuit 290b to the input / output port 205 is stopped at t10 (inner frame input). (The output from the output port output circuit 290b to the input / output port 205 becomes zero volts at t10).

  As shown in FIG. 26 (a), when the power of the pachinko machine 500 is turned off after t11 (when the DC voltage supplied from the DC power supply DC1 becomes zero volts), the inner frame terminal board output circuit 290a and the inner frame The supply of power by the DC power source DC1 to the input / output port output circuit 290b is stopped. However, even when the power of the pachinko machine 500 is off, the power from the capacitor CD1 is supplied to the inner frame terminal board output circuit 290a. Therefore, as shown in FIG. 26 (b), when the switch SW3-1 becomes conductive (the inner frame 12 is in the open state) at t12, charging of the capacitor CD7 is started, as shown in FIG. 26 (c). The TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts (at t12). Then, following this, as shown in FIG. 26D, the OUT terminal voltage of the timer IC 1 rises from zero volts to about 9.6 volts (at t12). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the inner frame terminal plate output circuit 290a are conducted, and the light emitting diode on the primary side of the photocoupler PR1 of the inner frame external output terminal plate 291 (see FIG. 25), Current supply is started (at t12). Then, as shown in FIG. 26 (e), the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the inner frame external output terminal plate 291 is changed from the low state to the high state at t12. Switch to state. Thereby, output of a pulse signal indicating opening of the inner frame 12 to the hall computer 262 is started. On the other hand, as shown in FIG. 26B, even when the switch SW3-2 is in the conductive state (the inner frame 12 is in the open state) at t12, the resistors R11 and R12 of the inner frame input / output port output circuit 290b are provided. Is not supplied with power from the DC power supply DC1 (since the DC voltage supplied by the DC power supply DC1 is zero volts), the voltage applied to the resistor R12 is zero volts (at t12). Therefore, as shown in FIG. 26 (f), the signal output from the inner frame input / output port output circuit 290b to the input / output port 205 maintains the stopped state (input from the inner frame input / output port output circuit 290b). The output to output port 205 remains at zero volts).

  The charge stored in the capacitor CD7 of the inner frame terminal board output circuit 290a between t9 and t10 is instantaneously completed via the zener diode D3 of the inner frame terminal board output circuit 290a at t12. . The discharge period of the capacitor CD7 is a period that is much shorter than about 2 milliseconds, in which the voltage at the TRG terminal of the timer IC1 is changed from about 10.3 volts to zero volts and is again about 10.3 volts. It does not significantly affect the voltage applied to the TRG terminal. In addition to this discharge, the charge stored in the capacitor CD7 from t9 to t10 is also discharged by self-discharge of the capacitor CD7.

  At t12, the TRG terminal of the timer IC1 of the inner frame terminal board output circuit 290a stores the voltage of about 10.3 volts supplied from the capacitor CD1 and the capacitor CD7 of the inner frame terminal board output circuit 290a. An overvoltage of a magnitude that destroys the timer IC1 may be applied by superimposing a voltage of about 10.3 volts associated with the generated charge. However, since a Zener diode D3 having a limit voltage (zener voltage) of about 10.5 volts is connected to the preceding stage of the TRG terminal of the timer IC1, the maximum value of the voltage applied to the TRG terminal of the timer IC1 is The overvoltage which is about 10.5 volts and destroys the timer IC1 is not applied to the TRG terminal of the timer IC1.

  Next, as shown in FIG. 26 (c), when about 2 milliseconds have elapsed since t12, the charging of the capacitor CD7 of the inner frame terminal board output circuit 290a is completed, and the TRG terminal voltage of the timer IC1 becomes zero volts again. To about 10.3 volts. However, since about 10 milliseconds have not elapsed since the voltage of the OUT terminal of the timer IC1 rose from zero volts to about 9.6 volts (from t12), the OUT terminal voltage of the timer IC1 is about 9.6 volts. Is maintained.

  Thereafter, when about 10 milliseconds elapse from t12, the timer IC1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts as shown in FIG. Then, the collector terminal and the emitter terminal of the transistor TR1 of the inner frame terminal plate output circuit 290a are cut off, and the current supply to one end of the resistor R7a of the inner frame external output terminal plate 291 is stopped. Therefore, the output of the inner frame external output terminal plate 291 switches from the high state to the low state as shown in FIG. 26 (e) when about 10 milliseconds elapse from t12. Thereby, the output of the pulse signal output to the hall computer 262 is stopped. Thus, by switching the output of the inner frame external output terminal plate 291, the pulse width of the pulse signal output from the inner frame external output terminal plate 291 to the hall computer 262 can be kept at about 10 milliseconds. .

  As shown in FIG. 26 (b), when the switch SW3-1 is cut off (the inner frame 12 is closed) at t13, the inner frame terminal board output circuit 290a again detects the inner frame 12. Is set to a possible state. Similarly, as shown in FIG. 26 (b), when the switch SW 3-2 is cut off (the inner frame 12 is closed) at t 13, the inner frame input / output port output circuit 290 b causes the pachinko machine 500 to Is set to a state in which the inner frame 12 can be detected.

  As described above, when power is supplied to the pachinko machine 500 and a DC voltage of 12 volts is supplied from the DC power supply DC1 (until t11), the inner frame 12 is opened and the inner frame 12 is opened. When the switch SW3-1 provided in the terminal board output circuit 290a is turned on, the inner frame terminal board output circuit 290a sends a pulse signal having a pulse width of 10 msec from the inner frame external output terminal board 291 to the hall computer 262. Output. Further, when the inner frame 12 is opened and the switch SW3-2 provided in the inner frame input / output port output circuit 290b is turned on, a signal of 5 volts is supplied from the inner frame input / output port output circuit 290b to the input / output port 205. Is entered.

  Further, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine 500 is interrupted (even after t11), the inner frame terminal board output circuit 290a includes Since the power is supplied from the capacitor CD1, when the inner frame 12 is opened and the switch SW3-1 provided in the inner frame terminal plate output circuit 290a conducts, the inner frame terminal plate output circuit 290a A pulse signal having a pulse width of 10 milliseconds is output from the inner frame external output terminal plate 291 to the hall computer 262. However, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 500 is cut off (in the case of after t11), a DC voltage of 12 volts is applied from the DC power source DC1 to the inner frame. Since the internal frame 12 is opened and the switch SW3-2 provided in the internal frame input / output port output circuit 290b is turned on, the internal frame input / output is not supplied to the internal input / output port output circuit 290b. No signal is output from the port output circuit 290b to the input / output port 205 (the DC voltage output from the inner frame input / output port output circuit 290b to the input / output port 205 is zero volts).

  Thus, when power is supplied to the pachinko machine 500, when the inner frame 12 is opened, a function of outputting a signal to the input / output port 205 and a function of outputting a pulse signal to the hall computer 262, The function of outputting a pulse signal to the hall computer 262 when the inner frame 12 is opened when the power supply to the pachinko machine 500 is cut off is a single circuit inner frame open detection circuit 290. Can demonstrate.

  In addition, when the switch SW3-1 and the switch SW3-2 are in a conductive state (the inner frame 12 is in an open state), the timer IC1 of the inner frame terminal board output circuit 290a determines whether the switch SW3-1 is in a conductive period (in the inner frame 12). Regardless of the open period), when the switch SW3-1 becomes conductive (the inner frame 12 is open) and the TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts, the timer The voltage at the OUT terminal of IC1 is switched from about 9.6 volts to zero volts. Thereby, the supply period of the current supplied to the photocoupler PR1 of the inner frame external output terminal plate 291 is about 10 milliseconds.

  Thus, for example, the business hours of the amusement hall are terminated and the power supply to the pachinko machine is cut off, and a DC voltage of 12 volts from the DC power supply DC1 is supplied to the inner frame terminal board output circuit 290a and the inner frame external output terminal board 291. Is supplied, that is, when a DC voltage of about 10.3 volts is supplied from the capacitor CD1 to the inner frame terminal plate output circuit 290a and the inner frame external output terminal plate 291, the capacitor CD1 to the photocoupler PR1. The supply period of the supplied current can be limited to about 10 milliseconds per opening of the inner frame 12. Therefore, the power consumption due to the opening of the inner frame 12 can be kept small.

  Next, each control process executed by the MPU 201 in the main control device 110 of the pachinko machine 500 according to the fourth embodiment will be described with reference to the flowcharts of FIGS. 27 and 28. Each control process executed by the main control device 110 of the pachinko machine 500 according to the fourth embodiment is the main process (of the control processes executed by the main control device 110 of the pachinko machine 10 according to the first embodiment). 12) and the timer interrupt process (see FIG. 15), and other control processes are the same as the control processes executed by the main control device 110 of the pachinko machine 10 of the first embodiment. It is. Therefore, in the pachinko machine 500 according to the fourth embodiment, the main process shown in FIG. 27 and the timer interrupt process shown in FIG. 28 will be described, and description of other control processes will be omitted. For convenience of explanation, the timer interrupt process (FIG. 28) will be described first, and then the main process (FIG. 27) will be described.

  With reference to FIG. 28, the timer interruption process performed with the main control apparatus 110 of the pachinko machine 500 of 4th Embodiment is demonstrated. FIG. 28 is a flowchart showing a timer interrupt process executed by the MPU 201 in the main controller 110. The timer interrupt process is executed by the MPU 201 of the main control device 110, for example, every 2 milliseconds. Note that the timer interrupt process executed by the main controller 110 of the pachinko machine 500 of the fourth embodiment shown in FIG. 28 is the timer interrupt process executed by the main controller 110 of the pachinko machine 10 of the first embodiment. A process of setting the inner frame release flag 203a and the front frame release flag 203b to ON or OFF (the processes of S506 to S513) is added between the processes of S501 and S502 (see FIG. 15). Therefore, the same parts as those of the timer interrupt process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 15 are denoted by the same reference numerals, and the description thereof is omitted. Only different parts will be described.

  In the timer interrupt process, first, a process for reading various winning switches is executed (S501). That is, the state of various switches connected to the main controller 110 is read, and the state of the switch is determined and the detection information (winning detection information) is stored.

  Next, an output reading process of the inner frame input / output port output circuit 290b is executed (S506). That is, the voltage value of the signal output from the inner frame input / output port output circuit 290b to the input / output port 205 is read. Then, it is determined whether or not the output (signal) of the read inner frame input / output port output circuit 290b is 5 volts (S507). If the read output (signal) of the input / output port output circuit 290b for the inner frame is 5 volts (S507: Yes), the inner frame 12 is opened, so the inner frame release flag 203a is turned on (S508). . On the other hand, if the output (signal) of the read inner frame input / output port output circuit 290b is zero volts (S507: No), the inner frame 12 is closed, so the inner frame release flag 203a is turned off (S509). ).

  After the processing of S508 or S509, output reading processing of the front frame input / output port output circuit 292b is executed (S510). That is, the voltage value of the signal output from the front frame input / output port output circuit 292b to the input / output port 205 is read. Then, it is determined whether or not the read output (signal) of the front frame input / output port output circuit 292b is 5 volts (S511). If the output (signal) of the read front frame input / output port output circuit 292b is 5 volts (S511: Yes), the front frame 14 is opened, so the front frame release flag 203b is turned on (S512). . On the other hand, if the output (signal) of the read front frame input / output port output circuit 292b is zero volts (S511: No), the front frame 14 is closed, so the front frame open flag 203b is turned off (S513). ). After the processing of S512 or S513, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S502).

  Thus, if the read output (signal) of the input / output port output circuit 290b for the inner frame is 5 volts, the main frame 110 is turned on because the inner frame 12 is opened. To. On the other hand, if the read output (signal) of the inner frame input / output port output circuit 290b is zero volts, the inner frame 12 is closed, so the inner frame release flag 203a is turned off. Further, if the output (signal) of the read front frame input / output port output circuit 292b is 5 volts, the main controller 110 opens the front frame open flag 203b because the front frame 14 is open. . On the other hand, if the read output (signal) of the front frame input / output port output circuit 292b is zero volts, the front frame 14 is closed, so the front frame open flag 203b is turned off.

  Next, with reference to FIG. 27, the main process performed with the main controller 110 of the pachinko machine 500 of 4th Embodiment is demonstrated. FIG. 27 is a flowchart showing main processing executed by the MPU 201 in the main control device 110. In this main process, the main process of the game is executed. As an outline, each process of S201 to S206 and S215 to S220 is executed as a periodic process with a period of 4 milliseconds, and the counter update process of S209 and S210 is executed in the remaining time.

  The main process executed by the main controller 110 of the pachinko machine 500 according to the fourth embodiment shown in FIG. 27 is the main process executed by the main controller 110 of the pachinko machine 10 according to the first embodiment (see FIG. 12). ) Between the processing of S201 and S202 in FIG. 5B, a process of transmitting either the inner frame opening command or the inner frame closing command, or the front frame opening command or the front frame closing command to the sound lamp control device 113 (S215 to S215). The process of S220 is added. Therefore, the same parts as those in the main process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 12 are denoted by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

  In the main process executed by the main control device 110 of the pachinko machine 10 according to the fourth embodiment, an external output for transmitting output data such as a command updated in the previous process to each control device (peripheral control device) on the sub side. After the process (S201) is executed, it is determined whether the inner frame release flag 203a is on (S215). If the inner frame opening flag 203a is on (S215: Yes), that is, if the inner frame 12 is opened, an inner frame opening command is transmitted to the sound lamp control device 113 (S216). On the other hand, if the inner frame opening flag 203a is off (S215: No), that is, if the inner frame 12 is closed, an inner frame closing command is transmitted to the sound lamp control device 113 (S217). After the process of S216 or S217, it is determined whether or not the front frame release flag 203b is on (S218). If the front frame opening flag 203b is ON (S218: Yes), that is, if the front frame 14 is opened, a front frame opening command is transmitted to the sound lamp control device 113 (S219). On the other hand, if the front frame opening flag 203b is off (S218: No), that is, if the front frame 14 is closed, a front frame closing command is transmitted to the sound lamp control device 113 (S220). After the process of S219 or S220, the fluctuation type counters CS1, CS2, CS3 are updated (S202).

  Thus, main controller 110 repeatedly transmits an inner frame release command to voice lamp controller 113 if inner frame release flag 203a is on, that is, inner frame 12 is opened. On the other hand, if the inner frame opening flag 203a is off, that is, if the inner frame 12 is closed, the inner frame closing command is repeatedly transmitted to the sound lamp control device 113. Further, the main control device 110 repeatedly transmits a front frame opening command to the sound lamp control device 113 when the front frame opening flag 203b is ON, that is, when the front frame 14 is opened. On the other hand, if the front frame opening flag 203b is OFF, that is, if the front frame 14 is closed, a front frame closing command is repeatedly transmitted to the sound lamp control device 113.

  The command transmission of main controller 110 may be as follows. For example, when the inner frame 12 is opened and the inner frame opening flag 203a is turned on, the main control device 110 transmits an inner frame opening command once to the sound lamp control device 113, and the inner frame 12 is closed. Thus, when the inner frame opening flag 203a is turned off, the inner frame closing command may be transmitted once to the sound lamp control device 113. Similarly, when the front frame 14 is opened and the front frame opening flag 203b is turned on, the main control device 110 transmits a front frame opening command once to the sound lamp control device 113, and the front frame 14 is closed. Then, when the front frame opening flag 203b is turned off, the front frame closing command may be transmitted once to the sound lamp control device 113.

  Next, processing performed by the audio lamp control device 113 will be described with reference to FIGS. FIG. 29 is a flowchart showing a start-up process executed by the MPU 221 in the sound lamp control device 113, and this start-up process is started when the power is turned on.

  When the start-up process is executed, first, an initial setting process associated with power-on is executed (S701). Specifically, a predetermined value set in advance for the stack pointer is set. Thereafter, depending on whether or not the power-off process flag is turned on, the power-on process of S816 (see FIG. 30) is performed due to an instantaneous voltage drop (momentary power failure, so-called “momentary power failure”). ) Is determined during execution (S702). As will be described later with reference to FIG. 30, when the sound lamp control device 113 receives a power-off command from the main control device 110 (see S812 in FIG. 30), it executes a power-off process in S816. The power-off process flag is turned on before the power-off process is executed, and the power-off process flag is turned off after the power-off process ends. Therefore, whether or not the power-off process in S815 is in progress can be determined based on the state of the power-off process flag.

  If the power-off process flag is off (S702: No), the current start-up process is started after the power supply is completely shut off, or after a momentary power failure has occurred and the power-off process at S816 is completed. It was started after the execution of the process was completed, or started only after the MPU 221 of the sound lamp control device 113 was reset due to noise or the like (without receiving a power-off command from the main control device 110). is there. Therefore, in these cases, it is confirmed whether or not the data in the RAM 223 is destroyed (S703).

  Confirmation of data destruction of the RAM 223 is performed as follows. That is, data as a keyword “55AAh” is written in a specific area of the RAM 223 by the processing of S706. Therefore, the data stored in the specific area is checked, and if the data is “55AAh”, there is no data destruction in the RAM 223. Conversely, if the data is not “55AAh”, the data destruction in the RAM 223 can be confirmed. If data destruction of the RAM 223 is confirmed (S703: Yes), the process proceeds to S704, and initialization of the RAM 223 is started. On the other hand, if data destruction of the RAM 223 is not confirmed (S703: No), the process proceeds to S708.

  If the current start-up process is started after the power supply is completely shut down, the keyword “55AAh” is not stored in the specific area of the RAM 223 (the memory of the RAM 223 is lost due to the power-off). ), It is determined that the data in the RAM 223 has been destroyed (S703: Yes), and the process proceeds to S704. On the other hand, this startup process was started after an instantaneous power failure and after completing the power-off process in S816, or reset only to the MPU 221 of the audio lamp control device 113 due to noise or the like. When the process starts, since the keyword “55AAh” is stored in the specific area of the RAM 223, it is determined that the data in the RAM 223 is normal (S703: No), and the process proceeds to S708.

  If the power-off process flag is on (S702: Yes), the startup process of this time is after the momentary power failure has occurred and during the execution of the power-off process of S816, the sound lamp control device 113. The MPU 221 is started after being reset. In such a case, since the power-off process is being executed, the storage state of the RAM 223 is not necessarily correct. Therefore, since control cannot be continued in such a case, the process proceeds to S704 and initialization of the RAM 223 is started.

  In the process of S704, the entire storage area of the RAM 223 is checked (S704). As a check method, first, “0FFh” is written for each byte, and it is read for each byte to check whether it is “0FFh”. The writing and checking for each byte are performed in the order of “55h”, “0AAh”, and “00h” after “0FFh”. This RAM 223 read / write check clears all storage areas of the RAM 223 to zero.

  If it is determined that the read / write check is normal for all the storage areas of the RAM 223 (S705: Yes), the keyword “55AAh” is written in the specific area of the RAM 223 and the RAM destruction check data is set (S706). By checking the keyword “55AAh” written in the specific area, it is checked whether or not there is data corruption in the RAM 223. On the other hand, if an abnormality of the read / write check is detected in any storage area of the RAM 223 (S705: No), the abnormality of the RAM 223 is notified (S707), and an infinite loop is performed until the power is shut off. The abnormality of the RAM 223 is notified by the display lamp 34. Note that the audio output device 226 may output a sound to notify the RAM 223 of an abnormality.

  In the process of S708, it is determined whether or not the power-off flag is turned on (S708). Since the power-off flag is turned on when the power-off process in S816 is executed (see S815 in FIG. 30), the power-off flag is turned on by the process in S815 as described later with reference to FIG. In other words, since the power-off flag is turned on before the power-off process of S816 is executed, the startup process of this time is the moment when the power-off flag is turned on. This is a case where the process is started after a power failure has occurred and the execution of the power-off process in S816 is not completed. Therefore, in such a case (S708: Yes), the RAM work area is cleared to initialize each process of the sound lamp control device 113 (S709), the initial value of the RAM 223 is set (S710), and an interrupt is performed. The permission is set (S711), and the process proceeds to the main process. Note that the work area of the RAM 223 is an area other than an area for storing commands received from the main control device 110.

  On the other hand, when the power-off flag is turned off, the process of S708 is reached because the current start-up process is started after, for example, the power supply is completely shut down, so that the process of S708 is performed via the processes of S704 to S706. This is a case where the processing has been reached, or the MPU 221 of the sound lamp control device 113 is reset only (without receiving a power-off command from the main control device 110) due to noise or the like. Therefore, in such a case (S708: No), S709, which is the process of clearing the work area of the RAM 223, is skipped, the process proceeds to S710, the initial value of the RAM 223 is set (S710), and interrupt permission is set. In step S711, the process proceeds to the main process.

  Note that the reason for skipping the clear process in S709 is that if the process from S704 to S708 is reached via the process in S706, all storage areas in the RAM 223 have already been cleared by the process in S704. When only the MPU 221 of the sound lamp control device 113 is reset due to noise or the like and the start-up process is started, the data in the work area of the RAM 223 is stored without being cleared, so that the sound lamp control device 113 is saved. This is because the control can be continued.

  Next, with reference to FIG. 30, the main process executed after the startup process of the sound lamp control device 113 will be described. FIG. 30 is a flowchart showing main processing executed by the MPU 221 of the sound lamp control device 113. When the main process is executed, it is first determined whether or not 1 msec or more has elapsed since the main process started (S801). If 1 msec or more has not elapsed (S801: No), S802 to S809. The process proceeds to S810 without performing the process. In step S801, it is determined whether or not 1 msec has passed. In steps S802 to S809, the process is related to display (production), and it is not necessary to edit in a short cycle (within 1 msec). This is because it is preferable to execute the counter update process and the command reception process in S811 in a short cycle. As a result, it is possible to prevent omission of a command transmitted from the main controller 110.

  If 1 msec or more has passed in the process of S801 (S801: Yes), the output of each lamp is set so that the lighting mode of the display lamp 34 is set or the lighting mode of the lamp edited in the processing of S807 described later is set. (S802) Then, a power-on notification process is executed (S803). In the power-on notification process, when the power is turned on, a notification is given to notify that the power is turned on for a predetermined time (for example, 30 seconds). The notification is performed by the audio output device 226 or the lamp display device 227. Is called. Moreover, it is good also as what transmits a command to the display control apparatus 114 to alert | report that power was supplied on the screen of the 3rd symbol display apparatus 81. FIG. If it is not when the power is turned on, the process proceeds to S804 without performing the notification by the power-on notification process.

  In the process of S804, a waiting-for-customer effect is executed, and then a hold number display update process is executed (S805). In the customer waiting effect, when a predetermined time elapses when the pachinko machine 500 is not played by the player, a setting for switching the display of the third symbol display device 81 to the title screen is performed, and the setting is displayed as a command as a display control device. 114. In the number-of-holds display update process, a process for turning on the hold lamp 85 in accordance with the operation hold ball N is performed.

  Thereafter, frame button input monitoring / effect processing is executed (S806). This frame button input monitoring / production process monitors the input of whether or not the frame button 22 operated by the player has been pressed to enhance the production effect, and corresponds to the case where the input of the frame button 22 is confirmed. This is a process for setting to produce an effect. For example, when a notice character appears at the start of fluctuation display, the expected value of the jackpot due to the current fluctuation is displayed by pressing the frame button 22, or the feeling of expectation for the jackpot is displayed by pressing the frame button 22 during reach production. It is good also as a decision button for changing to the production which can have, or selecting one reach production out of a plurality of reach productions. If the frame button 22 is not provided, the process of S806 is omitted.

  When the frame button input monitoring / production process ends, a lamp editing process is executed (S807), and then a sound editing / output process is executed (S808). In the lamp editing process, lighting patterns and the like of the illumination units 29 to 33 are set so as to correspond to the display performed on the third symbol display device 81. In the sound editing / output process, an output pattern of the sound output device 226 is set so as to correspond to the display performed on the third symbol display device 81, and sound is output from the sound output device 226 according to the setting.

  Thereafter, a liquid crystal effect execution management process is executed (S809), and the process proceeds to S810. In the liquid crystal effect execution management process, a time synchronized with the time required for the variable display performed by the third symbol display device 81 is set based on the change pattern command and the effect time addition command transmitted from the main control device 110. Based on the time set in the liquid crystal effect execution monitoring process, the effect time of the lamp editing process in S807 and the sound editing / output process in S808 is set.

  In the process of S810, the variable display process of the third symbol display device 81 is executed. In this variation display process, a plurality of counters (a counter for setting a stop symbol at the time of big hit, a counter for selecting a stop symbol at the time of disconnection, etc.) mounted on the sound lamp control device 113 are updated. Based on the variation pattern command and the stop symbol command transmitted from the control device 110, the symbol to be stopped and displayed on the third symbol display device 81 is set, or the variation display pattern (rear / rear out, front / rear non-rear reach, complete out) Etc. are set. The stop symbol and the variation pattern are transmitted to the display control device 114 as a command.

  In the processing of S810, for example, when the command of the variation pattern transmitted from the main control device 110 is “completely out”, a complete out A pattern is selected from a plurality of patterns corresponding to complete out, and the third symbol display A command is transmitted to the display control device 110 so that the device 81 can produce a completely off A pattern. Therefore, since the detailed variation pattern displayed on the third symbol display device 81 is determined by the sound lamp control device 113 with respect to one variation pattern determined by the main control device 110, the control of the main control device 110 is performed. The burden can be reduced. Furthermore, since the pattern of each effect determined in the main controller 110 can be reduced, the storage capacity of the ROM 202 can be reduced and the cost can be reduced.

  Then, the command from the main controller 110 is received (S811). When a command from the main control device 110 is received, if the command is used in the sound lamp control device 113 in accordance with the command, processing corresponding to the command is performed, the processing result is stored in the RAM 233, and used in the display control device 114. If it is a command, the command is transmitted to the display control device 114.

  When the processing of S811 is completed, it is determined whether or not the information on occurrence of power interruption is stored in the work RAM 233 (S812). The information on the occurrence of power-off is stored when a power-off command is received from the main controller 110. If power failure occurrence information is stored in the processing of S812 (S812: Yes), both the power interruption flag and the power interruption processing flag are turned on (S815), and the power interruption processing is executed (S816). After the power-off process is executed, the power-off process flag is turned off (S817), and then the process loops infinitely. In the power-off process, the generation of the interrupt process is prohibited and each output port is turned off to turn off the output from the audio output device 226 and the lamp display device 227. Further, the storage of the information on occurrence of power interruption is also erased.

  On the other hand, if the information on occurrence of power interruption is not stored in the process of S812 (S812: No), either the inner frame 12 or the front frame 14 is opened, or both the inner frame 12 and the front frame 14 are opened. If there is, the door opening notification process (S813) for performing notification using the audio output device 226 and the lamp display device 227 is executed.

  Here, the door opening notification process will be described with reference to FIG. FIG. 31 is a flowchart showing a door opening notification process executed by the MPU 221 of the sound lamp control device 113. This door opening notification process determines whether or not the voice lamp control device 113 has received four commands of an inner frame opening command, a front frame opening command, an inner frame closing command, or a front frame closing command, and according to the determination. This is a process for performing notification.

  In the door opening notification process, it is first determined in step S811 (see FIG. 30) whether or not an inner frame opening command indicating that the inner frame 12 is opened has been received (S901). When the inner frame release command is received (S901: Yes), it is determined whether or not the inner frame release command reception flag 223a is on (S902). If the inner frame release command reception flag 223a is not on (S902: No), the inner frame release notification process, which is the process of S905 described later, has not yet been started, so that the inner frame release notification process is started. Transition to subsequent processing. First, the inner frame release command reception flag 223a is turned on to indicate that the inner frame release command has been received (S903), and the inner frame release command is transmitted to the display control device 114 (S904). And the inner frame open | release notification process which alert | reports that the inner frame 12 is open | released using the audio | voice output device 226 and the lamp | ramp display device 227 is started (S905). In the inner frame release notification process, the voice output device 226 is used to notify, for example, an electronic sound that “the inner frame is open” or the inner frame 12 is opened using the lamp display device 227. For example, blinking is performed four times per second. Thereby, it is possible to notify an unspecified number of people that the inner frame 12 has been opened.

  The main controller 110 repeatedly transmits an inner frame release command to the sound lamp controller 113 during the period when the inner frame 12 is open. Therefore, when the inner frame release command has already been received and the processing of steps S903 to S905 has been executed and the inner frame release command is received again (S901: Yes), the inner frame release command reception flag 223a. Is determined to be on (S902: Yes), and the already started inner frame release notification process (S905) is continued (S906). Thereby, during the period when the inner frame 12 is opened, the inner frame release notification process (S905) is continuously executed. If the inner frame release command has not been received in the process of S811 (S901: No), the processes of S903 to S906 are skipped.

  Next, in the process of S811 (see FIG. 30), it is determined whether or not a front frame opening command indicating that the front frame 14 is open is received (S907). When the front frame release command is received (S907: Yes), it is determined whether or not the front frame release command reception flag 223b is on (S908). If the front frame release command reception flag 223b is not on (S908: No), the front frame release notification process, which is the process of S911 described later, has not been started yet, so that the front frame release notification process is started. Transition to subsequent processing. First, the front frame release command reception flag 223b is turned on to indicate that the front frame release command has been received (S909), and the front frame release command is transmitted to the display control device 114 (S910). Then, the front frame opening notification process for notifying that the front frame 14 is opened using the audio output device 226 and the lamp display device 227 is started (S911). In this front frame opening notification process, the voice output device 226 is used to notify, for example, an electronic sound that “the front frame is open” or the front frame 14 is opened using the lamp display device 227. For example, blinking is performed once per second. Thereby, it is possible to notify an unspecified number of people that the front frame 14 has been opened.

  The main control device 110 repeatedly transmits a front frame opening command to the sound lamp control device 113 while the front frame 14 is open. Therefore, when the front frame release command has already been received and the processing of S909 to S911 has been executed and the front frame release command is received again (S907: Yes), the front frame release command reception flag 223b. Is determined to be on (S908: Yes), and the already started front frame opening notification process (S911) is continuously executed (S912). Thereby, during the period when the front frame 14 is opened, the front frame open notification process (S911) is continuously executed. If the front frame release command has not been received in the process of S811 (S907: No), the processes of S909 to S912 are skipped.

  Next, in the process of S811 (see FIG. 30), it is determined whether or not an inner frame closing command indicating that the inner frame 12 is closed is received (S913). When the inner frame closing command is received (S913: Yes), it is determined whether or not the inner frame opening command reception flag 223a is on (S914). If the inner frame release command reception flag 223a is on (S914: Yes), the inner frame release notification process (S905) is started, but the process (S917) for ending the inner frame release notification process described later is still executed. Since it is not performed, the process proceeds to S915 and subsequent steps in order to execute a process for ending the inner frame release notification process. First, the inner frame opening command reception flag 223a is turned off to indicate that the inner frame closing command has been received (S915), and the inner frame closing command is transmitted to the display control device 114 (S916). Then, the inner frame release notification process that has been executed using the audio output device 226 and the lamp display device 227 is terminated (S917). Thereby, the notification indicating the opening of the inner frame 12 performed using the audio output device 226 or the lamp display device 227 can be terminated.

  The main control device 110 repeatedly transmits an inner frame closing command to the sound lamp control device 113 while the inner frame 12 is closed. Therefore, when the inner frame closing command has already been received and the processing of S915 to S917 has been executed and the inner frame closing command is received again (S913: Yes), the inner frame opening command reception flag 223a. Is determined to be off (S914: No), and the processing of S915 to S917 is skipped. Further, even when the inner frame closing command is not received in the processing of S811 (S913: No), the processing of S915 to S917 is skipped.

  Next, in the process of S811 (see FIG. 30), it is determined whether or not a front frame closing command indicating that the front frame 14 is closed is received (S918). When the front frame closing command is received (S918: Yes), it is determined whether or not the front frame opening command reception flag 223b is on (S919). If the front frame release command reception flag 223b is ON (S919: Yes), the front frame release notification process (S911) is started, but the process (S922) for ending the front frame release notification process described later is still executed. Since it is not performed, the process proceeds to S920 and subsequent steps in order to execute a process for ending the front frame opening notification process. First, the front frame open command reception flag 223b is turned off to indicate that the front frame close command has been received (S920), and the front frame close command is transmitted to the display control device 114 (S921). And the front frame open | release alerting | reporting process currently performed using the audio | voice output apparatus 226 and the lamp display apparatus 227 is complete | finished (S922). Thereby, the notification indicating the opening of the front frame 14 performed using the audio output device 226 and the lamp display device 227 can be terminated.

  The main control device 110 repeatedly transmits a front frame closing command to the sound lamp control device 113 while the front frame 14 is closed. Therefore, when the front frame closing command has already been received and the processing of S920 to S922 has been executed and the front frame closing command is received again (S918: Yes), the front frame opening command reception flag 223a. Is determined to be off (S919: No), and the processing of S920 to S922 is skipped. Further, even when the front frame closing command is not received in the process of S811 (S918: No), the processes of S920 to S922 are skipped.

  As described above, when the voice lamp control device 113 receives the inner frame release command in the process of S811 (see FIG. 30), the inner frame release command reception flag 223a indicates that the inner frame release command has been received. It is turned on (S903), an inner frame release command is transmitted to the display control device 114 (S904), and an inner frame release notification process is started (S905). Since the inner frame opening notification process (S905) is continuously performed until the inner frame 12 is closed, it is possible to notify an unspecified number of people that the inner frame 12 is being opened. Similarly, when the voice lamp control device 113 receives a front frame release command in the process of S811 (see FIG. 30), the front frame release command reception flag 223b is turned on to indicate that the front frame release command has been received. (S909), a front frame release command is transmitted to the display control device 114 (S910), and a front frame release notification process is started (S911). Since the front frame opening notification process (S911) is continuously performed until the front frame 14 is closed, it is possible to notify an unspecified number of people that the front frame 14 is open.

  In addition, when the voice lamp control device 113 receives the inner frame closing command in the process of S811 (see FIG. 30), and the inner frame opening notification process (S905) has already been performed, the inner frame opening command reception flag. 223a is turned off to indicate that the inner frame closing command has been received (S915), the inner frame closing command is transmitted to the display control device 114 (S916), and the inner frame opening notification process is terminated (S917). Similarly, when a front frame closing command is received in the process of S811 (see FIG. 30) and the front frame opening notification process (S911) has already been performed, the front frame opening command reception flag 223b is set. The command indicating that the command has been received is turned off (S920), a front frame closing command is transmitted to the display control device 114 (S921), and the front frame opening notification process is terminated (S922).

  Returning to the description of FIG. After the door opening notification process (S813) is executed, it is determined whether or not the RAM 223 is destroyed based on the keyword stored in the RAM 223 (S814). If the RAM 223 is not destroyed (S814: No), Returning to the process, the main process is repeatedly executed. On the other hand, if the RAM 223 is destroyed (S814: Yes), the processing is looped infinitely in order to stop the subsequent processing. Here, if it is determined that the RAM is destroyed and an infinite loop is performed, the main process is not executed, and thereafter the display on the third symbol display device 81 does not change. Therefore, since the player can know that an abnormality has occurred, he can call a hall clerk or the like to request repair of the pachinko machine 500 or the like. Further, when it is confirmed that the RAM 223 is destroyed, the sound output device 226 or the lamp display device 227 may notify the RAM destruction.

  Next, processing performed by the display control device 114 will be described with reference to FIGS. 32 and 33. For convenience of explanation, the external interrupt process of FIG. 33 will be described first, and then the main process of FIG. 32 will be described.

  FIG. 33 is a flowchart showing an external interrupt process executed by the MPU 231 in the display control device 114, and is executed when a command is received from the audio lamp control device 113. When the external interrupt process is executed, the command received by the processes of S1101 to S1106 is determined. If the received command is an effect permission command (S1101: Yes), the effect permission flag 233a of the work RAM 233 is turned on (S1108), and the external interrupt process is terminated. If the received command is a variation pattern command (S1101: No, S1102: Yes), the variation start flag 233b of the work RAM 233 is turned on (S1109), and the external interrupt process is terminated.

  Next, if the received command is an inner frame release command (S1101: No, S1102: No, S1103: Yes), the display inner frame release command reception flag 233c of the work RAM 233 has been received. Is turned on (S1110), and the display of “the inner frame is open” is started on the third symbol display device 81 (S1111). Thereafter, the external interrupt process is terminated. By starting the display on the third symbol display device 81, it is possible to notify an unspecified number of people that the inner frame 12 is being opened. It should be noted that the characters “inner frame is open” displayed on the third symbol display device 81 are superimposed on the effect display displayed on the third symbol display device 81. Further, the characters “inner frame is open” indicate that the inner frame 12 is closed, that is, the inner frame 12 is closed and the display inner frame release command reception flag 233c is turned off. This is continuously displayed on the third symbol display device 81 until the process of S1115 is performed.

  Next, if the received command is a front frame release command (S1101: No, S1102: No, S1103: No, S1104: Yes), the display front frame release command reception flag 233d of the work RAM 233 is set to the front frame release command. When it is turned on to indicate that it has been received (S1112), the display of “the front frame is open” is started on the third symbol display device 81 (S1113). Thereafter, the external interrupt process is terminated. By starting display on the third symbol display device 81, it is possible to notify an unspecified number of people that the front frame 14 is open. The characters “front frame is open” displayed on the third symbol display device 81 are displayed superimposed on the effect display displayed on the third symbol display device 81. The character “front frame is open” indicates that the front frame 14 is closed, that is, the front frame 14 is closed and the display front frame open command reception flag 233d is turned off. It is continuously displayed on the third symbol display device 81 until the processing of S1117 is performed.

  Next, if the received command is an inner frame closing command (S1101: No, S1102: No, S1103: No, S1104: No, S1105: Yes), the display inner frame release command reception flag 233c of the work RAM 233 is set. The display indicating that the inner frame closing command has been received is turned off (S1114), and the display of “the inner frame is open” on the third symbol display device 81 is deleted (S1115). Thereafter, the external interrupt process is terminated.

  Next, if the received command is a front frame closing command (S1101: No, S1102: No, S1103: No, S1104: No, S1105: No, S1106: Yes), a display front frame opening command reception of the work RAM 233 is received. The flag 233d is turned off to indicate that the front frame closing command has been received (S1116), and the display of “front frame is open” on the third symbol display device 81 is deleted (S1117). Thereafter, the external interrupt process is terminated.

  Finally, if the received command is not any of the effect permission command, the variation pattern command, the inner frame opening command, the front frame opening command, the inner frame closing command or the front frame closing command (S1101: No, S1102: No, S1103: No, S1104: No, S1105: No, S1106: No), processing corresponding to the other received command is executed (S1107), and the external interrupt processing is terminated. For example, if the received command is a stop command, a process for stopping the fluctuation performed in the third symbol display device 81 is executed.

  As described above, when receiving the inner frame release command, the display control device 114 turns on the display inner frame release command reception flag 233c of the work RAM 233 to indicate that the inner frame release command has been received (S1110). The display of “the inner frame is open” is started on the three symbol display device 81 (S1111). By starting the display on the third symbol display device 81, it is possible to notify an unspecified number of people that the inner frame 12 is being opened. Similarly, when receiving the front frame release command, the display control device 114 turns on the display front frame release command reception flag 233d of the work RAM 233 to indicate that the front frame release command has been received (S1112), The display of “the front frame is open” is started on the symbol display device 81 (S1113). By starting display on the third symbol display device 81, it is possible to notify an unspecified number of people that the front frame 14 is open.

  When the display control device 114 receives the inner frame closing command when the display of “the inner frame is open” is started on the third symbol display device 81, the display inner frame opening command of the work RAM 233 is displayed. The reception flag 233c is turned off to indicate that the inner frame closing command has been received (S1114), and the display of “the inner frame is open” on the third symbol display device 81 is deleted (S1115). Similarly, when the display control device 114 receives a front frame closing command when the display of “front frame is open” is started on the third symbol display device 81, the display front frame for display of the work RAM 233 is released. The command reception flag 233d is turned off to indicate that the front frame closing command has been received (S1116), and the “front frame is open” display on the third symbol display device 81 is deleted (S1117).

  Next, with reference to FIG. 32, main processing executed by the display control device 114 will be described. FIG. 32 is a flowchart showing a main process executed by the MPU 231 in the display control apparatus 114, and this main process is started when the power is turned on. First, initial setting processing accompanying power-on is executed (S1001). Specifically, processing for initializing the MPU 231 and clearing the storage of the work RAM 233 and the video RAM 234 is performed. Thereafter, the compressed character information stored in the character ROM 235 is read (S1002), the read character information is decompressed, and the decompressed character information is stored in the video RAM 234 (S1003). Further, in order to display the initial screen, information corresponding to the initial screen is extracted from the character information written in the video RAM 234, and the video RAM 234 is different from the area in the video RAM 234 that stores the character information decompressed in the processing of S1003. The extracted character information is written in the area (S1004).

  Next, it is determined whether or not the effect permission flag 233a is turned on in order to determine whether or not the effect permission command transmitted from the main controller 110 has been received (S1005), and if the effect permission flag 233a is not turned on. (S1005: No), until the production permission command is transmitted from the main control device 110, that is, until the production permission flag 233a is turned on, the processing after S1006 is waited.

  If the result permission flag 233a is turned on as a result of the determination in S1005 (S1005: Yes), the character information extracted in the process of S1004 is displayed on the third symbol display device 81. And it transfers to the process after S1006.

  In the processing of S1006, it is determined whether or not the display executed on the third symbol display device 81 is a big hit (S1006). If it is not a big hit (S1006: No), the third symbol display device 81 It is determined whether or not the variation start flag 233b for permitting the start of variation display is turned on (S1007). As a result, if the variation start flag 233b is turned on (S1007: Yes), the variation start flag 233b is turned off (S1008), and the variation corresponding to the variation pattern command is started on the display screen of the third symbol display device 81. (S1009). Here, in the process of S1008, the fluctuation start flag 233b is turned off. In the pachinko machine 500 of this embodiment, when the fluctuation start flag 233b is turned on, fluctuation display is started on the third symbol display device 81. (S1007: Yes to S1009), unless the fluctuation start flag 233b is turned off, the fluctuation start process (S1009) is repeatedly executed, and normal processing is not executed.

  On the other hand, if the variation start flag 233b is OFF as a result of the determination in the processing of S1007 (S1007: No), or when variation starts in the processing of S1009, the variation effect processing is performed (S1010). In the variation effect process, when the variable display is continuously performed, the character information and the effect pattern information are updated and set (new extraction of the character information from the video RAM 234 and the extracted character information to the video RAM 234). When the variable display is not performed, the process proceeds to S1011 without performing any particular process. Here, in the process of S1011, in order to execute the process (S1006 to S1010) for performing the effect in the third symbol display device 81 every 20 milliseconds, whether or not 20 milliseconds or more have elapsed since the process of S1006 was started. (S1011), if not, it waits until 20 milliseconds or more have passed (S1011: No), and if 20 milliseconds or more have passed (S1011: Yes), the process proceeds to the process of S1006 To do.

  Further, if the result of the processing in S1006 is a big hit (S1006: Yes), the big hit effect processing is executed (S1012). In the jackpot effect process, the number of rounds, the number of prize balls are updated, images of backgrounds that are different for each round, etc. (new extraction of character information from the video RAM 234 and video RAM 234 of extracted character information) Write). After the big hit effect process (S1012) ends, the process shifts to the process of S1011.

  As described above, according to the pachinko machine 500 of the fourth embodiment, the inner frame input / output port output circuit 290b of the inner frame open frame detection circuit 290 is supplied with power to the pachinko machine 500, When a DC voltage of 12 volts is supplied from the DC power source DC1, when the switch SW3-2 is turned on and the opening of the inner frame 12 is detected, a signal of a DC voltage of 5 volts is output to the input / output port 205. When this signal is input to the input / output port 205, the pachinko machine 500 transmits an inner frame release command to the audio lamp control device 113, and uses the audio output device 226 and the lamp display device 227 to Announce the opening. The pachinko machine 500 transmits an inner frame release command to the display control device 114 via the sound lamp control device 113 and displays a message indicating the release of the inner frame 12 on the third symbol display device 81. Therefore, it is possible to clearly notify an unspecified number of persons that the inner frame 12 is being opened.

  Similarly, according to the pachinko machine 500 of the fourth embodiment, the front frame input / output port output circuit 292b of the front frame open frame detection circuit 292 is supplied with power to the pachinko machine 500 from the DC power source DC1. When a DC voltage of 12 volts is supplied, when the switch SW4-2 is turned on and the opening of the front frame 14 is detected, a signal of a DC voltage of 5 volts is output to the input / output port 205. When this signal is input to the input / output port 205, the pachinko machine 500 transmits a front frame opening command to the audio lamp control device 113, and uses the audio output device 226 and the lamp display device 227 to display the front frame 14. Announce the opening. The pachinko machine 500 transmits a front frame opening command to the display control device 114 via the sound lamp control device 113 and displays a message indicating the opening of the front frame 14 on the third symbol display device 81. Therefore, it is possible to clearly notify an unspecified number of persons that the front frame 14 is being opened.

  On the other hand, according to the pachinko machine 500 of the fourth embodiment, the inner frame terminal board output circuit 290a of the inner frame open frame detection circuit 290 is added to the case where a DC voltage of 12 volts is supplied from the DC power source DC1. For example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine 500 is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1 (the main controller 110 is stopped). If the switch SW3-1 is turned on and the opening of the inner frame 12 is detected, a pulse signal having a pulse width of 10 milliseconds is output from the inner frame external output terminal plate 291 to the hall computer 262. . The pulse signal output from the inner frame external output terminal plate 291 is stored in the hall computer 262. Therefore, by analyzing the pulse signal stored in the hall computer 262, for example, even when the business hours of the game hall are over and the power supply to the pachinko machine 500 is shut off, Opening can be detected.

  Similarly, according to the pachinko machine 500 of the fourth embodiment, the front frame terminal board output circuit 292a of the front frame open frame detection circuit 292 is supplied when a DC voltage of 12 volts is supplied from the DC power source DC1. In addition, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine 500 is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1 (the main controller 110 is stopped) When the switch SW4-1 is turned on and the opening of the front frame 14 is detected, a pulse signal having a pulse width of 10 milliseconds is output from the front frame external output terminal plate 293 to the hall computer 262. To do. The pulse signal output from the front frame external output terminal plate 293 is stored in the hall computer 262. Therefore, by analyzing the pulse signal stored in the hall computer 262, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine 500 is cut off, Opening can be detected.

  As described above, when the inner frame 12 is opened when power is supplied to the pachinko machine 500, the function of outputting a pulse signal to the hall computer 262 and the power supply to the pachinko machine 500 are cut off. When the inner frame 12 is opened, the function of outputting a pulse signal to the hall computer 262 can be exhibited by the inner frame terminal board output circuit 290a which is one circuit.

  In addition, when the front frame 14 is opened when power is supplied to the pachinko machine 500, the function of outputting a pulse signal to the hall computer 262 and the power supply to the pachinko machine 500 are cut off. Sometimes, when the front frame 14 is opened, the function of outputting a pulse signal to the hall computer 262 can be exhibited by the front frame terminal board output circuit 292a which is one circuit.

  The hall computer 262 continues to operate for 24 hours. Therefore, the inner frame terminal plate output circuit 290a determines that the pulse signal is output from the inner frame external output terminal plate 291 and the time when the pulse signal is output, that is, the opening time of the inner frame 12 is also the hall computer. 262 can be stored. Similarly, the front frame terminal board output circuit 292a is configured so that the pulse signal is output from the front frame external output terminal board 293, and the time at which the pulse signal is output, that is, the opening time of the front frame 14 is also a hall. It can be stored in the computer 262.

  In the fourth embodiment, the pachinko machine 500 separately notifies the opening of the inner frame 12 and the opening of the front frame 14 using the audio output device 226 and the lamp display device 227. Further, the pachinko machine 500 uses the third symbol display device 81 to separately display the opening of the inner frame 12 and the opening of the front frame 14. However, the present invention is not limited to this, and the opening of the inner frame 12 and the opening of the front frame 14 may be performed in the same notification mode and display mode. Specifically, the notification performed using the audio output device 226 and the lamp display device 227 may be the same when the inner frame 12 is opened and when the front frame 14 is opened. Similarly, the display performed using the third symbol display device 81 may be the same when the inner frame 12 is opened and when the front frame 14 is opened. In this case, when either one of the inner frame 12 and the front frame 14 is opened, or when both are opened, the third symbol display device 81 may display “the door is open”.

  In the fourth embodiment, the pachinko machine 500 performs notification using the audio output device 226 and the lamp display device 227 when the inner frame 12 is opened or the front frame 14 is opened. Display was performed using the symbol display device 81. However, the present invention is not limited to this, and either one of notification using the audio output device 226 and the lamp display device 227 or display using the third symbol display device 81 may be performed.

  Next, a pachinko machine 600 according to a fifth embodiment will be described with reference to FIGS. The pachinko machine 600 according to the fifth embodiment includes three switches SW3-1, SW3-2, and SW3-3 that are connected to the inner frame open frame detection circuit 290 of the pachinko machine 500 according to the fourth embodiment. The switch SW3A is changed to a switch SW3A having a built-in switch, and the switch SW4 connected to the front frame opening detection circuit 292 of the pachinko machine 500 according to the fourth embodiment is replaced with the switches SW4-1, SW4-2, and SW4-3. After changing to the switch SW4A having two built-in switches, the Zener diode D3 used for the inner frame opening detection circuit 290 and the front frame opening detection circuit 292 of the pachinko machine 500 of the fourth embodiment is removed. (Without removing the Zener diode D3, the inner frame opening detection circuit 290 and the front frame opening detection It may be connected in the same manner as the circuit 292). In the future, what has been changed to the inner frame opening detection circuit 290 of the pachinko machine 500 of the fourth embodiment will be referred to as an inner frame opening detection circuit 300 in the pachinko machine 600 of the fifth embodiment, In the pachinko machine 600 according to the fifth embodiment, a front frame frame opening detection circuit 302 is obtained by changing the front frame opening detection circuit 292 of the pachinko machine 500 according to the fourth embodiment. Therefore, the inner frame terminal board output circuit 290a of the pachinko machine 500 of the fourth embodiment is changed to the inner frame terminal board output circuit 300a of the pachinko machine 600 of the fifth embodiment. In the pachinko machine 600 of the fifth embodiment, the inner frame input / output port output circuit 290b of the pachinko machine 500 of the embodiment is changed to the inner frame input / output port output circuit 300b. Likewise, the front frame terminal board output circuit 292a of the pachinko machine 500 according to the fourth embodiment is changed to the front frame terminal board output circuit 302a in the pachinko machine 600 according to the fifth embodiment. In the pachinko machine 600 according to the fifth embodiment, the front frame input / output port output circuit 292b of the pachinko machine 500 according to the fourth embodiment is changed to the front frame input / output port output circuit 302b.

  According to the pachinko machine 600 of the fifth embodiment, when the inner frame 12 is opened, it is stored in the capacitor CD7 of the integrating circuit 281 of the inner frame frame open detection circuit 300 (inner frame terminal board output circuit 300a). When the inner frame 12 is closed, the generated charge is instantaneously discharged to the ground via the switch SW3-3 connected to the inner frame frame open detection circuit 300 (inner frame terminal board output circuit 300a). can do. Similarly, when the front frame 14 is opened, the charge stored in the capacitor CD7 of the integrating circuit 281 of the front frame open detection circuit 302 (front frame terminal board output circuit 302a) is closed. In this case, it is possible to instantaneously discharge to the ground via the switch SW4-3 connected to the front frame open frame detection circuit 302 (front frame terminal board output circuit 302a).

  Thus, the charge stored in the capacitor CD7 of the integration circuit 281 is always zero before the inner frame 12 or the front frame 14 is again opened, so that the inner frame 12 or the front frame 14 is Even if the circuit is opened a plurality of times in a short time, the integration circuit 281 operates normally, and the voltage applied to the TRG terminal of the timer IC 1 regardless of the open period of the inner frame 12 or the front frame 14. The falling period can be a certain period (about 2 milliseconds).

  Further, according to the pachinko machine 600 of the fifth embodiment, as described above, the charge stored in the capacitor CD7 of the integrating circuit 281 of the inner frame open-circuit detection circuit 300 (inner frame terminal board output circuit 300a) When the inner frame 12 is closed, it is discharged to the ground via the switch SW3-3 and stored in the capacitor CD7 of the integrating circuit 281 of the front frame open frame detection circuit 302 (front frame terminal plate output circuit 302a). The electric charge is discharged to the ground via the switch SW4-3 when the front frame 14 is closed. Therefore, unlike the pachinko machine 500 according to the fourth embodiment, when the inner frame 12 or the front frame 14 is opened again and the switch SW3-1 or the switch SW4-1 is turned on, the electric charge stored in the capacitor CD7 is reduced. An overvoltage (for example, a voltage of 12.3 volts) that is superimposed on the voltage supplied from the capacitor CD1 and destroys the timer IC1 is not applied to the TRG terminal of the timer IC1. Accordingly, it is possible to eliminate the need for the Zener diode D3 that prevents the application of an overvoltage large enough to destroy the timer IC1.

  Also, according to the pachinko machine 600 of the fifth embodiment, as with the pachinko machine 500 of the fourth embodiment, when a DC voltage of 12 volts is supplied from the DC power supply DC1, the inner frame 12 and the front frame 14 Is released separately using the pachinko machine 600, whether the inner frame 12 has been opened, the front frame 14 has been opened, or both have been opened. be able to. Furthermore, according to the pachinko machine 600 of the fifth embodiment, in the same manner as the pachinko machine 500 of the fourth embodiment, in addition to the case where a DC voltage of 12 volts is supplied from the DC power supply DC1, 12 volts from the DC power supply DC1. Even when the DC voltage is not supplied, if either the inner frame 12 or the front frame 14 is opened, pulse signals can be separately output to the hall computer 262. Therefore, it is possible to identify whether the inner frame 12 has been opened, the front frame 14 has been opened, or both have been opened by the pulse signal stored in the hall computer 262.

  In the description of the pachinko machine 600 according to the fifth embodiment, the same parts as those of the pachinko machine 500 according to the fourth embodiment are denoted by the same reference numerals, and the description thereof is omitted. Only different parts will be described.

  The structure of the switch SW3A connected to the inner frame frame opening detection circuit 300 and the switch SW4A connected to the front frame frame opening detection circuit 302 will be described with reference to FIG. The switch SW3A is obtained by adding the switch SW3-3 to the switch SW3 incorporating the switches SW3-1 and SW3-2, and the other structure is the same as the switch SW3. Similarly, the switch SW4A is obtained by adding the switch SW4-3 to the switch SW4 incorporating the switches SW4-1 and SW4-2, and the other structure is the same as the switch SW4. Therefore, in the switch SW3A and the switch SW4A, the same parts as those of the switches SW3 and SW4 are denoted by the same reference numerals, description thereof is omitted, and only different parts are described. Since the switch SW3A and the switch SW4A have the same structure, the structure of the switch SW3A will be described, and the description of the switch SW4A will be omitted.

  FIG. 34 is a cross-sectional view of the switch SW3A. FIG. 34A is a cross-sectional view showing a state (cut-off state) of the switch SW3A in a state where the inner frame 12 is closed. FIG. 34B is a cross-sectional view showing the state of the switch SW3A when the inner frame 12 is in the middle of opening or closing. Further, FIG. 34C is a cross-sectional view showing a state (conductive state) of the switch SW3A in a state where the inner frame 12 is opened.

  As shown in FIG. 34 (a), the switch SW3A connected to the inner frame open frame detection circuit 300 is provided with a switch SW3-1 that performs the reverse operation of the switch SW3-1 and the switch SW3-2. Yes. The switch SW3-3 is a conductor plate SW3-3a made of a metal that is a conductive member disposed on the movable shaft SW3a that contacts the closed state of the inner frame 12, and the conductor plate SW3-3a is opposed to the conductor plate SW3-3a. A pair of terminal plates SW3-3b made of metal disposed at a position, a support plate SW3-3c for arranging the pair of terminal plates SW3-3b in the housing SW3b, and a conductor plate SW3-3a A pair of springs SW3ca is provided on a surface facing the pair of terminal plates SW3-3b, and generates a biasing force in a direction opposite to the pair of terminal plates SW3-3b with respect to the conductor plate SW3-3a. ing. As described above, the switch SW3 includes three switches, ie, the switch SW3-1, the switch SW3-2, and the switch SW3-3.

  As shown in FIG. 34A, in a state where the inner frame 12 is closed, the movable shaft SW3a abuts on the inner frame 12, and the movable shaft SW3a is pushed into the housing SW3b. Therefore, the contact between the conductor plate SW3-1a and the pair of terminal plates SW3-1b is prevented, and the contact between the conductor plate SW3-2a and the pair of terminal plates SW3-2b is prevented. On the other hand, the conductor plate SW3-3a and the pair of terminal plates SW3-3b are in contact with each other. Therefore, when the inner frame 12 is closed, both the switch SW3-1 and the switch SW3-2 are cut off, while the switch SW3-3 is turned on.

  Next, as shown in FIG. 34 (b), when the inner frame 12 is in the middle of opening or closing, the contact of the movable shaft SW3a with the inner frame 12 is released, so that the pair of springs SW3ca is attached. Due to the force, the contact between the conductor plate SW3-1a and the pair of terminal plates SW3-1b, the contact between the conductor plate SW3-2a and the pair of terminal plates SW3-2b, and the conductor plate SW3-3a and the pair of terminal plates SW3-3b. Any contact with is prevented. Therefore, when the inner frame 12 is in the middle of opening or closing, the switch SW3-1, the switch SW3-2, and the switch SW3-3 are all disconnected.

  Further, as shown in FIG. 34 (c), when the inner frame 12 is opened, the conductor plate SW3-1a and the pair of terminal plates SW3-1b come into contact with each other by the biasing force of the pair of springs SW3ca. The conductor plate SW3-2a and the pair of terminal plates SW3-2b are in contact with each other. On the other hand, the contact between the conductor plate SW3-3a and the pair of terminal plates SW3-3b is hindered. Therefore, when the inner frame 12 is opened, both the switch SW3-1 and the switch SW3-2 are in a conductive state, while the switch SW3-3 is in a disconnected state.

  As described above, the switch SW3-1 and the switch SW3-2 built in the housing SW3b are both in a cut-off state when the inner frame 12 is closed, and are in a conductive state when the inner frame 12 is opened. It becomes. On the other hand, the switch SW3-3 built in the housing SW3b operates in the reverse manner to the switch SW3-1 and the switch SW3-2, and becomes conductive when the inner frame 12 is closed. In a state where 12 is opened, a cut-off state is established. That is, the switch SW3-1 and the switch SW3-2 have a structure in which the conduction state and the cutoff state operate in conjunction with each other, and the switch SW3-3 is in a state opposite to the state of the switch SW3-1 and the switch SW3-2. It has a structure that performs the following operations. However, the structure of the switch SW3A is not limited to the shape shown in FIG. 34. When the inner frame 12 is closed, the switch SW3-1 and the switch SW3-2 are cut off, and the switch SW3-3 is turned on. On the other hand, when the inner frame 12 is open, the switch SW3-1 and the switch SW3-2 are in a conductive state and the switch SW3-3 is in a cut-off state. The same applies to the structure of the switch SW4A.

  Next, with reference to FIG. 35, the inner frame open frame detection circuit 300 and the inner frame external output terminal plate 291 used in the pachinko machine 600 of the fifth embodiment will be described. FIG. 35 is a block diagram showing the electrical configuration of the inner frame open frame detection circuit 300 and the inner frame external output terminal plate 291. In addition, the inner frame open frame detection circuit 300 of the pachinko machine 600 according to the fifth embodiment replaces the switch SW3 connected to the inner frame open frame detection circuit 290 of the pachinko machine 500 according to the fourth embodiment with the switch SW3-1. , SW3-2 and SW3-3 are changed to a switch SW3A having a built-in switch, and the Zener diode D3 used in the inner frame open frame detection circuit 290 of the pachinko machine 500 of the fourth embodiment is removed. Is. The inner frame opening detection circuit 300 has the same configuration as the inner frame opening detection circuit 290 described above with reference to FIG. Also, the inner frame external output terminal plate 291 of the pachinko machine 600 of the fifth embodiment has the same structure as the inner frame external output terminal plate 291 of the pachinko machine 500 of the fourth embodiment. Therefore, the inner frame opening detection circuit 300 and the inner frame external output terminal plate 291 are not included in the same parts as the inner frame opening detection circuit 290 and the inner frame external output terminal plate 291 described above with reference to FIG. The same number is attached | subjected and the description is abbreviate | omitted and only a different part is demonstrated.

  Further, the front frame open frame detection circuit 302 used in the pachinko machine 600 of the fifth embodiment is different from the inner frame open frame detection circuit 300 used in the pachinko machine 600 of the fifth embodiment. The switch to be used is only changed from the switch SW3A to the switch SW4A, and the other configuration is the same as that of the inner frame opening detection circuit 300. Further, the front frame external output terminal plate 293 used in the pachinko machine 600 of the fifth embodiment has the same configuration as the internal frame external output terminal plate 291 used in the pachinko machine 600 of the fifth embodiment. That is, it has the same structure as the external output terminal plate 291 for the inner frame of the pachinko machine 500 of the fourth embodiment described above with reference to FIG. Therefore, the description of the front frame open frame detection circuit 302 and the front frame external output terminal plate 293 is omitted.

  As shown in FIG. 35, the switch SW3-3 provided in the switch SW3A (see FIG. 34) has one end of the switch SW3-3 (one end of the terminal board 3-3b) connected to the other end of the switch SW3-1 ( The other end of the switch SW3-3 (the other end of the terminal plate 3-3b) is grounded while being connected to the other end of the terminal plate 3-2b) and one end of the capacitor CD7. As described above, the inner frame terminal board output circuit 300a of the pachinko machine 600 according to the fifth embodiment is obtained by adding the switch SW3-3 to the inner frame terminal board output circuit 290a of the pachinko machine 500 according to the fourth embodiment. Become. The inner-frame input / output port output circuit 300b of the pachinko machine 600 according to the fifth embodiment has the same configuration as the inner-frame input / output port output circuit 290b of the pachinko machine 500 according to the fourth embodiment.

  As described above, the switch SW3-3 used in the inner frame terminal board output circuit 300a performs an operation that is in a state opposite to the state of the switch SW3-1 and the switch SW3-2. Therefore, in a state in which the inner frame 12 is closed, the switch SW3-3 is turned on and one end of the capacitor CD7 is grounded, while the switch SW3-1 and the switch SW3-2 are cut off. Become.

  When the inner frame 12 changes from the closed state to the open state, the switch SW3-3 is first cut off and then the switch SW3-1 and the switch SW3-2 are turned on due to the structure of the switch SW3A (FIG. 34 (a) → FIG. 34 (b) → see FIG. 34 (c)). Thus, when the inner frame 12 changes from the closed state to the opened state, first, one end of the capacitor CD7 is disconnected from the ground by the switch SW3-3, and then the power from the capacitor CD1 is switched to the switch SW3-1. To the capacitor CD7. Therefore, when the inner frame 12 changes from the closed state to the open state, the capacitor CD1 that supplies power is not short-circuited to the ground. Therefore, when the inner frame 12 changes from the closed state to the opened state, the power from the capacitor CD1 flows into the ground, and the inner frame frame open detection circuit 300 (the inner frame terminal board output circuit 300a) is short-circuited. Absent. When the inner frame 12 is opened, the switch SW3-1 is turned on, and the power of the capacitor CD1 is supplied to the capacitor CD7, the charge is stored in the capacitor CD7 as described above, and the increase of the stored charge is increased. As a result, the voltage generated in the capacitor CD7 increases. The falling period of the voltage applied to the TRG terminal of the timer IC1 can be set to a certain period (about 2 milliseconds) due to the change in the voltage generated in the capacitor CD7. In this way, the falling period of the voltage applied to the TRG terminal of the timer IC 1 is adjusted by the integrating circuit 281, that is, adjusted by the capacitor CD 7 and the resistor R 10, so that a simple circuit can be used without using a complicated circuit. The falling period of the voltage applied to the TRG terminal of the timer IC 1 can be set to a fixed period at a low cost with a configuration.

  Next, when the inner frame 12 changes from the opened state to the closed state, the switch SW3-1 and the switch SW3-2 are first cut off and then the switch SW3-3 is turned on due to the structure of the switch SW3A ( FIG. 34 (c) → FIG. 34 (b) → see FIG. 34 (a)). As described above, when the inner frame 12 changes from the open state to the closed state, the power supplied from the capacitor CD1 to the capacitor CD7 is first stopped by the switch SW3-1, and then one end of the capacitor CD7 is connected. Grounded through the switch SW3-3. Therefore, when the inner frame 12 changes from the open state to the closed state, the capacitor CD1 that supplies power is not short-circuited to the ground. Therefore, when the inner frame 12 changes from the open state to the closed state, the power from the capacitor CD1 does not flow into the ground, and the inner frame frame open detection circuit 300 is not short-circuit broken.

  When the inner frame 12 is closed and the switch SW3-1 is cut off and the power supplied from the capacitor CD1 to the capacitor CD7 is stopped, one end of the capacitor CD7 is grounded by the switch SW3-3. Can do. Therefore, when the inner frame 12 is closed, the charge stored in the capacitor CD7 when the inner frame 12 is opened can be instantaneously discharged through the switch SW3-3 to zero. . Accordingly, since the charge stored in the capacitor CD7 is always zero before the inner frame 12 is opened again, even if the inner frame 12 is opened several times in a short time. Thus, the integration circuit 281 operates normally, and the falling period of the voltage applied to the TRG terminal of the timer IC 1 can be set to a fixed period (about 2 milliseconds) regardless of the opening period of the inner frame 12.

  Further, as described above, when the inner frame 12 is in the closed state, the inner frame opening detection circuit 300 (inner frame terminal board output circuit 300a) stores in the capacitor CD7 when the inner frame 12 is in the opened state. The generated charge can be instantaneously discharged to the ground via the switch SW3-3. Therefore, when the inner frame 12 is opened and the switch SW3-1 is turned on, the charge stored in the capacitor CD7 is superimposed on the voltage supplied from the capacitor CD1, and an overvoltage (a voltage that destroys the timer IC1) For example, a voltage of 12.3 volts) is not applied to the TRG terminal of the timer IC1. Accordingly, it is possible to eliminate the need for a Zener diode that prevents the application of an overvoltage large enough to destroy the timer IC1.

  Further, as described above, the inner frame open frame detection circuit 300 changes the switch SW3 connected to the inner frame open frame detection circuit 290 of the pachinko machine 500 of the fourth embodiment to the switch SW3A, and performs the fourth embodiment. The zener diode D3 used in the inner frame frame opening detection circuit 290 of the pachinko machine 500 is removed, and the configuration is the same as that of the inner frame frame opening detection circuit 290 except for the above changes. Also, the inner frame external output terminal plate 291 of the pachinko machine 600 of the fifth embodiment has the same structure as the inner frame external output terminal plate 291 of the pachinko machine 500 of the fourth embodiment.

  Therefore, similarly to the pachinko machine 500 of the fourth embodiment, when the power is supplied to the pachinko machine 600 and a DC voltage of 12 volts is supplied from the DC power supply DC1, the inner frame 12 is opened, When the switch SW3-2 provided in the inner frame input / output port output circuit 300b is turned on, a signal of 5 volts is output from the inner frame input / output port output circuit 300b to the input / output port 205. When a signal of 5 volts is input to the input / output port 205, the pachinko machine 600 notifies the opening of the inner frame 12 using the audio output device 226 and the lamp display device 227. In addition, the pachinko machine 600 displays a message indicating the opening of the inner frame 12 on the third symbol display device 81. Further, when the inner frame 12 is opened and the switch SW3-1 provided in the inner frame terminal board output circuit 300a is turned on, the inner frame terminal board output circuit 300a opens from the inner frame external output terminal board 291 to the hall. A pulse signal having a pulse width of 10 milliseconds is output to the computer 262.

  On the other hand, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 600 is cut off, a DC voltage of 12 volts is not supplied from the DC power supply DC1, so the inner frame 12 is opened. Even if the switch SW3-2 provided in the inner frame input / output port output circuit 300b is turned on, no signal is input from the inner frame input / output port output circuit 300b to the input / output port 205 (inner frame input / output). The DC voltage input from the port output circuit 300b to the input / output port 205 becomes zero volts). However, for example, even when the business hours of the amusement hall are over and the power supply to the pachinko machine 600 is cut off, the inner frame terminal board output circuit 300a is supplied with power from the capacitor CD1. Therefore, when the inner frame 12 is opened and the switch SW3-1 provided in the inner frame terminal plate output circuit 300a is turned on, the inner frame terminal plate output circuit 300a is connected to the inner frame external output terminal plate 291. A pulse signal having a pulse width of 10 milliseconds is output to the hall computer 262.

  The pulse signal output from the inner frame external output terminal plate 291 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 is opened can be specified by the pulse signal stored in the hall computer 262. Furthermore, the pulse signal is output from the external output terminal board 291 for the inner frame to the hall computer 262, and the output time of the output pulse signal is stored, so that the specified inner frame 12 of the pachinko machine is opened. The time can be detected.

  As described above, when the inner frame 12 is opened when power is supplied to the pachinko machine 600, a function of outputting a signal to the input / output port 205 and a function of outputting a pulse signal to the hall computer 262, In addition, when the inner frame 12 is opened when the power supply to the pachinko machine 600 is cut off, the function of outputting a pulse signal to the hall computer 262 has the function of detecting the inner frame frame opening detection circuit 300 as one circuit. Can demonstrate.

  One end of the switch SW3-2 of the inner frame input / output port output circuit 300b is connected to the DC power supply DC1 and the anode terminal of the diode D1. Therefore, when the inner frame 12 is opened when the power of the pachinko machine 600 is turned on, the switch SW3-2 becomes conductive, and power is supplied from the DC power source DC1 to the inner frame input / output port output circuit 300b. Thus, the inner frame input / output port output circuit 300b is in an operating state. On the other hand, when the power of the pachinko machine 600 is turned off, no power is supplied from the DC power source DC1 to the inner frame input / output port output circuit 300b, so the inner frame 12 is opened and the switch SW3-2 is opened. Even so, the inner frame input / output port output circuit 300b is stopped.

  On the other hand, one end of the switch SW3-1 of the inner frame terminal board output circuit 300a is connected to one end of the capacitor CD1 via the diode D2 and the resistor R10. Therefore, when the inner frame 12 is opened while the power of the pachinko machine 600 is turned on, the switch SW3-1 becomes conductive, and power is supplied from the DC power source DC1 to the inner frame terminal board output circuit 300a. The inner frame terminal board output circuit 300a is in an operating state. On the other hand, when the power of the pachinko machine 600 is turned off, the power supply from the DC power source DC1 to the inner frame terminal board output circuit 300a is stopped, but the inner frame 12 is opened and the switch SW3-1 is turned on. Then, since electric power is supplied from the capacitor CD1 to the inner frame terminal board output circuit 300a, the inner frame terminal board output circuit 300a enters an operating state. Here, when the power of the pachinko machine 600 is turned off and power is supplied from the capacitor CD1 to the inner frame terminal board output circuit 300a, power supply to the inner frame input / output port output circuit 300b is performed. It can be blocked by a diode D1 that exhibits a backflow prevention function. Therefore, when the power of the pachinko machine 600 is turned off, the number of times that the inner frame terminal board output circuit 300a can be operated can be increased, and the number of times that the inner frame 12 can be detected can be increased.

  The timer IC1 of the inner frame terminal board output circuit 300a is activated when the inner frame 12 is opened, the switch SW3-1 is turned on, and the voltage applied to the TRG terminal of the timer IC1 falls to zero volts. It functions as a monostable multivibrator that raises the voltage at the OUT terminal of the timer IC1 from zero volts to about 9.6 volts for about 10 milliseconds after falling. By providing the integration circuit 281 in front of the TRG terminal of the timer IC1, when the inner frame 12 is opened, the voltage applied to the TRG terminal of the timer IC1 can be increased regardless of the opening period of the inner frame 12. The period from falling to zero volts until returning to about 10.3 volts can be adjusted to be shorter than the period in which the voltage at the OUT terminal of the timer IC 1 rises from zero volts to about 9.6 volts. In this way, the integration circuit 281 makes the timer functioning as a monostable multivibrator by setting the falling period of the TRG terminal voltage of the timer IC 1 to a fixed period (about 2 milliseconds) regardless of the opening period of the inner frame 12. It is possible to keep IC1 operating normally and to keep the voltage at the OUT terminal of timer IC1 rising from zero volts to about 9.6 volts to about 10 milliseconds. As a result, the period during which current is supplied from the capacitor CD1 to the photocoupler PR1 can be kept at about 10 milliseconds, and the output period of the pulse signal output from the inner frame external output terminal plate 291 to the hall computer 262 is about 10 m. You can stay in seconds.

  Next, referring to FIG. 36, the voltage (charge stored in capacitor CD7) applied to capacitor CD7, which changes according to the open / closed state of inner frame 12, regardless of the on / off state of power of pachinko machine 600, is shown. , The TRG terminal voltage of the timer IC1 of the inner frame terminal board output circuit 300a, the OUT terminal voltage of the timer IC1 of the inner frame terminal board output circuit 300a, and the output of the inner frame external output terminal board 291 (of the hall computer 262). The relationship between the input) and the output of the inner frame input / output port output circuit 300b that changes according to the open / closed state of the inner frame 12 when the power of the pachinko machine 600 is turned on will be described. FIG. 36 shows an on / off state of the power supply of the pachinko machine 600 (a state of a direct current voltage supplied by the direct current power source DC1), an open state of the inner frame 12, a conduction state of the switch SW3-3, a switch SW3-1, The conduction cut-off state of the switch SW3-2, the voltage applied to the capacitor CD7 (charge stored in the capacitor CD7), the TRG terminal voltage of the timer IC1 of the inner frame terminal plate output circuit 300a, and the inner frame terminal plate output 5 is a timing chart showing the relationship among the OUT terminal voltage of the timer IC1 of the circuit 300a, the output of the inner frame external output terminal plate 291 (input of the hall computer 262), and the output of the inner frame input / output port output circuit 300b. is there.

  As described above, the front frame terminal board output circuit 302a provided in the front frame frame open detection circuit 302 is different from the inner frame terminal board output circuit 300a in that the switch to be connected is the switch SW4-1. It is only a place where it is a switch SW3-1 and a switch SW4-3 or a switch SW3-3. Accordingly, the operation of the front frame terminal board output circuit 302a is the same as the operation of the inner frame terminal board output circuit 300a, and therefore the description of the operation of the front frame terminal board output circuit 302a is omitted. Also, the front frame input / output port output circuit 302b differs from the inner frame input / output port output circuit 300b only in whether the connected switch is the switch SW4-2 or the switch SW3-2. is there. Therefore, since the operation of the front frame input / output port output circuit 302b is the same as the operation of the inner frame input / output port output circuit 300b, the description of the operation of the front frame input / output port output circuit 302b is omitted. . Furthermore, since the front frame external output terminal plate 293 has the same configuration as the inner frame external output terminal plate 291 as described above with reference to FIG. 35, the operation of the front frame external output terminal plate 293 is performed for the inner frame. This is the same as the external output terminal plate 291. Therefore, the description of the operation of the front frame external output terminal plate 293 is omitted.

  As shown in FIG. 36 (a), the power source of the pachinko machine 600 is in an on state until t18 o'clock (the DC voltage supplied by the DC power supply DC1 is in a 12 volt state until t18 o'clock). The power source of the machine 600 is turned off (the DC voltage supplied from the DC power source DC1 is zero volts). Therefore, the power from the DC power supply DC1 is supplied to the inner frame terminal board output circuit 300a and the inner frame input / output port output circuit 300b until t18. Then, after t18 time, the supply of power by the DC power source DC1 to the inner frame terminal board output circuit 300a and the inner frame input / output port output circuit 300b is stopped. However, since the capacitor CD1 is provided in the inner frame terminal board output circuit 300a, power is supplied from the capacitor CD1 to the inner frame terminal board output circuit 300a after t18. Therefore, the inner frame terminal board output circuit 300a is operable even after t18.

  As shown in FIG. 36 (b), when the inner frame 12 changes from the closed state to the open state between the time t14 and the time t15, the switch SW3-3 follows the same as shown in FIG. 36 (c). From the conduction state to the cutoff state (at t14). Thereafter, as shown in FIG. 36 (d), the switch SW3-1 and the switch SW3-2 are changed from the cutoff state to the conductive state (at time t15). The switch SW3-3 is cut off at t14 and the switch SW3-1 and the switch SW3-2 are turned on at t15 due to the structure of the switch SW3A (FIG. 34 (a) → FIG. 34 (b) → (See FIG. 34 (c)).

  When the switch SW3-1 becomes conductive at t15, charging of the capacitor CD7 is started, and as shown in FIG. 36 (e), the voltage applied to the capacitor CD7 starts to rise from zero volts (at t15). When the switch SW3-1 is turned on, the TRG terminal voltage of the timer IC1 becomes the same as the voltage applied to the capacitor CD7, so that the TRG terminal voltage of the timer IC1 is about 10 as shown in FIG. • Falling from 3 volts to zero volts, and starts to rise (at t15). Following this, as shown in FIG. 36 (g), the OUT terminal voltage of the timer IC1 rises from zero volts to about 9.6 volts (at t15). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the inner frame terminal plate output circuit 300a are conducted, and the light emitting diode on the primary side of the photocoupler PR1 of the outer output terminal plate 291 for the inner frame (see FIG. 35), Current supply is started (at t15). Then, as shown in FIG. 36 (h), the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the inner frame external output terminal plate 291 is changed from the low state to the high state at t15. Switch to state. Thereby, output of a pulse signal indicating opening of the inner frame 12 to the hall computer 262 is started. Further, as shown in FIG. 36 (d), when the inner frame 12 changes from the closed state to the open state between t14 and t15, and the switch SW3-2 becomes conductive (at t15), the inner frame is inserted. Power from the DC power supply DC1 is supplied to the resistors R11 and R12 of the output port output circuit 300b, and the voltage applied to the resistor R12 becomes 5 volts (at t15). Therefore, as shown in FIG. 36 (i), a signal having a DC voltage of 5 volts is output from the inner frame input / output port output circuit 300b to the input / output port 205 (at t15).

  Next, as shown in FIG. 36 (e), when about 2 milliseconds elapse from t15, the charging of the capacitor CD7 is completed, and the voltage applied to the capacitor CD7 becomes about 10.3 volts. Then, as shown in FIG. 36 (f), the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again (about 2 milliseconds have elapsed since t15). However, since about 10 milliseconds have not elapsed since the voltage at the OUT terminal of the timer IC1 rose from zero volts to about 9.6 volts (from t15), the OUT terminal voltage of the timer IC1 is about 9.6 volts. Is maintained.

  Thereafter, when about 10 milliseconds elapse from t15, as shown in FIG. 36 (g), the timer IC1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts. Then, the collector terminal and the emitter terminal of the transistor TR1 of the inner frame terminal plate output circuit 300a are cut off, and the current supply to one end of the resistor R7a of the inner frame external output terminal plate 291 is stopped. Therefore, the output of the inner frame external output terminal plate 291 is switched from the high state to the low state as shown in FIG. Thereby, the output of the pulse signal output to the hall computer 262 is stopped. Thus, by switching the output of the inner frame external output terminal plate 291, the pulse width of the pulse signal output from the inner frame external output terminal plate 291 to the hall computer 262 can be kept at about 10 milliseconds. .

  As shown in FIG. 36 (b), when the inner frame 12 changes from the open state to the closed state between time t16 and time t17, as shown in FIG. 36 (d), the switch SW3-1 and the switch SW3-2. Is changed from the conductive state to the cut-off state at t16. Thereafter, as shown in FIG. 36 (c), the switch SW3-3 becomes conductive again (at time t17). The switch SW3-1 and the switch SW3-2 are cut off at t16, and the switch SW3-3 is turned on at t17 due to the structure of the switch SW3A ((FIG. 34 (c) → FIG. 34 (b) (See FIG. 34 (a))).

  As shown in FIG. 36 (d), the switch SW3-1 is turned off (at t16), and thereafter, as shown in FIG. 36 (c), when the switch SW3-3 is turned on (at t17), the capacitor CD7 is turned on. One end is grounded, and as shown in FIG. 36 (e), the electric charge stored in the capacitor CD7 is instantaneously discharged between t15 and t16 (at t17). As a result, as shown in FIG. 36 (e), the charge stored in the capacitor CD7 becomes zero and the voltage applied to the capacitor CD7 becomes zero volts (at t17). Therefore, the inner frame terminal board output circuit 300a is again set to a state in which the inner frame 12 can be detected (at t17). Further, as shown in FIG. 36 (d), when the switch SW3-2 is cut off (at t16), power is supplied from the DC power source DC1 to the resistors R11 and R12 of the input / output port output circuit 300b for the inner frame. Is stopped, and the voltage applied to the resistor R12 becomes zero volts (at t16). Therefore, as shown in FIG. 36 (i), the signal of the DC voltage of 5 volts output from the inner frame input / output port output circuit 300b to the input / output port 205 is stopped at t16 (inner frame input). The output from the output port output circuit 300b to the input / output port 205 is zero volts at t16).

  Next, as shown in FIG. 36A, when the power source of the pachinko machine 600 is turned off after t18 (when the DC voltage supplied from the DC power source DC1 becomes zero volts), the inner frame terminal board output circuit 300a. In addition, the supply of power by the DC power source DC1 to the inner frame input / output port output circuit 300b is stopped. However, even when the power of the pachinko machine 600 is off, the power from the capacitor CD1 is supplied to the inner frame terminal board output circuit 300a. Therefore, when the inner frame 12 changes again from the closed state to the open state from t17 when the previous closed state is reached, for example, between t19 and t20, after about 3 minutes have elapsed, FIG. As shown in c), the switch SW3-3 is changed from the conductive state to the cut-off state (at t19), and thereafter, as shown in FIG. 36 (d), the switch SW3-1 and the switch SW3-2 are changed from the cut-off state to the conductive state. (Time t20), charging of the capacitor CD7 is started. Therefore, as shown in FIG. 36 (e), the voltage applied to the capacitor CD7 starts to rise from zero volts (at t20). The switch SW3-3 is cut off at t19 and the switch SW3-1 and the switch SW3-2 are turned on at t20 due to the structure of the switch SW3A (FIG. 34 (a) → FIG. 34 (b) → (See FIG. 34 (c)).

  As shown in FIG. 36 (d), when the switch SW3-1 changes from the cutoff state to the conductive state (at t20), the TRG terminal voltage of the timer IC1 becomes the same as the voltage applied to the capacitor CD7. As shown in (f), the TRG terminal voltage of the timer IC 1 once rises from about 10.3 volts to zero volts, and then starts to rise (at t20). Following this fall, as shown in FIG. 36 (g), the OUT terminal voltage of the timer IC 1 rises from zero volts to about 9.6 volts (at t20). As a result, the collector terminal and the emitter terminal of the transistor TR1 of the inner frame terminal plate output circuit 300a are electrically connected to the light emitting diode on the primary side of the photocoupler PR1 of the inner frame external output terminal plate 291 (see FIG. 35). Current supply is started (at t20). Then, as shown in FIG. 36 (h), the output of the light receiving element (phototransistor) on the secondary side of the photocoupler PR1, that is, the output of the inner frame external output terminal plate 291 is changed from the low state to the high state at t20. Switch to state. Thereby, output of a pulse signal indicating opening of the inner frame 12 to the hall computer 262 is started. On the other hand, as shown in FIG. 36 (d), even when the inner frame 12 changes from the closed state to the open state again from t19 to t20, and the switch SW3-2 becomes conductive (at t20). Since power from the DC power supply DC1 is not supplied to the resistors R11 and R12 of the inner frame input / output port output circuit 300b (since the DC voltage supplied from the DC power supply DC1 is zero volts), the voltage applied to the resistor R12 Becomes zero volts (at t20). Therefore, as shown in FIG. 36 (i), the signal output from the inner frame input / output port output circuit 300b to the input / output port 205 maintains the stopped state (input from the inner frame input / output port output circuit 300b). The output to output port 205 remains at zero volts).

  Next, as shown in FIG. 36 (e), when about 2 milliseconds elapse from t20, the charging of the capacitor CD7 is completed, and the voltage applied to the capacitor CD7 becomes about 10.3 volts. Then, as shown in FIG. 36 (f), the TRG terminal voltage of the timer IC1 returns from zero volts to about 10.3 volts again (about 2 milliseconds have elapsed since t20). However, since about 10 milliseconds have not elapsed since the voltage at the OUT terminal of the timer IC1 rose from zero volts to about 9.6 volts (from t20), the OUT terminal voltage of the timer IC1 is about 9.6 volts. Is maintained.

  Thereafter, when about 10 milliseconds elapse from t20, the timer IC 1 switches the voltage at the OUT terminal from about 9.6 volts to zero volts as shown in FIG. Then, the collector terminal and the emitter terminal of the transistor TR1 of the inner frame terminal plate output circuit 300a are cut off, and the current supply to one end of the resistor R7a of the inner frame external output terminal plate 291 is stopped. Therefore, the output of the inner frame external output terminal plate 291 is switched from the high state to the low state as shown in FIG. 36 (h) when about 10 milliseconds elapse from t20. Thereby, the output of the pulse signal output to the hall computer 262 is stopped. Thus, by switching the output of the inner frame external output terminal plate 291, the pulse width of the pulse signal output from the inner frame external output terminal plate 291 to the hall computer 262 can be kept at about 10 milliseconds. .

  As shown in FIG. 36 (b), when the inner frame 12 changes from the open state to the closed state between time t21 and time t22, as shown in FIG. 36 (d), the switch SW3-1 and the switch SW3- 2 changes from the conduction state to the cutoff state at t21. Thereafter, as shown in FIG. 36 (c), the switch SW3-3 becomes conductive again (at t22). The switch SW3-1 and the switch SW3-2 are cut off at t21, and the switch SW3-3 is turned on at t22 due to the structure of the switch SW3A ((FIG. 34 (c) → FIG. 34 (b) → FIG. 34 (a)))).

  As shown in FIG. 36 (d), the switch SW3-1 is turned off (at time t21), and thereafter, as shown in FIG. 36 (c), when the switch SW3-3 is turned on (at time t22), the capacitor One end of CD7 is grounded, and as shown in FIG. 36 (e), the electric charge stored in the capacitor CD7 is instantaneously discharged between t20 and t21 (at t22). As a result, as shown in FIG. 36 (e), the charge stored in the capacitor CD7 becomes zero and the voltage applied to the capacitor CD7 becomes zero volts (at t22). Therefore, the inner frame terminal board output circuit 300a is again set to a state in which the inner frame 12 can be detected (at t22). Also, as shown in FIG. 36 (d), when the switch SW3-2 is turned off (at t21), the inner frame input / output port output circuit 300b causes the inner frame when the power of the pachinko machine 600 is turned on. 12 is set in a state where detection is possible (at t21).

  As described above, the inner frame opening detection circuit 300 (the inner frame terminal board output circuit 300a) shuts off the switch SW3-1 when the inner frame 12 is in a closed state (at t17 and t22), and the capacitor CD1. After the power supplied to the capacitor CD7 is stopped, one end of the capacitor CD7 can be grounded by the switch SW3-3. Therefore, when the inner frame 12 is closed (at t17 and t22), the charge stored in the capacitor CD7 when the inner frame 12 is opened (from the charge stored at t15 to t16 and from t20) The charge stored at t21) can be instantaneously discharged through the switch SW3-3 to zero (at t17 and t22). As a result, since the electric charge stored in the capacitor CD7 is always zero before the inner frame 12 is again opened, it is assumed that the inner frame 12 has been continuously opened several times in a short time. However, the integration circuit 281 operates normally, and the falling period of the voltage applied to the TRG terminal of the timer IC 1 can be set to a certain period (about 2 milliseconds) regardless of the opening period of the inner frame 12.

  Further, the inner frame opening detection circuit 300 (inner frame terminal board output circuit 300a) is configured such that when the inner frame 12 changes from the closed state to the opened state (from t14 to t15 and from t19 to t20), the switch SW3A Structurally, first, after the switch SW3-3 is cut off (at t14 and t19), the switch SW3-1 and the switch SW3-2 are turned on (at t15 and t20). Thus, when the inner frame 12 changes from the closed state to the open state, first, one end of the capacitor CD7 is disconnected from the ground by the switch SW3-3 (at t14 and t19), and then from the capacitor CD1. Is supplied to the capacitor CD7 via the switch SW3-1 (at t15 and t20). Therefore, when the inner frame 12 changes from the closed state to the open state, the capacitor CD1 that supplies power is not short-circuited to the ground. Therefore, when the inner frame 12 changes from the closed state to the opened state, the power from the capacitor CD1 flows into the ground, and the inner frame frame open detection circuit 300 (the inner frame terminal board output circuit 300a) is short-circuited. Absent.

  Similarly, when the inner frame 12 changes from the open state to the closed state (from t16 to t17 and from t21 to t22), the inner frame opening detection circuit 300 (inner frame terminal board output circuit 300a) switches SW3A. First, after the switch SW3-1 and the switch SW3-2 are cut off (at t16 and t21), the switch SW3-3 is turned on (at t17 and t22, see FIG. 34). . In this way, when the inner frame 12 changes from the open state to the closed state, first, the power supplied from the capacitor CD1 to the capacitor CD7 is stopped by the switch SW3-1 (at t16 and t21), and thereafter Then, one end of the capacitor CD7 is grounded via the switch SW3-3 (at t17 and t22). Therefore, when the inner frame 12 changes from the open state to the closed state, the capacitor CD1 that supplies power is not short-circuited to the ground. Therefore, when the inner frame 12 changes from the open state to the closed state, the power from the capacitor CD1 flows into the ground, and the inner frame open-circuit detection circuit 300 (inner frame terminal board output circuit 300a) is short-circuited. Absent.

  Further, the inner frame opening detection circuit 300 (the inner frame terminal board output circuit 300a) is configured such that when the inner frame 12 is in the closed state (at t17 and t22), The charge stored in CD7 (the charge stored from t15 to t16 and the charge stored from t20 to t21) can be instantaneously discharged to the ground via the switch SW3-3 (at t17 and t22). Therefore, when the inner frame 12 is opened and the switch SW3-1 is turned on (at t15 and t20), the charge stored in the capacitor CD7 is superimposed on the voltage supplied from the capacitor CD1, and the timer IC1 is set. An overvoltage (for example, a voltage of 12.3 volts) having such a magnitude as to destroy is not applied to the TRG terminal of the timer IC1. Accordingly, it is possible to eliminate the need for a Zener diode that prevents the application of an overvoltage large enough to destroy the timer IC1.

  Further, as described above, the inner frame open frame detection circuit 300 changes the switch SW3 connected to the inner frame open frame detection circuit 290 of the pachinko machine 500 of the fourth embodiment to the switch SW3A, and performs the fourth embodiment. The zener diode D3 used in the inner frame frame opening detection circuit 290 of the pachinko machine 500 is removed, and the configuration is the same as that of the inner frame frame opening detection circuit 290 except for the above changes. Also, the inner frame external output terminal plate 291 of the pachinko machine 600 of the fifth embodiment has the same structure as the inner frame external output terminal plate 291 of the pachinko machine 500 of the fourth embodiment.

  Therefore, similarly to the pachinko machine 500 of the fourth embodiment, when power is supplied to the pachinko machine 600 and a DC voltage of 12 volts is supplied from the DC power source DC1 (until t18 o'clock), When the frame 12 is opened and the switch SW3-1 provided in the inner frame terminal board output circuit 300a is turned on, the inner frame terminal board output circuit 300a is transferred from the inner frame external output terminal board 291 to the hall computer 262. A pulse signal having a pulse width of 10 milliseconds is output. Further, when the inner frame 12 is opened and the switch SW3-2 provided in the inner frame input / output port output circuit 300b is turned on, a signal of 5 volts is sent from the inner frame input / output port output circuit 300b to the input / output port 205. Is output.

  Further, for example, even when the business hours of the game hall are over and the power supply to the pachinko machine 600 is interrupted (even after t18), the inner frame terminal board output circuit 300a has Since the power is supplied from the capacitor CD1, when the inner frame 12 is opened and the switch SW3-1 provided in the inner frame terminal plate output circuit 300a is turned on, the inner frame terminal plate output circuit 300a is A pulse signal having a pulse width of 10 milliseconds is output from the inner frame external output terminal plate 291 to the hall computer 262. However, for example, when the business hours of the game hall are over and the power supply to the pachinko machine 600 is cut off (in the case of t18 or later), a DC voltage of 12 volts from the DC power source DC1 is Since the internal frame 12 is opened and the switch SW3-2 provided in the internal frame input / output port output circuit 300b is turned on, the internal frame input / output is not supplied to the internal input / output port output circuit 300b. No signal is output from the port output circuit 300b to the input / output port 205 (the DC voltage output from the inner frame input / output port output circuit 300b to the input / output port 205 is zero volts).

  Thus, when power is supplied to the pachinko machine 600, when the inner frame 12 is opened, a function of outputting a signal to the input / output port 205 and a function of outputting a pulse signal to the hall computer 262, The function of outputting a pulse signal to the hall computer 262 when the inner frame 12 is opened when the power supply to the pachinko machine 600 is cut off is a single circuit inner frame open detection circuit 300. Can demonstrate.

  The pulse signal output from the inner frame external output terminal plate 291 is stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12 is opened can be specified by the pulse signal stored in the hall computer 262. Furthermore, the pulse signal is output from the external output terminal board 291 for the inner frame to the hall computer 262, and the output time of the output pulse signal is stored, so that the specified inner frame 12 of the pachinko machine is opened. The time can be detected.

  When the inner frame 12 is opened and the switch SW3-1 and the switch SW3-2 are in a conductive state, the timer IC1 of the inner frame terminal board output circuit 300a does not depend on the conduction period of the switch SW3-1. Regardless of the opening period of the inner frame 12, when the switch SW3-1 becomes conductive and the TRG terminal voltage of the timer IC1 falls from about 10.3 volts to zero volts, about 10 milliseconds elapses, the OUT terminal of the timer IC1 Is switched from about 9.6 volts to zero volts. Thereby, the supply period of the current supplied to the photocoupler PR1 of the inner frame external output terminal plate 291 is about 10 milliseconds.

  Thus, for example, the business hours of the amusement hall are over, and the power supply to the pachinko machine 600 is cut off, and the DC power supply DC1 to 12 volts DC is supplied to the inner frame terminal board output circuit 300a and the inner frame external output terminal board 291. When no voltage is supplied, that is, when a DC voltage of about 10.3 volts is supplied from the capacitor CD1 to the inner frame terminal board output circuit 300a and the inner frame external output terminal board 291, the photocoupler PR1 is supplied from the capacitor CD1. The supply period of the current supplied to can be kept at about 10 milliseconds per opening of the inner frame 12. Therefore, the power consumption due to the opening of the inner frame 12 can be kept small.

  As mentioned above, although this invention was demonstrated based on the pachinko machine of 1st Embodiment to 5th Embodiment, this invention is not limited to the said form at all, and various in the range which does not deviate from the meaning of this invention. It can be easily inferred that the deformation can be improved.

  It goes without saying that the pachinko machines having the functions of the respective embodiments can be realized by combining the pachinko machines described in the first to fifth embodiments.

  In the first to fifth embodiments, the pachinko machine has an installation place for the pulse signals output from the external output terminal plate 261, the external output terminal plate 291 for the inner frame, and the external output terminal plate 293 for the front frame. Although output to a different hall computer 262, the present invention is not limited to this. A dedicated storage device having the function of the hall computer 262 may be provided for each pachinko machine, and the dedicated storage device may be provided on the back side of each pachinko machine in which the main controller 110 and the like are provided. In this case, more preferably, a dedicated storage device such as the main control device 110, the payout control device 111, and the launch control device 112 is stored in the substrate box, and the box base and the box cover provided in the substrate box are stored. Are connected by a sealing unit (not shown) so that they cannot be opened (connection by caulking structure). Then, a seal seal (not shown) is attached to the connecting portion between the box base and the box cover so as to cover the box cover and the box base.

  In the fourth and fifth embodiments, the inner frame external output terminal plate 291 and the front frame external output terminal plate 293 are provided on separate substrates, but the present invention is not limited to this. The inner frame external output terminal plate 291 and the front frame external output terminal plate 293 may be provided on the same substrate. Even when the inner frame external output terminal plate 291 and the front frame external output terminal plate 293 are provided on the same substrate, the inner frame external output terminal plate 291 is provided with the inner frame frame open detection circuit 290. The front frame external output terminal plate 293 is connected to the front frame open frame detection circuit 292. Then, the inner frame external output terminal plate 291 and the front frame external output terminal plate 293 separately output pulse signals to the hall computer 262.

  In the fourth and fifth embodiments, the inner frame opening detection circuit 290 for detecting the opening of the inner frame 12 and the front frame opening detection circuit 292 for detecting the opening of the front frame 14 are separately provided. However, the present invention is not limited to this. When outputting to the hall computer 262 without distinguishing the opening of the inner frame 12 and the front frame 14, the following configuration may be used. First, the front frame opening detection circuit 292 and the front frame external output terminal plate 293 are removed, and the inner frame opening detection circuit 290 and the inner frame external output terminal plate 291 are left in the main controller 110. Then, the switch SW3 and the switch SW4 may be connected in parallel and connected to the inner frame opening detection circuit 290. With this configuration, it is possible to output to the hall computer 262 without distinguishing the opening of the inner frame 12 and the front frame 14. It should be noted that what is left in main controller 110 may be front frame open frame detection circuit 292 and front frame external output terminal plate 293 instead of inner frame open frame detection circuit 290 and inner frame external output terminal plate 291. .

  In the fourth and fifth embodiments, the inner frame input / output port output circuit 290b is used to output a signal of 5 volts to the input / output port 205 when the inner frame 12 is opened. It is not limited. When a 5 volt signal is output to the input / output port 205 when the inner frame 12 is opened without using the inner frame input / output port output circuit 290b, the following configuration may be used. First, the inner frame input / output port output circuit 290b is removed from the inner frame frame open detection circuit 290 (the DC power source DC1 remains). Next, a resistor is connected in series between the emitter terminal e of the transistor TR1 and the ground, and the input / output port 205 is connected to a connection point between the emitter terminal e of the transistor TR1 and the resistor connected in series. When the collector terminal c and the emitter terminal e of the transistor TR1 are conducted, that is, when the inner frame 12 is opened, a resistor connected in series so that a signal of 5 volts is output to the input / output port 205. Adjust the value. As a result, when the inner frame 12 is opened while the switch SW3-2, the resistor R11, and the resistor R12 are not required, a 5 volt signal is output to the input / output port 205, and a pulse signal with a pulse width of 10 milliseconds is halled. The data can be output to the computer 262. In the above description, the case where the inner frame input / output port output circuit 290b is not necessary has been described. However, when the front frame input / output port output circuit 292b is not required, the front frame frame open detection circuit is also provided. A similar procedure may be applied to 292.

In the first to fifth embodiments, the external output terminal plate 261, the internal frame external output terminal plate 291 and the front frame external output terminal plate 293 are connected to the hall computer 262, and the external output terminal plate 261 is connected. A pulse signal was output from the inner frame external output terminal plate 291 and the front frame external output terminal plate 293 to the hall computer 262, and the hall computer 262 memorized the opening of the inner frame 12 or the front frame 14. It is not limited to. For example, a pachinko machine with an EEPROM (Electronically Erasable
and Programmable Read Only Memory) and backup RAM. Then, the external output terminal plate 261, the internal frame external output terminal plate 291 and the front frame external output terminal plate 293 are connected to the EEPROM and the backup RAM. With this configuration, the opening of the inner frame 12 or the front frame 14 can be stored in the EEPROM or the backup RAM. When the power of the pachinko machine is turned on, the MPU 201 confirms the storage of the EEPROM and the backup RAM. Thereby, opening of the inner frame 12 or the front frame 14 can be detected using a pachinko machine. That is, the role of the hall computer 262 can be assigned to the EEPROM or the backup RAM (the role of the “specific device” described in the claims can be assigned to the EEPROM or the backup RAM). Note that the RAM 203 may be used as the backup RAM.

  Next, a pachinko machine 10x according to a sixth embodiment will be described with reference to FIGS. Hereinafter, an embodiment of a pachinko gaming machine (hereinafter simply referred to as “pachinko machine”) will be described with reference to the drawings. FIG. 37 is a front view of the pachinko machine 10x, FIG. 38 is a front view of the game board 13x of the pachinko machine 10x, and FIG. 39 is a rear view of the pachinko machine 10x.

  As shown in FIG. 37, the pachinko machine 10x has an outer frame 11x in which an outer shell is formed by a wooden frame combined in a substantially rectangular shape, and has an outer shape substantially the same as the outer frame 11x. And an inner frame 12x supported to be openable and closable. In order to support the inner frame 12x, two metal hinges 18x are attached to the outer frame 11x at the upper and lower two positions on the left side when viewed from the front (see FIG. 37). The frame 12x is supported so as to be openable and closable toward the front front side.

  A game board 13x (see FIG. 38) having a large number of nails, winning holes 63x, 64x and the like is detachably mounted on the inner frame 12x from the back side. A ball ball game is performed when the ball flows down the front surface of the game board 13x. The inner frame 12x has a ball launch unit 112ax (see FIG. 42) that launches a ball to the front area of the game board 13x and a shot that guides the ball launched from the ball launch unit 112ax to the front area of the game board 13x. A rail (not shown) or the like is attached.

  On the front side of the inner frame 12x, a front frame 14x that covers the upper side of the front surface and a lower dish unit 15x that covers the lower side are provided. In order to support the front frame 14x and the lower plate unit 15x, metal hinges 19x are attached to the upper and lower two places on the left side when viewed from the front (see FIG. 37), and the side on which the hinges 19x are provided is used as an opening / closing axis 14x and the lower pan unit 15x are supported so as to be openable and closable toward the front front side. Note that the locking of the inner frame 12x and the locking of the front frame 14x are respectively released by inserting a dedicated key into the key hole 21x of the cylinder lock 20x and performing a predetermined operation.

  The front frame 14x is an assembly of decorative resin parts, electrical parts, and the like, and a window part 14cx that is formed in an approximately elliptical shape is provided at a substantially central part thereof. A glass unit 16x having two glass plates is disposed on the back side of the front frame 14x, and the front surface of the game board 13x is visible on the front side of the pachinko machine 10x through the glass unit 16x. On the front frame 14x, an upper plate 17x for storing a ball is formed in a substantially box shape projecting forward to open the upper surface, and prize balls, rental balls and the like are discharged to the upper plate 17x. The bottom surface of the upper plate 17x is formed so as to be inclined downward toward the right side when viewed from the front (see FIG. 37), and the ball thrown into the upper plate 17x is guided to the ball launch unit 112ax by the inclination. A frame button 22x is provided on the upper surface of the upper plate 17x. This frame button 22x is operated by the player, for example, when changing the effect pattern of the variable display displayed on the third symbol display device 81x or changing the effect content at the reach effect.

  In addition, the front frame 14x is provided with light emitting means such as various lamps around the periphery (for example, a corner portion). These light-emitting means play a role of enhancing the effect of the game during the game by changing or controlling the light-emitting mode by turning on or flashing according to the change in the gaming state at the time of big hit or predetermined reach. On the periphery of the window portion 14cx, there are provided electrical decoration portions 29x to 33x incorporating light emitting means such as LEDs. In the pachinko machine 10x, these lighting parts 29x to 33x function as effect lamps such as jackpot lamps, and the lighting parts 29x to 33x are turned on by lighting or blinking of the built-in LEDs at the time of jackpot or reach effects. Alternatively, it blinks to notify that the jackpot is being hit or that the reach is one step before the jackpot.

  Further, in the upper left part of the front frame 14x when viewed from the front (see FIG. 37), there is provided a display lamp 34x that has built-in light emitting means such as an LED and can display when a prize ball is being paid out and when an error has occurred. In addition, a small window 35x is formed by attaching a transparent resin from the rear surface side so that the rear surface side of the front frame 14x can be visually recognized below the right-side illumination part 32x, and a sticking space K1x on the front surface of the game board 13x (see FIG. 38) is visible from the front surface of the pachinko machine 10x. In addition, in the pachinko machine 10x, a plated member 36x made of ABS resin, which is chrome-plated, is attached to the area around the electric decoration portions 29x to 33x in order to bring out more gorgeousness.

  A ball lending operation unit 40x is disposed below the window 14cx. The ball lending operation unit 40x is provided with a frequency display unit 41x, a ball lending button 42x, and a return button 43x. When the ball lending operation unit 40x is operated with a bill or a card inserted in a card unit (ball lending unit) (not shown) arranged on the side of the pachinko machine 10x, Loans are made. Specifically, the frequency display portion 41x is an area where the remaining amount information such as a card is displayed, and a built-in LED is lit to display the remaining amount as remaining amount information. The ball lending button 42x is operated to obtain a lending ball based on information recorded on a card or the like (recording medium), and the lending ball is supplied to the upper plate 17x as long as there is a remaining amount on the card or the like. Is done. The return button 43x is operated when requesting the return of a card or the like inserted into the card unit. In addition, in a pachinko machine in which balls are lent directly to the upper plate 17x from a ball lending device or the like without using a card unit, a so-called cash machine does not require the ball lending operation unit 40x. In this case, the ball lending operation unit 40x A decorative seal or the like may be added to the installation portion of the parts to make the parts configuration common. A pachinko machine using a card unit and a cash machine can be shared.

  In the lower tray unit 15x located on the lower side of the upper tray 17x, a lower tray 50x for storing a ball that could not be stored in the upper tray 17x is formed in a substantially box shape having an open upper surface. Yes. On the right side of the lower plate 50x, an operation handle 51x that is operated by a player to drive a ball into the front surface of the game board 13x is provided, and the operation of the ball launch unit 112ax is permitted inside the operation handle 51x. Touch sensor 51ax, a push button-type stop switch 51bx for stopping the firing of the ball during the pressing operation, and a variable resistor for detecting the amount of rotation of the operation handle 51x by a change in electric resistance (Not shown). When the operation handle 51x is rotated clockwise by the player, the touch sensor is turned on and the resistance value of the variable resistor changes in accordance with the operation amount, and according to the rotation operation amount of the operation handle 51x. A ball is fired with a strength corresponding to the resistance value of the variable resistor that changes, and the ball is driven into the front surface of the game board 13x with a jump amount corresponding to the player's operation. Further, when the operation handle 51x is not operated by the player, the touch sensor 51ax and the stop switch 51bx are turned off.

  A ball removal lever 52x for operating the ball stored in the lower plate 50x downward is provided at the lower front portion of the lower plate 50x. The ball release lever 52x is always urged to the right, and by sliding to the left against the urge, the bottom opening formed on the bottom surface of the lower plate 50x is opened. A ball naturally falls from the bottom opening and is discharged. The operation of the ball pulling lever 52x is normally performed in a state where a box (generally referred to as “a thousand box”) that receives the balls discharged from the lower plate 50x is placed below the lower plate 50x. As described above, the operation handle 51x is disposed on the right side of the lower plate 50x, and the ashtray 53x is attached to the left side of the lower plate 50x.

  As shown in FIG. 38, the game board 13x has a wooden base plate 60x cut into a substantially square shape when viewed from the front, a large number of ball guide nails, windmills and rails 61x and 62x, a general winning opening 63x, The ball entrance 64x, the variable winning device 65x, the variable display device unit 80x, and the like are assembled, and the peripheral edge thereof is attached to the back side of the inner frame 12x. The general winning opening 63x, the first winning opening 64x, the variable winning device 65x, and the variable display device unit 80x are arranged in a through hole formed in the base plate 60x by router processing, and the wood screw from the front side of the game board 13x. It is fixed by etc. Further, the front center portion of the game board 13x can be viewed from the front side of the inner frame 12x through the window portion 14cx (see FIG. 37) of the front frame 14x. Below, the structure of the game board 13x is demonstrated.

  An outer rail 62x formed by bending a belt-shaped metal plate into a substantially arc shape is planted on the front surface of the game board 13x, and a belt-shaped metal plate is formed at an inner position of the outer rail 62x in the same manner as the outer rail 62x. The arc-shaped inner rail 61x formed in the above is planted. The inner rail 61x and the outer rail 62x surround the outer periphery of the front surface of the game board 13x, and the game board 13x and the glass unit 16x (see FIG. 37) surround the front and rear. A game area where a game is played is formed according to the behavior. The game area is a front surface of the game board 13x and is a substantially circular area formed by dividing the two rails 61x and 62x and the arc member 70x (a winning opening etc. are provided, Area that flows down).

  The two rails 61x and 62x are provided to guide the ball fired from the ball launch unit 112ax to the upper part of the game board 13x. A return ball prevention member 68x is attached to the front end portion of the inner rail 61x (the upper left part in FIG. 38) to prevent a situation where a ball guided to the upper part of the game board 13x once returns to the ball guide path again. Is done. A return rubber 69x is attached to the tip of the outer rail 62x (upper right part of FIG. 38) at a position corresponding to the maximum flying portion of the sphere, and the sphere launched at a predetermined momentum or more hits the return rubber 69x and gains momentum. Is bounced back to the center while being attenuated. Further, a resin arc member 70x formed by providing an arc connecting the rails on the inner surface side between the tip portion on the lower right side of the inner rail 61x and the tip portion on the upper right side of the outer rail 62x is a base. The plate 60x is driven and fixed.

  A first symbol display device 37x provided with a plurality of LEDs 37ax serving as light emitting means and a 7-segment display 37bx is disposed in the upper right part of the game area when viewed from the front (upper right part of FIG. 38). The first symbol display device 37x displays information corresponding to each control performed by the main controller 110x, and mainly displays the gaming state of the pachinko machine 10x. The plurality of LEDs 37ax indicate whether the pachinko machine 10x is in a certain change, in a short time, or in a normal state by a lighting state, whether it is changing or not by a lighting state, or a symbol corresponding to a probable big hit Whether the symbol is a symbol corresponding to a normal jackpot or an out-of-game symbol is indicated by a lighting state, or the number of reserved balls is indicated by a lighting state. The 7-segment display 37bx is for displaying the number of rounds that are a big hit and an error display. In addition, LED37ax is comprised so that the light emission color (for example, red, green, blue) of each LED may differ, The various game states of the pachinko machine 10x can be suggested with few LEDs by the combination of the light emission color.

  It should be noted that the fact that the pachinko machine 10x described above is being probabilistic means a game state in which the jackpot probability is increased and it is easy to shift to the special game state. Further, during the probability change in the present embodiment, the game is in a state where the probability of hitting the second symbol increases and the ball easily enters the first entrance 64x. In addition, when the time of the pachinko machine 10x is short, the game is in a state where it is easy for the ball to easily enter the first entrance 64x because the hit probability of the second symbol is increased and the hit probability of the second symbol is increased. In addition, when the pachinko machine 10x is normal, it is a game state (a state where neither the big hit probability nor the second symbol hit probability is up) which is neither probable nor short. It should be noted that, depending on the gaming state of the pachinko machine 10x, the time for opening the electric accessory (not shown) associated with the first entrance 64x and the number of times the electric accessory is released per time are changed. It is good as a thing.

  The game area is provided with a plurality of general winning openings 63x through which 5 to 15 balls are paid out as winning balls when the balls win. In addition, a variable display device unit 80x is disposed in the central portion of the game area. The variable display device unit 80x has a third symbol display device 81x configured with a liquid crystal display (hereinafter simply referred to as “display device”) that displays the third symbol in a variable manner with a winning at the first entrance 64x as a trigger. And a second symbol display device 82x configured by a light emitting diode (hereinafter abbreviated as “LED”) that displays the second symbol in a variable manner triggered by the passage of the ball at the second entrance 67x. .

  The display content of the third symbol display device 81x is controlled by a display control device 114x, which will be described later, and, for example, three symbol rows of left, middle, and right are displayed. Each symbol row is composed of a plurality of symbols, and these symbols are vertically scrolled for each symbol row so that the third symbol is variably displayed on the display screen of the third symbol display device 81x. In the present embodiment, the third symbol display device 81x is constituted by a large 8-inch liquid crystal display. The variable display device unit 80x surrounds the outer periphery of the third symbol display device 81x so as to surround the center frame. 86x is arranged. In the third symbol display device 81x of the present embodiment, the display of the gaming state accompanying the control of the main control device 110x is performed on the first symbol display device 37x, whereas the display of the first symbol display device 37x is performed. The decorative display according to is performed. Instead of the display device, for example, the third symbol display device 81x may be configured using a reel or the like.

  In addition, when the ball enters the first entrance 64x before the stop symbol (any one of the probable big hit symbol, the normal big hit symbol, or the off symbol) is displayed on the first symbol display device 37x. The number of times of entering the ball is held up to 4 times, and the number of times of holding is indicated by the first symbol display device 37x as well as the number of lighting of the holding lamp 85x. Four hold lamps 85x are provided corresponding to the maximum number of holds, and are arranged symmetrically above the third symbol display device 81x. In the present embodiment, the winning at the first entrance 64x is configured to be held up to 4 times, but the maximum holding number is not limited to 4 times, but 3 times or less. Alternatively, the number may be set to 5 times or more (for example, 8 times). In addition, the hold lamp 85x is deleted, and the number of times the variable display is held based on the winning at the first entrance 64x is held in a part of the 3rd symbol display device 81x as a number or in an area divided into four areas. You may make it display in a different aspect (for example, a color and a lighting pattern) by the frequency | count. In addition, since the number of times of holding is indicated by the first symbol display device 37x, the lighting display may not be performed by the holding lamp 85x.

  The second symbol display device 82x has a second symbol display portion 83x and a holding lamp 84x, and each time a ball passes through the second entrance 67x, the display portion 83x displays a display symbol (second symbol). When the “○” symbol and “×” symbol are alternately lit and displayed in a varying manner, the variation display is stopped when the symbol is stopped at a predetermined symbol (in this embodiment, the symbol “O”). One entrance 64x is configured to be activated (opened) for a predetermined time. The number of passes through the second entrance 67x of the sphere is suspended up to a maximum of 4 times, and the number of suspensions is displayed by the first symbol display device 37x described above and is also lit on the hold lamp 84x. The second symbol variation display is performed by switching on and off of a plurality of lamps in the display unit 83x as in the present embodiment, as well as the first symbol display device 37x and the third symbol display device. You may make it carry out using a part of 81x. Similarly, the hold lamp 84x may be turned on by a part of the third symbol display device 81x. In addition, the passage of the second entrance 67x is not limited to 4 times as in the case of the first entrance 64x, and is not limited to 4 times, but 3 times or less (for example, (8 times) may be set. Moreover, since the number of times of holding is indicated by the first symbol display device 37x, the lighting display may not be performed by the holding lamp 84x.

  Below the variable display unit 80x, a first entrance 64x through which a sphere can enter is disposed. When a ball enters the first entrance 64x, a first entrance switch (not shown) provided on the back side of the game board 13x is turned on, and the first entrance switch is turned on. The main control device 110x performs a lottery lottery, and a display corresponding to the lottery result is indicated by the LED 37ax of the first symbol display device 37x. The first entrance 64x is also one of the entrances through which 5 balls are paid out as prize balls when a ball enters.

  A variable winning device 65x is disposed below the first ball entrance 64x, and a horizontally-long rectangular specific winning opening (large opening) 65ax is provided at a substantially central portion thereof. In the pachinko machine 10x, when the lottery in the main controller 110x is a big hit, after a predetermined time (fluctuation time) has elapsed, the LED 37ax of the first symbol display device 37x is turned on so as to become a big hit stop symbol, The stop symbol corresponding to the jackpot is displayed on the third symbol display device 81x to indicate the occurrence of the jackpot. Thereafter, the gaming state transitions to a special gaming state (big hit) where the ball is easy to win. As this special gaming state, the special winning opening 65ax that is normally closed is opened for a predetermined time (for example, until 30 seconds elapse or 10 balls are won).

  The specific winning opening 65ax is closed when a predetermined time elapses, and after the closing, the specific winning opening 65ax is opened again for a predetermined time. The opening / closing operation of the specific winning opening 65ax can be repeated up to 16 times (16 rounds), for example. The state in which the opening / closing operation is performed is a form of a special gaming state advantageous to the player, and the player is given out a larger amount of prize balls than usual in order to give a gaming value (game value). Is done.

  Specifically, the variable winning device 65x includes a horizontally-long rectangular opening / closing plate that covers the specific winning opening 65ax, and a large opening solenoid (not shown) for opening and closing forward with the lower side of the opening / closing plate as an axis. And. The special winning opening 65ax is normally closed so that the ball cannot win or is difficult to win. In the case of a big hit, the large opening opening solenoid is driven to tilt the opening / closing plate downward, and the ball temporarily forms an open state in which it is easy to win the specific winning opening 65ax. It operates to repeat the state and the state alternately.

  Note that the special gaming state is not limited to the above-described form. When the game area is provided with a large opening that is opened and closed separately from the specific winning opening 65ax, and the LED 37ax corresponding to the jackpot is turned on in the first symbol display device 37x, the specific winning opening 65ax is opened for a predetermined time, and the specific winning opening A special gaming state is a game state in which a large opening provided separately from the specific winning port 65ax is opened for a predetermined time and a predetermined number of times when a ball wins into the specific winning port 65ax while the port 65ax is opened. You may make it form.

  Adhesive spaces K1x and K2x for adhering certificate papers, identification labels, etc. are provided at the left and right corners on the lower side of the game board 13x, and the certificate paper or the like attached to the adhering space K1x is a front frame 14x. Can be visually recognized through the small window 35x (see FIG. 37).

  Further, the game board 13x is provided with an out port 66x. A ball that has not entered any of the winning ports 63x, 64x, 65ax is guided to a ball discharge path (not shown) through the out port 66x. A number of nails are planted on the game board 13x in order to appropriately disperse and adjust the falling direction of the ball, and various members (instruments) such as a windmill are arranged.

  As shown in FIG. 39, control board units 90x and 91x and a back pack unit 94x are mainly provided on the back side of the pachinko machine 10x. The control board unit 90x is unitized by mounting a main board (main control apparatus 110x), an audio lamp control board (audio lamp control apparatus 113x), and a display control board (display control apparatus 114x). The control board unit 91x is unitized by mounting a payout control board (payout control apparatus 111x), a firing control board (launching control apparatus 112x), a power supply board (power supply apparatus 115x), and a card unit connection board 116x.

  The back pack unit 94x has a back pack 92x and a dispensing unit 93x forming a protective cover unit. In addition, each control board is used for MPU as a one-chip microcomputer that controls each control, a port for communicating with various devices, a random number generator used for various lotteries, time counting and synchronization. A clock pulse generation circuit or the like is mounted as necessary.

  The main control device 110x, the sound lamp control device 113x, the display control device 114x, the payout control device 111x, the firing control device 112x, the power supply device 115x, and the card unit connection board 116x are housed in the board boxes 100x to 104x, respectively. . The board boxes 100x to 104x include a box base and a box cover that covers the opening of the box base. The box base and the box cover are connected to each other, and each control device and each board are accommodated.

  The board box 100x (main controller 110x) and the board box 102x (payout controller 111x and launch controller 112x) connect the box base and the box cover so that they cannot be opened by a sealing unit (not shown) (caulking structure). Consolidated). In addition, a seal (not shown) is attached to the connecting portion between the box base and the box cover so as to cover the box base and the box cover. This seal seal is made of a brittle material. If the seal is to be peeled off to open the board boxes 100x and 102x, or if the board boxes 100x and 102x are forcibly opened, the box base side and the box cover will be removed. Cut to the side. Therefore, it is possible to know whether or not the substrate boxes 100x and 102x have been opened by checking the sealing unit or the sealing seal.

  The payout unit 93x includes a tank 130x that is located at the top of the back pack unit 94x and that opens upward, a tank rail 131x that is connected to the lower side of the tank 130x and gently inclines toward the downstream side, and downstream of the tank rail 131x. A case rail 132x that is vertically connected to the side, and a payout device 133x that is provided at the most downstream portion of the case rail 132x and that pays out a ball with a predetermined electrical configuration of the payout motor 216x (see FIG. 42). ing. Balls supplied from the island facilities of the game hall are sequentially replenished to the tank 130x, and a required number of balls are paid out appropriately by the payout device 133x. A vibrator 134x for attaching vibration to the tank rail 131x is attached to the tank rail 131x.

  The payout control device 111x is provided with a state return switch 120x, the firing control device 112x is provided with a variable resistor operation knob 121x, and the power supply device 115x is provided with a RAM erase switch 122x. The state return switch 120x is operated to eliminate ball clogging (return to a normal state) when a payout error occurs, such as a ball clogging in the payout motor 216x (see FIG. 42). The operation knob 121x is operated to adjust the firing force of the firing solenoid. The RAM erase switch 122x is operated when the power is turned on to return the pachinko machine 10x to the initial state.

  Next, the internal configuration of the pachinko machine 10x will be described with reference to FIG. FIG. 40 is a perspective view of the pachinko machine 10x in a state where the inner frame 12x, the front frame 14x, and the lower dish unit 15x are opened.

  The pachinko machine 10x is provided with an outer frame 11x that forms an outer shell, and the inner frame 12x is supported so as to be openable and closable with respect to the outer frame 11x. In the game hall, the outer peripheral surface of the outer frame 11x is fixed to an installation location called an island of the game hall. Since the inner frame 12x, the front frame 14x, and the lower dish unit 15x are configured to be openable to the front side with respect to the outer frame 11x, the inner side 12x, the front frame 14x, and the lower plate unit 15x are not touched from the front side of the pachinko machine 10x. Inspection and adjustment are performed with the inner frame 12x and the like opened to the front side with respect to the outer frame 11x.

  In order to support the inner frame 12x, a metal upper hinge (not shown) and a lower hinge (not shown) are attached to the outer frame 11x at two locations on the left side when viewed from the front. The inner frame 12x is supported to be openable and closable with the side on which the upper and lower hinges are provided as an opening / closing axis.

  The inner frame 12x is mainly configured by an ABS resin-made inner frame base 55x formed in a rectangular shape, and a substantially circular central window 55ax is formed at the center of the inner frame base 55x. A mounting portion for the game board 13x is provided on the back side of the inner frame base 55x, and the game board 13x is detachably mounted.

  The lower side of the central window 55ax of the inner frame base 55x is formed in a concave shape with the front side open, and a flat mounting surface 52bx is formed on the back side. The mounting surface 52bx is attached with a launch unit 140x for firing a ball onto the front surface of the game board 13x, a passage forming member 54x that forms a passage for discharging the ball to the upper plate 17x and the lower plate 50x, and the like.

  A switch SW1x for detecting opening and closing of the inner frame 12x is provided between the outer frame 11x and the inner frame 12x. Between the inner frame 12x and the front frame 14x, the opening and closing of the front frame 14x A switch SW2x for detecting closing is provided.

  Here, the structure of the switch SW1x and the switch SW2x will be described with reference to FIG. Since the switch SW1x and the switch SW2x have the same structure, the structure of the switch SW1x will be described, and the description of the switch SW2x will be omitted.

  FIG. 41 is a cross-sectional view of the switch SW1x. FIG. 41A is a cross-sectional view showing a state (blocking state) of the switch SW1x in a state where the inner frame 12x is closed. FIG. 41B is a cross-sectional view showing a state (conductive state) of the switch SW1x in a state where the inner frame 12x is opened.

  As shown in FIG. 41 (a), the switch SW1x disposed on the surface of the outer frame 11x facing the inner frame 12x includes a movable shaft SW1ax that is in contact with the closed inner frame 12x and its movable shaft. A conductor plate SW1-1ax made of metal which is a conductive member disposed on SW1ax, and a pair of terminal plates SW1-1bx made of metal disposed at a position facing the conductor plate SW1-1ax. The pair of terminal plates SW1-1bx are arranged on a surface opposite to the surface facing the pair of terminal plates SW1-1bx on the conductor plate SW1-1ax and the support plate SW1-1cx disposed in the housing SW1bx. And a pair of springs SW1cx that generate a biasing force in the direction toward the pair of terminal plates SW1-1bx with respect to the conductor plate SW1-1ax.

  As shown in FIG. 41A, in a state where the inner frame 12x is closed, the movable shaft SW1ax comes into contact with the inner frame 12x, and the movable shaft SW1ax is pushed into the housing SW1bx. Therefore, contact with conductor board SW1-1ax and a pair of terminal board SW1-1bx is prevented. Therefore, in a state where the inner frame 12x is closed, the switch SW1x is in a state where conduction is cut off.

  On the other hand, as shown in FIG. 41 (b), in the state where the inner frame 12x is opened, the contact between the movable shaft SW1ax and the inner frame 12x is released, so that the conductor is applied by the biasing force of the pair of springs SW1cx. The board SW1-1ax and the pair of terminal boards SW1-1bx are in contact with each other. Therefore, in a state where the inner frame 12x is opened, the switch SW1x is in a conductive state.

  As described above, the switch SW1x is cut off when the inner frame 12x is closed, and is turned on when the inner frame 12x is opened. Note that the structure of the switch SW1x is not limited to the shape shown in FIG. 41. When the inner frame 12x is closed, the switch SW1x is cut off, while the inner frame 12x is opened. Any structure may be used as long as the switch SW1x is in a conductive state. The same applies to the structure of the switch SW2x.

  Next, the electrical configuration of the pachinko machine 10x will be described with reference to FIG. FIG. 42 is a block diagram showing an electrical configuration of the pachinko machine 10x.

  The power supply device 115x is a RAM provided with a power supply unit 251x for supplying power to each part of the pachinko machine 10x, a power failure monitoring circuit 252x for monitoring power interruption due to a power failure, etc., and a RAM erase switch 122x (see FIG. 39). It has an erasing switch circuit 253x and a reset circuit 254x that outputs a reset signal SG3ax that makes the arithmetic processing of the MPU 201x executable. The power supply unit 251x is a device that supplies a necessary operating voltage to each of the control devices 110x to 114x through a power supply path (not shown). As its outline, the power supply unit 251x takes in the voltage of AC 24 volts supplied from the outside, and various switches such as various switches 208x, solenoids such as solenoid 209x, 12 volts voltage for driving a motor, A 5 volt voltage for logic, a backup voltage for RAM backup, and the like are generated, and the 12 volt voltage, the 5 volt voltage, and the backup voltage are supplied to the control devices 110x to 114x. The power supply unit 251x outputs a drive voltage Vax of 5 volts to the input terminal I13x of the multiplexer MP1x.

  When a power interruption occurs due to a power failure or the like when the power of the pachinko machine 10x is on, the power failure monitoring circuit 252x is connected to the input terminal I11x of the multiplexer MP1x and the NMI terminal of the MPU 211x of the payout control device 111x. This is a circuit for outputting a power failure signal SG1ax which is a positive pulse signal. The power failure monitoring circuit 252x monitors the DC stable voltage of 24 volts, which is the maximum voltage output from the power supply unit 251x, and determines that a power failure (power interruption, power interruption) occurs when this voltage is less than 22 volts. Then, the power failure signal SG1ax is output to the multiplexer MP1x and the payout control device 111x. Based on the output of the power failure signal SG1ax, the main control device 110x and the payout control device 111x recognize the occurrence of the power failure and execute the NMI interrupt process. The power supply unit 251x outputs a voltage of 5 volts, which is a drive voltage of the control system, for a time sufficient to execute the NMI interrupt processing even after the DC stable voltage of 24 volts becomes less than 22 volts. Is maintained at a normal value. Therefore, main controller 110x and payout controller 111x can normally execute and complete the NMI interrupt process (see FIG. 53).

  The RAM erase switch circuit 253x is a circuit for outputting a RAM erase signal SG2x for clearing backup data to the main controller 110x when the RAM erase switch 122x is pressed. The main control device 110x and the payout control device 111x are used to clear the backup data in the payout control device 111x when the RAM erase signal SG2x is input when the pachinko machine 10x is turned on. A payout initialization command is transmitted to the payout control device 111x.

  The reset circuit 254x is a circuit that outputs a reset signal SG3ax that puts the MPU 201x into a state in which arithmetic processing can be executed. The reset circuit 254x outputs a voltage of 5 volts output from the power supply unit 251x as the reset signal SG3ax. When the reset signal SG3ax is input to the MPU 201x via the multiplexer MP2x, the MPU 201x is in a state in which arithmetic processing can be performed. On the other hand, when the output of the reset signal SG3ax is stopped, the MPU 201x is in a state where the arithmetic processing cannot be executed. Although not shown, the reset signal SG3ax output from the reset circuit 254x is also input to the MPU 211x of the payout control device 111x, the MPU 221x of the sound lamp control device 113x, and the MPU 231x of the display control device 114x.

  In the pachinko machine 10x, the power failure monitoring circuit 252x, the RAM erasure switch circuit 253x, and the reset circuit 254x are provided in the power supply device 115x. Any of the reset circuits 254x may be provided in the main controller 110x. Further, a combination of any two of the power failure monitoring circuit 252x, the RAM erasing switch circuit 253x, or the reset circuit 254x may be provided in the main controller 110x. Furthermore, three circuits of the power failure monitoring circuit 252x, the RAM erasure switch circuit 253x, and the reset circuit 254x may be provided in the main controller 110x. When the RAM erase switch circuit 253x is provided in the main controller 110x, the RAM erase switch 122x is also provided in the main controller 110x.

  The main controller 110x is equipped with an MPU 201x as a one-chip microcomputer that is an arithmetic unit. The MPU 201x includes a ROM 202x storing various control programs executed by the MPU 201x and fixed value data, and a memory for temporarily storing various data when executing the control program stored in the ROM 202x. A RAM 203x and various other circuits such as an interrupt circuit, a timer circuit, and a data transmission / reception circuit are incorporated. Various commands are transmitted from the main control device 110x to the sub-control device by the data transmission / reception circuit in order to instruct the sub-control device such as the payout control device 111x and the sound lamp control device 113x. Such a command is transmitted only in one direction from the main control device 110x to the sub-control device.

  The MPU 201x includes a power supply terminal to which the driving voltage Vax or the driving voltage Vbx that enables the MPU 201x to be input, and a reset signal SG3ax or a reset signal SG3bx that enables the arithmetic processing of the MPU 201x. And a NMI terminal (non-maskable interrupt terminal) to which either the power failure signal SG1ax or the power failure signal SG1bx is input.

  The lower limit value of the voltage at which the MPU 201x can operate is about 4.0 volts. Therefore, if the drive voltage Vax or drive voltage Vbx supplied to the power supply terminal of the MPU 201x exceeds about 4.0 volts, the MPU 201x is in a startable state (operable state), while the power supply terminal of the MPU 201x. When the drive voltage Vax or the drive voltage Vbx supplied to is less than about 4.0 volts, the MPU 201x becomes inoperable. Further, the lower limit value of the voltage at which the MPU 201x can execute the calculation is about 4.3 volts. Therefore, if the voltage (reset signal SG3ax or reset signal SG3bx) supplied to the reset terminal of the MPU 201x exceeds about 4.3 volts, the MPU 201x is ready to perform arithmetic processing, while the MPU 201x has a reset terminal. When the supplied voltage (reset signal SG3ax or reset signal SG3bx) is about 4.3 volts or less, the MPU 201x is in a state where it cannot execute the arithmetic processing. Further, the power failure signal SG1ax output from the power failure monitoring circuit 252x or the power failure signal SG1bx output from the frame opening detection circuit 260x is input to the NMI terminal of the MPU 201x, and the power failure signal SG1ax or power failure signal is output. When any of SG1bx is input to the MPU 201x, an NMI interrupt process (see FIG. 53) as a power failure process is immediately executed.

  An input / output port 205x is connected to the MPU 201x of the main controller 110x via a bus line 204x composed of an address bus and a data bus. The input / output port 205x includes a payout control device 111x, an audio lamp control device 113x, a first symbol display device 37x, a second symbol display device 82x, various switches 208x including a switch group and a sensor group (not shown), and a specific prize. A solenoid 209x including a large opening solenoid for driving to open / close forward with the lower side of the opening / closing plate of the port 65ax as an axis, a solenoid for driving an electric accessory, and the like is connected.

  In addition, a hall computer 262x that continues to operate for 24 hours is connected to the input / output port 205x. When the power of the pachinko machine 10x is turned off, when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on, the frame opening detection circuit 260x described later temporarily activates the MPU 201x. The MPU 201x that has temporarily started up outputs a pulse signal having a pulse width of about 1 msec to the hall computer 262x via the input / output port 205x. The pulse signal output via the input / output port 205x is stored in the hall computer 262x. Therefore, by analyzing the pulse signal stored in the hall computer 262x, it is possible to detect the opening of the inner frame 12x or the front frame 14x performed while the power of the pachinko machine 10x is turned off. Furthermore, the pachinko machine 10x in which the inner frame 12x or the front frame 14x is opened can be specified.

  The main controller 110x is provided with a frame opening detection circuit 260x that detects opening of the inner frame 12x when the switch SW1x is turned on and detects opening of the front frame 14x when the switch SW2x is turned on. The frame opening detection circuit 260x is connected to a switch SW1x that detects opening of the inner frame 12x and a switch SW2x that detects opening of the front frame 14x. The switch SW1x and the switch SW2x are connected to the frame opening detection circuit 260x via an input / output unit (not shown) that is different from the input / output port 205x (latch circuit, etc.) for inputting and outputting signals. Has been done. Although details will be described with reference to FIG. 43, the frame opening detection circuit 260x is provided with a power supply capacitor CD1x, so that when the power of the pachinko machine 10x is off, the inner frame 12x or the front surface Even if the frame 14x is opened, the frame open detection circuit 260x can detect the opening and temporarily start the MPU 201x. If the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is on, the frame opening detection circuit 260x naturally operates. Here, when the power of the pachinko machine 10x is on, the MPU 201x has already started up, and it is not necessary to start up the MPU 201x by the frame opening detection circuit 260x. At this time, the inner frame 12x or the front frame 14x is released In this case, the frame opening detection circuit 260x outputs only the reset signal SG3bx to the input / output port 205x instead of starting up the MPU 201x by the operations of the multiplexers MP1x to MP3x.

  Also, the frame open detection circuit 260x receives an input from the multiplexer MP1x when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on when the power of the pachinko machine 10x is turned off. The terminal I21x is provided with a power interruption signal output terminal for outputting the power failure signal SG1bx for about 4.4 seconds from when the switch SW1x or the switch SW2x is turned on. The power interruption signal output terminal of the frame opening detection circuit 260x is connected to the input terminal I21x of the multiplexer MP1x in which the output terminal O1x is connected to the NMI terminal of the MPU 201x. The input terminal I11x of the multiplexer MP1x is connected to the power failure monitoring circuit 252x, and the control terminal S1x of the multiplexer MP1x is connected to the power supply unit 251x. Therefore, when the power supply of the pachinko machine 10x is on, a voltage of 5 volts for logic is input from the power supply unit 251x to the control terminal S1x of the multiplexer MP1x. On the other hand, when the power of the pachinko machine 10x is off, the power supply unit 251x does not operate, so no voltage is input to the control terminal S1x of the multiplexer MP1x (the voltage of the control terminal S1x of the multiplexer MP1x is zero volts). Become).

  Here, regarding the relationship between the power failure signal SG1ax output from the power failure monitoring circuit 252x and the power failure signal SG1bx output from the power failure signal output terminal of the frame opening detection circuit 260x, the power of the pachinko machine 10x is turned on. A description will be given separately when the power of the pachinko machine 10x is turned off.

  When the power of the pachinko machine 10x is on, a voltage of 5 volts is input from the power supply unit 251x to the control terminal S1x of the multiplexer MP1x. When a voltage of 5 volts is input to the control terminal S1x, the multiplexer MP1x conducts the input terminal I11x of the multiplexer MP1x and the output terminal O1x of the multiplexer MP1x (the input terminal I21x of the multiplexer MP1x and the output terminal of the multiplexer MP1x) When the power of the pachinko machine 10x is on, the power failure signal SG1ax output from the power failure monitoring circuit 252x can be input to the NMI terminal of the MPU 201x (frame open detection). Even if the power failure signal SG1bx is output from the power interruption signal output terminal of the circuit 260x, it is not input to the NMI terminal of the MPU 201x). On the other hand, when the power of the pachinko machine 10x is turned off, a voltage of zero volts is input from the power supply unit 251x to the control terminal S1x of the multiplexer MP1x. When the voltage of zero volt is input to the control terminal S1x, the multiplexer MP1x conducts the input terminal I21x of the multiplexer MP1x and the output terminal O1x of the multiplexer MP1x (the input terminal I11x of the multiplexer MP1x and the output terminal O1x of the multiplexer MP1x). When the power of the pachinko machine 10x is off, the power failure signal SG1bx output from the power interruption signal output terminal of the frame opening detection circuit 260x can be input to the NMI terminal of the MPU 201x. It becomes. As described above, the multiplexer MP1x outputs a signal to be output to the NMI terminal of the MPU 201x according to the voltage input from the power supply unit 251x to the control terminal S1x, that is, according to the on / off state of the power supply of the pachinko machine 10x. Switch to one of the signals SG1bx.

  Also, the frame open detection circuit 260x receives an input from the multiplexer MP2x when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on when the power of the pachinko machine 10x is turned off. The terminal I22x and the input / output port 205x are provided with a reset signal output terminal for outputting the reset signal SG3bx for about 9.4 seconds from when the switch SW1x or the switch SW2x is turned on. The reset signal output terminal of the frame open detection circuit 260x is connected to the input terminal I22x and the input / output port 205x of the multiplexer MP2x in which the output terminal O2x is connected to the reset terminal of the MPU 201x. The input terminal I12x of the multiplexer MP2x is connected to the reset circuit 254x, and the control terminal S2x of the multiplexer MP2x is connected to the power supply unit 251x. Therefore, when the power of the pachinko machine 10x is on, a logic voltage of 5 volts is input from the power supply unit 251x to the control terminal S2x of the multiplexer MP2x. On the other hand, when the power of the pachinko machine 10x is off, the power supply unit 251x does not operate, so no voltage is input to the control terminal S2x of the multiplexer MP2x (the voltage of the control terminal S2x of the multiplexer MP2x is zero volts). Become).

  Here, regarding the relationship between the reset signal SG3ax output from the reset circuit 254x and the reset signal SG3bx output from the reset signal output terminal of the frame opening detection circuit 260x, the pachinko machine 10x is turned on and the pachinko machine A description will be given separately when the 10x power supply is turned off.

  When the power of the pachinko machine 10x is on, a voltage of 5 volts is input from the power supply unit 251x to the control terminal S2x of the multiplexer MP2x. When a voltage of 5 volts is input to the control terminal S2x, the multiplexer MP2x conducts between the input terminal I12x of the multiplexer MP2x and the output terminal O2x of the multiplexer MP2x (the input terminal I22x of the multiplexer MP2x and the output terminal of the multiplexer MP2x) When the power of the pachinko machine 10x is turned on, the reset signal SG3ax output from the reset circuit 254x can be input to the reset terminal of the MPU 201x (frame open detection circuit). Even if the reset signal SG3bx is output from the 260x reset signal output terminal, it is not input to the reset terminal of the MPU 201x). On the other hand, when the power of the pachinko machine 10x is turned off, a voltage of zero volts is input from the power supply unit 251x to the control terminal S2x of the multiplexer MP2x. When the voltage of zero volt is input to the control terminal S2x, the multiplexer MP2x conducts the input terminal I22x of the multiplexer MP2x and the output terminal O2x of the multiplexer MP1x (the input terminal I12x of the multiplexer MP2x and the output terminal O2x of the multiplexer MP1x). When the power of the pachinko machine 10x is turned off, the reset signal SG3bx output from the reset signal output terminal of the frame opening detection circuit 260x can be input to the reset terminal of the MPU 201x. Become. As described above, the multiplexer MP2x outputs a signal to be output to the reset terminal of the MPU 201x according to the voltage input from the power supply unit 251x to the control terminal S, that is, according to the ON / OFF state of the power supply of the pachinko machine 10x. Switch to one of the signals SG3bx.

  The reset signal output terminal of the frame opening detection circuit 260x is also connected to the input / output port 205x as described above. Therefore, when the inner frame 12x or the front frame 14x is opened, the reset signal SG3bx is output from the reset signal output terminal of the frame open detection circuit 260x to the input / output port 205x regardless of whether the power of the pachinko machine 10x is turned on. Is output. With the reset signal SG3bx output to the input / output port 205x, the MPU 201x can detect the opening of the inner frame 12x or the front frame 14x.

  The frame opening detection circuit 260x has an input terminal I13x of the multiplexer MP3x when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on when the power of the pachinko machine 10x is turned off. A power output terminal is provided for supplying a drive voltage Vbx having a maximum value of about 5 volts for about 9.9 seconds after the switch SW1x or the switch SW2x is turned on. The power output terminal of the frame opening detection circuit 260x is connected to the input terminal I23x of the multiplexer MP3x in which the output terminal O3x is connected to the power terminal of the MPU 201x. The input terminal I13x of the multiplexer MP3x is connected to the power supply unit 251x, and the control terminal S3x of the multiplexer MP3x is also connected to the power supply unit 251x. Therefore, when the power of the pachinko machine 10x is on, a voltage of 5 volts for logic is input from the power supply unit 251x to the control terminal S3x of the multiplexer MP3x. On the other hand, when the power of the pachinko machine 10x is off, the power supply unit 251x does not operate, so no voltage is input to the control terminal S3x of the multiplexer MP3x (the voltage of the control terminal S3x of the multiplexer MP3x is zero volts). Become).

  Here, regarding the relationship between the drive voltage Vax output from the power supply unit 251x and the drive voltage Vbx having a maximum value of about 5 volts output from the power supply output terminal of the frame open detection circuit 260x, the power of the pachinko machine 10x is turned on. A case where the power supply of the pachinko machine 10x is turned off will be described separately.

  When the power of the pachinko machine 10x is on, a voltage of 5 volts is input from the power supply unit 251x to the control terminal S3x of the multiplexer MP3x. When a voltage of 5 volts is input to the control terminal S3x, the multiplexer MP3x conducts between the input terminal I13x of the multiplexer MP3x and the output terminal O3x of the multiplexer MP3x (the input terminal I23x of the multiplexer MP3x and the output terminal of the multiplexer MP3x) Therefore, when the power of the pachinko machine 10x is turned on, the drive voltage Vax output from the power supply unit 251x can be input to the power supply terminal of the MPU 201x (frame open detection circuit). Even if the drive voltage Vbx is output from the power supply output terminal of 260x, it is not input to the power supply terminal of MPU201x). On the other hand, when the power of the pachinko machine 10x is turned off, a voltage of zero volts is input from the power supply unit 251x to the control terminal S3x of the multiplexer MP3x. When the voltage of zero volt is input to the control terminal S3x, the multiplexer MP3x conducts the input terminal I23x of the multiplexer MP3x and the output terminal O3x of the multiplexer MP3x (the input terminal I13x of the multiplexer MP3x and the output terminal O3x of the multiplexer MP3x). Therefore, when the power of the pachinko machine 10x is turned off, the drive voltage Vbx output from the power output terminal of the frame opening detection circuit 260x can be input to the power terminal of the MPU 201x. . Thus, the multiplexer MP3x outputs the voltage output from the power supply unit 251x to the power supply terminal of the MPU 201x according to the voltage input from the power supply unit 251x to the control terminal S1x, that is, according to the on / off state of the power supply of the pachinko machine 10x. The drive voltage Vax is switched to either the output drive voltage Vax or the drive voltage Vbx output from the power supply output terminal of the frame opening detection circuit 260x.

  Although not shown, the output terminal O3x of the multiplexer MP3x is also connected to the input / output port 205x. Therefore, when the power of the pachinko machine 10x is turned off, when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on, it is output from the power output terminal of the frame open detection circuit 260x. The drive voltage Vbx is also supplied to the input / output port 205x.

  As described above, when the power of the pachinko machine 10x is turned on, various signals (power failure signal SG1ax and reset signal SG3ax) from each circuit (power supply unit 251x, power failure monitoring circuit 252x, and reset circuit 254x) of the power supply device 115x. The drive voltage Vax is output to each terminal (NMI terminal, reset terminal, and power supply terminal) of the MPU 201x via the multiplexers MP1x to MP3x. When the power of the pachinko machine 10x is turned on, when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on, only the reset signal SG3bx is input from the frame open detection circuit 260x. The data is output to the output port 205x. On the other hand, when the power of the pachinko machine 10x is turned off, when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on, various signals (power failure signal SG1bx) are output from the frame open detection circuit 260x. The reset signal SG3bx) and the drive voltage Vbx are output to each terminal (NMI terminal, reset terminal, and power supply terminal) of the MPU 201x through the multiplexers MP1x to MP3x for a certain period. Therefore, even if the power of the pachinko machine 10x is turned off, the frame opening detection circuit 260x causes the MPU 201x to temporarily turn on (this embodiment) when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on. In about 9.9 seconds) you can start up.

  As described above, the output terminal O3x of the multiplexer MP3x is also connected to the input / output port 205x, although not shown. Therefore, when the power of the pachinko machine 10x is turned off, when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on, the power output terminal of the frame open detection circuit 260x is connected to the input / output port 205x. The drive voltage Vbx is also output. Accordingly, even when the power of the pachinko machine 10x is turned off, the frame opening detection circuit 260x causes the input / output port 205x to be connected when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on. It can be temporarily started (in this embodiment, about 9.9 seconds).

  The RAM 203x is a stack area that stores the contents of the internal registers of the MPU 201x and the return address of a control program executed by the MPU 201x, and a work area that stores various flags, counters, I / O values, etc. Area). Further, the RAM 203x has an off-in-frame release flag 203ax and an on-in-frame release flag 203bx. Note that the RAM 203x is configured such that the backup voltage is supplied from the power supply device 115x and data can be retained (backed up) even after the power of the pachinko machine 10x is shut off, and all data stored in the RAM 203x is backed up. .

  When the power is shut down due to the occurrence of a power failure or the like, the stack pointer and the value of each register when the power is shut off (including when the power failure occurs, the same applies hereinafter) are stored in the RAM 203x. On the other hand, at the time of power-on (including power-on due to power failure cancellation, the same applies hereinafter), the state of the pachinko machine 10x is restored to the state before power-off based on information stored in the RAM 203x. Writing to the RAM 203x is executed when the power is shut off by the main process (see FIG. 48), and restoration of each value written to the RAM 203x is executed in a startup process (see FIG. 47) when the power is turned on.

  The off-frame open flag 203ax indicates that when the power of the pachinko machine 10x is turned off, the inner frame 12x or the front frame 14x is opened, the switch SW1x or the switch SW2x is turned on, and the MPU 201x is turned on by the frame open detection circuit 260x. This is a flag that is turned on when it is temporarily started up (S112x processing of startup processing of the main controller 110x described later). When the off-in-frame release flag 203ax is turned on, the MPU 201x can detect that the inner frame 12x or the front frame 14x has been opened when the power of the pachinko machine 10x is turned off. When the off-in-frame release flag 203ax is on and the power of the pachinko machine 10x is turned on, the MPU 201x performs notification using the audio output device 226x and the lamp display device 227x. Thereby, the pachinko machine 10x can notify an unspecified number of persons (such as store clerk and player) that the inner frame 12x or the front frame 14x has been opened while the pachinko machine 10x is powered off. On the other hand, the off-in-frame release flag 203ax is turned off when the RAM deletion switch 122x is operated to clear the used RAM area in step S116x of the startup process of the main controller 110x (see FIG. 47). . Therefore, once the off-in-frame release flag 203ax is turned on, the off-in-frame release flag 203ax cannot be turned off unless the RAM deletion switch 122x is operated to clear the used RAM area in the process of S116x. Therefore, when the power of the pachinko machine 10x is turned on, the pachinko machine 10x does not reliably release the inner frame 12x or the front frame 14x when the power of the pachinko machine 10x is turned off. A specific number of persons can be notified.

  When the power of the pachinko machine 10x is turned on, the on-in-frame release flag 203bx releases the inner frame 12x or the front frame 14x, the switch SW1x or the switch SW2x is turned on, and the reset signal of the frame release detection circuit 260x This flag is turned on when the reset signal SG3bx is output from the output terminal to the input / output port 205x (the process of S219x in the main process). When the opened inner frame 12x or the opened front frame 14x is closed, the on-in-frame frame release flag 203bx is turned off in the process of S220x of the main process. When the on-in-frame release flag 203bx is turned on, the MPU 201x can detect that the inner frame 12x or the front frame 14x has been opened when the power of the pachinko machine 10x is turned on. If the on-frame open flag 203bx is turned on when the power of the pachinko machine 10x is turned on, the MPU 201x performs notification using the audio output device 226x and the lamp display device 227x. Thereby, the pachinko machine 10x can notify an unspecified number of persons that the inner frame 12x or the front frame 14x has been opened while the pachinko machine 10x is powered on.

  The payout control device 111x drives the payout motor 216x to perform payout control of prize balls and rental balls. The MPU 211x that is an arithmetic unit has a ROM 212x that stores a control program executed by the MPU 211x, fixed value data, and the like, and a RAM 213x that is used as a work memory or the like.

  The RAM 213x of the payout control device 111x, like the RAM 203x of the main control device 110x, stores a stack area for storing the contents of the internal registers of the MPU 211x, the return address of the control program executed by the MPU 211x, and various flags and counters. And a work area (work area) in which values such as I / O are stored. The RAM 213x is configured to retain (backup) data by being supplied with a backup voltage from the power supply device 115x even after the power of the pachinko machine 10x is cut off, and all data stored in the RAM 213x is backed up. The NMI terminal of the MPU 211x is configured so that the power failure signal SG1ax is input from the power failure monitoring circuit 252x when the power is shut down due to the occurrence of a power failure or the like, and when the power failure signal SG1ax is input to the MPU 211x, The NMI interrupt process (see FIG. 53) as a process is immediately executed.

  An input / output port 215x is connected to the MPU 211x of the payout control device 111x via a bus line 214 composed of an address bus and a data bus. A main controller 110x, a payout motor 216x, a launch controller 112x, and the like are connected to the input / output port 215x. Although not shown, the payout control device 111x is connected with a prize ball detection switch for detecting a prize ball that has been paid out. The prize ball detection switch is connected to the payout control device 111x, but is not connected to the main control device 110x.

  The launch control device 112x controls the ball launch unit 112ax to have a launch strength according to the amount of rotation of the operation handle 51x when an instruction to launch a ball is given by the main control device 110x. The ball launch unit 112ax includes a launch solenoid and an electromagnet (not shown), and the launch solenoid and the electromagnet are permitted to be driven when predetermined conditions are met. Specifically, the operation handle 51x is detected on the condition that the player touches the operation handle 51x by the touch sensor 51ax, and the stop switch 51bx for stopping the ball firing is turned off (not operated). The firing solenoid is excited in accordance with the amount of rotation of 51x, and a ball is launched with a strength according to the amount of operation of the operation handle 51x.

  The sound lamp control device 113x outputs sound in the sound output device (such as a speaker (not shown)) 226x, outputs light on and off in the lamp display devices (such as the lighting units 29x to 33x and the display lamp 34x), and the display control device 114x. It controls the setting of the display mode of the third symbol display device 81x to be performed. The MPU 221x that is an arithmetic unit includes a ROM 222x that stores a control program executed by the MPU 221x, fixed value data, and the like, and a RAM 223x that is used as a work memory or the like.

  An input / output port 225x is connected to the MPU 221x of the sound lamp control device 113x via a bus line 224x including an address bus and a data bus. A main control device 110x, a display control device 114x, an audio output device 226x, a lamp display device 227x, and the like are connected to the input / output port 225x.

  The display control device 114x controls the variation display of the third symbol on the third symbol display device (LCD) 81x. The display control device 114x includes an MPU 231x, a ROM (program ROM) 232x, a work RAM 233x, a video RAM 234x, a character ROM 235x, an image controller 236x, an input port 237x, an output port 238x, and bus lines 239x and 240x. have. The input side of the input port 237x is connected to the output side of the sound lamp controller 113x, and the output side of the input port 237x is connected to the MPU 231x, ROM 232x, work RAM 233x, and image controller 236x. A video RAM 234x and a character ROM 235x are connected to the image controller 236x, and an output port 238x is connected via a bus line 240x. A third symbol display device 81x is connected to the output side of the output port 238x. Even if the pachinko machine 10x is a different model with different winning probability for winning the jackpot and the number of prize balls to be paid out in one jackpot, there is a model with the same specifications as the symbols displayed on the third symbol display device 81x. Therefore, the display control device 114x is made into a common part to reduce the cost.

  The MPU 231x of the display control device 114x controls the display content of the third symbol display device 81x based on the symbol display command input from the sound lamp control device 113x. The ROM 232x is a memory for storing various control programs executed by the MPU 231x and fixed value data. The work RAM 233x is a memory for temporarily storing work data and flags used when various programs are executed by the MPU 231x. The character ROM 235x is a memory that stores data for effects such as symbols (background symbols and third symbols) displayed on the third symbol display device 81x. The video RAM 234x is a memory for storing effect data displayed on the third symbol display device 81x, and the display content of the third symbol display device 81x is changed by rewriting the contents of the video RAM 234x.

  The image controller 236x adjusts the timing of the MPU 231x, the video RAM 234x, and the output port 238x to intervene in reading and writing data, and reads the display data stored in the video RAM 234x at a predetermined timing to read the third symbol display device 81x. Is displayed.

  Next, the frame opening detection circuit 260x will be described with reference to FIG. FIG. 43 is a circuit diagram showing an electrical configuration of the frame opening detection circuit 260x. A frame opening detection circuit 260x that detects opening of the inner frame 12x or opening of the front frame 14x includes a DC power source DC1x that supplies a DC voltage of 12 volts, diodes D1x to D5x, capacitors CD1x to CD4x, and resistors R1x to R5x. Timer IC1x (LMC555 manufactured by National Semiconductor), transistor TR1x, FET1x to FET3x, reset IC2x (BD4843 manufactured by ROHM Co., Ltd.), and NOTIC3x which is a logic negation circuit. is doing.

  In order to detect the opening of the inner frame 12x when the switch SW1x is turned on and to detect the opening of the front frame 14x when the switch SW2x is turned on, the frame opening detection circuit 260x has the above components shown in FIG. Connected according to circuit diagram. Since the switch SW1x and the switch SW2x are connected in parallel and connected to the frame opening detection circuit 260x, if either one of the switches is turned on, the frame opening detection circuit 260x is connected to the inner frame 12x or the front frame. The opening of 14x can be detected.

  The DC power source DC1x is a power source that supplies a DC voltage of 12 volts to the frame opening detection circuit 260x. Power (power) to the DC power source DC1x is supplied from a power supply unit 251x provided in the power supply device 115x through a power supply path (not shown). This DC power supply DC1x is connected to the anode terminal of the diode D1x. One end of a 1F (farad) capacitor CD1x is connected to the cathode terminal of the diode D1x. The other end of the capacitor CD1x is grounded. One end of the capacitor CD1x is connected to one end of the switch SW1x, one end of the switch SW2x, the VDD terminal of the timer IC1x, and the RES terminal of the timer IC1x.

  The capacitor CD1x functions as a rechargeable battery that supplies a DC voltage to the open frame detection circuit 260x when the power supply to the pachinko machine 10x is cut off and a DC voltage of 12 volts is not supplied from the DC power supply DC1x. It is a part.

  The capacitor CD1x is applied to the capacitor 1F (farad) of the capacitor CD1x and the capacitor CD1x when power is supplied to the pachinko machine 10x and a DC voltage of 12 volts is supplied from the DC power source DC1x. The electric charge obtained by the product of the DC voltage (about 11.3 volts obtained by subtracting about 0.7 volts of the voltage drop at the diode D1x from 12 volts supplied from the DC power supply DC1x) is stored.

  On the other hand, the capacitor CD1x is stored in the capacitor CD1x when, for example, the business hours of the amusement hall are over and the power supply to the pachinko machine 10x is cut off and no DC voltage of 12 volts is supplied from the DC power supply DC1x. The electric power based on the generated electric charge is supplied to the open frame detection circuit 260x.

  Accordingly, the frame opening detection circuit 260x operates naturally when power is supplied to the pachinko machine 10x and a DC voltage of 12 volts is supplied from the DC power supply DC1x. Even when the power supply to the pachinko machine 10x is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1x, the inner frame is operated by the power supplied by the capacitor CD1x. The opening of 12x and the opening of the front frame 14x can be detected. In the present embodiment, the capacitor CD1x is used as a component for supplying power to the open frame detection circuit 260x when a DC voltage of 12 volts is not supplied from the DC power supply DC1x. However, the present invention is not limited to this, and the capacitor CD1x may be a secondary battery (rechargeable battery) with a larger amount of stored electricity or a primary battery that does not require charging.

  In addition, the cathode terminal of the diode D1x is connected to one end of the capacitor CD1x, and the diode D1x performs the function of preventing the backflow of current. However, the voltage generated with the power is not applied to the DC power source DC1x, and the DC power source DC1x is not damaged.

  The timer IC 1x is a C-MOS timer, and the inner frame 12x is opened or the front frame 14x is opened by connecting a 200kΩ resistor R1x, a 100kΩ resistor R2x, a 22μF capacitor CD2x, and a 0.1μF capacitor CD3x. It functions as a circuit that detects opening and makes the transistor TR1x conductive for about 4.4 seconds. When the transistor TR1x is turned on, the drive voltage Vbx having a maximum value of about 5 volts is started to be output from the power output terminal, the reset signal SG3bx is started to be output from the reset signal output terminal, and the power failure is output from the power interruption signal output terminal. Output of the signal SG1bx is started.

  The timer IC 1x is supplied with power by the capacitor CD1x, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10x is cut off and no DC voltage of 12 volts is supplied from the DC power supply DC1x. The case where the power is supplied to the pachinko machine 10x and the case where a DC voltage of 12 volts is supplied from the DC power source DC1x is also used. Therefore, of course, the timer IC 1x can operate with a DC voltage of 12 volts or less supplied to the open frame detection circuit 260x when power is supplied to the pachinko machine 10x. Furthermore, since the timer IC 1x is a timer composed of a C-MOS semiconductor, power consumption during operation can be suppressed and long-time operation is possible.

  The VDD terminal of the timer IC1x is a terminal for inputting a DC voltage supplied to the timer IC1x, and is connected to one end of the switch SW1x, one end of the switch SW2x, one end of the capacitor CD1x, and the RES terminal of the timer IC1x. The RES terminal of the timer IC 1x is a terminal for activating a reset function for forcibly stopping the voltage output from the OUT terminal (zero volts) when a pulse signal is input to the RES terminal. However, since the reset function is not used in the open frame detection circuit 260x, the RES terminal of the timer IC 1x is connected to the VDD terminal of the timer IC 1x so that the reset function does not operate. Since the VDD terminal of the timer IC 1x and the RES terminal of the timer IC 1x are connected to one end of the capacitor CD1x as described above, a DC voltage of about 11.3 volts is applied to the VDD terminal and the RES terminal of the timer IC 1x. Applied.

  When the switch SW1x and the switch SW2x are cut off (when the inner frame 12x and the front frame 14x are closed), the TRG terminal of the timer IC1x reduces the voltage output from the OUT terminal of the timer IC1x. When the switch SW1x or the switch SW2x, or both the switch SW1x and the switch SW2x are turned on, either the inner frame 12x or the front frame 14x, or When both the inner frame 12x and the front frame 14x are opened), the voltage output from the OUT terminal of the timer IC 1x is set from about 10.6 volts to zero volts after about 4.4 seconds from the conduction. It is a terminal to do. The TRG terminal of the timer IC 1x is connected to the other end of the resistor R2x.

  The resistor R2x connected to the TRG terminal of the timer IC 1x is connected to the timer R1x when the inner frame 12x or the front frame 14x is opened and the switch SW1x or switch SW2x is turned on (see FIG. 41B). This is a resistor for applying a DC voltage (about 11.3 volts) to the TRG terminal of IC1x. Note that the input impedance of the TRG terminal of the timer IC 1x is sufficiently larger than the resistance value (100 kΩ) of the resistor R2x, so that a voltage drop due to the resistor R2x hardly occurs. Therefore, when the switch SW1x or the switch SW2x becomes conductive, a voltage of about 11.3 volts supplied from one end of the capacitor CD1x is applied to the TRG terminal of the timer IC1x.

  With the above connection, when the switch SW1x and the switch SW2x are in the cut-off state (when the inner frame 12x and the front frame 14x are in the closed state), no voltage is supplied to the resistor R2x, so that the voltage is applied to the TRG terminal of the timer IC 1x. The voltage will be zero volts. At this time, the voltage output from the OUT terminal of the timer IC 1x is about 10.6 volts.

  On the other hand, when either the switch SW1x or the switch SW2x, or both the switch SW1x and the switch SW2x are in a conductive state (either the inner frame 12x or the front frame 14x, or both the inner frame 12x and the front frame 14x Since the voltage is supplied to the resistor R2x (when in the open state), the voltage applied to the TRG terminal of the timer IC 1x is about 11.3 volts, the same as the voltage applied to one end of the capacitor CD1x. At this time, the voltage output from the OUT terminal of the timer IC 1x is about 10.6 for about 4.4 seconds after either the switch SW1x or the switch SW2x, or both the switch SW1x and the switch SW2x are turned on. It becomes a bolt, and then it becomes zero volts.

  Thus, the voltage output from the OUT terminal of the timer IC 1x can be set to either about 10.6 volts or zero volts by the voltage applied to the TRG terminal of the timer IC 1x. When the switch SW1x or the switch SW2x is turned on (the inner frame 12x or the front frame 14x is opened) and the voltage applied to the TRG terminal of the timer IC 1x changes from zero volts to about 11.3 volts, as described above, After about 4.4 seconds from the rise of the voltage, the voltage of about 10.6 volts output from the OUT terminal of the timer IC 1x falls to zero volts. As will be described in detail later, the transistor is determined by the time difference (about 4.4 seconds) between the rising edge of the voltage applied to the TRG terminal of the timer IC 1x and the falling edge of the voltage output from the OUT terminal of the timer IC 1x. TR1x conducts for about 4.4 seconds.

  When the switch SW1x and the switch SW2x are cut off (the inner frame 12x and the front frame 14x are closed) and the voltage applied to the TRG terminal of the timer IC1x becomes zero volts, the OUT terminal of the timer IC1x is about 10.6 volts. When the switch SW1x or the switch SW2x is turned on (the inner frame 12x or the front frame 14x is opened) and the voltage applied to the TRG terminal of the timer IC 1x rises to about 11.3 volts, about This is a terminal for setting the output voltage of about 10.6 volts to zero volts with a delay of 4.4 seconds. This OUT terminal is connected to the gate terminal G of the FET 1x and the gate terminal G of the FET 2x.

  The FET 1x is an N-MOS switching element that switches between conduction and interruption according to the voltage output from the OUT terminal of the timer IC 1x. Connected. The emitter terminal e of the transistor TR1x is connected to one end of the resistor R3x, one end of the resistor R2x, and the input terminal of the NOTIC3x. The collector terminal c of the transistor TR1x is connected to one end of the capacitor CD4x, one end of the resistor R4x, the anode terminal of the diode D3x, and the anode terminal of the diode D4x. The source terminal S of the FET 1x is connected to the cathode terminal of the Zener diode D2x. Note that the anode terminal of the Zener diode D2x is grounded.

  When the voltage output from the OUT terminal of the timer IC 1x is about 10.6 volts, the FET 1x (when the inner frame 12x or the front frame 14x is opened and about 4.4 seconds elapses from the opening) When the inner frame 12x and the front frame 14x are closed), the drain terminal D and the source terminal S of the FET 1x are brought into conduction. On the other hand, when the voltage output from the OUT terminal of the timer IC 1x is zero volts (when the inner frame 12x or the front frame 14x is opened and about 4.4 seconds have elapsed since the opening), the FET 1x The drain terminal D and the source terminal S are turned off.

  Here, three scenes of the operation of the FET 1x and the operation of the transistor TR1x will be described in time series. First, the operation of the FET 1x and the operation of the transistor TR1x from when the inner frame 12x or the front frame 14x is opened until about 4.4 seconds elapse will be described. When the inner frame 12x or the front frame 14x is opened, the switch SW1x or the switch SW2x is in a conductive state. Therefore, until about 4.4 seconds elapse after the inner frame 12x or the front frame 14x is opened (switch The current supplied from the DC power source DC1x or the capacitor CD1x is connected to the drain terminal D and the source terminal S of the FET 1x via the resistor R3x (until approximately 4.4 seconds after the SW1x or the switch SW2x becomes conductive). And flows into the cathode terminal of the Zener diode D2x. Here, the limiting voltage of the Zener diode D2x is about 5.7 volts. When the drain terminal D and the source terminal S of the FET 1x are in a conductive state, the impedance between the drain terminal D and the source terminal S of the FET 1x is about several Ω. Therefore, the voltage at the base terminal b of the transistor TR1x is approximately 5.7 volts, which is substantially the same voltage as the limit voltage of the Zener diode D2x. In addition, when a voltage is generated in the resistor R3x, a bias voltage is applied to the base terminal b of the transistor TR1x and the emitter terminal e of the transistor. Accordingly, the terminal between the emitter terminal e and the collector terminal c of the transistor TR1x is also brought into conduction, and the current supplied from the DC power source DC1x or the capacitor CD1x flows from the emitter terminal e of the transistor TR1x to the collector terminal c. Here, when the base terminal b and the collector terminal c of the transistor TR1x are in a conductive state, the impedance between the base terminal b and the collector terminal c of the transistor TR1x is about several Ω. Accordingly, the voltage at the collector terminal c of the transistor TR1x is approximately the same voltage as the limit voltage of the Zener diode D2x until approximately 4.4 seconds elapse after the inner frame 12x or the front frame 14x is opened. It becomes a bolt. By this operation, a voltage of about 5.7 volts is applied to the capacitor CD4x until about 4.4 seconds elapse after the inner frame 12x or the front frame 14x is opened, and the capacitor CD4x is charged and the power supply A drive voltage Vbx having a maximum value of about 5 volts is started from the output terminal (a voltage obtained by subtracting 0.7 volts from the diode D3x from about 5.7 volts applied to the capacitor CD4x), and from the reset signal output terminal The reset signal SG3bx starts to be output, and the power failure signal SG1bx starts to be output from the power interruption signal output terminal.

  Next, the operation of the FET 1x and the operation of the transistor TR1x when the inner frame 12x or the front frame 14x is opened and about 4.4 seconds have elapsed from the opening will be described. When the inner frame 12x or the front frame 14x is opened and about 4.4 seconds have elapsed since the opening, the drain terminal D and the source terminal S of the FET 1x are cut off. Therefore, even if the switch SW1x or the switch SW2x is in a conductive state, the current supplied from the DC power source DC1x or the capacitor CD1x does not flow into the resistor R3x, and the voltage generated in the resistor R3x becomes zero. Therefore, the conduction between the emitter terminal e and the collector terminal c of the transistor TR1x is cut off. Therefore, when the inner frame 12x or the front frame 14x is opened and about 4.4 seconds have elapsed since the opening, the voltage at the collector terminal c of the transistor TR1x becomes zero volts. By this operation, the inner frame 12x or the front frame 14x is opened, and when about 4.4 seconds have elapsed from the opening, the voltage applied to the capacitor CD4x becomes zero volts, and the electric power stored in the capacitor CD4x is discharged. .

  Finally, the operation of the FET 1x and the operation of the transistor TR1x when the inner frame 12x and the front frame 14x are closed will be described. When the inner frame 12x and the front frame 14x are closed, the voltage output from the OUT terminal of the timer IC 1x is approximately 10.6 volts, and the drain terminal D and the source terminal S of the FET 1x are conducted, but the switch SW1x and the switch SW2x is in a cut-off state. Therefore, when the inner frame 12x and the front frame 14x are closed, the drain terminal D and the source terminal S of the FET 1x become conductive, but no current is supplied from the DC power source DC1x or the capacitor CD1x, and the transistor TR1x The voltage between the base terminal b and the emitter terminal e is zero volts. Thereby, conduction between the emitter terminal e and the collector terminal c of the transistor TR1x is cut off. Therefore, when the inner frame 12x and the front frame 14x are closed, no voltage is applied to the collector terminal c of the transistor TR1x, and the voltage at the collector terminal c of the transistor TR1x is zero volts. With this operation, even when the inner frame 12x and the front frame 14x are closed, the voltage applied to the capacitor CD4x becomes zero volts, and the electric power stored in the capacitor CD4x is discharged.

  Returning to the description of FIG. Capacitor CD4x charges the power supplied via transistor TR1x, discharges the charged power, and has a capacitance value 1F that supplies power to the power supply output terminal and reset IC 2x excluding the power interruption signal output terminal. Farad) capacitor. One end of the capacitor CD4x is connected to the collector terminal c of the transistor TR1x, one end of the resistor R4x, the anode terminal of the diode D3x, and the anode terminal of the diode D4x. On the other hand, the other end of the capacitor CD4x is grounded.

  By this connection, the capacitor CD4x is electrically connected to the drain terminal D and the source terminal S of the FET 1x and the emitter terminal of the transistor TR1x until about 4.4 seconds have elapsed after the inner frame 12x or the front frame 14x is opened. e and the collector terminal c are electrically connected), so that electric power supplied from the DC power source DC1x or the capacitor CD1x via the transistor TR1x is stored. In the capacitor CD4x, when the inner frame 12x or the front frame 14x is opened, and about 4.4 seconds have elapsed since the opening, the drain terminal D and the source terminal S of the FET 1x are cut off, and the emitter terminal of the transistor TR1x e and the collector terminal c are cut off), the stored power is discharged to supply power to the power output terminal and the reset IC 2x. Note that when the drain terminal D and the source terminal S of the FET 1x are in the cut-off state, naturally, the conduction between the drain terminal D and the source terminal S of the FET 2x is also cut-off, so that the current accompanying the power discharged by the capacitor CD4x is reduced. It does not flow into the resistor R5x. Therefore, the voltage accompanying the power discharged from the capacitor CD4x is not output to the power interruption signal output terminal. Therefore, the capacitor CD4x does not supply power to the power interruption signal output terminal, but supplies power to the power supply output terminal and the reset IC 2x.

  Note that the discharge time until the power stored in the capacitor CD4x becomes zero is the input impedance of the input terminal I23x of the multiplexer MP3x connected to the power supply output terminal and the power supply terminal of the MPU 201x connected to the output terminal O3x of the multiplexer MP3x. Input impedance, input impedance of the input terminal IN of the reset IC 2x, input impedance of the input terminal I22x of the multiplexer MP2x connected to the reset signal output terminal, and input impedance of the reset terminal of the MPU 201x connected to the output terminal O2x of the multiplexer MP2x Etc. are determined. In the present embodiment, when the capacitor CD4x is fully charged, the discharge time until the fully charged power becomes zero is set to about 20 seconds. However, when the capacitor CD4x is fully charged, the discharge time until the fully charged power becomes zero is shorter than about 20 seconds or longer than about 20 seconds by adjusting the above impedance. May be set.

  The discharge of the electric power stored in the capacitor CD4x is also caused when the inner frame 12x or the front frame 14x is opened, about 4.4 seconds have passed since the opening, and the inner frame 12x and the front frame 14x are closed. continue. When the inner frame 12x and the front frame 14x are closed, the voltage output from the OUT terminal of the timer IC 1x is about 10.6 volts, and the drain terminal D and the source terminal S of the FET 1x are conducted. The switches SW1x and SW2x are in the cut-off state. Therefore, when the inner frame 12x and the front frame 14x are closed, the drain terminal D and the source terminal S of the FET 1x conduct, but no current is supplied from the DC power source DC1x or the capacitor CD1x, and the base of the transistor TR1x The voltage between the terminal b and the emitter terminal e is zero volts. Accordingly, since the emitter terminal e and the collector terminal c of the transistor TR1x are cut off, the inner frame 12x or the front frame 14x is opened, and the capacitor CD4x is stored in the same manner as when about 4.4 seconds have elapsed since the opening. The discharged power is discharged to supply power to the power output terminal and the reset IC 2x. Here, when the inner frame 12x and the front frame 14x are closed, the drain terminal D and the source terminal S of the FET 2x are in a conductive state as in the FET 1x, and the power failure signal SG1bx is output from the power interruption signal output terminal. In this case, since the drain terminal D and the source terminal S of the FET 3x described later are in a conductive state, the power failure signal SG1bx is not output from the power interruption signal output terminal. This description will be described in detail later.

  In addition, when the electric power stored in the capacitor CD4x becomes zero, the discharge is naturally terminated (stopped). Thereby, the power supplied from the capacitor CD4x to the power output terminal and the reset IC 2x is also stopped.

  The FET 2x is an N-MOS switching element that switches between conduction and cutoff according to the voltage output from the OUT terminal of the timer IC 1x, like the FET 1x, and the drain terminal D of the FET 2x is connected to the other end of the resistor R4x of 100 kΩ. The One end of the resistor R4x is connected to one end of the capacitor CD4x, the collector terminal c of the transistor TR1x, the anode terminal of the diode D3x, and the anode terminal of the diode D4x. The source terminal S of the FET 2x is connected to the anode terminal of the backflow preventing diode D5x and one end of the 100 MΩ resistor R5x. The other end of the resistor R5x is grounded. The cathode terminal of the diode D5x is connected to the power interruption signal output terminal.

  When the voltage output from the OUT terminal of the timer IC 1x is about 10.6 volts, the FET 2x (when the inner frame 12x or the front frame 14x is opened and about 4.4 seconds have elapsed since the opening) When the inner frame 12x and the front frame 14x are closed), the drain terminal D and the source terminal S of the FET 2x are brought into conduction. On the other hand, when the voltage output from the OUT terminal of the timer IC 1x is zero volts, the FET 2x (when the inner frame 12x or the front frame 14x is opened and approximately 4.4 seconds elapses), the FET 2x The drain terminal D and the source terminal S are turned off.

  NOTIC3x is a logic negation circuit that applies a voltage to the gate terminal G of the FET3x. The NOTIC 3x has an input terminal connected to the other end of the switch SW1x, the other end of the switch SW2x, one end of the resistor R1x, one end of the resistor R2x, and one end of the resistor R3x. Further, the power supply terminal of the NOTIC 3x is connected to one end of the capacitor CD1x, which is not shown. Therefore, when the inner frame 12x or the front frame 14x is opened, the switch SW1x or the switch SW2x is turned on, and a voltage of about 11.3 volts is applied to the input terminal of the NOTIC3x, zero volts is applied from the output terminal of the NOTIC3x. Is output. On the other hand, when the inner frame 12x and the front frame 14x are closed, the switch SW1x and the switch SW2x are cut off, and zero volt is applied to the input terminal of the NOTIC3x, a voltage of about 11.3 volts is generated from the output terminal of the NOTIC3x. Is output.

  The FET 3x is an N-MOS switching element that controls the power failure signal SG1bx output from the power interruption signal output terminal. The gate terminal G of the FET 3x is connected to the output terminal of the NOTIC 3x. The drain terminal D of the FET 3x is connected to the anode terminal of the diode D5x, and the source terminal S of the FET 3x is grounded. Therefore, when zero volt is output from the output terminal of the NOTIC 3x, that is, when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x becomes conductive, the drain terminal D and the source terminal S of the FET 3x. Is interrupted. Therefore, when the inner frame 12x or the front frame 14x is opened, the power failure signal SG1bx can be output from the power interruption signal output terminal. On the other hand, when a voltage of about 11.3 volts is output from the output terminal of the NOTIC 3x, that is, when the inner frame 12x and the front frame 14x are closed and the switch SW1x and the switch SW2x are cut off, the drain of the FET 3x The terminals D and the source terminal S are electrically connected. Therefore, when the inner frame 12x or the front frame 14x is closed, the power failure signal SG1bx cannot be output from the power interruption signal output terminal.

  Here, the operation of the FET 2x and the FET 3x will be described in chronological order as in the case of the FET 1x. First, the operation of the FET 2x and the FET 3x from when the inner frame 12x or the front frame 14x is opened until about 4.4 seconds have elapsed will be described. When the inner frame 12x or the front frame 14x is opened, the switch SW1x or the switch SW2x is in a conductive state. Therefore, until about 4.4 seconds elapse after the inner frame 12x or the front frame 14x is opened (switch The current supplied from the DC power source DC1x or the capacitor CD1x is connected to the drain terminal D of the FET 2x and the source of the FET 2x through the resistor R4x (until approximately 4.4 seconds after the SW1x or the switch SW2x becomes conductive). It passes between the terminals S and flows into the resistor R5x. At this time, as described above, since the voltage of the collector terminal c of the transistor TR1x is about 5.7 volts, the voltage applied to one end of the resistor R4x is also about 5.7 volts. Here, when the drain terminal D and the source terminal S of the FET 2x are in the conductive state, the impedance between the drain terminal D and the source terminal S of the FET 2x is about several Ω. On the other hand, since the inner frame 12x or the front frame 14x is open, the conduction between the drain terminal D and the source terminal S of the FET 3x is interrupted. Therefore, the voltage of about 5.7 volts applied to one end of the resistor R4x is divided by the resistor R4x and the resistor R5x. The resistance ratio between the resistor R4x and the resistor R5x is 1: 1000. Therefore, until about 4.4 seconds have passed after the inner frame 12x or the front frame 14x is opened, the voltage applied to the resistor R5x is approximately 5.7 volts, which is substantially the same voltage as the limit voltage of the Zener diode D2x. It becomes. By this operation, the power failure signal SG1bx is output from the power interruption signal output terminal until about 4.4 seconds have elapsed after the inner frame 12x or the front frame 14x is opened. At this time, the power failure signal SG1bx outputted from the power interruption signal output terminal is about 5.0 volts obtained by subtracting about 0.7 volts from the diode D5x from about 5.7 volts applied to the resistor R5x. It becomes.

  Further, until approximately 4.4 seconds have elapsed after the inner frame 12x or the front frame 14x is opened (until approximately 4.4 seconds have elapsed since the switch SW1x or the switch SW2x is turned on), the DC power supply DC1x Alternatively, the voltage supplied from the capacitor CD1x is applied to the power supply signal output terminal via the diode D3x and also applied to the input terminal IN of the reset IC 2x via the diode D4x. Accordingly, the drive voltage is output from the power signal output terminal, and the reset signal SG3bx is also output from the reset signal output terminal.

  Next, the operation of the FET 2x and the FET 3x when the inner frame 12x or the front frame 14x is opened and about 4.4 seconds have elapsed since the opening is described. When the inner frame 12x or the front frame 14x is opened and about 4.4 seconds have elapsed since the opening, the drain terminal D and the source terminal S of the FET 2x are cut off. At this time, as described above, since the conduction between the drain terminal D and the source terminal S of the FET 1x is also cut off, even if the switch SW1x or the switch SW2x is in the conduction state, the emitter terminal e and the collector terminal of the transistor TR1x c is interrupted. Thereby, the voltage supply from the DC power source DC1x or the capacitor CD1x is stopped. By stopping the voltage supply, the capacitor CD4x starts to be discharged. Here, if the drain terminal D and the source terminal S of the FET 2x are cut off, even if the conduction between the drain terminal D and the source terminal S of the FET 3x is cut off, the voltage associated with the discharge of the capacitor CD4x is an electric current. Not applied to the disconnect signal output terminal. Therefore, the power failure signal SG1bx output from the power interruption signal output terminal is stopped. On the other hand, the voltage accompanying the discharge of the capacitor CD4x is applied to the power supply output terminal via the diode D3x and also applied to the input terminal IN of the reset IC 2x via the diode D4x. By this operation, the inner frame 12x or the front frame 14x is opened, and when about 4.4 seconds have passed since the opening, the power failure signal SG1bx output from the power interruption signal output terminal is stopped and output from the power output terminal. The drive voltage Vbx and the reset signal SG3bx output from the reset signal output terminal are continuously output. When the electric power stored in the capacitor CD4x becomes zero due to discharge, the output of the drive voltage Vbx and the reset signal SG3bx output from the power supply output terminal is stopped.

  Finally, the operation of the FET 2x and the FET 3x when the inner frame 12x and the front frame 14x are closed will be described. When the inner frame 12x and the front frame 14x are closed, the voltage output from the OUT terminal of the timer IC 1x is about 10.6 volts, and the drain terminal D and the source terminal S of the FET 2x are conducted, but the switch SW1x and the switch SW2x is in a cut-off state. Therefore, when the inner frame 12x and the front frame 14x are closed, the drain terminal D and the source terminal S of the FET 2x are electrically connected, but no power is supplied from the DC power source DC1x or the capacitor CD1x, and the capacitor CD4x Discharging continues. Here, since the drain terminal D and the source terminal S of the FET 2x become conductive, a path is generated in which a current accompanying the discharge of the capacitor CD4x flows into the resistor R5x. However, in this case, since the inner frame 12x and the front frame 14x are closed, the terminal between the drain terminal D and the source terminal S of the FET 3x is also conductive. When the drain terminal D and the source terminal S of the FET 3x become conductive, the impedance between the drain terminal D and the source terminal S of the FET 3x is about several Ω, which is higher than the resistance value 100 MΩ of the resistor R5x. The value is sufficiently small. Therefore, when the inner frame 12x and the front frame 14x are closed, the drain terminal D and the source terminal S of the FET 2x are brought into conduction, and a path through which a current accompanying the discharge of the capacitor CD4x flows into the resistor R5x is generated. Since the current accompanying the discharge of CD4x flows into the drain terminal D of the FET 3x, no current flows into the resistor R5x. Thereby, the power failure signal SG1bx is not output from the power interruption signal output terminal. Therefore, when the inner frame 12x and the front frame 14x are closed, the power failure signal SG1bx output from the power interruption signal output terminal is stopped, while the drive voltage Vbx output from the power output terminal and the reset signal output terminal The reset signal SG3bx output from is continuously output. As described above, when the power stored in the capacitor CD4x becomes zero due to discharge, the output of the drive voltage Vbx and the reset signal SG3bx output from the power supply output terminal is stopped).

  If the voltage input to the input terminal IN exceeds 4.3 volts, the reset IC 2x outputs the voltage input to the input terminal IN as it is from the output terminal OUT, while the voltage input to the input terminal IN is When the voltage is 4.3 volts or less, the reset semiconductor circuit stops voltage output from the output terminal OUT (sets the output voltage of the output terminal OUT to zero volts). The input terminal IN of the reset IC 2x is connected to the cathode terminal of the backflow prevention diode D4x. The anode terminal of the diode D4x is connected to the anode terminal of the backflow preventing diode D3x, and is connected to one end of the resistor R4x, one end of the capacitor CD4x, and the collector terminal c of the transistor TR1x. The cathode terminal of the diode D3x is connected to the power supply output terminal. The output terminal OUT of the reset IC 2x is connected to the reset signal output terminal.

  Although the output terminal OUT of the reset IC 2x is directly connected to the reset signal output terminal, a backflow preventing diode may be connected to the output terminal OUT of the reset IC 2x. In this case, the anode terminal of the backflow prevention diode may be connected to the output terminal OUT of the reset IC 2x, and the cathode terminal of the backflow prevention diode may be connected to the reset signal output terminal.

  Here, the operation of the reset IC 2x will be described. When the inner frame 12x or the front frame 14x is opened and approximately 4.4 seconds have elapsed since the opening, the capacitor CD4x discharges the stored power and starts supplying power to the power supply output terminal and the reset IC 2x. Since the power supplied from the capacitor CD4x decreases with the discharge time, the voltage generated by the discharge of the capacitor CD4x also decreases with the discharge time. Since only the backflow prevention diode D3x is connected between the power supply output terminal and the capacitor CD4x, the voltage (drive voltage Vbx) output to the power supply output terminal is generated by the discharge of the capacitor CD4x. The voltage drops from the voltage by the forward voltage of the diode D3x (about 0.7 volts). On the other hand, the reset IC 2x is connected between the reset signal output terminal and the capacitor CD4x in addition to the connection of the diode D4x for preventing backflow. As a result, the voltage output to the reset signal output terminal (reset signal SG3bx) is a voltage obtained by dropping the voltage generated by the discharge of the capacitor CD4x by the forward voltage of the diode D4x (about 0.7 volts). When the voltage exceeds 3 volts, that is, when the voltage input to the input terminal IN of the reset IC 2x exceeds about 4.3 volts, the input voltage itself is the same. On the other hand, when the voltage dropped by the forward voltage of the diode D4x from the voltage generated by the discharge of the capacitor CD4x is about 4.3 volts or less, that is, the voltage input to the input terminal IN of the reset IC 2x. Is about 4.3 volts or less, the voltage output to the reset signal output terminal is zero volts.

  Thus, if the voltage input to the input terminal IN exceeds about 4.3 volts, the reset IC 2x outputs the voltage input to the input terminal IN as it is from the output terminal OUT and outputs it to the reset signal output terminal. While the voltage is output (the reset signal SG3bx is output), when the voltage input to the input terminal IN becomes about 4.3 volts or less, the voltage output from the output terminal OUT is stopped and the reset signal output terminal is output. The output voltage is set to zero volts (the reset signal SG3bx is stopped). Since the voltage (drive voltage Vbx) output to the power supply output terminal can be 4.3 volts or less, the voltage generated by the discharge of the capacitor CD4x after the voltage output from the reset signal output terminal becomes zero volts. Is continuously output until the voltage reaches zero volts.

  Here, in order to terminate the MPU 201x normally, when the driving voltage Vbx of about 5 volts is supplied to the power supply terminal of the MPU 201x, the MPU 201x is first reset during the period of 10 clocks with the operation clock of the MPU 201x. The reset signal SG3bx input to the terminal is stopped to make it impossible to perform arithmetic processing, and then the drive voltage supplied to the power supply terminal of the MPU 201x is set to about 4.0 volts or less to make the operation impossible. There is a need. For example, if the operation clock of the MPU 201x is 100 MHz, in order to terminate the MPU 201x normally, when the 5V drive voltage Vbx is supplied to the power terminal of the MPU 201x, the MPU 201x is first input to the reset terminal of the MPU 201x. The reset signal SG3bx is stopped for at least 100 nsec so that the arithmetic processing cannot be performed, and then the drive voltage Vbx supplied to the power supply terminal of the MPU 201x is set to about 4.0 volts or less to be inoperable. There is a need to. In order to realize this, the frame opening detection circuit 260x first sets the voltage input to the input terminal IN of the reset IC 2x to about 4.3 volts or less, and stops the reset signal SG3bx output from the reset signal output terminal. As a result, the MPU 201x is made inoperable, and thereafter the drive voltage Vbx output from the power supply output terminal is set to about 4.0 volts or less to make the MPU 201x inoperable. Here, in the frame open detection circuit 260x, after the reset signal SG3bx output from the reset signal output terminal is stopped, the drive voltage Vbx output from the power output terminal is about 4.0 volts or less. A period of 0.5 seconds is secured. Thus, even when the MPU 201x is temporarily started up by the frame opening detection circuit 260x when the power of the pachinko machine 10x is off, the MPU 201x that has been started up is normally terminated by the frame opening detection circuit 260x. Can do.

  In addition, when the voltage input to the input terminal IN of the reset IC 2x exceeds 4.3 volts, when the voltage is input to the input terminal IN of the reset IC 2x, it is delayed by about 40 μs from the input of the voltage. Thus, a voltage is output from the output terminal OUT. Due to the delay characteristic of the reset IC 2x, the reset signal SG3bx output to the reset signal output terminal is output with a delay of about 40 μs from the drive voltage Vbx output to the power supply output terminal.

  Here, in order to start up the MPU 201x normally, first, the driving voltage Vbx of about 5 volts is supplied to the power supply terminal of the MPU 201x to make the MPU 201x operable, and then at least 10 operation clocks of the MPU 201x. After that, it is necessary to input a reset signal SG3bx to the reset terminal of the MPU 201x so that the arithmetic processing can be executed. For example, in order to start up the MPU 201x whose operation clock is 100 MHz normally, first, supply the drive voltage Vbx of 5 volts to the power terminal of the MPU 201x to make the MPU 201x operable, and then at least 100 ns After that, it is necessary to input a reset signal SG3bx to the reset terminal of the MPU 201x so that the arithmetic processing can be executed. In order to realize this, the frame open detection circuit 260x first outputs a drive voltage Vbx of about 5 volts from the power supply output terminal, and outputs a reset signal SG3bx from the reset signal output terminal about 40 μs after the output. Thus, even when the MPU 201x is temporarily started up by the frame opening detection circuit 260x when the power of the pachinko machine 10x is off, the startup can be performed normally.

  The TH terminal of the timer IC 1x is a terminal that measures the voltage applied to the TH terminal, and is connected to the other end of the resistor R1x, one end of the capacitor CD2x, and the DCH terminal of the timer IC 1x. The DCH terminal of the timer IC 1x is a voltage (about 7.5 volts) that is 2/3 of the DC voltage (about 11.3 volts) input to the VDD terminal of the timer IC 1x when the voltage applied to the TH terminal of the timer IC 1x. In this case, the terminal switches the impedance of the DCH terminal from an infinite state to a zero state. When the impedance of the DCH terminal becomes zero (ground state), a voltage cannot be applied to the capacitor CD2x. On the other hand, when the impedance of the DCH terminal becomes infinite, a voltage can be applied to the capacitor CD2x.

  The resistor R1x and the capacitor CD2x connected to the TH terminal of the timer IC1x and the DCH terminal of the timer IC1x have the inner frame 12x or the front frame 14x opened based on the time constant that is the product of the resistance value of the resistor R1x and the capacitor CD2x. In this case, it is a part for determining the period until the voltage of about 10.6 volts output from the OUT terminal of the timer IC 1x is switched to zero volts to about 4.4 seconds. One end of the resistor R1x is connected to the other end of the switch SW1x, the other end of the switch SW2x, one end of the resistor R2x, an input terminal of the NOTIC3x, one end of the resistor R3x, and an emitter terminal e of the transistor TR1x. The other end of the resistor R1x is connected to the TH terminal of the timer IC1x, the DCH terminal of the timer IC1x, and one end of the capacitor CD2x. The other end of the capacitor CD2x is grounded.

  Here, the resistor R1x and the capacitor CD2x will be described together with the TRG terminal of the timer IC1x, the TH terminal of the timer IC1x, the DCH terminal of the timer IC1x, and the OUT terminal of the timer IC1x.

  When the inner frame 12x and the front frame 14x are in the closed state (when the switch SW1x and the switch SW2x are in the cut-off state), no voltage is supplied to the resistor R1x, so the voltage applied to the TH terminal of the timer IC 1x is zero volts (about 7.5 volts). Therefore, the impedance of the DCH terminal of the timer IC 1x is set to an infinite state. Therefore, a voltage can be applied to the capacitor CD2x, and the capacitor CD2x is in a chargeable state (a state in which charge can be stored). However, when the switch SW1x and the switch SW2x are cut off, the connection between one end of the capacitor CD1x and the resistor R1x is cut off, so that no voltage is applied to the capacitor CD2x, and the voltage applied to the capacitor CD2x is zero volts. It becomes. Thus, the capacitor CD2x is in a chargeable state, but is not charged. At this time, the voltage at the OUT terminal of the timer IC 1x is about 10.6 volts, and there is a gap between the drain terminal D and the source terminal S of the FET 1x and between the drain terminal D and the source terminal S of the FET 2x. Conducted. However, since the switch SW1x and the switch SW2x are in the cut-off state, no voltage is generated in the resistor R3x (between the base terminal b and the emitter terminal e of the transistor TR1x), and the emitter terminal e and the collector terminal c of the transistor TR1x. And is cut off. Moreover, since the inner frame 12x and the front frame 14x are closed, the terminals between the drain terminal D and the source terminal D of the FET 3x are in a conductive state. Therefore, the power from the capacitor CD4x can be supplied to the power output terminal and the reset IC 2x except for the power interruption signal output terminal (when the power stored in the capacitor CD4x is zero due to the discharge, the power Supply is not performed).

  Next, when the inner frame 12x or the front frame 14x is opened (see FIG. 41B) and the switch SW1x or the switch SW2x is turned on, the voltage applied to the TRG terminal of the timer IC 1x is from zero volts. Switch to approximately 11.3 volts. At this time, the voltage at the OUT terminal of the timer IC 1x is about 10.6 volts, and the terminal between the drain terminal D and the source terminal S of the FET 1x and the terminal between the drain terminal D and the source terminal S of the FET 2x are conducted. is doing. A voltage is generated in the resistor R3x (between the base terminal b and the emitter terminal e of the transistor TR1x), and the emitter terminal e and the collector terminal c of the transistor TR1x are conducted. As a result, a voltage of about 5.7 volts is generated at the collector terminal c of the transistor TR1x, and the generated voltage becomes about 5.0 volts via the diode D3x and is output to the power output terminal. The voltage of about 5.7 volts generated at the collector terminal c of the transistor TR1x becomes about 5.0 volts via the diode D4x and the reset IC 2x, and is output to the reset signal output terminal. In addition, since the inner frame 12x or the front frame 14x is in an open state and the drain terminal D and the source terminal D of the FET 3x are cut off, about 5.7 volts generated at the collector terminal c of the transistor TR1x. The voltage becomes approximately 5.0 volts via the diode D5x and is output to the power interruption signal output terminal. Further, charging of the capacitor CD4x is started by a voltage of about 5.7 volts generated at the collector terminal c of the transistor TR1x.

  At the same time as the voltage applied to the TRG terminal of the timer IC 1x is switched from zero volts to about 11.3 volts, the voltage is applied to the capacitor CD2x, and charging of the capacitor CD2x is started. At this time, the voltage applied to the TH terminal of the timer IC 1x starts to rise.

  The voltage at the OUT terminal of the timer IC1x is 2 / of the voltage (approximately 11.3 volts) input to the VDD terminal of the timer IC1x (the voltage applied to the capacitor CD2x) applied to the TH terminal of the timer IC1x. Continue to maintain about 10.6 volts until equal to a voltage of 3, ie, about 7.5 volts. When the voltage applied to the TH terminal of the timer IC 1x (the voltage applied to the capacitor CD2x) rises and becomes equal to about 7.5 volts, the impedance of the DCH terminal of the timer IC 1x is changed from the infinite state to the zero state (ground To the ( Then, the voltage applied to the capacitor CD2x becomes a zero volt state, and the electric charge stored in the capacitor CD2x is discharged. As a result, the voltage applied to the TH terminal of the timer IC 1x is switched from about 7.5 volts to zero volts. By switching the voltage applied to the TH terminal of the timer IC 1x, the voltage at the OUT terminal of the timer IC 1x switches from about 10.6 volts to zero volts. Then, the conduction between the drain terminal D and the source terminal S of the FET 1x and between the drain terminal D and the source terminal S of the FET 2x are cut off, and the resistor R3x (the base terminal b and the emitter terminal e of the transistor TR1x) The voltage generated between the terminals is zero volts. Thereby, the capacitor CD4x discharges the stored power and supplies the power to the power output terminal and the reset IC 2x.

  In this way, when the inner frame 12x or the front frame 14x is in an open state and the switch SW1x or the switch SW2x is in a conductive state (see FIG. 41B), the signal is output from the OUT terminal of the timer IC 1x. A period until the voltage of about 10.6 volts is switched to zero volts, that is, a period until the voltage applied to the TH terminal of the timer IC 1x (voltage applied to the capacitor CD2x) is changed from zero volts to about 7.5 volts. Based on the time constant which is the product of the resistance value of the resistor R1x and the capacitance of the capacitor CD2x, it is determined to be about 4.4 seconds. Then, when the inner frame 12x or the front frame 14x is opened, the frame open detection circuit 260x outputs a voltage to the power output terminal, the reset signal output terminal, and the power interruption signal output terminal for about 4.4 seconds. To do. When about 4.4 seconds elapse after the inner frame 12x or the front frame 14x is opened, the frame open detection circuit 260x applies a voltage of about 10.6 volts output from the OUT terminal of the timer IC 1x. Switching to zero volts cuts off the conduction between the emitter terminal e and the collector terminal c of the transistor TR1x, stops the voltage output to the power interruption signal output terminal, and starts discharging the capacitor CD4x. As a result, the frame open detection circuit 260x causes the power source output terminal to exclude the power interruption signal output terminal by discharging the capacitor CD4x after about 4.4 seconds have elapsed since the inner frame 12x or the front frame 14x is opened. And outputs a voltage to the reset signal output terminal. As described above, when the voltage input to the input terminal IN of the reset IC 2x becomes about 4.3 volts or less due to the discharge of the capacitor CD4x, the reset IC 2x outputs the voltage output from the output terminal OUT, that is, the reset signal output. Set the terminal voltage to zero volts. On the other hand, the voltage at the power supply output terminal is output until the discharge by the capacitor CD4x stops. Therefore, when about 4.4 seconds elapse after the inner frame 12x or the front frame 14x is opened, the frame open detection circuit 260x first outputs the voltage (power failure signal SG1bx) output to the power interruption signal output terminal. Next, the voltage output to the reset signal output terminal (reset signal SG3bx) is stopped, and finally, the voltage output to the power supply output terminal (drive voltage Vbx) is stopped. Therefore, even when the MPU 201x is temporarily started up when the power of the pachinko machine 10x is off, the frame opening detection circuit 260x can normally end the started up MPU 201x.

  In addition, after about 4.4 seconds have passed since the inner frame 12x or the front frame 14x is opened, the inner frame 12x and the front frame 14x are changed from the opened state to the closed state (the switch SW1x and the switch SW2x are cut off from the conductive state). In other words, when the voltage applied to the TRG terminal of the timer IC 1x switches from about 11.3 volts to zero volts, the voltage at the OUT terminal of the timer IC 1x switches from zero volts to about 10.6 volts. In this state, as described above, the terminal between the drain terminal D and the source terminal S of the FET 1x and the terminal between the drain terminal D and the source terminal S of the FET 2x are conductive, but the switch SW1x and the switch SW2x are cut off. Therefore, no power is supplied from the DC power supply DC1x or the capacitor CD1x, and the discharge state of the capacitor CD4x continues. When the inner frame 12x or the front frame 14x is in a closed state, the drain terminal D and the gate terminal S of the FET 3x are electrically connected, so that the voltage due to the discharge of the capacitor CD4x is the power output terminal and the power output terminal excluding the power interruption signal output terminal. The voltage is applied to the input terminal IN of the reset IC 2x.

  Here, when the power of the pachinko machine 10x is off, the inner frame 12x or the front frame 14x is opened, and before the elapse of about 4.4 seconds, the inner frame 12x and the front frame 14x are closed, When the switch SW1x and the switch SW2x are cut off, the voltage at the OUT terminal of the timer IC 1x remains at about 10.6 volts without switching to zero volts. However, also in this case, the frame opening detection circuit 260x can stop the power failure signal SG1bx, then stop the reset signal SG3bx, and finally stop the drive voltage Vbx. This case will be described. First, when the inner frame 12x or the front frame 14x is in an open state and the switch SW1x or the switch SW2x is turned on, the frame open detection circuit 260x has a power output terminal, a reset signal output terminal, and a power interruption signal output, as described above. A voltage is output to the terminal and the capacitor CD4x is charged. When the inner frame 12x and the front frame 14x are closed within about 4.4 seconds from the open state, the switch SW1x and the switch SW2x are switched from the conductive state to the cut-off state, and thus the emitter terminal e and the collector terminal c of the transistor TR1x. And the discharge of the capacitor CD4x is started. Here, since the inner frame 12x and the front frame 14x are in the closed state, the drain terminal D and the source terminal S of the FET 3x are electrically connected. Therefore, when the inner frame 12x and the front frame 14x are in the closed state, the voltage due to the discharge of the capacitor CD4x is not applied to the power interruption signal output terminal, so that the power failure signal SG1bx is stopped. On the other hand, the voltage generated by discharging the capacitor CD4x is applied to the power supply output terminal and the input terminal IN of the reset IC 2x. Thereafter, the voltage accompanying the discharge of the capacitor CD4x decreases with time, the reset signal SG3bx output from the reset signal output terminal is stopped, and finally the drive voltage Vbx output from the power supply output terminal is stopped. . By this operation, even if the inner frame 12x and the front frame 14x are closed within about 4.4 seconds after the inner frame 12x or the front frame 14x is opened, the frame open detection circuit 260x It is possible to stop the power failure signal SG1bx, then stop the reset signal SG3bx, and finally stop the drive voltage Vbx. Therefore, when the power of the pachinko machine 10x is off, the inner frame 12x or the front frame 14x is opened, and the inner frame 12x and the front frame 14x are closed before approximately 4.4 seconds have elapsed from the opening, and the switch Even when the SW1x and the switch SW2x are cut off, the frame opening detection circuit 260x can normally terminate the started MPU 201x even if the MPU 201x is temporarily started.

  Returning to the description of FIG. The CNT terminal of the timer IC 1x is a terminal that adjusts the output period of the voltage output from the OUT terminal of the timer IC 1x by a signal input to the CNT terminal. The CNT terminal of the timer IC 1x is connected to one end of the capacitor CD3x. The other end of the capacitor CD3x is grounded. In this frame open detection circuit 260x, the output period of the voltage output from the OUT terminal of the timer IC 1x is not adjusted (the output period of the voltage output from the OUT terminal of the timer IC 1x is fixed to about 4.4 seconds). The CNT terminal of the timer IC 1x is AC-grounded by the capacitor CD3x.

  As described above, when the power of the pachinko machine 10x is off, the frame opening detection circuit 260x opens the inner frame 12x or the front frame 14x, and the switch SW1x or the switch SW2x becomes conductive (FIG. 41 (b)), and outputs a voltage to the power output terminal, the reset signal output terminal, and the power interruption signal output terminal. On the other hand, the frame open detection circuit 260x first stops the voltage (power failure signal SG1bx) output to the power interruption signal output terminal after about 4.4 seconds have passed since the inner frame 12x or the front frame 14x is opened. At the same time, the capacitor CD4x starts to discharge, thereafter, the voltage (reset signal SG3bx) output to the reset signal output terminal is stopped, and finally, the drive voltage Vbx output to the power supply output terminal is stopped. Therefore, even when the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily activated when the power of the pachinko machine 10x is off, the frame opening detection circuit 260x does not detect the MPU 201x that has been activated. It can be completed normally.

  Although details will be described later, when the power of the pachinko machine 10x is off, when the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily started up by the frame open detection circuit 260x, the pachinko machine 10x turns on the off-in-frame release flag 203ax. When the off-in-frame release flag 203ax is turned on, it is possible to identify the pachinko machine 10x in which the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned off. As will be described in detail later, when the pachinko machine 10x is powered off, if the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily activated by the frame open detection circuit 260x, the pachinko machine 10x outputs a pulse signal having a pulse width of 1 msec to the hall computer 262x in addition to turning on the off-in-frame release flag 203ax. This output pulse signal is stored in the hall computer 262x that continues to operate for 24 hours.

  Here, there is a case where the game hall has a security contract with a private security company. In this case, if there is an intruder into the game hall, the security company's guard immediately rushes to the game hall. However, fraudulent acts are carried out in a short time, so when security guards rush, in most cases the intruder has already escaped from the playground. Therefore, even if a security contract is signed with a private security company, there is a problem that it is impossible to determine which pachinko machine 10x is illegally operated. The pachinko machine 10x that has been cheated must return to a normal state, but if it is not known which pachinko machine 10x has been cheated, the inner frame 12x and the front frame 14x of all the pachinko machines 10x Opening them and inspecting them one by one, it was a considerable hard work to perform this work in a game hall where a large number of pachinko machines 10x are installed.

  However, according to the pachinko machine 10x of the present embodiment, when the power of the pachinko machine 10x is off, the inner frame 12x or the front frame 14x is opened, and the MPU 201x is temporarily activated by the frame open detection circuit 260x. Then, in addition to turning on the off-in-frame opening flag 203ax, a pulse signal having a pulse width of 1 ms is output to the hall computer 262x. This output pulse signal is stored in the hall computer 262x that continues to operate for 24 hours. Therefore, the pachinko machine 10x in which the inner frame 12x or the front frame 14x is opened can also be identified by the pulse signal stored in the hall computer 262x. Further, the hall computer 262x outputs a pulse signal from the pachinko machine 10x, and stores the output time of the output pulse signal, so that the opening time of the specified inner frame 12x of the pachinko machine 10x or the front frame 14x opening time can be detected.

  However, as described above, when the power of the pachinko machine 10x is off, if the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily activated by the frame open detection circuit 260x, the off-in-frame frame is released. Since the flag 203ax is turned on, it is possible to identify the pachinko machine 10x in which the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned off without using the hall computer 262x. is there. Therefore, according to the pachinko machine 10x of the present embodiment, the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is off even in a game hall where the hall computer 262x has not been operated for 24 hours. And the pachinko machine 10x can be specified.

  Further, as described above, since the frame opening detection circuit 260x is provided with the 1F capacitor CD1x, the frame opening detection circuit 260x is supplied with power to the pachinko machine 10x and is supplied with 12 volts from the DC power supply DC1x. When the DC voltage is supplied, the operation is naturally performed. Further, for example, the business hours of the amusement hall are terminated, the power supply to the pachinko machine 10x is cut off, and a DC voltage of 12 volts is supplied from the DC power supply DC1x. Even if not, the MPU 201x can be started up for a certain period of time by detecting the opening of the inner frame 12x and the opening of the front frame 14x.

  For example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10x is cut off, and the DC voltage is supplied from the capacitor CD1x to the frame opening detection circuit 260x, the inner frame 12x or the front frame 14x When increasing the total supply period of the current from the capacitor CD1x due to opening or increasing the number of times the opening of the inner frame 12x or the front frame 14x is detected, the capacitance of the capacitor CD1x is increased (for example, the capacitor The capacity of CD1x is assumed to be 10F), and the capacitor CD1x may be changed to a secondary battery with a large charged amount.

  However, when the power of the pachinko machine 10x is turned off and the inner frame 12x and the front frame 14x are closed, the amount that the frame open detection circuit 260x consumes the power of the capacitor CD1x is the standby power of the timer IC1x and the power consumption of the NOTIC3x. Therefore, the charging amount of the capacitor CD1x is not significantly reduced. In addition, since only the voltage is applied to the gate terminals G of the FETs 1x to 3x, the power consumed by the FETs 1x to 3x is very small. Therefore, the frame opening detection circuit 260x can be manufactured at low cost by setting the capacity of the capacitor CD1x to 1F, which is widely used.

  The door opening detection circuit 260 uses LMC555 as the timer IC 1x to detect the opening of the inner frame 12x or the opening of the front frame 14x, and realizes a circuit that makes the transistor TR1x conductive for about 4.4 seconds. It is not limited to. That is, a circuit that generates one pulse signal for one opening of the inner frame 12x or one opening of the front frame 14x is realized by using another integrated circuit or the like for the timer IC 1x. Any transistor that energizes the transistor TR1x for a predetermined period based on the pulse signal may be used.

  Next, referring to FIG. 44, when the power of the pachinko machine 10x is turned off, one of the inner frame 12x or the front frame 14x is opened and both the inner frame 12x and the front frame 14x are opened. An explanation will be given of the case. FIG. 44 shows the voltage at the TRG terminal of the timer IC1x and the voltage at the OUT terminal of the timer IC1x that change according to the state of the switch SW1x (the state of the inner frame 12x) and the state of the switch SW2x (the state of the front frame 14x). , The voltage of the capacitor CD4x, the voltage of the power supply output terminal of the frame opening detection circuit 260x (output voltage to the multiplexer MP3x), and the voltage of the reset signal output terminal of the frame opening detection circuit 260x (to the multiplexer MP2x and the input / output port 205x) It is a timing chart showing the relationship between the output voltage) and the voltage at the power interruption signal output terminal of the frame open detection circuit 260x (output voltage to the multiplexer MP1x). Note that Ax in FIG. 44 (f) is an enlarged view of the voltage at the reset signal output terminal of the frame opening detection circuit 260x that changes from about t1x to about 0.01 second later. In FIG. 44 (f), Ax shows the voltage of the reset signal output terminal from t1x to about 0.01 second, but from t3x to about 0.01 second, from t5x to about 0.01 second. The voltage of the reset signal output terminal until later and from about t7x to about 0.01 seconds later has the same waveform as the voltage of the reset signal output terminal from about t1x to about 0.01 seconds later, so illustration is omitted. is doing.

  First, as shown in FIG. 44A, when the switch SW1x is in a conductive state (the inner frame 12x is in an open state) at t1x, as shown in FIG. 44C, the TRG terminal voltage of the timer IC 1x is t1x. Sometimes it switches from zero volts to about 11.3 volts. At this time, as shown in FIG. 44 (d), the timer IC 1x continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds have elapsed since t1x. As a result, the emitter terminal e and the collector terminal c of the transistor TR1x (see FIG. 43) become conductive, and charging of the capacitor CD4x (see FIG. 43) is started (at time t1x) as shown in FIG. 44 (e). . This charging is completed in about 0.01 seconds after the switch SW1x becomes conductive as shown in FIG. 44 (e). When the charging of the capacitor CD4x is completed, the voltage of the capacitor CD4x becomes about 5.7 volts as shown in FIG. In addition, it takes about 0.01 seconds to charge the capacitor CD4x, but it is physically impossible to open and close the inner frame 12x or the front frame 14x in about 0.01 seconds. Therefore, when the inner frame 12x or the front frame 14x is opened, the charging of the capacitor CD4x is always completed.

  Also, the voltage at the power supply output terminal of the frame opening detection circuit 260x (the output voltage to the input terminal I23x of the multiplexer MP3x) starts to rise at t1x and is about 0 from t1x, as shown in FIG. It will be about 5.0 volts after .01 seconds. As a result, the drive voltage Vbx of about 5.0 volts is started to be output from the power output terminal of the frame opening detection circuit 260x. Further, the voltage at the reset signal output terminal of the frame opening detection circuit 260x (the output voltage to the input terminal I22x of the multiplexer MP2x and the input / output port 205x) is as indicated by Ax in FIGS. 44 (g) and 44 (f). , Starts to rise about 40 μs after t1x, and reaches about 5.0 volts after about 0.01 seconds from t1x. As a result, the reset signal SG3bx starts to be output from the reset signal output terminal of the frame opening detection circuit 260x. Note that the voltage increase at the reset signal output terminal of the frame opening detection circuit 260x is about 40 μsec after t1x due to the delay characteristic of the reset IC 2x (see FIG. 43). As shown in FIGS. 44 (f) and 44 (g), the voltage increase at the power supply output terminal of the frame open detection circuit 260x is about 40 μs earlier than the voltage increase at the reset signal output terminal of the frame open detection circuit 260x. After the drive voltage Vbx of about 5 volts is supplied to the power terminal of the MPU 201x, the reset signal SG3bx is input to the reset signal output terminal of the MPU 201x. Therefore, the frame opening detection circuit 260x can normally start up the MPU 201x when the power to the pachinko machine 10x is turned off.

  Although details will be described later, when the power of the pachinko machine 10x is off, when the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily started up by the frame open detection circuit 260x, the pachinko machine 10x turns on the off-in-frame release flag 203ax. When the off-in-frame release flag 203ax is turned on, the pachinko machine 10x in which the inner frame 12x or the front frame 14x has been opened can be specified. As will be described in detail later, when the pachinko machine 10x is powered off, if the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily activated by the frame open detection circuit 260x, the pachinko machine 10x outputs a pulse signal having a pulse width of 1 msec to the hall computer 262x. This output pulse signal is stored in the hall computer 262x that continues to operate for 24 hours.

  Furthermore, as shown in FIG. 44 (e), when the voltage of the capacitor CD4x becomes about 5.7 volts, the voltage at the power interruption signal output terminal of the open frame detection circuit 260x (the output voltage to the input terminal I21x of the multiplexer MP1x). As shown in FIG. 44 (h), the rise starts at t1x and becomes about 5.0 volts after about 0.01 second from t1x. Here, since the switch SW1x is in a conductive state (the inner frame 12x is in an open state), the terminal between the drain terminal D and the source terminal S of the FET 3x is blocked. Thereby, the power failure signal SG1bx is started to be output from the power interruption signal output terminal of the frame opening detection circuit 260x.

  When about 4.4 seconds elapse from t1x, the timer IC 1x switches the voltage at the OUT terminal from about 10.6 volts to zero volts as shown in FIG. Then, the conduction between the drain terminal D and the source terminal S of the FET 1x is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1x (see FIG. 43) is cut off, so that the charging of the capacitor CD4x is completed. To do. Then, since the discharge of the capacitor CD4x is started, as shown in FIG. 44 (e), the voltage of the capacitor CD4x starts to drop (after about 4.4 seconds from the time t1x). Following this, as shown in FIG. 44 (f), the voltage of the power supply output terminal of the open frame detection circuit 260x (the driving voltage Vbx having a maximum value of about 5.0 volts) starts to drop (from time t1x). After about 4.4 seconds). Also, as shown in FIG. 44 (g), the voltage (reset signal SG3bx) at the reset signal output terminal of the frame opening detection circuit 260x starts to drop (after about 4.4 seconds have elapsed since t1x).

  When about 4.4 seconds elapse from t1x, the conduction between the drain terminal D and the source terminal S of the FET 2x is cut off, so that no current is supplied to the power interruption signal output terminal of the frame opening detection circuit 260x. Therefore, as shown in FIG. 44 (h), the voltage (power failure signal SG1bx) at the power interruption signal output terminal of the frame opening detection circuit 260x becomes zero volts when about 4.4 seconds elapse from t1x. Accordingly, when about 4.4 seconds elapse after the inner frame 12x is opened and the switch SW1x is turned on, the power failure signal SG1bx output from the power interruption signal output terminal of the frame opening detection circuit 260x to the NMI terminal of the MPU 201x Stopped.

  Next, when about 9.4 seconds have elapsed from time t1x (after about 4.4 seconds have elapsed from time t1x, and further about 5.0 seconds have elapsed), as shown in FIG. 44 (e), the voltage of the capacitor CD4x Drops to about 5.0 volts. Then, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the frame open detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) drops to about 4.3 volts (from time t1x). After about 9.4 seconds). Also, as shown in FIG. 44 (g), the voltage (reset signal SG3bx) at the reset signal output terminal of the frame opening detection circuit 260x drops to about 4.3 volts, and thereafter, the reset IC 2x operates to zero volts. (After about 9.4 seconds from t1x). Therefore, when about 9.4 seconds have elapsed after the inner frame 12x is opened and the switch SW1x is turned on, the reset signal SG3bx output from the reset signal output terminal of the frame open detection circuit 260x to the reset terminal of the MPU 201x is the power failure signal. Next to SG1bx, it is stopped. As a result, the MPU 201x is set in a state in which it cannot execute the arithmetic processing (after about 9.4 seconds have elapsed since t1x).

  Furthermore, when about 9.9 seconds have elapsed from time t1x (after about 9.4 seconds have elapsed from time t1x, and further about 0.5 seconds have elapsed), as shown in FIG. Drop to about 4.7 volts. Then, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the open frame detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) drops to about 4.0 volts (from time t1x). After about 9.9 seconds). Here, the lower limit value of the operating voltage of the MPU 201x is about 4.0 volts. Therefore, when about 9.9 seconds have elapsed after the inner frame 12x is opened and the switch SW1x is turned on, the drive voltage Vbx output from the power supply output terminal of the frame open detection circuit 260x to the power supply terminal of the MPU 201x is finally As a result, the MPU 201x becomes inoperable. That is, the MPU 201x is set in an inoperable state (after about 9.4 seconds from the time t1x) after being set in a state where the execution of the arithmetic processing is impossible (about 9.9 seconds from the time t1x). After). Therefore, even if the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off and the MPU 201x is temporarily activated by the frame opening detection circuit 260x, the frame opening detection circuit 260x The launched MPU 201x can be terminated normally.

  When about 20 seconds elapse from t1x, the voltage of the capacitor CD4x becomes zero volts as shown in FIG. Following this, the voltage at the power supply output terminal of the frame opening detection circuit 260x (also the drive voltage Vbx) becomes zero volts (before about 20 seconds have elapsed since t1x). Therefore, when about 20 seconds elapse from t1x, the charge amount of the capacitor CD4x becomes zero.

  Finally, as shown in FIG. 44 (a), when the switch SW1x is in the cut-off state (the inner frame 12x is closed) at t2x, the TRG terminal voltage of the timer IC 1x is reduced to about approximately as shown in FIG. 44 (c). At the same time as switching from 11.3 volts to zero volts, the OUT terminal voltage of the timer IC 1x switches from zero volts to about 10.6 volts (at t2x). At t2x, when the switch SW1x is cut off (the inner frame 12x is closed), the terminal between the drain terminal D and the source terminal S of the FET 3x becomes conductive. As a result, the frame opening detection circuit 260x is set to a state in which the inner frame 12x and the front frame 14x can be detected again.

  Next, as shown in FIG. 44 (b), when the switch SW2x becomes conductive (the front frame 14x is in an open state) at t3x, the TRG terminal voltage of the timer IC 1x becomes as shown in FIG. 44 (c). At t3x, it switches from zero volts to about 11.3 volts. At this time, as shown in FIG. 44D, the timer IC 1x continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds have elapsed since t3x. As a result, the terminals of the emitter terminal e and the collector terminal c of the transistor TR1x (see FIG. 43) become conductive, and charging of the capacitor CD4x (see FIG. 43) is started as shown in FIG. t3x). This charging is completed in about 0.01 seconds after the switch SW2x becomes conductive as shown in FIG. 44 (e). When the charging of the capacitor CD4x is completed, the voltage of the capacitor CD4x becomes about 5.7 volts as shown in FIG.

  Also, the voltage at the power supply output terminal of the frame opening detection circuit 260x (the output voltage to the input terminal I23x of the multiplexer MP3x) starts to rise at t3x and is about 0 from t3x, as shown in FIG. It will be about 5.0 volts after 0.01 second. As a result, the drive voltage Vbx having a maximum value of about 5.0 volts is started to be output from the power supply output terminal of the frame opening detection circuit 260x. Further, the voltage at the reset signal output terminal of the frame opening detection circuit 260x (the output voltage to the input terminal I22x of the multiplexer MP2x and the input / output port 205x) is about 40 μs after t3x as shown in FIG. The rise starts (refer to Ax in FIG. 44 (f)), and becomes about 5.0 volts about 0.01 seconds after t3x. As a result, the reset signal SG3bx starts to be output from the reset signal output terminal of the frame opening detection circuit 260x. Note that the voltage increase at the reset signal output terminal of the frame opening detection circuit 260x is about 40 μs after t3x, as described above, due to the delay characteristics of the reset IC 2x (see FIG. 43). As shown in FIGS. 44 (f) and 44 (g), the voltage increase at the power supply output terminal of the frame open detection circuit 260x is about 40 μs earlier than the voltage increase at the reset signal output terminal of the frame open detection circuit 260x. After the drive voltage Vbx of about 5 volts is supplied to the power terminal of the MPU 201x, the reset signal SG3bx is input to the reset signal output terminal of the MPU 201x. Therefore, when the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily started up when the power of the pachinko machine 10x is turned off, the startup can be performed normally.

  Furthermore, as shown in FIG. 44 (e), when the voltage of the capacitor CD4x reaches about 5.7 volts, the voltage at the power interruption signal output terminal of the open frame detection circuit 260x (the output voltage to the input terminal I21x of the multiplexer MP1x). As shown in FIG. 44 (h), the rise starts at t3x and becomes about 5.0 volts after about 0.01 second from t3x. Here, since the switch SW2x is in a conductive state (the front frame 14x is in an open state), the terminal between the drain terminal D and the source terminal S of the FET 3x is blocked. Thereby, the power failure signal SG1bx is started to be output from the power interruption signal output terminal of the frame opening detection circuit 260x.

  When about 4.4 seconds elapse from t3x, the timer IC 1x switches the voltage at the OUT terminal from about 10.6 volts to zero volts as shown in FIG. Then, the conduction between the drain terminal D and the source terminal S of the FET 1x is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1x (see FIG. 43) is cut off. Charging to CD4x ends. Then, since the discharge of the capacitor CD4x is started, as shown in FIG. 44E, the voltage of the capacitor CD4x starts to drop (after about 4.4 seconds have elapsed from the time t3x). Following this, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the open frame detection circuit 260x (the driving voltage Vbx having a maximum value of about 5.0 volts) starts to drop (from time t3x). After about 4.4 seconds). Also, as shown in FIG. 44 (g), the voltage (reset signal SG3bx) at the reset signal output terminal of the frame opening detection circuit 260x starts to drop (after about 4.4 seconds have elapsed since t3x).

  When about 4.4 seconds elapse from t3x, the conduction between the drain terminal D and the source terminal S of the FET 2x is cut off, so that a current is supplied to the interruption signal output terminal of the open frame detection circuit 260x. Not. Therefore, as shown in FIG. 44 (h), the voltage (power failure signal SG1bx) at the power interruption signal output terminal of the frame opening detection circuit 260x becomes zero volts when about 4.4 seconds elapse from t3x. Accordingly, when about 4.4 seconds elapse after the front frame 14x is opened and the switch SW2x is turned on, the power failure signal SG1bx output from the power interruption signal output terminal of the frame opening detection circuit 260x to the NMI terminal of the MPU 201x Stopped.

  Next, when about 9.4 seconds have elapsed from time t3x (after about 4.4 seconds have elapsed from time t3x, and further about 5.0 seconds have elapsed), as shown in FIG. 44 (e), the voltage of the capacitor CD4x Drops to about 5.0 volts. Then, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the frame open detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) drops to about 4.3 volts (from time t3x). After about 9.4 seconds). Also, as shown in FIG. 44 (g), the voltage (reset signal SG3bx) at the reset signal output terminal of the frame opening detection circuit 260x drops to about 4.3 volts, and thereafter, the reset IC 2x operates to zero volts. (After about 9.4 seconds from t3x). Accordingly, when about 9.4 seconds have elapsed after the front frame 14x is opened and the switch SW2x is turned on, the reset signal SG3bx output from the reset signal output terminal of the frame open detection circuit 260x to the reset terminal of the MPU 201x is a power failure signal. Next to SG1bx, it is stopped. As a result, the MPU 201x is set in a state where it cannot execute the arithmetic processing (after about 9.4 seconds have elapsed since t3x).

  Further, when about 9.9 seconds have elapsed from time t3x (after about 9.4 seconds have elapsed since time t3x, and further about 0.5 seconds have elapsed), as shown in FIG. Drop to about 4.7 volts. Then, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the frame opening detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) drops to about 4.0 volts (from time t3x). After about 9.9 seconds). Here, as described above, the lower limit value of the operating voltage of the MPU 201x is about 4.0 volts. Therefore, when about 9.9 seconds have elapsed after the front frame 14x is opened and the switch SW2x is turned on, the drive voltage Vbx output from the power supply output terminal of the frame open detection circuit 260x to the power supply terminal of the MPU 201x is finally As a result, the MPU 201x becomes inoperable. In other words, the MPU 201x is set in an inoperable state (after about 9.4 seconds from the time t3x) after being set in a state where the execution of the arithmetic processing is impossible (after about 9.4 seconds from the time t3x). After). Therefore, even if the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off and the MPU 201x is temporarily activated by the frame opening detection circuit 260x, the frame opening detection circuit 260x The launched MPU 201x can be terminated normally.

  When about 20 seconds elapse from the time t3x, the voltage of the capacitor CD4x becomes zero volts as shown in FIG. Following this, the voltage at the power supply output terminal of the frame opening detection circuit 260x (also the drive voltage Vbx) becomes zero volts (before about 20 seconds have elapsed since t3x). Therefore, when about 20 seconds elapse from t3x, the charge amount of the capacitor CD4x becomes zero.

  Finally, as shown in FIG. 44 (a), when the switch SW2x is cut off (the front frame 14x is closed) at t4x, as shown in FIG. 44 (c), the TRG terminal voltage of the timer IC 1x is reduced to about At the same time as switching from 11.3 volts to zero volts, the OUT terminal voltage of the timer IC 1x switches from zero volts to about 10.6 volts (at t4x). At t4x, when the switch SW2x is cut off (the front frame 14x is closed), the terminal between the drain terminal D and the source terminal S of the FET 3x becomes conductive. As a result, the frame opening detection circuit 260x is set to a state in which the inner frame 12x and the front frame 14x can be detected again.

  As described above, the frame open detection circuit 260x resets after outputting the drive voltage Vbx and the power failure signal SG1bx when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off. The signal SG3bx is output. Therefore, when the MPU 201x is temporarily started up when the power of the pachinko machine 10x is turned off, the startup can be performed normally. Further, the frame open detection circuit 260x opens the inner frame 12x or the front frame 14x when the power of the pachinko machine 10x is turned off, and the switch SW1x or the switch SW2x is turned on, and about 4.4 after the turn-on. When seconds elapse, first, the power failure signal SG1bx is stopped. Then, the frame open detection circuit 260x stops the reset signal SG3bx when about 9.4 seconds have elapsed after the switch SW1x or the switch SW2x is turned on. Further, the frame open detection circuit 260x reduces the drive voltage Vbx output to the power supply terminal of the MPU 201x to about 4.0 volts when about 9.9 seconds have elapsed after the switch SW1x or the switch SW2x is turned on. Therefore, even if the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off and the MPU 201x is temporarily started by the frame open detection circuit 260x, the MPU 201x that has been started up is normal. Can be terminated.

  As described above, the operation of the frame opening detection circuit 260x is the same when the inner frame 12x is opened and when the front frame 14x is opened. Therefore, the operation of the frame opening detection circuit 260x from t5x to t6x, which will be described next, will be described only when the inner frame 12x is opened.

  As shown in FIG. 44 (a), when the switch SW1x is in a conductive state (the inner frame 12x is in an open state) at t5x, the TRG terminal voltage of the timer IC 1x is as shown in FIG. Switch from zero volts to about 11.3 volts. At this time, as shown in FIG. 44 (d), the timer IC 1x continues to output a voltage of about 10.6 volts from the OUT terminal. As a result, the terminals of the emitter terminal e and the collector terminal c of the transistor TR1x (see FIG. 43) become conductive, and charging of the capacitor CD4x (see FIG. 43) is started as shown in FIG. t5x). When the charging of the capacitor CD4x is completed, as shown in FIG. 44 (e), the voltage of the capacitor CD4x becomes about 5.7 volts (after about 0.01 seconds have elapsed since t5x).

  Also, the voltage at the power supply output terminal of the frame opening detection circuit 260x (the output voltage to the input terminal I23x of the multiplexer MP3x) starts to rise at t5x and is about 0 from t5x, as shown in FIG. It will be about 5.0 volts after 0.01 second. As a result, the drive voltage Vbx of about 5.0 volts is started to be output from the power output terminal of the frame opening detection circuit 260x. Also, the voltage at the reset signal output terminal of the frame opening detection circuit 260x (the output voltage to the input terminal I22x of the multiplexer MP2x and the input / output port 205x) is about 40 μs after t5x, as shown in FIG. 44 (g). The rise starts (refer to Ax in FIG. 44 (f)), and becomes about 5.0 volts about 0.01 seconds after t5x. As a result, the reset signal SG3bx starts to be output from the reset signal output terminal of the frame opening detection circuit 260x. Note that the voltage increase at the reset signal output terminal of the frame opening detection circuit 260x is about 40 μs after t5x, as described above, due to the delay characteristics of the reset IC 2x (see FIG. 43). As shown in FIGS. 44 (f) and 44 (g), the voltage increase at the power supply output terminal of the frame open detection circuit 260x is about 40 μs earlier than the voltage increase at the reset signal output terminal of the frame open detection circuit 260x. After the drive voltage Vbx of about 5 volts is supplied to the power terminal of the MPU 201x, the reset signal SG3bx is input to the reset signal output terminal of the MPU 201x. Therefore, when the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily started up when the power of the pachinko machine 10x is turned off, the startup can be performed normally.

  Furthermore, as shown in FIG. 44 (e), when the voltage of the capacitor CD4x reaches about 5.7 volts, the voltage at the power interruption signal output terminal of the open frame detection circuit 260x (the output voltage to the input terminal I21x of the multiplexer MP1x). As shown in FIG. 44 (h), the rise starts at t5x, and becomes about 5.0 volts about 0.01 second after t5x. Here, since the switch SW1x is in a conductive state (the inner frame 12x is in an open state), the terminal between the drain terminal D and the source terminal S of the FET 3x is blocked. Thereby, the power failure signal SG1bx is started to be output from the power interruption signal output terminal of the frame opening detection circuit 260x.

  If the inner frame 12x is closed before about 4.4 seconds have elapsed from the time t5x (when the inner frame 12x is closed at about t6x after about 3.0 seconds from the time t5x), FIG. As shown, the timer IC 1x continues to output a voltage of about 10.6 volts without switching the voltage at the OUT terminal to about 10.6 volts. At this time, the terminal between the drain terminal D and the source terminal S of the FET 1x remains conductive, but the switch SW1x is cut off with the closing of the inner frame 12x, so that the emitter of the transistor TR1x (see FIG. 43). A voltage is no longer applied to the terminal e and the base terminal b, and conduction between the emitter terminal e and the collector terminal c of the transistor TR1x is interrupted. Thereby, the charging to the capacitor CD4x is completed (at the time of t6x). Then, since the discharge of the capacitor CD4x is started, the voltage of the capacitor CD4x starts to drop (at t6x) as shown in FIG. Following this, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the open frame detection circuit 260x (the driving voltage Vbx having a maximum value of about 5.0 volts) starts to drop (at t6x). . Also, as shown in FIG. 44 (g), the voltage (reset signal SG3bx) at the reset signal output terminal of the frame opening detection circuit 260x starts to drop (at t6x).

  When the inner frame 12x is closed and the switch SW1x is cut off (at time t6x), the capacitor CD4x starts to be discharged. The voltage generated by this discharge is applied to the power interruption signal output terminal of the frame open detection circuit 260x. Not supplied. As described above, since the switch SW1x is cut off when the inner frame 12x is closed, the terminal between the drain terminal D and the source terminal S of the FET 3x conducts and is generated by the discharge of the capacitor CD4x. This is because the current does not flow through the resistor R5x but flows into the drain terminal D of the FET 3x. Therefore, as shown in FIG. 44 (h), the voltage (power failure signal SG1bx) at the power interruption signal output terminal of the frame opening detection circuit 260x becomes zero volts at t6x. Therefore, if the inner frame 12x is closed and the switch SW1x is shut off before the inner frame 12x is opened and about 4.4 seconds elapses, the frame open detection circuit is turned off when the switch SW1x is turned off. The power failure signal SG1bx output from the power interruption signal output terminal of 260x to the NMI terminal of the MPU 201x is first stopped.

  Next, when about 5.0 seconds elapse from t6x, the voltage of the capacitor CD4x drops to about 5.0 volts as shown in FIG. Then, as shown in FIG. 44 (f), the voltage of the power supply output terminal of the open frame detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) drops to about 4.3 volts (from time t6x). After about 5.0 seconds). Also, as shown in FIG. 44 (g), the voltage (reset signal SG3bx) at the reset signal output terminal of the frame opening detection circuit 260x drops to about 4.3 volts, and thereafter, the reset IC 2x operates to zero volts. (About 5.0 seconds after t6x). Therefore, when about 5.0 seconds elapse after the inner frame 12x is closed and the switch SW1x is cut off, the reset signal SG3bx output from the reset signal output terminal of the frame opening detection circuit 260x to the reset terminal of the MPU 201x is changed to the power failure signal. Next to SG1bx, it is stopped. As a result, the MPU 201x is set in a state where it cannot execute the arithmetic processing (after about 5.0 seconds have elapsed since t6x).

  Further, when about 5.5 seconds have elapsed from t6x time (after about 5.0 seconds have passed since t6x time, and further about 0.5 seconds have elapsed), as shown in FIG. Drop to about 4.7 volts. Then, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the frame opening detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) drops to about 4.0 volts (from t6x time). After about 5.5 seconds). Here, the minimum operating voltage of the MPU 201x is about 4.0 volts. Therefore, when about 5.5 seconds have elapsed after the inner frame 12x is closed and the switch SW1x is cut off, the drive voltage Vbx output from the power supply output terminal of the frame open detection circuit 260x to the power supply terminal of the MPU 201x is finally stopped. As a result, the MPU 201x becomes inoperable. In other words, the MPU 201x is set in an inoperable state (after about 5.0 seconds from the time t6x) after being set in a state in which the execution of the arithmetic processing is impossible (about 5.5 seconds from the time t6x). After). Therefore, even if the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off and the MPU 201x is temporarily activated by the frame opening detection circuit 260x, the frame opening detection circuit 260x The launched MPU 201x can be terminated normally.

  When about 20 seconds elapse from the time t5x, the voltage of the capacitor CD4x becomes zero volts as shown in FIG. Following this, the voltage at the power supply output terminal of the frame opening detection circuit 260x (also the drive voltage Vbx) becomes zero volts (before about 20 seconds have elapsed since t5x). Therefore, when about 20 seconds elapse from t5x, the charge amount of the capacitor CD4x becomes zero.

  Here, in the operation of the frame opening detection circuit 260x from t5x to t6x, the capacitor CD4x is discharged even after the inner frame 12x is closed at t6x. Even in this case, when the inner frame 12x is closed at t6x and the switch SW1x is cut off, the frame opening detection circuit 260x conducts between the drain terminal D and the source terminal S of the FET 3x. The current generated by the CD4x discharge does not flow through the resistor R5x, but flows through the drain terminal D of the FET 3x. Therefore, when the inner frame 12x is closed at t6x, as shown in FIG. 44 (h), the voltage (power failure signal SG1bx) of the power interruption signal output terminal of the frame opening detection circuit 260x can be zero volt.

  After the power failure signal SG1bx output from the power interruption signal output terminal of the frame opening detection circuit 260x is stopped, the voltage accompanying the discharge of the capacitor CD4x decreases with time, and the reset output from the reset signal output terminal The signal SG3bx is stopped, and finally the drive voltage Vbx output from the power supply output terminal is stopped. By this operation, even if the inner frame 12x is closed before about 4.4 seconds have elapsed from the time t5x when the inner frame 12x is opened (the inner frame 12x is not changed at time t6x after about 3.0 seconds from the time t5x). Even if it is closed, the power failure signal SG1bx can be stopped first, then the reset signal SG3bx can be stopped, and finally the drive voltage Vbx can be stopped. Therefore, when the power of the pachinko machine 10x is turned off, the inner frame 12x is opened, and the opened inner frame is released within about 4.4 seconds until the voltage output from the OUT terminal of the timer IC 1x is switched. Even if the frame 12x is closed, the MPU 201x can be temporarily activated by the frame opening detection circuit 260x, and the activated MPU 201x can be normally terminated.

  After the inner frame 12x is closed at t6x, as shown in FIG. 44 (e), the voltage of the capacitor CD4x decreases to about 4.7 volts, and as shown in FIG. When the drive voltage Vbx output from the output terminal to the end becomes about 4.0 volts and the MPU 201x ends normally, the frame opening detection circuit 260x is set to a state in which the inner frame 12x or the front frame 14x can be detected again. Is done.

  Finally, a case will be described in which the switch SW2x is in a conductive state (the front frame 14x is in an open state) when the switch SW1x is in a conductive state (the inner frame 12x is in an open state). As shown in FIG. 44 (a), at time t7x, the switch SW1x is in a conductive state (inner frame 12x is in an open state). Further, as shown in FIG. When the frame 14x is in the open state), as shown in FIG. 44C, the TRG terminal voltage of the timer IC 1x switches from zero volts to about 11.3 volts at t7x. At this time, as shown in FIG. 44 (d), the timer IC 1x continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds have elapsed since t7x. As a result, the terminals of the emitter terminal e and the collector terminal c of the transistor TR1x (see FIG. 43) become conductive, and charging of the capacitor CD4x (see FIG. 43) is started as shown in FIG. t7x). This charging is completed in about 0.01 seconds after the switch SW1x becomes conductive as shown in FIG. 44 (e). When the charging of the capacitor CD4x is completed, the voltage of the capacitor CD4x becomes about 5.7 volts as shown in FIG.

  Also, the voltage at the power supply output terminal of the frame opening detection circuit 260x (the output voltage to the input terminal I23x of the multiplexer MP3x) starts to rise at t7x and is about 0 from t7x, as shown in FIG. It will be about 5.0 volts after .01 seconds. As a result, the drive voltage Vbx of about 5.0 volts is started to be output from the power output terminal of the frame opening detection circuit 260x. Also, the voltage at the reset signal output terminal of the frame opening detection circuit 260x (the output voltage to the input terminal I22x of the multiplexer MP2x and the input / output port 205x) is about 40 μs after t7x, as shown in FIG. Starting to rise, it becomes about 5.0 volts about 0.01 seconds after t7x. As a result, the reset signal SG3bx starts to be output from the reset signal output terminal of the frame opening detection circuit 260x. Note that the voltage increase at the reset signal output terminal of the frame opening detection circuit 260x is about 40 μs after t7x, as described above, due to the delay characteristics of the reset IC 2x (see FIG. 43). As shown in FIGS. 44 (f) and 44 (g), the voltage increase at the power supply output terminal of the frame open detection circuit 260x is about 40 μs earlier than the voltage increase at the reset signal output terminal of the frame open detection circuit 260x. After the drive voltage Vbx of about 5 volts is supplied to the power terminal of the MPU 201x, the reset signal SG3bx is input to the reset signal output terminal of the MPU 201x. Therefore, when the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily started up when the power of the pachinko machine 10x is turned off, the startup can be performed normally.

  Further, as shown in FIG. 44 (e), when the voltage of the capacitor CD4x becomes about 5.7 volts, the voltage of the power interruption signal output terminal of the open frame detection circuit 260x (output voltage to the input terminal I21x of the multiplexer MP1x) As shown in FIG. 44 (h), the rise starts at t7x and becomes about 5.0 volts after about 0.01 second from t7x. Here, since the switch SW1x is in a conductive state (the inner frame 12x is in an open state), the terminal between the drain terminal D and the source terminal S of the FET 3x is blocked. Thereby, the power failure signal SG1bx is started to be output from the power interruption signal output terminal of the frame opening detection circuit 260x.

  When about 4.4 seconds elapse from t7x, the timer IC 1x switches the voltage at the OUT terminal from about 10.6 volts to zero volts as shown in FIG. Then, the conduction between the drain terminal D and the source terminal S of the FET 1x is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1x (see FIG. 43) is cut off. Charging to CD4x ends. Then, since the discharge of the capacitor CD4x is started, as shown in FIG. 44E, the voltage of the capacitor CD4x starts to drop (after about 4.4 seconds have elapsed from the time t7x). Following this, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the open frame detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) starts to drop (from time t7x). After about 4.4 seconds). Also, as shown in FIG. 44 (g), the voltage (reset signal SG3bx) at the reset signal output terminal of the frame opening detection circuit 260x starts to drop (after about 4.4 seconds have elapsed since t7x).

  When about 4.4 seconds elapse from t7x, the conduction between the drain terminal D and the source terminal S of the FET 2x is cut off, so that a current is supplied to the interruption signal output terminal of the open frame detection circuit 260x. Not. Therefore, as shown in FIG. 44 (h), the voltage at the power interruption signal output terminal of the frame opening detection circuit 260x (power failure signal SG1bx) becomes zero volts when about 4.4 seconds have elapsed from t7x. Accordingly, when about 4.4 seconds elapse after the inner frame 12x is opened and the switch SW1x is turned on, the power failure signal SG1bx output from the power interruption signal output terminal of the frame opening detection circuit 260x to the NMI terminal of the MPU 201x Stopped.

  Next, when about 9.4 seconds elapse from t7x (after about 4.4 seconds elapse from t7x, and further about 5.0 seconds elapse), as shown in FIG. 44 (e), the voltage of the capacitor CD4x Drops to about 5.0 volts. Then, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the open frame detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) drops to about 4.3 volts (from t7x time). After about 9.4 seconds). Also, as shown in FIG. 44 (g), the voltage (reset signal SG3bx) at the reset signal output terminal of the frame opening detection circuit 260x drops to about 4.3 volts, and thereafter, the reset IC 2x operates to zero volts. (After about 9.4 seconds from t7x). Therefore, when about 9.4 seconds have elapsed after the inner frame 12x is opened and the switch SW1x is turned on, the reset signal SG3bx output from the reset signal output terminal of the frame open detection circuit 260x to the reset terminal of the MPU 201x is the power failure signal. Next to SG1bx, it is stopped. As a result, the MPU 201x is set in a state in which the arithmetic processing cannot be executed (after about 9.4 seconds have elapsed since t7x).

  Further, when about 9.9 seconds have elapsed from t7x (after about 9.4 seconds have passed since t7x, and further about 0.5 seconds have elapsed), as shown in FIG. Drop to about 4.7 volts. Then, as shown in FIG. 44 (f), the voltage at the power supply output terminal of the frame opening detection circuit 260x (the drive voltage Vbx having a maximum value of about 5.0 volts) drops to about 4.0 volts (from time t7x). After about 9.9 seconds). Here, as described above, the lower limit value of the operating voltage of the MPU 201x is about 4.0 volts. Therefore, when about 9.9 seconds have elapsed after the inner frame 12x is opened and the switch SW1x is turned on, the drive voltage Vbx output from the power supply output terminal of the frame open detection circuit 260x to the power supply terminal of the MPU 201x is finally stopped. As a result, the MPU 201x becomes inoperable. That is, the MPU 201x is set in an inoperable state (after about 9.4 seconds have elapsed since t7x) after being set in a state where execution of arithmetic processing is impossible (about 9.9 seconds since t7x). After). Therefore, even when the MPU 201x is temporarily activated by the frame opening detection circuit 260x when the power of the pachinko machine 10x is turned off, the frame opening detection circuit 260x can normally terminate the MPU 201x that has been started up. it can.

  When about 20 seconds elapse from the time t7x, the voltage of the capacitor CD4x becomes zero volts as shown in FIG. Following this, the voltage at the power supply output terminal of the frame opening detection circuit 260x (also the drive voltage Vbx) becomes zero volts (before about 20 seconds have elapsed since t7x). Therefore, when about 20 seconds elapse from t7x, the charge amount of the capacitor CD4x becomes zero.

  Finally, as shown in FIG. 44 (a), at time t9x, the switch SW1x is cut off (the inner frame 12x is closed), and as shown in FIG. 44 (b), at time t10x, the switch SW2x is cut off. When the state (the front frame 14x is closed), as shown in FIG. 44 (c), at time t10x, the TRG terminal voltage of the timer IC 1x is switched from about 11.3 volts to zero volts, and the OUT terminal voltage of the timer IC 1x. Switches from zero volts to about 10.6 volts. Further, at t10x, when the switch SW2x is cut off (the front frame 14x is closed), the terminals of the drain terminal D and the source terminal S of the FET 3x become conductive. As a result, the frame opening detection circuit 260x is set to a state in which the inner frame 12x and the front frame 14x can be detected again.

  As described above, when the switch SW1x is in the conductive state (the inner frame 12x is in the open state), even when the switch SW2x is in the conductive state (the front frame 14x is in the open state), the timer IC 1x is in the conductive period of the switch SW1x. The switch SW1x or the switch SW2x is in a conductive state regardless of the length of the inner frame 12x (the length of the open period of the inner frame 12x) and the length of the conductive period of the switch SW2x (the length of the open period of the front frame 14x). When about 4.4 seconds have elapsed from when the inner frame 12x or the front frame 14x is open, the voltage at the OUT terminal is switched from about 10.6 volts to zero volts. As a result, the frame opening detection circuit 260x stops the power failure signal SG1bx and starts discharging the capacitor CD4x after about 4.4 seconds from when either the switch SW1x or the switch SW2x becomes conductive. . After that, the frame open detection circuit 260x stops the reset signal SG3bx after about 9.4 seconds from when either the switch SW1x or the switch SW2x becomes conductive, and either the switch SW1x or the switch SW2x The drive voltage Vbx is stopped after about 9.9 seconds from the time when one of them becomes conductive. Therefore, when the power of the pachinko machine 10x is turned off, the switch SW1x is in a conductive state (the inner frame 12x is in an open state), and then the switch SW2x is in a conductive state (the front frame 14x is in an open state) Even if the MPU 201x is temporarily activated by the frame opening detection circuit 260x, the frame opening detection circuit 260x can normally terminate the launched MPU 201x.

  As described above, when the power of the pachinko machine 10x is off, the frame opening detection circuit 260x is driven when one of the inner frame 12x or the front frame 14x and both the inner frame 12x and the front frame 14x are opened. After outputting the voltage Vbx and the power failure signal SG1bx, the reset signal SG3bx is output. Therefore, even if the power of the pachinko machine 10x is turned off, the MPU 201x can be temporarily started up normally. Although details will be described later, when the MPU 201x is temporarily started up by the frame opening detection circuit 260x when the power of the pachinko machine 10x is off, the pachinko machine 10x turns on the off-in-frame opening flag 203ax. To do. When the off-in-frame release flag 203ax is turned on, the pachinko machine 10x uses the audio output device 226x and the lamp display device 227x when the power to the pachinko machine 10x is turned on next time, so that the inner frame 12x or the front frame 14x is released. Therefore, the pachinko machine 10x in which the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off can be specified.

  As will be described in detail later, when the MPU 201x is temporarily activated by the frame release detection circuit 260x when the power of the pachinko machine 10x is off, the pachinko machine 10x turns on the off-in-frame release flag 203ax. In addition, a pulse signal having a pulse width of 1 msec is output to the hall computer 262x. This output pulse signal is stored in the hall computer 262x that continues to operate for 24 hours. Therefore, by analyzing the pulse signal stored in the hall computer 262x, the pachinko machine 10x in which the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off is specified. Can do.

  Further, the frame open detection circuit 260x first stops the power failure signal SG1bx when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on and about 4.4 seconds have elapsed after the turn-on. If the opened inner frame 12x or the opened front frame 14x is closed before about 4.4 seconds have elapsed since the switch SW1x or the switch SW2x is turned on, a power failure signal is generated at the time of closing. SG1bx is stopped). Next, the frame open detection circuit 260x stops the reset signal SG3bx when about 9.4 seconds have elapsed after the switch SW1x or SW2x is turned on (about 4.4 seconds have passed after the switch SW1x or switch SW2x is turned on). If the opened inner frame 12x or the opened front frame 14x is closed before, the reset signal SG3bx is stopped after about 5.0 seconds from the closing). Then, the frame open detection circuit 260x reduces the drive voltage Vbx output to the power supply terminal of the MPU 201x to about 4.0 volts when about 9.9 seconds elapse after the switch SW1x or the switch SW2x is turned on (switch SW1x or If the opened inner frame 12x or the opened front frame 14x is closed before about 4.4 seconds have elapsed after the switch SW2x is turned on, the drive is performed after about 5.5 seconds have elapsed since the closing. Reduce voltage Vbx to about 4.0 volts). Therefore, even if the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off and the MPU 201x is temporarily activated by the frame opening detection circuit 260x, the frame opening detection circuit 260x The launched MPU 201x can be terminated normally.

  Further, the frame open detection circuit 260x opens the inner frame 12x or the front frame when approximately 4.4 seconds elapses after the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on. Regardless of the open period of 14x, the transistor TR1x stops the output of the drive voltage Vbx, the output of the reset signal SG3bx, the output of the power failure signal SG1bx, and the charging of the capacitor CD4x performed by the power supplied from the capacitor CD1x. After the stop by the transistor TR1x, the frame opening detection circuit 260x outputs the drive voltage Vbx and the reset signal SG3bx by discharging the capacitor CD4x. Therefore, the frame opening detection circuit 260x, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10x is cut off, and a DC voltage of 12 volts is not supplied from the DC power supply DC1x to the frame opening detection circuit 260x. That is, when a DC voltage of about 11.3 volts is supplied from the capacitor CD1x to the frame open detection circuit 260x, the period in which power is supplied from the capacitor CD1x is the open period of the inner frame 12x or the front frame 14x. Regardless, it can be kept in about 4.4 seconds. Therefore, the frame opening detection circuit 260x can detect the opening of the inner frame 12x or the front frame 14x a plurality of times while suppressing the consumption of the electric power charged in the capacitor CD1x.

  Further, the frame open detection circuit 260x is configured so that even if the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on, the inner frame 12x or the front frame 14x is opened before approximately 4.4 seconds elapses. When the frame 12x or the opened front frame 14x is closed, the switch SW1x or the switch SW2x is shut off, the output of the drive voltage Vbx performed by the power supplied from the capacitor CD1x, the output of the reset signal SG3bx, the power failure signal SG1bx And the charging of the capacitor CD4x are stopped. After the inner frame 12x and the front frame 14x are closed, the drive voltage Vbx and the reset signal SG3bx are output by discharging the capacitor CD4x.

  As described above, when the charging of the capacitor CD4x is completed, the driving voltage Vbx and the reset signal SG3bx can be output by discharging the capacitor CD4x. Therefore, the open period of the inner frame 12x or the front frame 14x is approximately If the time is within 4.4 seconds, the output voltage Vbx, the reset signal SG3bx, the power failure signal SG1bx, and the capacitor CD4x that are supplied by supplying power from the capacitor CD1x are further shortened. Can be stopped. Therefore, the power consumption of the capacitor CD1x due to the opening of the inner frame 12x or the front frame 14x can be further suppressed.

  Here, since the capacitor CD1x has a capacitance of 1F and the voltage applied to the capacitor CD1x is approximately 11.3 volts, the charge stored in the capacitor CD1x is the product of the capacitance of the capacitor CD1x and the applied voltage of the capacitor CD1x. To about 11.3 C (coulomb). The electric charge of about 11.3 C stored in the capacitor CD1x is about the output period of the drive voltage Vbx, the output of the reset signal SG3bx, the output of the power failure signal SG1bx and the charge of the capacitor CD4x performed by the power supply from the capacitor CD1x In the case of 4.4 seconds, this corresponds to about 11 times of power supply. Therefore, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10x is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1x, the inner frame 12x is opened (the switch SW1x Continuity) or the opening of the front frame 14x (conduction of the switch SW2x) is performed a plurality of times, the frame opening detection circuit 260x opens the inner frame 12x or the front frame 14x (conduction or continuity of the switch SW1x). The conduction of the switch SW2x) is reliably detected every time up to about 11 times, and the MPU 201x can be temporarily raised normally to turn on the off-in-frame release flag 203ax. At this time, when the opening of the inner frame 12x or the opening of the front frame 14x is about 11 times, the power stored in the capacitor CD1x decreases, the drive voltage Vbx decreases, the reset signal SG3bx decreases, the power failure signal SG1bx decreases. A decrease and a decrease in the charge amount of the capacitor CD4x occur. However, when the inner frame 12x or the front frame 14x is opened, the voltage of the reset signal SG3bx output from the reset signal output terminal of the frame open detection circuit 260x exceeds about 4.3 volts, and the frame open detection circuit 260x. If the voltage of the drive voltage Vbx output from the power supply output terminal and the power failure signal SG1bx output from the power interruption signal output terminal of the frame open detection circuit 260x exceed about 4.0 volts, the power of the pachinko machine 10x is Even if it is turned off, the MPU 201x can be temporarily started up normally to turn on the off-in-frame release flag 203ax. Furthermore, a pulse signal having a pulse width of 1 msec can be output to the hall computer 262x.

  In the frame opening detection circuit 260x, the capacitances of the capacitors CD1x and CD4x are set to 1F, respectively. Since the capacitor serves as a power source for operating the open detection circuit 260x, the capacitance value may be larger than the capacitance value of the capacitor CD4x. By making the capacitance value of the capacitor CD1x larger than 1F, the opening of the inner frame 12x or the front frame 14x while the power of the pachinko machine 10x is turned off can be detected more than 11 times.

  In the frame open detection circuit 260x, when the inner frame 12x and the front frame 14x are closed (when the switch SW1x and the switch SW2x are shut off), the OUT terminal voltage of the timer IC 1x is about 10.6 volts. Therefore, the terminal between the drain terminal D and the source terminal S of the FET 1x of the frame opening detection circuit 260x and the terminal between the drain terminal D and the source terminal S of the FET 2x are brought into conduction. Further, since the inner frame 12x and the front frame 14x are closed, the terminals between the drain terminal D and the source terminal S of the FET 3x are brought into conduction. However, at this time, since the conduction between the terminals of the emitter terminal e and the collector terminal c of the transistor TR1x is cut off, the drain terminal D and the source terminal of the FET 2x are connected between the drain terminal D and the source terminal S of the FET 1x. The current from the capacitor CD1x does not flow between the terminals with S and between the drain terminal D and the source terminal S of the FET 3x. Therefore, when the inner frame 12x and the front frame 14x are closed, the power charged in the capacitor CD1x is between the drain terminal D and the source terminal S of the FET 1x and between the drain terminal D and the source terminal S of the FET 2x. It is not consumed by flowing between the terminals and between the drain terminal D and the source terminal S of the FET 3x.

  The amount of power that the frame open detection circuit 260x consumes the power of the capacitor CD1x when the power of the pachinko machine 10x is turned off and the inner frame 12x and the front frame 14x are closed is the standby power of the timer IC1x and the power consumption of the NOTIC3x. Degree. In addition, since only the voltage is applied to the gate terminals G of the FETs 1x to 3x, the power consumed by the FETs 1x to 3x is very small. Therefore, the consumption of these powers does not cause a significant decrease in the charge amount of the capacitor CD1x.

  Next, the display content of the third symbol display device 81x will be described with reference to FIG. FIG. 45 is a drawing for explaining the display screen of the third symbol display device 81x, and FIG. 45 (a) is a diagram schematically showing the area division setting and the effective line setting of the display screen, FIG. 45B is a diagram illustrating an actual display screen.

  The third symbol is composed of ten types of main symbols with numbers from “0” to “9” and one type of sub-shaped petal shape formed smaller than this main symbol. Each main symbol is composed of numbers from “0” to “9” on the rear symbol consisting of a wooden box, of which the main symbols with odd numbers (1, 3, 5, 7, 9) are A large number is added to almost the front of the wooden box. On the other hand, the main symbols with even numbers (0, 2, 4, 6, 8) are attached to the front of the wooden box almost fully, and attached symbols imitating characters such as furoshiki and helmets are added. An even number is small in green on the lower right side of the attached symbol and is added so as to be displayed on the front side of the attached symbol.

  Further, in the pachinko machine 10x of the present embodiment, when the lottery result by the main controller 110x is a big win, a variable display with the same main symbols is performed, and a big hit occurs after the variable display is finished It is configured to When shifting to the high probability state (probability variation state) after the big hit, the variable display in which the main symbols (corresponding to “high probability symbols”) to which odd numbers are added is arranged. On the other hand, when shifting to the low probability state after the big hit, the variable display is performed in which the main symbols to which the even numbers are added (corresponding to “low probability symbols”) are arranged. Here, the high probability state refers to a state in which the subsequent jackpot probability is increased as an added value after the jackpot ends, that is, a so-called probability fluctuation (probability change). Further, the normal state (low probability state) refers to a time when the probability of hitting is not probable, and refers to a state where the probability of jackpot is normal, that is, a state where the probability of jackpot is lower than that during probability change.

  As shown in FIG. 45 (a), the display screen of the third symbol display device 81x is roughly divided into two vertically, and the lower 2/3 is the main display area Dmx in which the third symbol is variably displayed, and the others The upper third is a sub display area Dsx for displaying a notice effect and a character.

  In the main display area Dmx, three symbol rows Z1x, Z2x, and Z3x of left, middle, and right are displayed. In each symbol row Z1x to Z3x, the above-described third symbols are displayed in a prescribed order. That is, in each of the symbol rows Z1x to Z3x, main symbols are arranged in ascending or descending numerical order, and one sub symbol is arranged between the main symbols. For this reason, a total of 20 third symbols of 10 main symbols and 10 sub-designs are set in each symbol row, and scrolls from top to bottom with periodicity for each symbol row Z1x to Z3x. The display is changed. In particular, in the left symbol row Z1x, the main symbol numbers are arranged so as to appear in descending order, and in the middle symbol row Z2x and the right symbol row Z3x, the main symbol numbers are arranged so as to appear in ascending order.

  In the main display area Dmx, the third symbols are displayed in the upper, middle, and lower three rows for each of the symbol rows Z1x to Z3x. Accordingly, the third symbol display device 81x displays a total of nine third symbols of 3 rows × 3 columns. In this main display area Dmx, five effective lines, that is, an upper line L1x, a middle line L2x, a lower line L3x, a right rising line L4x, and a left rising line L5x are set. In each game, the variable display stops in the order of left symbol row Z1x → right symbol row Z3x → middle symbol row Z2x, and a combination of jackpot symbols on any active line at the time of stoppage (in this embodiment, A jackpot video is displayed as a jackpot if the same combination of main symbols) is arranged.

  The sub display area Dsx is horizontally long above the main display area Dmx, and is further equally divided into three notice areas Ds1x to Ds3x in the left-right direction. Here, the left and right notice areas Ds1x and Ds3x are usually covered with a double-open opaque door that is electrically opened and closed by a solenoid (not shown), and sometimes the solenoid is excited and the door is on the front side. It is a display area that is visible to the player when it is opened. The center notice area Ds2x is a display area that is always visible without being covered by the door.

  As shown in FIG. 45 (b), in the actual display screen, a total of nine main symbols and sub symbols of the third symbol are displayed in the main display area Dmx. In the sub display area Dsx, the left and right doors are closed, and the left and right notice areas Ds1x and Ds3x are covered and the display screen cannot be visually recognized. If either one of the left and right doors or both doors are opened during the variable display, a video is displayed in the left and right notice areas Ds1x and Ds3x, and it is easy for the player to make a transition to a big hit than usual. It is suggested. In the notice area Ds2x in the center, a predetermined character (a boy with a bee in this embodiment) usually performs a predetermined action and sometimes performs a special action different from the predetermined action, A notice effect is performed by appearing. The display screen of the third symbol display device 81x is divided into upper and lower display regions Dmx and Dsx in principle, but the third symbol and characters are displayed larger across the display regions Dmx and Dsx. A display effect can be performed.

  Next, with reference to FIG. 46, a counter and the like provided in the RAM 203x of the main controller 110x will be described. These counters and the like are used in the MPU 201x of the main control device 110x to perform jackpot lottery, display setting of the first symbol display device 37x, lottery of display results of the second symbol display device 82x, and the like.

  For the jackpot lottery and display setting of the first symbol display device 37x, the first hit random number counter C1x used for the jackpot lottery, the first hit type symbol counter C2x used for the jackpot symbol selection, and the stop pattern selection counter C3x, a first initial value random number counter CINI1x used for setting an initial value of the first per-random number counter C1x, and variation type counters CS1x, CS2x, CS3x used for variation pattern selection are used. The second symbol random number counter C4x is used for the lottery of the second symbol display device 82x, and the second initial value random number counter CINI2x is used for setting the initial value of the second random number counter C4x. Each of these counters is a loop counter that adds 1 to the previous value every time it is updated and returns to 0 after reaching the maximum value.

  Each counter is updated at an interval of 4 milliseconds that is an execution interval of the main process (see FIG. 48) or at an interval of 2 milliseconds that is an execution interval of the timer interrupt process (see FIG. 51), and the updated value is a predetermined area of the RAM 203x. Are stored in the counter buffer set as follows. The RAM 203x is provided with a holding ball storage area composed of one execution area and four holding areas (holding first to fourth areas), and each of these areas has access to the first entrance 64x. Each value of the first per-random number counter C1x, the first per-type counter C2x, and the stop pattern selection counter C3x is stored in accordance with the winning timing of the ball.

  Each counter will be described in detail. The first random number counter C1x is, for example, incremented by 1 within a range of 0 to 738, and returns to 0 after reaching the maximum value (ie, 738). In particular, when the first random number counter C1x makes one round, the value of the first initial value random number counter CINI1x at that time is read as the initial value of the first random number counter C1x. Further, the first initial value random number counter CINI1x is configured as a loop counter that is updated in the same range as the first per-random number counter C1x (value = 0 to 738), and each time the timer interrupt process (see FIG. 51) is executed. It is updated once and updated repeatedly within the remaining time of the main process (see FIG. 48). The value of the first random number counter C1x is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the ball is stored in the RAM 203x at the timing when the ball wins the first entrance 64x. Stored in the area. The number of random number values that are jackpots is set at low probability and high probability, and the number of random numbers that are jackpots at low probability is 2, and the value is “373, 727” There are 14 random numbers that are big hits at high probability, and the values are "59, 109, 163, 211, 263, 317, 367, 421, 479, 523, 631, 683, 733".

  The first hit type counter C2x determines the display mode of the first symbol display device 37x in the case of a big win. In the present embodiment, the first hit type counter C2x is incremented by 1 within the range of 0 to 4, and the maximum ( That is, it is configured to return to 0 after reaching 4). The value of the first hit type counter C2x is updated, for example, regularly (in this embodiment, once for each timer interrupt process), and the ball is stored in the RAM 203x at the timing when the ball wins the first entrance 64x. Stored in the area. In addition, the value of the random number that becomes a high probability state after the jackpot is “1, 2, 3”, the value of the random number that becomes the low probability state after the jackpot is “0, 4”, and two types of hits are determined. The Therefore, the display mode corresponding to the stop symbol displayed on the first symbol display device 37x is a display mode corresponding to two types of jackpots of a high probability state and a low probability state, and one type of display mode corresponding to a deviation. Any one of the three display modes is selected.

  For example, the stop pattern selection counter C3x is incremented one by one within a range of 0 to 238, for example, and reaches a maximum value (that is, 238) and then returns to 0. In the present embodiment, the stop pattern selection counter C3x selects the effect pattern displayed on the third symbol display device 81x, and after reaching, the final stop symbol is shifted by one before and after the reach symbol. “Stop before and after detachment reach” (for example, a range of 0 to 8), and “Leach other than detachment before and after detachment” (for example, a range of 9 to 38) after the reach has occurred and the final stop symbol stops other than before and after the reach design. The three stop (effect) patterns are selected as “completely out” (for example, a range of 39 to 238) that does not cause reach. The value of the stop pattern selection counter C3x is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the reserved ball storage area of the RAM 203x at the timing when the ball wins the first entrance 64x. Stored in

  Further, the stop pattern selection counter C3x is provided with a plurality of tables having different ranges of random number values from which stop patterns are selected. This depends on whether the current state of the pachinko machine 10x is a high probability state or a low probability state, in which area of the reserved ball storage area each random number value is stored (that is, the number of held), etc. This is to change the stop pattern selection ratio.

  For example, in a high probability state, a table with a wide random value range of 10 to 238 corresponding to the stop pattern of “completely out” is selected so that a jackpot is likely to occur and a reach effect is not selected more than necessary. It becomes easy to select “completely off”. In this table, “front / rear out of reach” is narrowed to 0-5, and “reach other than front / rear out of reach” is also narrowed to 6-9, making it difficult to select “rear out of front / rear out of reach” or “reach out of front / rear out of reach”. In addition, if each random value is not stored in the reserved ball storage area in a low probability state, the randomness corresponding to the stop pattern of “completely missed” in order to secure the time for entering the ball to the first entrance 64x. A table with a narrow numerical value range of 51 to 238 is selected, and “completely out” is difficult to select. In this table, the range of random numbers corresponding to the stop pattern of “reach other than front / rear deviation” is as wide as 9 to 50, and “reach other than front / rear deviation” is easily selected. Therefore, in the low probability state, it is possible to secure the time for entering the ball into the first entrance 64x, so that the variable display by the third symbol display device 81x is easily performed continuously.

  Of the two variation type counters CS1x and CS2x, one variation type counter CS1x is incremented one by one within a range of 0 to 198, for example, and reaches a maximum value (that is, 198) and then returns to 0. On the other hand, the other variation type counter CS2x is configured to increment one by one within a range of, for example, 0 to 240 and return to 0 after reaching the maximum value (that is, 240). In the following description, CS1x is also referred to as “first variation type counter” and CS2x is also referred to as “second variation type counter”.

  Rough display modes such as so-called normal reach, super reach, and premium reach are determined by the first variation type counter CS1x. Specifically, the display mode is determined by determining the variation time of the symbol variation. Further, the second variation type counter CS2x determines a variation time (in other words, the number of variation symbols) until the final stop symbol (in this embodiment, the middle symbol) stops after the occurrence of reach. Based on the variation time determined by the variation type counters CS1x and CS2x, the display control device 114x determines the reach type and detailed symbol variation mode of the third symbol displayed on the third symbol display device 81x. Therefore, a variety of variation patterns can be easily realized by combining these variation type counters CS1x and CS2x. It is also possible to determine the symbol variation mode only by the first variation type counter CS1x, or to determine the symbol variation mode similarly by combining the first variation type counter CS1x and the stop symbol. The values of the variation type counters CS1x and CS2x are updated once every time a main process (see FIG. 48) described later is executed once, and are repeatedly updated within the remaining time in the main process.

  For example, the value of the variation type counter CS3x is incremented by 1 in order within a range of 0 to 162, and returns to 0 after reaching the maximum value (that is, 162). In the following description, CS3x is also referred to as a “third variation type counter”. The 3rd symbol display device 81x of this embodiment performs a decorative effect according to the display mode of the 1st symbol display device 37x, and in addition to the variation of the symbol, the symbol that is changing can be slid. A notice effect such as passing a notice character for notifying the occurrence of the reach effect is performed. The effect pattern of the notice effect is selected by the variation type counter CS3x. Specifically, the time required for the notice effect is added to the variable time, or on the contrary, the variable time is subtracted to shorten the variable display time, or an effect pattern that does not add or subtract the variable time is selected. . As with the stop pattern selection counter C3x, the variation type counter CS3x is provided with a plurality of tables with different ranges of random values from which the production pattern is selected, and whether the current state of the pachinko machine 10x is in a high probability state. Depending on the low probability state or in which area of the reserved ball storage area each random value is stored, the selection ratio of each effect pattern is different.

  As described above, the variation time of the symbol variation is determined by the variation type counters CS1x and CS2x, and the time to be added to or subtracted from the variation time is determined by the variation type counter CS3x. Therefore, the final fluctuation time until the final stop symbol stops is determined by the fluctuation type counters CS1x, CS2x, CS3x.

  The second random number counter C4x is configured as a loop counter that increments one by one within a range of 0 to 250, for example, and returns to 0 after reaching the maximum value (that is, 250). In the present embodiment, the value of the second per-random number counter C4x is periodically updated, for example, every timer interrupt process, and the ball has passed through either the left or right second entrance (through gate) 67x. Obtained when detected. The number of random number values to be won is 149, and the range is “5 to 153”. The second initial value random number counter CINI2x is configured as a loop counter that is updated in the same range as the second per-random number counter C4x (value = 0 to 250), and once every timer interrupt process (see FIG. 51). In addition to being updated, it is repeatedly updated within the remaining time of the main process (see FIG. 48).

  Next, each control process executed by the MPU 201x in the main controller 110x will be described with reference to the flowcharts in FIGS. The MPU 201x is roughly divided into a startup process that is started when the power is turned on, a main process that is executed after the startup process, and a startup process periodically (in this embodiment, at a cycle of 2 milliseconds). There are a timer interrupt process and an NMI interrupt process activated by the input of the power failure signal SG1ax or the power failure signal SG1bx to the NMI terminal. For convenience of explanation, the timer interrupt process and the NMI interrupt process will be described first. Thereafter, the startup process and the main process will be described.

  FIG. 51 is a flowchart showing the timer interrupt process. The timer interrupt process is executed by the MPU 201x of the main controller 110x, for example, every 2 milliseconds. In the timer interruption process, first, reading processes of various winning switches are executed (S501x). That is, the state of various switches connected to the main controller 110x is read, and the state of the switch is determined and the detection information (winning detection information) is stored.

  Next, the first initial value random number counter CINI1x and the second initial value random number counter CINI2x are updated (S502x). Specifically, the first initial value random number counter CINI1x is incremented by 1 and cleared to 0 when the counter value reaches the maximum value (738 in the present embodiment). Then, the updated value of the first initial value random number counter CINI1x is stored in the corresponding buffer area of the RAM 203x. Similarly, 1 is added to the second initial value random number counter CINI2x, and when the counter value reaches the maximum value (250 in the present embodiment), it is cleared to 0 and the second initial value random number counter CINI2x is updated. The value is stored in the corresponding buffer area of the RAM 203x.

  Further, the first per-random number counter C1x, the first per-type counter C2x, the stop pattern selection counter C3x, and the second per-random number counter C4x are updated (S503x). Specifically, 1 is added to each of the first per-random number counter C1x, the first per-type counter C2x, the stop pattern selection counter C3x, and the second per-random number counter C4x, and these counter values are the maximum values (this embodiment) Then, when they reach 738, 4, 238, 250), they are cleared to 0. Then, the updated values of the counters C1x to C4x are stored in the corresponding buffer area of the RAM 203x.

  Thereafter, a start winning process (see FIG. 52) associated with winning at the first entrance 64x is executed (S504x), a firing control process is executed (S505x), and the timer interrupt process is terminated. Note that the launch control process detects that the player is touching the operation handle 51x by the touch sensor 51ax, and turns on the ball launch on the condition that the stop switch 51bx for stopping the launch is not operated. This is a process for determining / off. The main controller 110x instructs the launch controller 112x to launch a sphere when the launch of the sphere is on.

  Here, the start winning process executed in the process of S504x will be described with reference to the flowchart of FIG. FIG. 52 is a flowchart showing the start winning process (S504x) executed in the timer interrupt process (see FIG. 51).

  When the start winning process is executed, first, it is determined whether or not the ball has won (start winning) at the first entrance 64x (S601x). If it is determined that the ball has won the first entrance 64x (S601x: Yes), whether or not the number N of active reserved balls of the first symbol display device 37x is less than the upper limit (4 in the present embodiment). Is determined (S602x). If there is a winning at the first entrance 64x and the number of reserved balls for operation N <4 (S602x: Yes), the number of reserved balls for operation N is incremented by 1 (S603x), and further updated in step S503x. The values of the first per-random number counter C1x, the first per-kind counter C2x, and the stop pattern selection counter C3x are stored in the first of the free reserved areas in the reserved ball storage area of the RAM 203x (S604x). On the other hand, whether or not there is no winning at the first entrance 64x (S601x: No), or even if there is a winning at the first entrance 64x, if the number of reserved balls N <4 is not satisfied (S602x: No) , S603x and S604x are skipped, the start winning process is terminated, and the process returns to the timer interrupt process.

  FIG. 53 is a flowchart showing NMI interrupt processing. In the NMI interrupt process, the power of the pachinko machine 10x is turned on. While the power is on, the power of the pachinko machine 10x is shut off due to the occurrence of a power failure, and the power failure signal output from the power failure monitoring circuit 252x. In addition to the case where SG1ax falls from 5 volts to zero volts, the power of the pachinko machine 10x is turned off. While the power is off, the inner frame 12x or the front frame 14x is opened, and the frame open detection circuit 260x This is a process executed by the MPU 201x of the main controller 110x when the MPU 201x is started up and the power failure signal SG1bx output from the frame opening detection circuit 260x falls from 5 volts to zero volts. When the MPU 201x detects the fall of the power failure signal SG1ax or the power failure signal SG1bx, the MPU 201x interrupts the control being executed and starts the NMI interrupt process, and the power failure occurrence information is set as the power failure occurrence information setting. Is stored in the RAM 203x (S701x), and the NMI interrupt process is terminated.

  The above NMI interrupt processing is similarly executed in the payout control device 111x when the power of the pachinko machine 10x is turned on, and information on occurrence of power interruption is stored in the RAM 213x by the NMI interrupt processing. . That is, when the power of the pachinko machine 10x is cut off due to the occurrence of a power failure or the like when the power of the pachinko machine 10x is turned on, the power failure signal SG1ax (falling) is sent from the power failure monitoring circuit 252x to the payout controller 111x. This is output to the NMI terminal of the MPU 211x, and the MPU 211x interrupts the control being executed and starts the NMI interrupt process.

  Next, with reference to FIG. 47, a startup process when the main controller 110x is powered on will be described. FIG. 47 is a flowchart showing start-up processing executed by the MPU 201x in the main controller 110x. This start-up process is started by a reset at power-on, and when the power of the pachinko machine 10x is turned off, the inner frame 12x or the front frame 14x is opened and the frame open detection circuit 260x The driving voltage Vbx and the reset signal SG3bx are output, and the MPU 201x becomes operable by the driving voltage Vbx. Thereafter, the MPU 201x is activated by the reset signal SG3bx. In the start-up process, first, an initial setting process associated with power-on is executed (S101x). Specifically, a predetermined value is set in advance in the stack pointer, and the sub-side control devices (peripheral control devices such as the sound lamp control device 113x and the payout control device 111x) become operable. In order to wait, a wait process (1 second in this embodiment) is executed. Next, access to the RAM 203x is permitted (S103x). Due to this wait processing, the main control device 110x shifts to the main processing after the payout control device 111x, the sound lamp control device 113x, and the display control device 114x shift to the main processing. Therefore, the payout control device 111x, the sound lamp control device 113x, and the display control device 114x can reliably receive the command transmitted from the main control device 110x (the payout control device 111x, the sound lamp control device 113x, and the display control). It is possible to prevent the device 114x from receiving a command from the main controller 110x).

  Thereafter, it is determined whether or not the RAM erase switch 122x (see FIG. 39) provided in the power supply device 115x is turned on (S104x). If it is turned on (S104x: Yes), the process proceeds to S115x. On the other hand, if the RAM erase switch 122x is not turned on (S104x: No), it is further determined whether or not the information on occurrence of power interruption is stored in the RAM 203x (S105x), and if not stored (S105x: No). Since there is a possibility that the process at the time of the previous power shutdown has not been completed normally, the process proceeds to S115x in this case as well.

  If the power failure occurrence information is stored in the RAM 203x (S105x: Yes), the RAM determination value is calculated (S106x). If the calculated RAM determination value is not normal (S107x: No), that is, the calculated RAM If the determination value does not match the RAM determination value stored at the time of power-off, the backed up data has been destroyed. In such a case as well, the process proceeds to S115x. As will be described later in the processing of S223x in FIG. 48, the RAM determination value is, for example, a checksum value at a work area address in the RAM 203x. Instead of the RAM determination value, the validity of the backup may be determined based on whether or not the keyword written in a predetermined area of the RAM 203x is correctly stored. The pachinko machine 10x is determined to be No in the process of S107x because the RAM determination value is always abnormal when the power is first turned on after being shipped from the production factory. Also in this case, the process proceeds to S115x.

  In the processing of S115x, a payout initialization command is transmitted in order to initialize the payout control device 111x as the sub-side control device (peripheral control device) (S115x). When the payout control device 111x receives this payout initialization command, the payout control device 111x clears the area (work area) other than the stack area of the RAM 213x, sets an initial value, and enters a state where the payout control of the game ball can be started. After transmitting the payout initialization command, main controller 110x executes initialization processing (S116x, S117x) of RAM 203x.

  As described above, in the pachinko machine 10x, when the RAM data is initialized when the power is turned on, for example, when the game hall is started, the power is turned on while the RAM erase switch 122x is pressed. Accordingly, if the RAM erase switch 122x is pressed during the start-up process, the RAM initialization process (S116x, S117x) is executed. Similarly, initialization processing (S116x, S117x) of the RAM 203x is executed even when the information on occurrence of power interruption is not set or when a backup abnormality is confirmed by the RAM determination value (checksum value or the like). . In the RAM initialization processing (S116x, S117x), the used area of the RAM 203x is cleared to 0 and the off-in-frame release flag 203ax is turned off (S116x), and then the initial value of the RAM 203x is set (S117x). After executing the initialization process of the RAM 203x, the process proceeds to S110x.

  On the other hand, if the RAM erasure switch 122x is not turned on (S104x: No), the occurrence information of the power-off is stored (S105x: Yes), and the RAM judgment value (checksum value etc.) is normal ( S107x: Yes) Clears the information on the occurrence of power interruption while holding backed up data in the RAM 203x (S108x), transmits a payout return command to the payout control device 111x (S109x), and proceeds to the processing of S110x. .

  In the processing of S110x, the voltage (reset signal SG3bx) output from the frame opening detection circuit 260x to the input / output port 205x is read (S110x). Then, it is determined whether or not the output (reset signal SG3bx) from the frame opening detection circuit 260x to the input / output port 205x is high (S111x). If the output from the frame open detection circuit 260x to the input / output port 205x is high (S111x: Yes), the off-frame open flag 203ax is turned on (S112x). On the other hand, if the output from the frame opening detection circuit 260x to the input / output port 205x is not high (S111x: No), the process of S112x is skipped. Whether the output from the frame opening detection circuit 260x to the input / output port 205x (reset signal SG3bx) is high or not depends on whether the voltage output from the frame opening detection circuit 260x to the input / output port 205x is about 4.3 volts. Judgment is made based on whether or not it exceeds.

  If the output from the frame opening detection circuit 260x to the input / output port 205x is determined to be high (S111x: Yes), the inner frame 12x or the front frame 14x is opened while the pachinko machine 10x is powered off. In addition to the case where the switch SW1x or the switch SW2x is turned on and the drive voltage Vbx, the power failure signal SG1bx and the reset signal SG3bx are output from the frame opening detection circuit 260x and the MPU 201x is temporarily started, there are two other patterns. Conceivable. In the first pattern, when the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is off, and the power of the pachinko machine 10x is turned on within about 9.4 seconds from the opening, that is, the pachinko machine When the power of 10x is off, the inner frame 12x or the front frame 14x is opened, and the pachinko machine 10x is in a state where the drive voltage Vbx, the power failure signal SG1bx, and the reset signal SG3bx are output from the frame open detection circuit 260x. This is when the power is turned on. The second pattern is a case where the power of the pachinko machine 10x is turned on, the inner frame 12x or the front frame 14x is opened before the processing of S110x, and the reset signal SG3bx is output from the frame open detection circuit 260x. Even in the case of the first pattern or the second pattern, there is no problem even if the off-in-frame opening flag 203ax is turned on (S112x). In order to fall under the first pattern or the second pattern, it is essential that the power of the pachinko machine 10x is turned on. The first pattern and the second pattern are the sales clerk before the game hall business hours. It is because it is a case where it is performed by. That is, when the first pattern or the second pattern is performed by the store clerk, at least the store clerk releases the inner frame 12x or the front frame 14x by itself when the power of the pachinko machine 10x is turned off. Is it recognized that the power of the pachinko machine 10x is turned on within about 9.4 seconds from the opening (first pattern) or immediately after the power of the pachinko machine 10x is turned on by itself (processing of S110x)? This is because it is recognized that the inner frame 12x or the front frame 14x is opened by itself (the second pattern). That is, even if the off-in-frame release flag 203ax is turned on, the store clerk recognizes that the off-in-frame release flag 203ax is on and then opens the inner frame 12x or the front frame 14x. is there. More specifically, the store clerk can perform an operation to turn off the off-in-frame release flag 203ax again. Therefore, even if it is determined that the output from the frame opening detection circuit 260x to the input / output port 205x is high in the above two patterns (S111x: Yes), there is no problem. That is, the above two patterns cannot occur during normal use of the pachinko machine 10x, so there is no problem even if they are not considered.

  As described above, when the power of the pachinko machine 10x is off, the inner frame 12x or the front frame 14x is opened, the switch SW1x or the switch SW2x is turned on, and the drive voltage Vbx, the power failure signal SG1bx and the reset are supplied from the frame open detection circuit 260x. In addition to the case where the signal SG3bx is output and the MPU 201x is temporarily started, also in the case of the above two patterns, the output from the frame opening detection circuit 260x to the input / output port 205x is determined to be high (S111x: Yes), the off-in-frame release flag 203ax is turned on (S112x).

  When it is determined No in S111x or when the process of S112x is executed, the payout return command at the time of power recovery for returning the sub-side control device (peripheral control device) to the gaming state at the time of the drive power interruption. Is transmitted (S113x), and the process proceeds to S114x. When the payout control device 111x receives this payout return command, the payout control device 111x is in a state where it can start payout control of the game ball while holding the data stored in the RAM 213x. In the process of S114x, an interrupt is permitted and the process proceeds to a main process described later.

  As described above, the power of the pachinko machine 10x is turned off, and the inner frame 12x or the front frame 14x is opened while the pachinko machine 10x is turned off, and the drive voltage Vbx, the power failure signal SG1bx, and the reset signal SG3bx are output from the frame open detection circuit 260x. When the MPU 201x is temporarily started up, the output from the frame open detection circuit 260x to the input / output port 205x becomes high (S111x: Yes), and the off-frame open flag 203ax is turned on (S112x). .

  Note that the processing of S110x to S112x is executed immediately after the processing of S109x is completed or immediately after the processing of S117x is completed. That is, the processing of S110x to S112x is executed immediately after various settings of the MPU 201x are completed. Therefore, when the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned off, the opening can be detected immediately by the processing of S110x to S112x.

  Next, with reference to FIG. 48, the main process executed after the above-described startup process will be described. FIG. 48 is a flowchart showing a main process executed by the MPU 201x in the main controller 110x. In this main process, the main process of the game is executed. As an outline, each process of S201x to S212x is executed as a periodic process with a period of 4 milliseconds, and each process of S215x to S220x is executed in the remaining time.

  In the main processing, first, output data such as a command updated in the previous processing is transmitted to each control device (peripheral control device) on the sub side (S201x). Specifically, the presence / absence of winning detection information detected in the switch reading process of S501x is determined, and if there is winning detection information, a winning ball command corresponding to the number of acquired balls is transmitted to the payout control device 111x. In addition, by this external output process, a variation pattern command, a stop symbol command, a stop command, an effect time addition command, and the like necessary for the variation display of the third symbol by the third symbol display device 81x are transmitted to the sound lamp control device 113x. Furthermore, when performing a sphere launch, a sphere launch signal is transmitted to the launch controller 112x.

  Next, each value of the variation type counters CS1x, CS2x, CS3x is updated (S202x). Specifically, the variation type counters CS1x, CS2x, CS3x are incremented by 1, and are cleared to 0 when their counter values reach the maximum values (198, 240, 162 in this embodiment). Then, the update values of the variation type counters CS1x, CS2x, CS3x are stored in the corresponding buffer area of the RAM 203x.

  When the update of the variation type counters CS1x, CS2x, CS3x is completed, the prize ball counting signal and the payout abnormality signal received from the payout control device 111x are read (S203x). Thereafter, it is determined whether or not the off-in-frame release flag 203ax is on (S204x). If the off-frame open flag 203ax is on (S204x: Yes), the inner frame 12x or the front frame 14x is open while the power of the pachinko machine 10x is turned off, which corresponds to the two patterns described above. An off frame open command is transmitted to the control device 113x (S205x). Upon receiving the off-in-frame opening command, the audio lamp control device 113x controls the audio output device 226x and the lamp display device 227x to start notifying that the inner frame 12x or the front frame 14x has been opened. Further, a pulse signal having a pulse width of about 1 ms is output to the hall computer 262x (S206x). This output pulse signal is stored in the hall computer 262x that continues to operate for 24 hours. If the inner frame 12x or the front frame 14x is opened while the pachinko machine 10x is powered off and the MPU 201x is temporarily started up, power is not supplied to the sound lamp control device 113x. Even when the off-frame opening command is transmitted to the sound lamp control device 113x, the sound output device 226x and the lamp display device 227x do not perform notification. Therefore, even if the inner frame 12x or the front frame 14x is opened by the fraudster while the power of the pachinko machine 10x is turned off, the pachinko machine 10x does not realize the off middle frame opening flag 203ax without being recognized by the fraudster. Can be used to memorize the opening of the inner frame 12x or the front frame 14x (without notification by the audio output device 226x and the lamp display device 227x, the inner frame 12x or the front Only open storage of the frame 14x can be performed).

  On the other hand, if the off-in-frame release flag 203ax is off (S204x: No), it is determined whether or not the on-in-frame release flag 203bx is on (S207x). If the on-in-frame release flag 203bx is on (S207x: Yes), an on-in-frame release command is transmitted to the audio lamp control device 113x (S208x). When receiving the on-frame open command, the audio lamp controller 113x controls the audio output device 226x and the lamp display device 227x to start notifying that the inner frame 12x or the front frame 14x has been opened. On the other hand, if the on-in-frame release flag 203bx is off (S207x: No), an on-in-frame closing command is transmitted to the sound lamp control device 113x (S209x). When the voice lamp control device 113x receives the on-in-frame closing command, the voice lamp control device 113x ends the notification performed by the voice output device 226x and the lamp display device 227x. If the on-frame open flag 203bx is on (S207x: Yes), a pulse signal having a pulse width of about 1 ms may be output to the hall computer 262x after the processing of S208x. In this case, since the output pulse signal is stored in the hall computer 262x that continues to operate for 24 hours, the hall computer 262x also identifies the pachinko machine 10x in which the inner frame 12x or the front frame 14x has been opened. be able to.

  After the process of S206x, S208x, or S209x, the process for performing the display by the first symbol display device 37x or the variation process for setting the variation pattern of the third symbol by the third symbol display device 81x is executed (S210x). Details of the variation process will be described later with reference to FIG.

  After the end of the variation process, a large opening opening / closing process for opening or closing the specific winning opening (large opening) 65ax of the variable winning device 65x is executed in the case of the big win state (S211x). That is, the specific winning opening 65ax is opened for each round of the big hit state, and it is determined whether the maximum opening time of the specific winning opening 65ax has elapsed or whether a specified number of balls have won the specific winning opening 65ax. And when any of these conditions is satisfied, the specific winning opening 65ax is closed. The opening and closing of the specific winning opening 65ax is repeatedly performed a predetermined number of rounds.

  Next, display control processing of the second symbol (for example, symbol “◯” or “x”) by the second symbol display device 82x is executed (S212x). Briefly, on the condition that the ball has passed through the second entrance (through gate) 67x, the value of the second random number counter C4x is acquired at the timing of passing and the second symbol display device 82x. The display part 83x displays the variation of the second symbol. Then, the lottery of the second symbol is performed based on the value of the second winning random number counter C4x, and when the winning state of the second symbol is reached, the electric accessory associated with the first entrance 64x is released for a predetermined time.

  Thereafter, it is determined whether or not the power failure occurrence information is stored in the RAM 203x (S213x). If the power failure occurrence information is not stored in the RAM 203x (S213x: No), the frame opening detection circuit 260x causes the MPU 201x to be stored. Has not been launched temporarily. Further, the falling of the power failure signal SG1ax output from the power failure monitoring circuit 252x is not detected, and the power of the pachinko machine 10x is not shut off. Therefore, in such a case, it is determined whether or not the execution timing of the next main process has been reached, that is, whether or not a predetermined time (4 msec in the present embodiment) has elapsed since the start of the previous main process (S214x). ). If the predetermined time has already passed (S214x: Yes), the process proceeds to S201x, and the above-described processes after S201x are repeatedly executed.

  On the other hand, if the power failure occurrence information is stored in the RAM 203x (S213x: Yes), the power of the pachinko machine 10x is turned off, and the inner frame 12x or the front frame 14x is opened while the power is turned off. As a result of the MPU 201x being temporarily raised by the frame opening detection circuit 260x and the power failure signal SG1bx output from the frame opening detection circuit 260x falling, the NMI interrupt processing of FIG. 53 has been executed, or the pachinko machine 10x 53 is turned on when the power is cut off due to the occurrence of a power failure or power off, and the power failure signal SG1ax output from the power failure monitoring circuit 252x falls, so that the NMI interrupt process of FIG. 53 is executed. Therefore, the process at the time of power-off after S221x is executed. First, the generation of each interrupt process is prohibited (S221x), and a power-off command indicating that the power has been cut off is sent to other control devices (peripheral control devices such as the payout control device 111x and the sound lamp control device 113x). (S222x). Then, the RAM determination value is calculated and stored (S223x), access to the RAM 203x is prohibited (S224x), and the infinite loop is continued until the power supply is completely shut down and the process cannot be executed. Here, the RAM determination value is, for example, a checksum value in the stack area and work area to be backed up in the RAM 203x.

  In the process of S214x, if the predetermined time has not yet elapsed since the start of the previous main process (S214x: No), the remaining time until the predetermined time is reached, that is, until the execution timing of the next main process is reached. , The first initial value random number counter CINI1x, the second initial value random number counter CINI2x, and the variation type counters CS1x, CS2x, CS3x are repeatedly updated (S215x, S216x).

  First, the first initial value random number counter CINI1x and the second initial value random number counter CINI2x are updated (S215x). Specifically, 1 is added to the first initial value random number counter CINI1x and the second initial value random number counter CINI2x, and when the counter value reaches the maximum value (738, 250 in this embodiment), it is cleared to 0. To do. Then, the updated values of the first initial value random number counter CINI1x and the second initial value random number counter CINI2x are stored in the corresponding buffer areas of the RAM 203x.

  Next, the fluctuation type counters CS1x, CS2x, CS3x are updated (S216x). Specifically, the variation type counters CS1x, CS2x, CS3x are incremented by 1, and are cleared to 0 when their counter values reach the maximum values (198, 240, 162 in this embodiment). Then, the update values of the variation type counters CS1x, CS2x, CS3x are stored in the corresponding buffer areas of the RAM 203x.

  Here, since the execution time of each process of S201x to S212x changes according to the state of the game, the remaining time until the next main process execution timing is not constant and varies. Therefore, the first initial value random number counter CINI1x and the second initial value random number counter CINI2x (that is, the second initial value random number counter CINI2x (that is, the second initial value random number counter CINI2x) (ie, the second initial value random number counter CINI1x and the second initial value random number counter CINI2x) are obtained. , The initial value of the first per-random number counter C1x and the initial value of the second per-random number counter C4x) can be updated at random. Similarly, the variation type counters CS1x, CS2x, and CS3x can also be updated at random.

  After the process of S216x, the voltage (reset signal SG3bx) output from the frame open detection circuit 260x to the input / output port 205x is read (S217x). Then, it is determined whether or not the output (reset signal SG3bx) from the frame opening detection circuit 260x to the input / output port 205x is high (S218x). If the output from the frame open detection circuit 260x to the input / output port 205x is high (S218x: Yes), the on-frame open flag 203bx is turned on (S219x). On the other hand, if the output from the frame open detection circuit 260x to the input / output port 205x is not high (S218x: No), the on-frame open flag 203bx is turned off (S220x). After the process of S219x or S220x, the process proceeds to S213x, and the processes after S213x are executed.

  Note that the power of the pachinko machine 10x is turned off, the inner frame 12x or the front frame 14x is opened while the power is turned off, and the MPU 201x is temporarily started up by the frame opening detection circuit 260x, and the frame opening detection circuit When the reset signal SG3bx is output from 260x, in addition to the off-in-frame release flag 203ax, the on-in-frame release flag 203bx is also turned on. This means that it takes about 4.4 seconds after the power failure signal SG1bx becomes 5 volts until the power failure signal SG1bx outputted from the power interruption signal output terminal of the frame open detection circuit 260x falls from 5 volts to zero volts ( It takes about 4.4 seconds until it is determined to be “Yes” in the process of S213x), and in the meantime, the process of S218x is executed in addition to the start-up process, and “Yes” is determined in this process. It is.

  However, even if the on-in-frame release flag 203bx is turned on in addition to the off-in-frame release flag 203ax, if the power of the pachinko machine 10x is turned on next time, it is determined as “Yes” in the process of S204x. Thus, the process does not proceed to S207x for determining the state of the on-in-frame release flag 203bx. Therefore, main controller 110x can transmit only the off-in-frame release command to audio lamp controller 113x. Therefore, when the MPU 201x is temporarily activated by the frame open detection circuit 260x, the on-in-frame release flag 203bx is turned on in addition to the off-in-frame release flag 203ax, but this does not cause any problem. is there.

  On the other hand, when the inner frame 12x and the front frame 14x are not opened while the power of the pachinko machine 10x is turned off (when the inner frame 12x and the front frame 14x are closed), naturally, The off-in-frame release flag 203ax is not turned on. Therefore, when the power of the pachinko machine 10x is turned on next time, it is determined as “No” in the process of S204x, and the process of S207x for determining the state of the on-in-frame release flag 203bx is executed. Naturally, the process of S218x is also executed. Therefore, when the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned on, the opening is detected by the processing of S217x and the processing of S218x, and the processing of S208x executed thereafter Thus, main controller 110x can transmit only the on-frame open command to audio lamp controller 113x.

  As described above, if the off-in-frame release flag 203ax is turned on (S204x: Yes), the pachinko machine 10x transmits an off-in-frame release command to the audio lamp control device 113x (S205x) and to the hall computer 262x. A pulse signal having a pulse width of about 1 ms is output (S206x).

  Note that the power of the pachinko machine 10x is turned off, and the inner frame 12x or the front frame 14x is opened while the power is turned off, and the drive voltage Vbx, the power failure signal SG1bx, and the reset signal SG3bx are output from the frame open detection circuit 260x. S201x to S213x: Yes to S224x, which are executed when the MPU 201x is temporarily started up, at least the reset signal of the frame opening detection circuit 260x due to the discharge of the capacitor CD4x (see FIG. 43). The program is set so that execution is completed during the period until the reset signal SG3bx output from the output terminal drops to about 4.3 volts, that is, during the period of about 5.0 seconds (see FIG. 44). ing. Note that this period of about 5.0 seconds is irrespective of the opening time of the inner frame 12x or the front frame 14x (the inner frame 12x or the front frame 14x opened immediately after the inner frame 12x or the front frame 14x is opened). This is a period that always occurs due to the discharge of the capacitor CD4x (see FIG. 44). Therefore, even when the MPU 201x is temporarily started, the pachinko machine 10x temporarily turns on the off-in-frame release flag 203ax regardless of the opening time of the inner frame 12x or the front frame 14x. The MPU 201x that has started up can be normally terminated.

  Note that the process of S213x is at the end of a series of processes corresponding to the game state change performed in S201x to S212x, or at the end of one cycle of the processes of S215x to S220x performed within the remaining time. It is running. Therefore, in the main process of the main controller 110x, the occurrence information of the power supply interruption is confirmed at the timing when each setting is completed. Therefore, when returning from the power supply interruption state, The process can be started from S201x. In other words, the process can be started from the process of S201x, as in the case where the process is initialized in the startup process. Therefore, in the process at power-off, the stack pointer is not stored in the initial setting process (S101x) without saving the contents of each register used by the MPU 201x to the stack area or saving the stack pointer value. By setting to a predetermined value (initial value), it is possible to start from the process of S201x. Therefore, the control burden on the main controller 110x can be reduced, and accurate control can be performed without causing the main controller 110x to malfunction or run away.

  Next, the variation process (S204x) will be described with reference to FIG. FIG. 49 is a flowchart showing the variation process (S204x) executed in the main process (see FIG. 48). In this variation process, first, it is determined whether or not a big hit is currently being made (S301x). The jackpot includes the jackpot game displayed on the third symbol display device 81x and the first symbol display device 37x and the middle of a predetermined time after the jackpot game is ended. As a result of the determination, if it is a big hit (S301x: Yes), this processing is terminated as it is.

  If it is not a big hit (S301x: No), it is determined whether or not the display mode of the first symbol display device 37x is changing (S302x), and if the display mode of the first symbol display device 37x is not changing. (S302x: No), it is determined whether or not the number N of working suspension balls is larger than 0 (S303x). If the number N of active suspension balls is 0 (S303x: No), this process is ended as it is. If the number of the operation reservation balls N> 0 (S303x: Yes), the operation reservation ball number N is decremented by 1 (S304x), and the data stored in the reservation ball storage area is shifted (S305x). This data shift process is a process of sequentially shifting the data stored in the reserved first to fourth areas of the reserved ball storage area to the execution area side, and the reserved first area → execution area, reserved second area → The data in each area is shifted such as the first hold area, the third hold area → the second hold area, the fourth hold area → the third hold area. After the data shift process, the fluctuation start process of the first symbol display device 37x is executed (S306x). The variation start process will be described later with reference to FIG.

  In the process of S302x, when it is determined that the display mode of the first symbol display device 37x is changing (S302x: Yes), it is determined whether or not the change time has elapsed (S307x). The display time during the change of the first symbol display device 37x is determined according to the change pattern selected by the change type counters CS1x and CS2x and the addition time selected by the change type counter CS3x. If it has not elapsed (S307x: No), the display of the first symbol display device 37x is updated (S308x).

  In the present embodiment, of the LEDs 37ax of the first symbol display device 37x, until the fluctuation time elapses after the fluctuation starts, for example, if the currently lit LED is red, the red LED is changed. Turn off and turn on the green LED. If the green LED is on, turn off the green LED and turn on the blue LED. If the blue LED is on, turn on the blue LED. A display mode is set for turning off the red LED and turning on the red LED.

  The variation process is executed every 4 milliseconds, but if the LED lighting color is changed every time the variation process is executed, the player cannot confirm the change in the LED lighting color. Therefore, a counter (not shown) is counted once each time the variation process is executed so that the player can confirm the change in the lighting color of the LED. Change the lighting color of. That is, the lighting color of the LED is changed every 0.4 seconds. The counter value is reset to 0 when the lighting color of the LED is changed.

  On the other hand, if the variation time of the first symbol display device 37x has elapsed (S307x: Yes), a display mode corresponding to the stop symbol of the first symbol display device 37x is set (S309x). Whether or not the stop symbol is set is determined based on the value of the first per-random number counter C1x, and if it is a big hit, the symbol that becomes a high probability state after the big hit is determined based on the value of the first per-type counter C2x. Or a symbol that is in a low probability state. In this embodiment, a red LED is turned on when a high probability state is reached after a big hit, a green LED is turned on when a low probability state is reached, and a blue LED is turned on when it is out of place. . In addition, although the lighting of each LED is released when the next fluctuation display is started, it may be turned on only for a few seconds after the fluctuation stops.

  When the display mode of the first symbol display device 37x corresponding to the stop symbol is set in the process of S309x, the third symbol display device 81x is stopped to synchronize with the lighting of the LED in the first symbol display device 37x. A command is set (S310x). When the sound lamp control device 113x receives this stop command, it instructs the display control device 114x to stop. When the variation time elapses, the third symbol display device 81x stops the variation, and upon receiving the stop command, one variation effect in the third symbol display device 81x ends.

  Next, the variation start process will be described with reference to FIG. FIG. 50 is a flowchart showing the change start process (S306x) executed in the change process (see FIG. 49). In the variation start process (S306x), first, it is determined whether or not a big hit is made based on the value of the first hit random number counter C1x stored in the execution area of the reserved ball storage area (S401x). Whether or not it is a big hit is determined based on the relationship between the value of the first random number counter C1x and the mode at that time. As described above, “373,727” is the winning value among the numerical values 0 to 738 of the first random number counter C1x at the normal low probability, and “59, 109, 163, 211, 263, 317, 367, "421,479,523,631,683,733" is the winning value.

  When it is determined that it is a big hit (S401x: Yes), the value of the first hit type counter C2x stored in the execution area of the reserved ball storage area is confirmed, and the display mode for the big hit is set (S402x) ). In the process of S402x, based on the value of the first hit type counter C2x, whether to shift to the high probability state or shift to the low probability state after the big hit is set. When the transition state after the big hit is set, the display mode (the lighting state of the LED 37ax) of the first symbol display device 37x is set. Further, based on the transition state after the jackpot, the jackpot stop symbol stopped and displayed on the third symbol display device 81x is set by the sound lamp control device 113x and the display control device 114x. In other words, the stop symbol in the third symbol display device 81x is set by setting the transition state after the big hit by the process of S402x. Of the numerical values 0 to 4 of the first hit type counter C2x, when “0, 4”, the state shifts to the low probability state, and when “1, 2, 3”, shifts to the high probability state. .

  Next, the variation pattern at the time of jackpot is determined (S403x). When the variation pattern is set in the process of S403x, the display time of the first symbol display device 37x is set, and the variation time of the third symbol until the third symbol display device 81x stops at the jackpot symbol is determined. The At this time, the values of the fluctuation type counters CS1x and CS2x stored in the counter buffer of the RAM 203x are confirmed, and rough symbol fluctuations such as normal reach, super reach, and premium reach are determined based on the value of the first fluctuation type counter CS1x. In addition to determining the variation time, the variation time (in other words, the number of variation symbols) until the final stop symbol (in this embodiment, the middle symbol Z2) stops after the occurrence of reach based on the value of the second variation type counter CS2x. decide.

  The relationship between the numerical value of the first variation type counter CS1x and the variation time and the relationship between the numerical value of the second variation type counter CS2x and the variation time are respectively defined in advance by a table or the like. However, the fluctuation time can be set using only the value of the first fluctuation type counter CS1x without using the value of the second fluctuation type counter CS2x, and is set only by the value of the first fluctuation type counter CS1x. Whether or not to set with both values of both variation type counters CS1x and CS2x is appropriately determined according to the value of the first variation type counter CS1x and the game conditions each time.

  When it is determined in the process of S401x that it is not a big hit (S401x: No), the display mode at the time of disconnection is set (S404x). In the process of S404x, the display mode of the first symbol display device 37x is set to a display mode corresponding to the off symbol, and based on the value of the stop pattern selection counter C3x stored in the execution area of the reserved ball storage area, An effect to be displayed on the third symbol display device 81x is set to indicate whether the reach is front / rear out of reach, reach other than front / rear out, or complete out. In the present embodiment, as described above, the range of values corresponding to each stop pattern of the stop pattern selection counter C3x depends on whether the state is a high probability state, a low probability state, and the operation suspension number N. Different tables are set up.

  Next, the variation pattern at the time of detachment is determined (S405x), the display time of the first symbol display device 37x is set, and the variation time of the third symbol until the third symbol display device 81x stops at the detachment symbol. Is determined. At this time, as in the process of S403x, the values of the variation type counters CS1x and CS2x stored in the counter buffer of the RAM 203x are confirmed, and the normal reach, super reach, and premium reach are determined based on the value of the first variation type counter CS1x. The fluctuation time until the final stop symbol (in this embodiment, the middle symbol Z2x) stops after the occurrence of reach is determined based on the value of the second variation type counter CS2x. For example, the number of fluctuation symbols) is determined.

  When the process of S403x or the process of S405x ends, the effect time to be added to or subtracted from the variation time determined by the first and second type counters CS1x and CS2x is determined (S406x). At this time, the addition / subtraction of the effect time is determined based on the value of the third type counter CS3x stored in the counter buffer of the RAM 203x, the display time of the first symbol display device 37x is set, and the third symbol display The variation time of the device 81x is set. In the present embodiment, the effect time addition / subtraction is determined according to the value of the third variation type counter CS3x, when the variation display time is not changed and when the variation display time is added for one second, the variation display time is set to 2. In the case of adding seconds, four types of addition values are determined for the case of subtracting 1 second from the variable display time.

  In addition, when the variable display time is added or subtracted, a notice effect that increases the expected value of the jackpot on the third symbol display device 81x (for example, a slip effect that causes the change time of the variable symbol to be longer than usual and causes a slip) An effect of displaying a notice character is produced, for example, an effect of making the change time of one change symbol shorter than usual and stopping it immediately). In addition, when the value of the first random number counter C1x is a big hit, since the probability that an added value of 2 seconds is selected is set high, the player expects a big hit by confirming the notice effect. Can do.

  Next, a variation pattern command is set according to the variation pattern (variation time) determined in the process of S403x or S405x (S407x), and a stop symbol command is set according to the stop symbol set in the process of S402x or S404x. (S408x). Then, an effect time addition command is set according to the added value of the effect time determined in the process of S406x (S409x), and the process returns to the variation process.

  Next, with reference to FIGS. 54 to 56, processing performed by the sound lamp control device 113x will be described. FIG. 54 is a flowchart showing a start-up process executed by the MPU 221x in the audio lamp control device 113x, and this start-up process is activated when the power is turned on.

  When the start-up process is executed, first, an initial setting process associated with power-on is executed (S1001x). Specifically, a predetermined value set in advance for the stack pointer is set. Thereafter, depending on whether or not the power-off process flag is turned on, the current start-up process is caused by an instantaneous voltage drop (momentary power failure, so-called “instantaneous power failure”). ) Is determined in the middle of execution (S1002x). As will be described later with reference to FIG. 55, when the sound lamp control device 113x receives a power-off command from the main control device 110x (see S1112x in FIG. 55), it executes a power-off process in S1115x. The power-off process flag is turned on before the power-off process is executed, and the power-off process flag is turned off after the power-off process ends. Therefore, whether or not the power-off process in S1115x is being executed can be determined by the state of the power-off process flag.

  If the power-off processing flag is off (S1002x: No), the current start-up processing is started after the power supply is completely shut down or after a momentary power failure occurs and the power-off in S1115x It was started after the execution of the process was completed, or started only after the MPU 221x of the sound lamp control device 113x was reset (without receiving a power-off command from the main control device 110x) due to noise or the like. is there. Therefore, in these cases, it is confirmed whether or not the data in the RAM 223x is destroyed (S1003x).

  Confirmation of data destruction of the RAM 223x is performed as follows. That is, data as a keyword “55AAh” is written in a specific area of the RAM 223x by the processing of S1006x. Therefore, the data stored in the specific area is checked. If the data is “55AAh”, there is no data destruction in the RAM 223x. If data destruction of the RAM 223x is confirmed (S1003x: Yes), the process proceeds to S1004x, and initialization of the RAM 223x is started. On the other hand, if data destruction of the RAM 223x is not confirmed (S1003x: No), the process proceeds to S1008x.

  If the current start-up process is started after the power supply is completely shut down, the keyword “55AAh” is not stored in the specific area of the RAM 223x (the memory of the RAM 223x is lost due to the power-off). ), It is determined that the data in the RAM 223x is destroyed (S1003x: Yes), and the process proceeds to S1004x. On the other hand, this startup process was started after an instantaneous power failure and after completing the power-off process in S1115x, or reset only to the MPU 221x of the audio lamp control device 113x due to noise or the like When the process starts, since the keyword “55AAh” is stored in the specific area of the RAM 223x, the data in the RAM 223x is determined to be normal (S1003x: No), and the process proceeds to S1008x.

  If the power-off process flag is on (S1002x: Yes), the startup process this time is after an instantaneous power failure has occurred and during the execution of the power-off process of S1115x, the sound lamp control device 113x. The MPU 221x is started after being reset. In such a case, since the power-off process is being executed, the storage state of the RAM 223x is not necessarily correct. Therefore, since control cannot be continued in such a case, the process proceeds to S1004x and initialization of the RAM 223x is started.

  In the processing of S1004x, the entire storage area of the RAM 223x is checked (S1004x). As a check method, first, “0FFh” is written for each byte, and it is read for each byte to check whether it is “0FFh”. The writing and checking for each byte are performed in the order of “55h”, “0AAh”, and “00h” after “0FFh”. As a result of the read / write check of the RAM 223x, all storage areas of the RAM 223x are cleared to zero.

  If it is determined that the read / write check is normal for all the storage areas of the RAM 223x (S1005x: Yes), the keyword “55AAh” is written in the specific area of the RAM 223x and the RAM destruction check data is set (S1006x). By checking the keyword “55AAh” written in the specific area, it is checked whether or not there is data corruption in the RAM 223x. On the other hand, if a reading / writing check abnormality is detected in any storage area of the RAM 223x (S1005x: No), the abnormality of the RAM 223x is notified (S1007x), and an infinite loop is performed until the power is shut off. The abnormality of the RAM 223x is notified by the display lamp 34x. Note that the sound output device 226x may output a sound to notify the RAM 223x of an abnormality.

  In the processing of S1008x, it is determined whether or not the power-off flag is turned on (S1008x). Since the power-off flag is turned on when the power-off process in S1115x is executed (see S1114x in FIG. 55), the power-off flag is turned on by the process in S1114x as described later with reference to FIG. In other words, since the power-off flag is turned on before the power-off process of S1115x is executed, the startup process this time is the moment when the power-off flag is turned on to reach the process of S1008x. This is a case where a power failure has occurred and started in a state where the execution of the power-off process in S1115x is not completed. Therefore, in such a case (S1008x: Yes), the RAM work area is cleared to initialize each process of the sound lamp control device 113x (S1009x), the initial value of the RAM 223x is set (S1010x), and an interrupt is performed. The permission is set (S1011x), and the process proceeds to the main process. The work area of the RAM 223x refers to an area other than an area for storing commands received from the main controller 110x.

  On the other hand, when the power-off flag is turned off, the process of S1008x is reached because the current start-up process is started after, for example, the power supply is completely shut down. This is a case where the process has been reached, or the MPU 221x of the sound lamp control device 113x is reset only (without receiving a power-off command from the main control device 110x) due to noise or the like. Therefore, in such a case (S1008x: No), S1009x, which is the work area clear process of RAM223x, is skipped, the process proceeds to S1010x, the initial value of RAM223x is set (S1010x), and interrupt permission is set. (S1011x) and the process proceeds to the main process.

  Note that the reason for skipping the clear process of S1009x is that when the process from S1004x to the process of S1008x goes through the process of S1006x, all the storage areas of the RAM 223x have already been cleared by the process of S1004x, When only the MPU 221x of the sound lamp control device 113x is reset due to noise or the like and the start-up process is started, the data in the work area of the RAM 223x is stored without being cleared, thereby the sound lamp control device 113x. This is because the control can be continued.

  Next, with reference to FIG. 55, the main process executed after the startup process of the sound lamp control device 113x will be described. FIG. 55 is a flowchart showing main processing executed by the MPU 221x of the sound lamp control device 113x. When the main process is executed, it is first determined whether or not 1 msec or more has elapsed since the main process was started (S1101x). If 1 msec or more has not elapsed (S1101x: No), S1102x to S1109x. The process proceeds to S1110x without performing the process. Whether or not 1 msec has passed in the processing of S1101x is processing relating to display (production) in S1102x to S1109x, and it is not necessary to edit in a short cycle (within 1 msec), whereas S1110x This is because it is preferable to execute the update processing of each counter and the reception processing of the command of S1111x in a short cycle. As a result, it is possible to prevent omission of a command transmitted from the main controller 110x.

  If 1 msec or more has elapsed in the processing of S1101x (S1101x: Yes), the output of each lamp is set so that the lighting mode of the display lamp 34x or the lighting mode of the lamp edited in the processing of S1107x described later is set. (S1102x), and then a power-on notification process is executed (S1103x). In the power-on notification process, when the power is turned on, a notification is given to notify that the power is turned on for a predetermined time (for example, 30 seconds). The notification is performed by the audio output device 226x or the lamp display device 227x. Is called. Moreover, it is good also as what transmits a command to the display control apparatus 114x so that it may alert | report that power was supplied on the screen of the 3rd symbol display apparatus 81x. If the power is not turned on, the process proceeds to S1104x without performing the notification by the power-on notification process.

  In the process of S1104x, a customer waiting effect is executed, and thereafter, a pending number display update process is executed (S1105x). In the customer waiting effect, when the time when the pachinko machine 10x is not played by the player has passed for a predetermined time, the setting of switching the display of the third symbol display device 81x to the title screen is performed, and the setting is displayed as a command as a display control device. 114x. In the number-of-holds display update process, a process for turning on the hold lamp 85x according to the operation hold ball N is performed.

  Thereafter, the frame button input monitoring / effect process is executed (S1106x). This frame button input monitoring / production process monitors the input of whether or not the frame button 22x operated by the player has been pressed to enhance the production effect, and corresponds to the case where the input of the frame button 22x is confirmed. This is a process for setting to produce an effect. For example, when a notice character appears at the start of variable display, pressing the frame button 22x displays the expected value of the jackpot due to the current change, or pressing the frame button 22x during reach production gives you a sense of expectation for the jackpot It is good also as a decision button for changing to the production which can be held, or selecting one reach production out of a plurality of reach productions. If the frame button 22x is not provided, the process of S1106x is omitted.

  When the frame button input monitoring / production process ends, the lamp editing process is executed (S1107x), and then the sound editing / output process is executed (S1108x). In the lamp editing process, lighting patterns and the like of the illumination units 29x to 33x are set so as to correspond to the display performed on the third symbol display device 81x. In the sound editing / output processing, an output pattern of the sound output device 226x is set so as to correspond to the display performed on the third symbol display device 81x, and sound is output from the sound output device 226x according to the setting.

  Thereafter, a liquid crystal effect execution management process is executed (S1109x), and the process proceeds to S1110x. In the liquid crystal effect execution management process, a time synchronized with the time required for the change display performed by the third symbol display device 81x is set based on the change pattern command and the effect time addition command transmitted from the main control device 110x. Based on the time set in the liquid crystal effect execution monitoring process, the effect time of the lamp editing process in S1107x and the sound editing / output process in S1108x is set.

  In the process of S1110x, the variable display process of the third symbol display device 81x is executed. In this variation display process, a plurality of counters (a counter for setting a stop symbol at the time of big hit, a counter for selecting a stop symbol at the time of losing, etc.) mounted on the sound lamp control device 113x are updated. Based on the variation pattern command and stop symbol command transmitted from the control device 110x, the symbol to be stopped and displayed on the third symbol display device 81x is set, or the variation display pattern (rear / rear out, front / rear non-rear reach, complete disengagement) Etc. are set. The stop symbol and the variation pattern are transmitted to the display control device 114x as a command.

  In the process of S1110x, for example, when the command of the variation pattern transmitted from the main controller 110x is “completely out”, the completely out A pattern is selected from the plurality of patterns corresponding to complete out, and the third symbol display A command is transmitted to the display control device 110 so that the device 81x produces a completely off A effect. Therefore, since the detailed variation pattern displayed on the third symbol display device 81x is determined by the sound lamp control device 113x with respect to one variation pattern determined by the main control device 110x, the control of the main control device 110x is performed. The burden can be reduced. Furthermore, since the pattern of each effect determined in the main controller 110x can be reduced, the storage capacity of the ROM 202x can be reduced and the cost can be reduced.

  Then, it receives a command from the main controller 110x (S1111x). When a command is received from the main control device 110x, if the command is used in the sound lamp control device 113x in accordance with the command, processing corresponding to the command is performed, the processing result is stored in the work RAM 233x, and the display control device 114x performs processing. If it is a command to be used, the command is transmitted to the display control device 114x.

  When the processing of S1111x ends, it is determined whether or not the information on occurrence of power interruption is stored in the work RAM 233x (S1112x). The information on occurrence of power interruption is stored when a power interruption command is received from the main controller 110x. If power failure occurrence information is stored in the processing of S1112x (S1112x: Yes), both the power interruption flag and the power interruption processing flag are turned on (S1114x), and the power interruption processing is executed (S1115x). After the power-off process is executed, the power-off process flag is turned off (S1116x), and then the process loops infinitely. In the power-off process, the generation of the interrupt process is prohibited and each output port is turned off to turn off the outputs from the audio output device 226x and the lamp display device 227x. Further, the storage of the information on occurrence of power interruption is also erased.

  On the other hand, if the information on the occurrence of power interruption is not stored in the process of S1112x (S1112x: No), either the inner frame 12x or the front frame 14x is opened, or both the inner frame 12x and the front frame 14x are opened. If there is, a door opening notification process (S1113x) for performing notification using the audio output device 226x and the lamp display device 227x is executed.

  Here, the door opening notification process (S1113x) will be described with reference to FIG. FIG. 56 is a flowchart showing the door opening notification process executed by the MPU 221x of the sound lamp control device 113x. In this door opening notification process, it is determined whether the voice lamp control device 113x has received any of the off-frame open command, the on-frame open command, or the frame close command, and the notification is made according to the determination. It is a process that starts or ends execution.

  In the door opening notification process, first, in the process of S1111x (see FIG. 55), an off-middle frame opening command indicating that the inner frame 12x or the front frame 14x has been opened while the power of the pachinko machine 10x is turned off is received. It is determined whether or not (S1201x). When the off-in-frame release command is received (S1201x: Yes), the voice output device 226x and the lamp display device indicate that the inner frame 12x or the front frame 14x has been released while the power of the pachinko machine 10x is turned off. Notification starts using 227x (S1202x). Specifically, in this notification, for example, in order to indicate that the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned off using the lamp display device 227x, for example, 1 Blinking starts once per second, or the sound output device 226x is used to start notification with an electronic sound "Please check". Thereby, it is possible to notify an unspecified number of people that the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned off.

  After the processing of S1202x, the frame release notification processing is terminated. In addition, when the notification by the process of S1202x has already been executed, when the off-in-frame release command is received again by the process of S1111x (S1201x: Yes), the process of S1202x is not performed again. The process of S1202x that has already been executed is continued.

  On the other hand, in the process of S1111x (see FIG. 55), if the off-in-frame release command has not been received (S1201x: No), the power of the pachinko machine 10x is turned on in the process of S1111x (see FIG. 55). During this time, it is determined whether or not an on-in-frame frame release command indicating that the inner frame 12x or the front frame 14x has been opened is received (S1203x). When the on-frame release command is received (S1203x: Yes), the voice output device 226x and the lamp display device indicate that the inner frame 12x or the front frame 14x has been released while the power of the pachinko machine 10x is turned on. Notification starts using 227x (S1204x). Specifically, in this notification, for example, in order to indicate that the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned on using the lamp display device 227x, for example, 2 Flashing once per second is started, or the sound output device 226x is used to start notification with an electronic sound that “the door is open”. Thereby, it is possible to notify an unspecified number of people that the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned on.

  Furthermore, if the on-frame release command is not received in the processing of S1111x (see FIG. 55) (S1203x: No), the power of the pachinko machine 10x is turned on in the processing of S1111x (see FIG. 55). During this time, it is determined whether or not an on-medium frame closing command indicating that the inner frame 12x and the front frame 14x are closed is received (S1205x). When the on-in-frame closing command is received (S1205x: Yes), the notification started in the process of S1204x is terminated (S1206x). Thereafter, the frame opening notification process is terminated. When the on-frame closing command is not received in the processing of S1111x (see FIG. 55) (S1205x: No), the frame opening notification processing is terminated.

  As described above, when the sound lamp control device 113x receives the off-in-frame release command in the process of S1111x (see FIG. 55), the inner frame 12x or the front frame is turned off while the power of the pachinko machine 10x is turned off. Notification that 14x has been released is started using the audio output device 226x and the lamp display device 227x (S1202x). This notification is made until the RAM erase switch 122x is operated, the power of the pachinko machine 10x is turned on, and the off-in-frame release flag 203ax is turned off in the processing of S116x of the startup processing of the main controller 110x. Continued.

  As described above, in order to turn off the off-in-frame release flag 203ax once turned on, the RAM erase switch 122x is operated, and the power of the pachinko machine 10x is turned on, and the used RAM area is cleared in the process of S116x. The off-in-frame release flag 203ax cannot be turned off. Therefore, when the power of the pachinko machine 10x is turned on, the pachinko machine 10x does not reliably confirm that the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned off. A specific number of persons can be notified.

  Further, as described above, when the sound lamp control device 113x receives the on-in-frame release command in the process of S1111x (see FIG. 55), while the power of the pachinko machine 10x is turned on, Notification that the front frame 14x is opened is started using the audio output device 226x and the lamp display device 227x (S1204x). This notification is continuously performed until the inner frame 12x and the front frame 14x are closed and an on-medium frame closing command is received, so the inner frame 12x or the front An unspecified number of people can be notified that the frame 14x is being opened.

  Returning to the description of FIG. After the door opening notification process (S1113x) is executed, it is determined based on the keyword stored in the RAM 223x whether or not the RAM 223x is destroyed (S1117x), and if the RAM 223x is not destroyed (S1117x: No), Returning to the process, the main process is repeatedly executed. On the other hand, if the RAM 223x is destroyed (S1117x: Yes), the processing is looped infinitely in order to stop the subsequent processing. Here, if it is determined that the RAM is destroyed and an infinite loop is performed, the main process is not executed, and thereafter the display by the third symbol display device 81x does not change. Therefore, since the player can know that an abnormality has occurred, he can call a store clerk or the like of the game hall and ask for repair of the pachinko machine 10x. In addition, when it is confirmed that the RAM 223x is destroyed, the RAM destruction may be notified by the audio output device 226x or the lamp display device 227x.

  As described above, according to the pachinko machine 10x, when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is off, the frame open detection circuit 260x detects the drive voltage Vbx and After outputting the power failure signal SG1bx, the reset signal SG3bx is output. Therefore, even if the power of the pachinko machine 10x is turned off, the MPU 201x can be temporarily started up normally. If the MPU 201x is temporarily activated by the frame opening detection circuit 260x when the power of the pachinko machine 10x is off, the pachinko machine 10x turns on the off-in-frame frame opening flag 203ax. When the off-in-frame release flag 203ax is turned on, the pachinko machine 10x uses the audio output device 226x and the lamp display device 227x when the power to the pachinko machine 10x is turned on next time, so that the inner frame 12x or the front frame 14x is released. Therefore, the pachinko machine 10x in which the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off can be specified. Therefore, even in a game arcade where the hall computer 262x has not been operated for 24 hours, it can be detected that the inner frame 12x or the front frame 14x has been opened when the power of the pachinko machine 10x is turned off.

  The off-in-frame release flag 203ax is turned off when the RAM deletion switch 122x is operated and the used RAM area is cleared in the process of S116x of the startup process of the main controller 110x. Therefore, once the off-in-frame release flag 203ax is turned on, the off-in-frame release flag 203ax cannot be turned off unless the RAM deletion switch 122x is operated to clear the used RAM area in the process of S116x. Therefore, when the inner frame 12x or the front frame 14x is opened and the off-in-frame release flag 203ax is turned on when the power of the pachinko machine is turned off, the fraudster then turns off the in-out frame. It is impossible to turn off the release flag 203ax. Furthermore, the off-frame open flag 203ax cannot be turned off unless the RAM erase switch 122x is operated to clear the used RAM area in the processing of S116x, so when the power of the pachinko machine 10x is turned on, The pachinko machine 10x can reliably notify an unspecified number of people that the inner frame 12x or the front frame 14x has been opened when the power of the pachinko machine 10x is turned off.

  When the power of the pachinko machine 10x is off and the MPU 201x is temporarily activated by the frame open detection circuit 260x, the pachinko machine 10x turns on the off-in-frame open flag 203ax, A pulse signal having a pulse width of 1 msec is output to 262x. This output pulse signal is stored in the hall computer 262x that continues to operate for 24 hours. Therefore, by analyzing the pulse signal stored in the hall computer 262x, the pachinko machine 10x in which the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off is specified. Can do. Further, the hall computer 262x outputs a pulse signal from the pachinko machine 10x, and stores the output time of the output pulse signal, so that the opening time of the specified inner frame 12x of the pachinko machine 10x or the front frame 14x opening time can be detected.

  Further, the frame open detection circuit 260x first stops the power failure signal SG1bx when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on and about 4.4 seconds have elapsed after the turn-on. If the opened inner frame 12x or the opened front frame 14x is closed before about 4.4 seconds have elapsed since the switch SW1x or the switch SW2x is turned on, a power failure signal is generated at the time of closing. SG1bx is stopped). Next, the frame open detection circuit 260x stops the reset signal SG3bx when about 9.4 seconds have elapsed after the switch SW1x or SW2x is turned on (about 4.4 seconds have passed after the switch SW1x or switch SW2x is turned on). If the opened inner frame 12x or the opened front frame 14x is closed before, the reset signal SG3bx is stopped after about 5.0 seconds from the closing). Then, the frame open detection circuit 260x reduces the drive voltage Vbx output to the power supply terminal of the MPU 201x to about 4.0 volts when about 9.9 seconds elapse after the switch SW1x or the switch SW2x is turned on (switch SW1x or If the opened inner frame 12x or the opened front frame 14x is closed before about 4.4 seconds have elapsed after the switch SW2x is turned on, the drive is performed after about 5.5 seconds have elapsed since the closing. Reduce voltage Vbx to about 4.0 volts). Therefore, even if the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine 10x is turned off and the MPU 201x is temporarily activated by the frame opening detection circuit 260x, the frame opening detection circuit 260x The launched MPU 201x can be terminated normally.

  Further, the frame open detection circuit 260x opens the inner frame 12x or the front frame when approximately 4.4 seconds elapses after the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on. Regardless of the open period of 14x, the transistor TR1x stops the output of the drive voltage Vbx, the output of the reset signal SG3bx, the output of the power failure signal SG1bx, and the charging of the capacitor CD4x performed by the power supplied from the capacitor CD1x. After the stop by the transistor TR1x, the frame opening detection circuit 260x outputs the drive voltage Vbx and the reset signal SG3bx by discharging the capacitor CD4x. Therefore, the frame opening detection circuit 260x, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10x is cut off, and a DC voltage of 12 volts is not supplied from the DC power supply DC1x to the frame opening detection circuit 260x. That is, when a DC voltage of about 11.3 volts is supplied from the capacitor CD1x to the frame open detection circuit 260x, the period in which power is supplied from the capacitor CD1x is the open period of the inner frame 12x or the front frame 14x. Regardless, it can be kept in about 4.4 seconds. Therefore, the frame opening detection circuit 260x can detect the opening of the inner frame 12x or the front frame 14x a plurality of times while suppressing the consumption of the electric power charged in the capacitor CD1x.

  Further, the frame open detection circuit 260x is configured so that even if the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on, the inner frame 12x or the front frame 14x is opened before approximately 4.4 seconds elapses. When the frame 12x or the opened front frame 14x is closed, the switch SW1x or the switch SW2x is shut off, the output of the drive voltage Vbx performed by the power supplied from the capacitor CD1x, the output of the reset signal SG3bx, the power failure signal SG1bx And the charging of the capacitor CD4x are stopped. After the inner frame 12x and the front frame 14x are closed, the drive voltage Vbx and the reset signal SG3bx are output by discharging the capacitor CD4x.

  As described above, when the charging of the capacitor CD4x is completed, the driving voltage Vbx and the reset signal SG3bx can be output by discharging the capacitor CD4x. Therefore, the open period of the inner frame 12x or the front frame 14x is approximately If the time is within 4.4 seconds, the output voltage Vbx, the reset signal SG3bx, the power failure signal SG1bx, and the capacitor CD4x that are supplied by supplying power from the capacitor CD1x are further shortened. Can be stopped. Therefore, the power consumption of the capacitor CD1x due to the opening of the inner frame 12x or the front frame 14x can be further suppressed.

  Here, since the capacitor CD1x has a capacitance of 1F and the voltage applied to the capacitor CD1x is approximately 11.3 volts, the charge stored in the capacitor CD1x is the product of the capacitance of the capacitor CD1x and the applied voltage of the capacitor CD1x. To about 11.3 C (coulomb). The electric charge of about 11.3 C stored in the capacitor CD1x is about the output period of the drive voltage Vbx, the output of the reset signal SG3bx, the output of the power failure signal SG1bx and the charge of the capacitor CD4x performed by the power supply from the capacitor CD1x In the case of 4.4 seconds, this corresponds to about 11 times of power supply. Therefore, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine 10x is cut off and the DC voltage of 12 volts is not supplied from the DC power supply DC1x, the inner frame 12x is opened (the switch SW1x Continuity) or the opening of the front frame 14x (conduction of the switch SW2x) is performed a plurality of times, the frame opening detection circuit 260x opens the inner frame 12x or the front frame 14x (conduction or continuity of the switch SW1x). The conduction of the switch SW2x) is reliably detected every time up to about 11 times, and the MPU 201x can be temporarily raised normally to turn on the off-in-frame release flag 203ax. At this time, when the opening of the inner frame 12x or the opening of the front frame 14x is about 11 times, the power stored in the capacitor CD1x decreases, the drive voltage Vbx decreases, the reset signal SG3bx decreases, the power failure signal SG1bx decreases. A decrease and a decrease in the charge amount of the capacitor CD4x occur. However, when the inner frame 12x or the front frame 14x is opened, the voltage of the reset signal SG3bx output from the reset signal output terminal of the frame open detection circuit 260x exceeds about 4.3 volts, and the frame open detection circuit 260x. If the voltage of the drive voltage Vbx output from the power supply output terminal and the power failure signal SG1bx output from the power interruption signal output terminal of the frame open detection circuit 260x exceed about 4.0 volts, the power of the pachinko machine 10x is Even if it is turned off, the MPU 201x can be temporarily started up normally to turn on the off-in-frame release flag 203ax. Furthermore, a pulse signal having a pulse width of 1 msec can be output to the hall computer 262x.

  In the frame open detection circuit 260x, when the inner frame 12x and the front frame 14x are closed (when the switch SW1x and the switch SW2x are shut off), the OUT terminal voltage of the timer IC 1x is about 10.6 volts. Therefore, the terminal between the drain terminal D and the source terminal S of the FET 1x of the frame opening detection circuit 260x and the terminal between the drain terminal D and the source terminal S of the FET 2x are brought into conduction. Further, since the inner frame 12x and the front frame 14x are closed, the terminals between the drain terminal D and the source terminal S of the FET 3x are brought into conduction. However, at this time, since the conduction between the terminals of the emitter terminal e and the collector terminal c of the transistor TR1x is cut off, the drain terminal D and the source terminal of the FET 2x are connected between the drain terminal D and the source terminal S of the FET 1x. The current from the capacitor CD1x does not flow between the terminals with S and between the drain terminal D and the source terminal S of the FET 3x. Therefore, when the inner frame 12x and the front frame 14x are closed, the power charged in the capacitor CD1x is between the drain terminal D and the source terminal S of the FET 1x and between the drain terminal D and the source terminal S of the FET 2x. It is not consumed by flowing between the terminals and between the drain terminal D and the source terminal S of the FET 3x.

  The amount of power that the frame open detection circuit 260x consumes the power of the capacitor CD1x when the power of the pachinko machine 10x is turned off and the inner frame 12x and the front frame 14x are closed is the standby power of the timer IC1x and the power consumption of the NOTIC3x. Degree. In addition, since only the voltage is applied to the gate terminals G of the FETs 1x to 3x, the power consumed by the FETs 1x to 3x is very small. Therefore, the consumption of these powers does not cause a significant decrease in the charge amount of the capacitor CD1x.

  In the pachinko machine 10x of the present embodiment, notification that the inner frame 12x or the front frame 14x has been opened is performed using the audio output device 226x and the lamp display device 227x controlled by the audio lamp control device 113x. However, it is not limited to this. The notification that the inner frame 12x or the front frame 14x has been opened is not performed using the audio output device 226x and the lamp display device 227x controlled by the audio lamp control device 113x, but can be operated with the rise of the MPU 201x. Of course, it is also possible to use an audio output device or a lamp display device controlled by the MPU 201x. However, in this case, when the power of the pachinko machine 10x is turned off, the inner frame 12x or the front frame 14x is opened by an unauthorized person, and the MPU 201x is temporarily started up by the frame opening detection circuit 260x. Then, an audio output device and a lamp display device that are controlled by the MPU 201x are also started up, and when the off-in-frame opening flag 203ax is turned on, a fraudulent person is notified. This is executed when the power of the pachinko machine 10x is turned off, the inner frame 12x or the front frame 14x is opened while the power is turned off, and the MPU 201x is temporarily started up by the frame opening detection circuit 260x. The processing of S201x to S213x: Yes to S224x (see FIG. 48), which is performed, is performed when at least the reset signal SG3bx output from the reset signal output terminal of the frame opening detection circuit 260x by discharging the capacitor CD4x is about 4. The program is programmed to complete execution during the period until it drops to 3 volts, that is, during a period of about 5.0 seconds (see FIG. 44). Taking advantage of this specification, when notifying with the audio output device or lamp display device controlled by the MPU 201x, the time after the power of the pachinko machine 10x is turned on is counted by a counter, for example, the power of the pachinko machine 10x is What is necessary is just to comprise so that alerting | reporting may be started 30 seconds after turning on (after a counter time-measures 30 seconds). Then, when the MPU 201x is temporarily started up by the frame opening detection circuit 260x, 30 seconds after the pachinko machine 10x is turned on, that is, before the counter counts 30 seconds. Since the MPU 201x has been shut down (because it has been terminated), the notification is not executed. On the other hand, when the power of the pachinko machine 10x is normally turned on and the MPU 201x is started, the notification is performed. Notification can be performed when the power of the pachinko machine 10x is turned on normally, while preventing notification to the actor.

  In the pachinko machine 10x of the present embodiment, when the power of the pachinko machine 10x is turned off, the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on. Although the output of the voltage Vbx, the output of the reset signal SG3bx, the output of the power failure signal SG1bx, and the charging of the capacitor CD4x are started, the present invention is not limited to this. That is, when the connection of each component mounted on the frame opening detection circuit 260x of the pachinko machine 10x is changed, the inner frame 12x or the front frame 14x is opened, and the opened inner frame 12x or front frame 14x is closed In addition, from the closing time, the output of the drive voltage Vbx, the output of the reset signal SG3bx, the output of the power failure signal SG1bx, and the charging of the capacitor CD4x may be started.

  However, in the frame open detection circuit 260x of the pachinko machine 10x of this embodiment, when the inner frame 12x or the front frame 14x is opened and the switch SW1x or the switch SW2x is turned on, the output of the reset signal SG3bx is started. Thus, the opening of the inner frame 12x or the front frame 14x can be detected quickly. Therefore, particularly during business hours when the power of the pachinko machine 10x is turned on, the inner frame 12x or the front frame 14x is opened before the main controller 110x or the game board 13x is cheated. Alternatively, the opening of the front frame 14x can be detected. Accordingly, it is possible to prevent an abnormal operation due to an illegal act that occurs when power is supplied to the pachinko machine 10x.

  In addition, the main frame opening detection circuit 260x is used to store separately the opening of the inner frame 12x or the front frame 14x using a flag, and separately notify the opening of the inner frame 12x or the front frame 14x. When it is desired to separately store in the hall computer 262x which of the inner frame 12x and the front frame 14x is opened, the following configuration may be used. First, one new frame opening detection circuit 260x used in this embodiment is added, the switch SW2x connected in parallel to the switch SW1x is disconnected, and the disconnected switch SW2x is newly added to the frame opening detection circuit 260x. Connecting. Specifically, one end of the disconnected switch SW2x is connected to one end of the capacitor CD1x of the newly added frame opening detection circuit 260x, the VDD terminal of the timer IC1x, and the RES terminal of the timer IC1x. The ends may be connected to one end of the resistor R1x, one end of the resistor R2x, one input terminal of the NOTIC3x, one end of the resistor R3x, and the emitter terminal e of the transistor TR1x of the newly provided frame opening detection circuit 260x.

  Then, the power supply output terminal, reset signal output terminal, and power interruption signal output terminal of the added frame opening detection circuit 260x are replaced with the power supply output terminal, reset signal output terminal, and power interruption signal output of the existing frame opening detection circuit 260x, respectively. Connect in parallel to the terminals. Further, the reset signal output terminal of the added frame opening detection circuit 260x is connected to an input port different from the input port to which the reset signal output terminal of the existing frame opening detection circuit 260x is connected to the input / output port 205x. Accordingly, the MPU 201x can be temporarily activated separately when the switch SW1x is conductive (the inner frame 12x is opened) and when the switch SW2x is conductive (the front frame 14x is opened). Further, when the switch SW1x is conductive (the inner frame 12x is opened), the reset signal SG3bx output from the existing frame open detection circuit 260x and the switch SW2x is conductive (the front frame 14x is opened). In addition, the reset signal SG3bx output from the newly added frame opening detection circuit 260x can be separately output to the input / output port 205x.

  In addition, four flags are provided in the RAM 203x: an inner frame release flag during OFF, a front frame release flag during OFF, an inner frame release flag during ON, and a front frame release flag during ON. In step S110x of the start-up process (see FIG. 47), the voltage (reset signal SG3bx) output from the existing frame opening detection circuit 260x to the input / output port 205x is read and the newly added frame opening detection is performed. The voltage (reset signal SG3bx) output from the circuit 260x to the input / output port 205x may be read. In accordance with the read result, in the process of S112x, the off inner frame release flag or the off front frame release flag is turned on separately.

  In the process of S205x of the main process (see FIG. 48), when the off-inner frame release flag is turned on, an “off-inner frame release command” is transmitted from the MPU 201x to the audio lamp control device 113x, and the off-inner frame release flag is turned off. When the middle front frame release flag is turned on, an “off middle front frame release command” is transmitted from the MPU 201x to the sound lamp control device 113x. When the voice lamp control device 113x receives each command transmitted from the MPU 201x when the power of the pachinko machine 10x is turned on, the voice lamp control device 113x receives the off-inner frame release command and is off. Different notifications are made when a front frame release command is received. For example, a different warning sound is emitted from the audio output device 226x, or the lighting mode of the lamp display device 227x is changed.

  Further, the pulse width of the pulse signal transmitted from the pachinko machine 10x to the hall computer 262x may be changed in the process of S206x according to the ON state of each flag of the off-inner inner frame release flag or the off-front frame release flag. For example, when the off-inner frame opening flag is on, a pulse signal having a pulse width of about 1 msec is transmitted to the hall computer 262x, and when the off-side front frame opening flag is on, the pulse width is about 2 msec. A pulse signal may be transmitted to the hall computer 262x. As a result, when the power of the pachinko machine 10x is turned off, the pachinko machine 10x can separately notify whether the inner frame 12x has been opened or the front frame 14x has been opened. It can be stored separately in the computer 262x.

  Further, in the process of S217x of the main process (see FIG. 48), the voltage (reset signal SG3bx) output from the existing frame opening detection circuit 260x to the input / output port 205x is read, and a newly added frame opening detection circuit. The voltage (reset signal SG3bx) output from 260x to the input / output port 205x may be read. Depending on the read result, in the process of S219x or S220x, the on-inner frame release flag or the on-front frame release flag is turned on separately.

  Then, in the process of S208x of the main process (see FIG. 48), when the on-inner frame release flag is turned on, an “on-inner frame release command” is transmitted from the MPU 201x to the sound lamp control device 113x and turned on. When the middle front frame release flag is turned on, an “on middle front frame release command” is transmitted from the MPU 201x to the sound lamp control device 113x. When each of the commands transmitted from the MPU 201x is received by the sound lamp control device 113x, the sound lamp control device 113x is different depending on whether it receives an on-inner frame release command or an on-front frame release command. An aspect is notified. For example, a different warning sound is emitted from the audio output device 226x, or the lighting mode of the lamp display device 227x is changed. Thereby, when the power of the pachinko machine 10x is turned on, the pachinko machine 10x can separately notify whether the inner frame 12x has been opened or the front frame 14x has been opened.

  In the present embodiment, the pulse signal output from the pachinko machine 10x is output to the hall computer 262x having a different installation location from the pachinko machine 10x. However, the present invention is not limited to this. A dedicated storage device having the function of the hall computer 262x may be provided for each pachinko machine 10x, and the dedicated storage device may be disposed on the back side of each pachinko machine 10x provided with the main controller 110x and the like. In this case, more preferably, a dedicated storage device, such as the main control device 110x, the payout control device 111x, and the launch control device 112x, is stored in the substrate box, and the box base and the box cover provided in the substrate box are stored. Are connected by a sealing unit (not shown) so that they cannot be opened (connection by caulking structure). Then, a seal seal (not shown) is attached to the connecting portion between the box base and the box cover so as to cover the box cover and the box base.

  Next, a pachinko machine according to a seventh embodiment will be described with reference to FIGS. The pachinko machine according to the seventh embodiment is obtained by changing the start-up process, the timer interrupt process, and the main process of the pachinko machine 10x according to the sixth embodiment. Specifically, in the pachinko machine according to the seventh embodiment, a power-on counter 203cx (not shown) that starts timing when the MPU 201x is started up is provided in the RAM 203x, and the timing period by the power-on counter 203cx is If there is information on the occurrence of a power interruption despite being within a predetermined period (within this embodiment, within 5.0 seconds), the inner frame 12x or the front frame when the pachinko machine is powered off. 14x is opened, and the frame open detection circuit 260x determines that the MPU 201x is temporarily started up, and turns on the off-frame open flag 203ax.

  According to the pachinko machine of the seventh embodiment, when the power of the pachinko machine is turned off, whether the inner frame 12x or the front frame 14x is opened is determined according to the timing of the power-on counter 203cx. To do. Therefore, when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off, power is supplied from the frame opening detection circuit 260x to the input / output port 205x, and the frame opening detection circuit 260x. It is not necessary for the MPU 201x to detect whether or not the output from the I / O port 205x is high. Therefore, according to the pachinko machine of the seventh embodiment, when the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine is turned off, the power is supplied from the frame open detection circuit 260x to the input / output port 205x. Compared with the pachinko machine 10x of the sixth embodiment (the power supply is supplied from the frame opening detection circuit 260x to the input / output port 205x, and the output from the frame opening detection circuit 260x to the input / output port 205x) Compared with the pachinko machine 10x of the sixth embodiment in which the MPU 201x detects whether or not is high), it is possible to suppress the consumption of the electric power stored in the capacitor CD1x.

  The power-on counter 203cx (not shown) is powered on by the pachinko machine 10x, and a start-up process (FIG. 57) is executed. After a start-up process S119x (see FIG. In this embodiment, it is a counter that measures whether or not 5.0 seconds) has elapsed. The power-on counter 203cx is set to “0 (zero)” in the start-up process, and starts counting up every time the timer interrupt process (see FIG. 58) is executed (every 2 milliseconds). ) Count up by one. When this count-up exceeds “2500 (5.0 seconds)” and reaches “2501”, the count-up is terminated. Therefore, the power-on counter 203cx can count whether 5.0 seconds have elapsed since S119x of the startup process.

  Next, with reference to FIG. 57, a startup process executed by the MPU 201x of the pachinko machine according to the seventh embodiment will be described. FIG. 57 is a flowchart showing start-up processing executed by the MPU 201x of the pachinko machine according to the seventh embodiment. Note that the same parts as those in the start-up process of the pachinko machine 10x according to the sixth embodiment described above with reference to FIG.

  In the pachinko machine startup process of the seventh embodiment, the processes of S110x to S112x of the startup process of the pachinko machine 10x of the sixth embodiment are deleted, and the processes of S118x and S119x are added. In the start-up process of the pachinko machine of the seventh embodiment, the power-on counter 203cx is set to “0 (zero)” after the process of S109x or S117x (S118x). Then, the power-on counter 203cx starts counting up (S119x). Thereafter, the process proceeds to S113x.

  Note that the processing of S118x to S119x is executed immediately after the processing of S109x is completed or immediately after the processing of S117x is completed. That is, the processing of S118x to S119x is executed immediately after various settings of the MPU 201x are completed. Therefore, when the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine 10x is turned off, the detection can be started immediately by the processing of S118x to S119x.

  Next, a timer interrupt process executed by the MPU 201x of the pachinko machine according to the seventh embodiment will be described with reference to FIG. FIG. 58 is a flowchart showing a timer interrupt process executed by the MPU 201x of the pachinko machine according to the seventh embodiment. The timer interrupt process of the pachinko machine of the seventh embodiment is executed, for example, every 2 milliseconds by the MPU 201x of the main controller 110x, similarly to the timer interrupt process of the pachinko machine 10x of the sixth embodiment. In addition, the same number is attached | subjected to the part same as the timer interruption process of the pachinko machine 10x of 6th Embodiment mentioned above in FIG. 51, the description is abbreviate | omitted, and only a different part is demonstrated.

  In the timer interrupt process of the pachinko machine of the seventh embodiment, the processes of S506x and S507x are added to the timer interrupt process of the pachinko machine 10x of the sixth embodiment. In the timer interrupt process of the pachinko machine of the seventh embodiment, after the process of S503x, it is determined whether or not the count value of the power-on counter 203cx is greater than “2500” (S506x). Since the timer interrupt process is executed every 2 msec, if the count value of the power-on counter 203cx is “2500”, the count value is 2500 (count value) × 2 msec, which is 5.0 sec, and the process of S119x This indicates that 5.0 seconds have elapsed since the power-on counter 203cx started counting up.

  If the count value of the power-on counter 203cx is equal to or smaller than “2500” (S506x: No), 5.0 seconds have elapsed since the count-up of the power-on counter 203cx was started (after the processing of S119x was started). Therefore, the count value of the power-on counter 203cx is incremented by “1” (S507x). On the other hand, if the count value of the power-on counter 203cx is larger than “2500”, that is, if the count value of the power-on counter 203cx is “2501” (S506x: Yes), the count-up of the power-on counter 203cx is started. Since 5.0 seconds have elapsed since the start of the process of S119x, the process of S507x is skipped and the count-up of the power-on counter 203cx is stopped.

  When it is determined “Yes” in the process of S506x and when the process of S507x is completed, the process proceeds to S504x.

  Next, with reference to FIG. 59, the main process performed by MPU201x of the pachinko machine of 7th Embodiment is demonstrated. FIG. 59 is a flowchart showing main processing executed by the MPU 201x of the pachinko machine according to the seventh embodiment. In addition, the same number is attached | subjected to the part same as the main process of the pachinko machine 10x of 6th Embodiment mentioned above in FIG. 48, the description is abbreviate | omitted, and only a different part is demonstrated.

  In the main process of the pachinko machine of the seventh embodiment, the processes of S225x and S226x are added to the main process of the pachinko machine 10x of the sixth embodiment. In the main process of the pachinko machine of the seventh embodiment, after the process of S222x, the count value of the power-on counter 203cx is “2500” or less (S225x), that is, the power-on counter 203cx is incremented in the process of S119x. It is determined whether or not 5.0 seconds have elapsed since the start. If the count value of the power-on counter 203cx is “2500” or less (S225x: Yes), the off-in-frame release flag 203ax is turned on (S226x), and the process proceeds to S223x. When the count value of the power-on counter 203cx is “2500” or less, the following two patterns can be considered, but the off-in-frame release flag 203ax is turned on regardless of which pattern occurs.

  The first pattern is a case where the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily activated by the frame open detection circuit 260x when the power of the pachinko machine is turned off. In this case, the falling edge of the power failure signal SG1bx is input to the MPU 201x together with the drive voltage Vbx and the reset signal SG3bx from the frame opening detection circuit 260x, and the NMI interrupt process (see FIG. 53) is executed. After the raising process (FIG. 57), it is determined in the process of S213x that there is information on occurrence of power interruption (S213x: Yes), and the processes of S221x to S225x are executed. Here, when the MPU 201x is temporarily raised by the frame opening detection circuit 260x, the power failure signal SG1bx output from the frame opening detection circuit 260x is output from the start of output of the power failure signal SG1bx (MPU 201x is started to rise). ) And will fall in about 4.4 seconds. Therefore, if the count value of the power-on counter 203cx is set to “2500” (set to 5.0 seconds), the processing is performed until the count value of the power-on counter 203cx reaches “2500”. It is possible to shift to the processing of S225x. Accordingly, when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off, and the MPU 201x is temporarily activated by the frame open detection circuit 260x, the count value of the power-on counter 203cx Is equal to or less than “2500” (S225x: Yes), it is determined that the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off, and the off-in-frame release flag 203ax is turned on. (S226x).

  The second pattern is a case where the power of the pachinko machine is turned on and the power of the pachinko machine is turned off within about 4.4 seconds after the power is turned on. In this case, after the power of the pachinko machine is turned off (before the determination of S213x), the power failure signal SG1ax output from the power failure monitoring circuit 252x falls, and the NMI interrupt process (see FIG. 53) is executed. In the process of S213x, it is determined that there is power-off occurrence information (S213x: Yes), and the processes of S221x to S225x are executed. Here, since the count value of the power-on counter 203cx is set to “2500” (because it is set to 5.0 seconds), the power of the pachinko machine is turned on, and about 4.4 from the time when the power is turned on. Even when the power of the pachinko machine is turned off within 2 seconds, it is determined that the count value of the power-on counter 203cx is “2500” or less (S225x: Yes), and the off-in-frame release flag 203ax is turned on (S226x).

  In the second pattern, the pachinko machine needs to be turned on and off, so that it cannot be executed by an unauthorized person and is limited to being executed by a store clerk. Therefore, in the case of the second pattern, the store clerk can recognize that the off-in-frame release flag 203ax is turned on by his / her own action, so the off-in-frame release flag 203ax that has been turned on is set to off again. can do. Therefore, even in the case of the second pattern, there is no problem even if the off-in-frame release flag 203ax is turned on in the process of S226x.

  If the count value of the power-on counter 203cx is not “2500” or less in the process of S225x (S225x: No), at least 5.0 seconds have elapsed since the count-up of the power-on counter 203cx was started in the process of S119x. Since it does not correspond to any of the two patterns described above, the process of S226x is skipped and the process proceeds to S223x. Since the frequency of occurrence of the two patterns described above is low, 5.0 seconds have elapsed since the count-up of the power-on counter 203cx is started in the process of S119x, that is, the count value of the power-on counter 203cx is “2500. It is normal to determine that it is not less than (S225x: No).

  Thus, according to the pachinko machine of the seventh embodiment, when the power of the pachinko machine is turned off, whether the inner frame 12x or the front frame 14x is opened is determined between the timings of the power-on counter 203cx. Accordingly, the determination is made (depending on whether or not 5.0 seconds have elapsed since the count-up of the power-on counter 203cx was started in the process of S119x). Therefore, when the power of the pachinko machine is turned off and the inner frame 12x or the front frame 14x is opened, power is supplied from the frame open detection circuit 260x to the input / output port 205x, and the frame open detection circuit 260x supplies the input / output port. It is not necessary for the MPU 201x to detect whether the output to the 205x is high. Therefore, according to the pachinko machine of the seventh embodiment, when the power of the pachinko machine is turned off and the inner frame 12x or the front frame 14x is opened, power is supplied from the frame open detection circuit 260x to the input / output port 205x. Compared with the pachinko machine 10x of the sixth embodiment (whether power is supplied from the frame opening detection circuit 260x to the input / output port 205x and the output from the frame opening detection circuit 260x to the input / output port 205x is high. In comparison with the pachinko machine 10x of the sixth embodiment in which the MPU 201x detects whether or not), the consumption of the electric power stored in the capacitor CD1x can be suppressed.

  Next, a pachinko machine according to an eighth embodiment will be described with reference to FIGS. The pachinko machine according to the eighth embodiment is obtained by changing the start-up process and the main process of the pachinko machine 10x according to the sixth embodiment. Specifically, the pachinko machine according to the eighth embodiment outputs a pulse signal having a pulse width of about 1 msec to the hall computer 262x every time the start-up process is executed.

  According to the pachinko machine of the eighth embodiment, each time the start-up process is executed, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262x, so that the power of the pachinko machine is turned off. Sometimes, the hall computer 262x that has been operating for 24 hours can store the fact that the inner frame 12x or the front frame 14x is opened and the MPU 201x is temporarily started up by the frame opening detection circuit 260x. As described above, when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off, a pulse signal of about 1 msec is output to the hall computer 262x to open the hall. Since it is stored in the computer 262x, when the power of the pachinko machine is turned off, the off-in-frame opening flag 203ax for storing that the inner frame 12x or the front frame 14x is opened can be made unnecessary. Therefore, the memory capacity of the RAM 203x can be reduced. Furthermore, since the determination regarding the off-in-frame release flag 203ax (the processes of S110x to S112x in FIG. 47 and S204x to S206x in FIG. 48) can be made unnecessary, the process for determining the off-in-frame release flag 203ax Program capacity can be reduced.

  First, with reference to FIG. 60, a startup process executed by the MPU 201x of the pachinko machine according to the eighth embodiment will be described. FIG. 60 is a flowchart showing start-up processing executed by the MPU 201x of the pachinko machine according to the eighth embodiment. Note that the same parts as those in the start-up process of the pachinko machine 10x according to the sixth embodiment described above with reference to FIG.

  In the pachinko machine startup process of the eighth embodiment, the processes of S110x to S112x of the startup process of the pachinko machine 10x of the sixth embodiment are deleted, and the process of S120x is added. Further, in the pachinko machine start-up process of the eighth embodiment, the processing content of S116x of the start-up process of the pachinko machine 10x of the sixth embodiment is changed to be the process of S121x.

  In the start-up process of the pachinko machine according to the eighth embodiment, after the process of S101x, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262x (S120x). Thereafter, the process proceeds to S102x. In the process of S120x, since a pulse signal having a pulse width of about 1 msec is output, at this time, at least about 1 msec is required to complete the process of S120x. When shortening the time until the completion of the processing of S120x (about 1 msec), the pulse signal output to the hall computer 262x is started in the processing of S120x, and then the processing is shifted to S102x and the wait of S102x The pulse signal being output may be stopped about 1 msec after the processing of S120x is started within the time. Since the wait process of S102x waits for about 1.0 second, there is no problem even if the process of stopping the pulse signal started to be output in the wait process is executed.

  Further, in the pachinko machine start-up process of the eighth embodiment, after the process of S115x, the used area of the RAM 203x is cleared to 0 (S121x), and then the process proceeds to S117x. In the pachinko machine according to the eighth embodiment, the off-in-frame release flag 203ax is not necessary. (Execution in the process) becomes unnecessary. Therefore, in the process of S121x, only the process of clearing the used area of the RAM 203x to 0 is executed.

  Next, with reference to FIG. 61, the main process performed by MPU201x of the pachinko machine of 8th Embodiment is demonstrated. FIG. 61 is a flowchart showing main processing executed by the MPU 201x of the pachinko machine according to the eighth embodiment. In addition, the same number is attached | subjected to the part same as the main process of the pachinko machine 10x of 6th Embodiment mentioned above in FIG. 48, the description is abbreviate | omitted, and only a different part is demonstrated.

  In the main process of the pachinko machine of the eighth embodiment, the processes of S204x to S206x of the main process of the pachinko machine 10x of the sixth embodiment are deleted. That is, in the main process of the pachinko machine according to the eighth embodiment, after the process of S203x, it is determined whether or not the on-in-frame release flag 203bx is on (S207x). If the on-frame open flag 203bx is on (S207x: Yes), the inner frame 12x or the front frame 14x is open while the power of the pachinko machine is on, so the on-frame open to the sound lamp control device 113x. A command is transmitted (S208x), and the process proceeds to S210x. On the other hand, if the on-in-frame release flag 203bx is off (S207x: No), the inner frame 12x or the front frame 14x is not opened (because the inner frame 12x and the front frame 14x are closed), so the sound lamp An on-frame closing command is transmitted to the control device 113x (S209x), and the process proceeds to S210x.

  Here, there is no determination (the processing of S204x to S206x) about the off-in-frame release flag 203ax provided in the pachinko machines of the sixth embodiment and the seventh embodiment for the following reason. That is, the pachinko machine according to the eighth embodiment has a pulse width of about 1 msec to the hall computer 262x when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off. By outputting a signal, it can be stored in the hall computer 262x that has been operating for 24 hours that the inner frame 12x or the front frame 14x has been opened. Thereby, in the pachinko machine according to the eighth embodiment, when the power of the pachinko machine is turned off, the off-in-frame release flag 203ax for storing that the inner frame 12x or the front frame 14x is released is unnecessary. Become. For this reason, in the pachinko machine of the eighth embodiment, there is no determination regarding the off-in-frame release flag 203ax.

  As described above, according to the pachinko machine of the eighth embodiment, the off-in-frame release flag 203ax is not necessary, so that the memory capacity of the RAM 203x can be reduced. Further, according to the pachinko machine of the eighth embodiment, the determination regarding the off-in-frame release flag 203ax (the processing of S110x to S112x in FIG. 47 and S204x to S206x in FIG. 48) is unnecessary, so the off-in-frame release. It is possible to reduce the program capacity of the process for performing the determination on the flag 203ax.

  Further, according to the pachinko machine of the eighth embodiment, every time the start-up process is executed, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262x, so that the power of the pachinko machine is turned off. When the inner frame 12x or the front frame 14x is opened, the fact that the MPU 201x is temporarily started up by the frame opening detection circuit 260x can be stored in the hall computer 262x that continues to operate for 24 hours. Therefore, the pachinko machine in which the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off can be specified by the pulse signal stored in the hall computer 262x. Further, the hall computer 262x outputs the pulse signal from the pachinko machine, and stores the output time of the output pulse signal, so that the inner frame 12x opening time of the specified pachinko machine or the front frame 14x The opening time can be detected.

  As mentioned above, although this invention was demonstrated based on the pachinko machine of 6th Embodiment to 8th Embodiment, this invention is not limited to the said form at all, and various in the range which does not deviate from the meaning of this invention. It can be easily guessed that the deformation can be improved.

  Needless to say, it is possible to combine the pachinko machines described in the sixth to eighth embodiments to realize a pachinko machine having the functions of the respective embodiments.

  In the sixth to eighth embodiments, when the off-in-frame opening flag 203ax is on, the off-in-frame opening command is transmitted to the sound lamp control device 113x, and a pulse having a pulse width of 1 msec is transmitted to the hall computer 262x. Although a signal is output, the present invention is not limited to this. When the off-in-frame release flag 203ax is on, the main controller 110x does not transmit a command to the sound lamp controller 113x, contrary to the pachinko machines of the sixth to eighth embodiments, and the hall While the pulse signal is not output to the computer 262x, if the off-in-frame opening flag 203ax is off, the main controller 110x sends a command to the sound lamp controller 113x and sends the pulse signal to the hall computer 262x. You may comprise so that it may output. When the main control device 110x is configured in this way, the sound lamp control device 113x does not receive a command from the main control device 110x within a predetermined time from the power-on of the pachinko machine. What is necessary is just to comprise so that it may determine with the inner frame 12x or the front frame 14x having been open | released during off. Similarly, when the hall computer 262x does not receive a pulse signal from the main controller 110x within a predetermined time from the power-on of the pachinko machine, the inner frame 12x or the front frame 14x is opened during the power-off of the pachinko machine. What is necessary is just to comprise so that it may determine. With the above configuration, when the off-in-frame opening flag 203ax is on, a pachinko machine that does not transmit a command to the audio lamp control device 113x and does not output a pulse signal to the hall computer 262x can be realized.

  In the sixth to eighth embodiments, a pulse signal having a pulse width of about 1 msec is output from the pachinko machine to the hall computer 262x, and the opening of the inner frame 12x or the front frame 14x is stored in the hall computer 262x. However, it is not limited to this. For example, a pachinko machine is provided with an EEPROM (Electronically Erasable and Programmable Read Only Memory) and a backup RAM. The EEPROM and backup RAM are connected to the input / output port 205x via a bus line. With this configuration, the opening of the inner frame 12x or the front frame 14x can be stored in the EEPROM or the backup RAM. Then, when the power of the pachinko machine is turned on, the storage of the EEPROM and the backup RAM is confirmed by the MPU 201x. Thereby, opening of the inner frame 12x or the front frame 14x can be detected using a pachinko machine without using the hall computer 262x. In other words, the role of the hall computer 262x can be assigned to the EEPROM or the backup RAM (the role of the “specific device” described in the claims can be assigned to the EEPROM or the backup RAM). Note that the RAM 203x may be used as the backup RAM.

  Further, in the sixth embodiment to the eighth embodiment, the MPU 201x is a target to be temporarily started by outputting the drive voltage Vbx, the reset signal SG3bx, and the power failure signal SG1bx from the frame opening detection circuit 260x, but is not limited thereto. It is not a thing. For example, when the CPU (MPU) and RAM different from the MPU 201x are provided in the main controller 110x, and the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off, The CPU (MPU) and the RAM may be temporarily started up by the frame opening detection circuit 260x. Specifically, first, an off-frame open flag 203ax is provided in a separately provided RAM. A CPU (MPU) provided separately from the power output terminal, reset signal output terminal, and power interruption signal output terminal of the frame opening detection circuit 260x is connected to a RAM provided separately from the power output terminal of the frame opening detection circuit 260x. Connect. Further, a separately provided CPU (MPU) and a separately provided RAM are connected. As a result, when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off, the CPU (MPU) and the RAM provided separately by the frame opening detection circuit 260x temporarily rise. The off-in-frame release flag 203ax provided in another RAM is turned on. Therefore, when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off, the opening can be stored in a separately provided RAM. Note that a single-chip integrated circuit in which a CPU (MPU) provided separately from the frame opening detection circuit 260x and a RAM provided separately is integrated may be used. In this case, since the signals (drive voltage Vbx, power failure signal SG1bx, and reset signal SG3bx) output from the frame opening detection circuit 260x are directly input to the CPU (MPU), the sixth embodiment to the eighth embodiment. The multiplexers MP1x to MP3x used in the pachinko machine are not necessary. Further, the RAM provided separately from the CPU (MPU) provided separately may be provided not in the main control device 110x but in, for example, the power supply device 115x outside the main control device 110x.

  In the sixth to eighth embodiments, the voltage output from the OUT terminal of the timer IC 1x provided in the frame open detection circuit 260x is the inner frame 12x or the front frame depending on the time constants of the resistor R1x and the capacitor CD2x. Although set to be zero volts about 4.4 seconds after the opening of 14x, it is not limited to this. For example, when the resistance value of the resistor R1x is set to 200 kΩ, the capacitance value of the capacitor CD2x is set to 10 μF, and the time constant is set to about 2 seconds, the voltage output from the OUT terminal of the timer IC1x is changed to the inner frame 12x or the front surface. It can be zero volts about 2 seconds after the frame 14x is opened. Therefore, the startup process (see FIG. 47) that is executed when the MPU 201x is temporarily started up by the frame opening detection circuit 260x, and the main processes S201x to S213x: Yes to S224x (see FIG. 48). ) Can be executed in a relatively short time (specifically, the above processing is performed for about 2 seconds when the inner frame 12x or the front frame 14x is opened and the voltage is output from the OUT terminal of the timer IC 1x). When the reset signal SG3bx output from the reset signal output terminal of the frame open detection circuit 260x can be executed in a total of 7 seconds, ie, about 5 seconds until the reset signal SG3bx drops to about 4.3 volts), Thus, by setting the time constant to about 2 seconds, the output period of the voltage output from the OUT terminal of the timer IC 1x after the inner frame 12x or the front frame 14x is opened It can be suppressed to approximately 2 seconds. Therefore, when the inner frame 12x or the front frame 14x is opened when the power of the pachinko machine is turned off, it is possible to suppress the consumption of the electric power stored in the capacitor CD1x.

  In the sixth to eighth embodiments, when the inner frame 12x or the front frame 14x is opened, the notification is executed using the audio lamp control device 113x. However, the present invention is not limited to this. . When the inner frame 12x or the front frame 14x is opened, notification may be executed using the display control device 114x in addition to notification using the sound lamp control device 113x. In this case, when the audio lamp control device 113x receives the off-in-frame release command or the on-in-frame release command, the audio lamp control device 113x receives the off-in-frame release command or the on-in-frame release command received by the display control device 114x. Send. When the display control device 114x receives the off-in-frame release command or the on-in-frame release command, the display control device 114x starts to display "Check" or "The door is open" on the third symbol display device 81x. What is necessary is just to comprise. With this configuration, in addition to the notification by the sound lamp control device 113x, the display control device 114x also provides notification, so that it is easier to understand and it is possible to notify an unspecified number of people that the inner frame 12x or the front frame 14x has been opened. it can.

  In the sixth to eighth embodiments, signals (drive voltage Vax, power failure signal SG1ax and reset signal SG3ax) output from the power supply device 115x and signals (drive voltage Vbx, output from the frame open detection circuit 260x) are output. The switching between the power failure signal SG1bx and the reset signal SG3bx) is performed using the multiplexers MP1x to MP3x, but is not limited thereto. Switching between signals (drive voltage Vax, power failure signal SG1ax and reset signal SG3ax) output from power supply device 115x and signals (drive voltage Vbx, power failure signal SG1bx and reset signal SG3bx) output from frame open detection circuit 260x, Instead of the multiplexers MP1x to MP3x, three OR circuits that are OR circuits may be used.

  In the sixth embodiment to the eighth embodiment, the process of S218x for determining whether the inner frame 12x or the front frame 14x is opened while the power of the pachinko machine is turned on, and the process of S218x Depending on the determination, the process of S219x for turning on the on-in-frame release flag 203bx and the process of S220x for turning off the on-in-frame release flag 203bx were executed in the remaining time of the main process, but this is limited to this. It is not a thing. You may perform this process of S218x-S220x within the regular process of a 4 msec period of a main process. Moreover, you may perform the process of S218x-S220x within the timer interruption process performed every 2 milliseconds.

  In the sixth embodiment and the seventh embodiment, when the off-in-frame opening flag 203ax is on, the sound output device 226x and the lamp display device 227x are used for notification, and the hall computer 262x is notified for 1 ms. However, the present invention is not limited to this. That is, when the off-in-frame opening flag 203ax is on, the 1 m-second pulse signal is not output to the hall computer 262x, and only the notification is performed using the audio output device 226x and the lamp display device 227x. May be. Conversely, when the off-in-frame opening flag 203ax is on, notification is not performed using the audio output device 226x and the lamp display device 227x, and only the output of the pulse signal to the hall computer 262x is performed. It may be configured.

  Next, a pachinko machine according to a ninth embodiment will be described with reference to FIGS. The pachinko machine according to the ninth embodiment changes a part of the electrical configuration of the pachinko machine 500 according to the fourth embodiment. The processing is changed, and further, the main processing executed by the sound lamp control device 113 of the pachinko machine 500 of the fourth embodiment is changed.

  According to the pachinko machine of the ninth embodiment, when power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power source DC1, if the inner frame 12 is opened, The frame opening detection circuit 290 detects the opening, and the main controller 110 transmits an inner frame opening command once to the sound lamp controller 113 within the main process. Similarly, according to the pachinko machine of the ninth embodiment, when power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power source DC1, the front frame 14 is opened. The front frame opening detection circuit 292 detects the opening, and the main control device 110 transmits a front frame opening command once to the audio lamp control device 113 within the main process.

  As described above, in the pachinko machine according to the ninth embodiment, when the inner frame 12 or the front frame 14 is opened, an inner frame opening command or a front frame opening command is sent from the main controller 110 to the sound lamp control device. It transmits to 113 only once. Therefore, when the inner frame 12 or the front frame 14 is released, the inner frame release command or the front frame release command is repeatedly transmitted from the main control device 110 to the sound lamp control device 113 during the opening period. Compared with the pachinko machine 500, in the pachinko machine of the ninth embodiment, the number of command transmissions of the main control device 110 can be reduced, and the processing load in the main process can be reduced.

  Further, when the inner frame 12 or the front frame 14 is released, the inner frame release command or the front frame release command is repeatedly transmitted to the sound lamp control device 113 every 4 milliseconds within the main process of the main control device 110. In contrast to the pachinko machine 500 of the embodiment, in the pachinko machine of the ninth embodiment, when the inner frame 12 or the front frame 14 is opened, an inner frame release command or a front frame release command is sent from the main controller 110 to the sound lamp. Since the data is transmitted only once to the control device 113, the repetition period (every 4 milliseconds) in the main process of the main control device 110 cannot be grasped. Thereby, it becomes impossible to grasp the update cycle of the first per-random number counter C1 used for the big hit lottery repeatedly performed in the main process of the main controller 110. Therefore, according to the pachinko machine of the ninth embodiment, it is possible to make it difficult to illegally acquire the update period of the first random number counter C1 or the like, for example, using a hanging board.

  Furthermore, according to the pachinko machine of the ninth embodiment, when the power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power supply DC1, the opened inner frame 12 is closed. Then, the inner frame opening detection circuit 290 detects the closing, and the main controller 110 transmits an inner frame closing command once to the sound lamp controller 113 within the main process. Similarly, according to the pachinko machine of the ninth embodiment, when the power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power supply DC1, the opened front frame 14 is closed. Then, the front frame opening detection circuit 292 detects the closing, and in accordance with the detection, the main control device 110 transmits a front frame closing command once to the sound lamp control device 113 within the main process.

  As described above, in the pachinko machine according to the ninth embodiment, when the opened inner frame 12 or the opened front frame 14 is closed, an inner frame closing command or a front frame closing command is issued to the main control device along with the closing. 110 is transmitted to the sound lamp control device 113 only once. Therefore, when the opened inner frame 12 or the opened front frame 14 is closed, the inner frame closing command or the front frame closing command is repeatedly transmitted from the main control device 110 to the sound lamp control device 113 during the closing period. Compared with the pachinko machine 500 according to the fourth embodiment, the pachinko machine according to the ninth embodiment can reduce the number of command transmissions of the main control device 110 and reduce the processing load in the main process.

  Further, when the inner frame 12 or the front frame 14 is closed, the inner frame closing command or the front frame closing command is repeatedly transmitted to the sound lamp control device 113 every 4 milliseconds within the main process of the main control device 110. In contrast to the pachinko machine 500 of the embodiment, in the pachinko machine of the ninth embodiment, when the inner frame 12 or the front frame 14 is closed, an inner frame close command or a front frame close command is sent from the main controller 110 to the sound lamp. Since the data is transmitted only once to the control device 113, the repetition period (every 4 milliseconds) in the main process of the main control device 110 cannot be grasped. Thereby, it becomes impossible to grasp the update cycle of the first per-random number counter C1 used for the big hit lottery repeatedly performed in the main process of the main controller 110. Therefore, according to the pachinko machine of the ninth embodiment, it is possible to make it difficult to illegally acquire the update period of the first random number counter C1 or the like, for example, using a hanging board.

  Note that the pachinko machine of the ninth embodiment is similar to the pachinko machine 500 of the fourth embodiment, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine is shut off, and 12 volts from the DC power supply DC1. When either the inner frame 12 or the front frame 14 is opened, the hall computer 262 is pulsed even when the DC voltage is not supplied, that is, when the control of the main controller 110 is stopped. Signals can be output separately. Therefore, it is possible to identify whether the inner frame 12 has been opened, the front frame 14 has been opened, or both have been opened by the pulse signal stored in the hall computer 262.

  First, the electrical configuration of the pachinko machine according to the ninth embodiment will be described with reference to FIG. FIG. 62 is a block diagram showing an electrical configuration of the pachinko machine according to the ninth embodiment. In the pachinko machine of the ninth embodiment, the following three changes will be described with respect to the description of the pachinko machine 500 of the fourth embodiment described above with reference to FIG. First, in the pachinko machine according to the ninth embodiment, a bus line BL2 for transmitting a strobe signal SG3 from the input / output port 205 of the main control device 110 to the input / output port 225 of the sound lamp control device 113 is added. Second, in the pachinko machine of the ninth embodiment, the inner frame opening command transmission counter 203c, the inner frame closing command transmission counter 203d, the front frame opening command transmission counter 203e, and the front frame closing command transmission are transmitted to the RAM 203 of the main controller 110. A counter 203f is added. Third, in the pachinko machine according to the ninth embodiment, a command reception memory 223c is added to the RAM 223 of the sound lamp control device 113. Except for these three changes, the electrical configuration of the pachinko machine according to the ninth embodiment and the electrical configuration of the pachinko machine 500 according to the fourth embodiment are the same. Therefore, in the block diagram showing the electrical configuration of the pachinko machine of the ninth embodiment shown in FIG. 62, the same parts as those in the block diagram of the pachinko machine 500 of the fourth embodiment described above with reference to FIG. Therefore, the description thereof is omitted, and only different portions will be described.

  Connected to the input / output port 205 of the main controller 110 is a bus line BL2 for transmitting a strobe signal SG3 to the input / output port 225 of the sound lamp controller 113. When an inner frame opening command, an inner frame closing command, a front frame opening command, a front frame closing command, or the like is started to be transmitted from the main controller 110 to the sound lamp controller 113 via the bus line BL1, a strobe signal is set accordingly. SG3 is output from the main controller 110 to the sound lamp controller 113 via the bus line BL2. When the sound lamp control device 113 receives the strobe signal SG3 transmitted from the main control device 110 via the bus line BL2, the sound lamp control device 113 receives the command transmitted from the main control device 110 via the bus line BL1. Start. The strobe signal SG3 is a pulse signal having a maximum value of 5 volts and a pulse width of 1 μsec.

  The RAM 203 of the MPU 201 is provided with an inner frame opening command transmission counter 203c, an inner frame closing command transmission counter 203d, a front frame opening command transmission counter 203e, and a front frame closing command transmission counter 203f.

  The inner frame release command transmission counter 203c is a counter that counts whether or not the inner frame 12 is released, and an inner frame release command is transmitted once from the main controller 110 to the sound lamp controller 113 as the inner frame 12 is released. is there. When the inner frame release command transmission counter 203c supplies power to the pachinko machine of the ninth embodiment and executes a main process (see FIG. 63) of the main controller 110 described later, first, the inner frame release command transmission counter 203c is opened. It is set to “0 (zero)” indicating that the command has not been transmitted yet. Then, while the power is supplied to the pachinko machine of the ninth embodiment and the DC voltage of 12 volts is supplied from the DC power source DC1, the inner frame 12 is opened, and the main controller 110 releases the inner frame opening command. Is transmitted once, the inner frame release command transmission counter 203c is set to “1” indicating that the inner frame release command has already been transmitted once. Note that the inner frame opening command transmission counter 203c is configured such that while the power supply is performed to the pachinko machine of the ninth embodiment and the DC voltage of 12 volts is supplied from the DC power supply DC1, the opened inner frame 12 When the main frame is closed and the inner frame closing command is transmitted once by the main controller 110, it is set to “0 (zero)” again.

  The inner frame closing command transmission counter 203d counts whether the opened inner frame 12 is closed and an inner frame closing command is transmitted once from the main control device 110 to the sound lamp control device 113 in accordance with the closing. Counter. When the inner frame closing command transmission counter 203d is supplied with power to the pachinko machine of the ninth embodiment and a main process (see FIG. 63) of the main controller 110 described later is executed, first, the inner frame closing command transmission counter 203d is closed. It is set to “1” indicating that the command has already been transmitted once. Then, while the power is supplied to the pachinko machine of the ninth embodiment and the DC voltage of 12 volts is supplied from the DC power source DC1, the inner frame 12 is opened, and the main controller 110 releases the inner frame opening command. Is transmitted once, contrary to the inner frame opening command transmission counter 203c, the inner frame closing command transmission counter 203d is set to “0 (zero)” indicating that the inner frame closing command has not been transmitted yet. The The inner frame closing command transmission counter 203d is configured such that when the power supply to the pachinko machine of the ninth embodiment is performed and a DC voltage of 12 volts is supplied from the DC power source DC1, the opened inner frame 12 is When it is closed and the inner frame closing command is transmitted once by the main controller 110, it is set to “1” again.

  Here, the reason why the inner frame closing command transmission counter 203d is first set to “1” in the main process of the main controller 110 will be described. Usually, in the pachinko machine, the inner frame 12 is in a closed state except during maintenance, for example. Therefore, for example, when the amusement hall is ready for opening, the power supply to the pachinko machine of the ninth embodiment is started, and the DC voltage of 12 volts is started to be supplied from the DC power supply DC1, usually, the inner frame 12 Is closed. When the inner frame 12 is in the closed state, the inner frame closing command has already been transmitted once by the main controller 110 when the inner frame 12 is closed. Therefore, the inner frame closing command transmission counter 203d is first set to “1” in the main process of the main controller 110.

  It should be noted that even when the inner frame 12 is opened when the power supply to the pachinko machine of the ninth embodiment is started and the DC voltage of 12 volts is started from the DC power source DC1, the inner frame 12 is opened (the opened inner frame 12 is opened). Is not closed and the inner frame closing command is not transmitted), the inner frame closing command transmission counter 203d is set to “1” in the main process. However, after that, when the opening of the inner frame 12 is detected by the inner frame opening detection circuit 290 and the inner frame opening command is transmitted once by the main controller 110, the inner frame closing command transmission counter 203d is normal. The value is set to “0 (zero)”. Therefore, when the supply of power to the pachinko machine of the ninth embodiment is started and the supply of a DC voltage of 12 volts from the DC power supply DC1 is started, no problem occurs even if the inner frame 12 is opened. The same applies to the case where the front frame 14 is opened when the supply of power to the pachinko machine of the ninth embodiment is started and the supply of a DC voltage of 12 volts from the DC power supply DC1 is started.

  The front frame opening command transmission counter 203e is a counter that counts whether or not the front frame opening command is transmitted once from the main control device 110 to the sound lamp control device 113 when the front frame 14 is opened. is there. Like the inner frame release command transmission counter 203c, the front frame release command transmission counter 203e performs power supply to the pachinko machine of the ninth embodiment and performs main processing (see FIG. 63) of the main controller 110 described later. When executed, first, “0 (zero)” indicating that the front frame opening command has not been transmitted is set. Then, the front frame opening command transmission counter 203e opens the front frame 14 while the 12-volt DC voltage is supplied from the DC power source DC1 while power is supplied to the pachinko machine of the ninth embodiment. When the front frame opening command is transmitted once by the main controller 110, the front frame opening command is set to “1” indicating that the front frame opening command has already been transmitted once. It should be noted that the front frame open command transmission counter 203e is provided with a power supply to the pachinko machine according to the ninth embodiment, and the front frame 14 opened while the DC voltage of 12 volts is supplied from the DC power supply DC1. When the main frame is closed and the front frame close command is transmitted once by the main control device 110, it is set to “0 (zero)” again.

  The front frame closing command transmission counter 203f counts whether or not the opened front frame 14 is closed and a front frame closing command is transmitted once from the main control device 110 to the sound lamp control device 113 in accordance with the closing. It is a counter for doing. Like the inner frame closing command transmission counter 203d, the front frame closing command transmission counter 203f supplies power to the pachinko machine according to the ninth embodiment and performs main processing (see FIG. 63) of the main controller 110 described later. When executed, the front frame closing command is first set to “1” indicating that it has already been transmitted once. Then, while the power is supplied to the pachinko machine according to the ninth embodiment and the DC voltage of 12 volts is supplied from the DC power supply DC1, the front frame 14 is opened, and the main controller 110 opens the front frame command. Is transmitted once, contrary to the front frame opening command transmission counter 203e, the front frame closing command transmission counter 203f is set to “0 (zero)” indicating that the front frame closing command has not been transmitted yet. The The front frame closing command transmission counter 203f is configured such that when the power is supplied to the pachinko machine of the ninth embodiment and a DC voltage of 12 volts is supplied from the DC power source DC1, When the main frame is closed and the front frame closing command is transmitted once by the main controller 110, it is set to “1” again.

  The reason why the front frame closing command transmission counter 203f is first set to “1” in the main process of the main controller 110 is as follows. First, for the same reason as that set to “1”.

  Each value of the inner frame opening command transmission counter 203c, the inner frame closing command transmission counter 203d, the front frame opening command transmission counter 203e, and the front frame closing command transmission counter 203f described above is either “0” or “1”. Therefore, the function equivalent to a flag for recording whether or not a predetermined condition is satisfied is exhibited.

  The command reception memory 223c provided in the RAM 223 of the sound lamp control device 113 is a memory for storing various commands transmitted from the main control device 110 via the bus line BL1. In the command reception memory 223c, in addition to the inner frame opening command, the inner frame closing command, the front frame opening command, and the front frame closing command, a variation pattern command necessary for the variation display of the third symbol by the third symbol display device 81, A stop symbol command, a stop command, an effect time addition command, and the like are stored. The MPU 221 of the sound lamp control device 113 decodes the command stored in the command reception memory 223c and performs control according to the decoded command.

  Next, with reference to the flowcharts of FIGS. 63 and 64, each control process executed by the MPU 201 provided in the main control device 110 of the pachinko machine according to the ninth embodiment will be described. In each control process executed by the main control device 110 (MPU 201) of the pachinko machine of the ninth embodiment, each control process executed by the main control device 110 (MPU 201) of the pachinko machine 500 of the fourth embodiment. Among them, the main process is changed. On the other hand, control processes other than the main process executed by the main control device 110 (MPU 201) of the pachinko machine of the ninth embodiment (start-up process, fluctuation process, fluctuation start process, timer interruption process, start winning process and NMI) (Interrupt process) is a control process (start-up process, variation process, variation start process, timer interrupt process, start winning process) executed by the main controller 110 (MPU 201) of the pachinko machine 500 of the fourth embodiment NMI interrupt processing). Therefore, in the pachinko machine of the ninth embodiment, the main process corresponding to the changed part (the main process shown in FIG. 63 and the door command transmission process shown in FIG. 64) will be described, and the other control processes will be described. Is omitted.

  First, with reference to FIG. 63, the main process performed by MPU201 provided in the main control apparatus 110 of the pachinko machine of 9th Embodiment is demonstrated. FIG. 63 is a flowchart showing a main process executed by the MPU 201 in the main controller 110. In this main process, the main process of the game is executed. As an overview, the processing of S221 is first executed, and thereafter, the processing of S201 to S206 is executed as a periodic processing with a period of 4 milliseconds, and the counter update processing of S209 and S210 and the door command transmission processing of S222 are performed in the remaining time. It is configured to be executed.

  In the main process executed by the main control device 110 (MPU 201) of the pachinko machine of the ninth embodiment shown in FIG. 63, the main process executed by the main control device 110 of the pachinko machine 500 of the fourth embodiment (FIG. 27), the following three changes are made. 1stly, in the main process of the pachinko machine of 9th Embodiment, the process of S221 is added to the head of the main process of the pachinko machine 500 of 4th Embodiment. 2ndly, in the main process of the pachinko machine of 9th Embodiment, the process of S215-S220 in the main process of the pachinko machine 500 of 4th Embodiment is deleted. Thirdly, in the main process of the pachinko machine of the ninth embodiment, a door command transmission process (a process of S222) is added after the process of S210. Except for these three changes, the main process of the pachinko machine of the ninth embodiment and the main process of the pachinko machine 500 of the fourth embodiment are the same process. Therefore, in the main process of the pachinko machine of the ninth embodiment shown in FIG. 63, the same parts as the main process of the pachinko machine 500 of the fourth embodiment described above with reference to FIG. Omitted, only different parts will be described.

  In the main process executed by the MPU 201 provided in the main control device 110 of the pachinko machine according to the ninth embodiment, first, the inner frame opening command transmission counter 203c is set to “0 (zero)”, and the inner frame closing command is set. The transmission counter 203d is set to “1”, the front frame opening command transmission counter 203e is set to “0 (zero)”, and the front frame closing command transmission counter 203f is set to “1” (S221). Thereby, the initial setting of the inner frame opening command transmission counter 203c, the inner frame closing command transmission counter 203d, the front frame opening command transmission counter 203e, and the front frame closing command transmission counter 203f is completed (S221). Thereafter, the process proceeds to S201.

  Next, after the execution of the processing of S201 to S206, if the occurrence information of the power interruption is not stored in the RAM 203 (S207: No), whether or not the next main processing execution timing has been reached, that is, the previous main processing. It is determined whether or not a predetermined time (4 ms in the present embodiment) has elapsed since the start of S (S208), and if the predetermined time has not yet elapsed since the start of the previous main process (S208: No), the predetermined Update of the first initial value random number counter CINI1, the second initial value random number counter CINI2, and the variation type counters CS1, CS2, CS3 within the remaining time until the execution timing of the next main process until the time is reached Are repeatedly executed (S209, S210), and the door command transmission process is repeatedly executed (S222).

  In this door command transmission process (S222), any one of the inner frame opening command, the inner frame closing command, the front frame opening command, or the front frame closing command is sent to the inner frame 12 or the front frame 14 or the inner frame 12 is opened. Or the process which transmits to the audio | voice lamp control apparatus 113 only once with the closure of the front frame 14 is performed (S222). When the door command transmission process (S222) is completed, the process proceeds to S207. When it is determined “No” again in S207, the process of S208 is executed again. In the process of S208, if it is determined that the predetermined time has elapsed since the start of the previous main process as a result of the processes of S209, S210, and S222 being repeatedly executed, the process proceeds to S201 (S208: Yes). ).

  Here, the door command transmission process (S222) is executed after the process of S210, but the execution position of the door command transmission process (S222) may be arranged between immediately after the process of S201 and immediately after S206. . In this way, the door command transmission process (S222) can be executed periodically every 4 milliseconds.

  In addition, each process of S211 to S214 that is executed when the power failure occurrence information is stored in the RAM 203 (when it is determined “Yes” in the process of S207) is the pachinko machine 500 according to the fourth embodiment. Since this is the same process as the processes of S211 to S214 in the main process executed by the main controller 110, description thereof will be omitted.

  Next, with reference to FIG. 64, the door command transmission process (process of S222) performed by MPU201 provided in the main control apparatus 110 of the pachinko machine of 9th Embodiment is demonstrated. FIG. 64 is a flowchart showing door command transmission processing executed by the MPU 201 in the main controller 110. In this door command transmission process, it is first determined whether or not the inner frame release flag 203a is on (S230). Note that the on / off switching of the inner frame release flag 203a is executed by a timer interrupt process (not shown) of the pachinko machine according to the ninth embodiment. In the timer interrupt process of the pachinko machine of the ninth embodiment, exactly the same process as the timer interrupt process (see FIG. 28) of the pachinko machine 500 of the fourth embodiment is executed. Therefore, in the timer interrupt process of the pachinko machine of the ninth embodiment, as described in the timer interrupt process of the pachinko machine 500 shown in FIG. 28, when the power of the pachinko machine of the ninth embodiment is turned on, When the inner frame 12 is opened and the output of the inner frame input / output port output circuit 290b becomes 5 volts (see S507 in FIG. 28: Yes), the inner frame release flag 203a is set to ON (see S508 in FIG. 28). ). On the other hand, when the power of the pachinko machine of the ninth embodiment is turned on, the inner frame 12 is closed and the output of the inner frame input / output port output circuit 290b becomes zero volts (see S507 in FIG. 28: No). The inner frame release flag 203a is set to OFF (see S509 in FIG. 28).

  Returning to the description of FIG. If the inner frame release flag 203a is on (S230: Yes), the inner frame 12 is released while the power of the pachinko machine of the ninth embodiment is turned on, so the inner frame release command and the strobe signal SG3. Is transferred to the sound lamp control device 113 and the process proceeds to S231 and subsequent steps. In the process of S231, it is determined whether or not the value of the inner frame release command transmission counter 203c is “0 (zero)”. If the value of the inner frame release command transmission counter 203c is “0 (zero)” (S231: Yes), the inner frame release command has not yet been transmitted to the audio lamp controller 113 after the inner frame 12 is released. In order to transmit this, transmission of an inner frame release command is started (S232). Thereafter, processing is waited for 1 μsec (S233), and transmission of the strobe signal SG3 is started (S234). When the strobe signal SG3 is received by the sound lamp control device 113, the sound lamp control device 113 starts receiving an inner frame opening command. Note that after the transmission of the inner frame release command is started, the process waits for 1 μs in the process of S233, and then the transmission of the strobe signal SG3 is started from the input / output port 205 of the main controller 110. This is to stabilize the output inner frame release command.

  After the process of S234, it is determined whether 1 microsecond has elapsed from the start of transmission of the strobe signal SG3 (from the start of the process of S234) (S235). If 1 microsecond has elapsed since the start of transmission of the strobe signal SG3 (S235: Yes), the transmission of the strobe signal SG3 is terminated (S236). Through the processing of S233 to S236, transmission of the strobe signal SG3 is started 1 μsec after the start of transmission of the inner frame release command, and the strobe signal SG3 that has started transmission is transmitted to the audio lamp control device 113 for 1 μsec. (The pulse width of the strobe signal SG3 is 1 μsec).

  On the other hand, if 1 μs has not elapsed since the start of transmission of the strobe signal SG3 (S235: No), the transmission of the strobe signal SG3 is not terminated (the transmission of the strobe signal SG3 is continued), and the process proceeds to S251. . Whether or not 1 μs has elapsed from the start of transmission of the strobe signal SG3 is determined by a counter (not shown) that counts the elapsed time since the start of transmission of the strobe signal SG3. Judgment based on. The same applies to each processing of S245, S256, and S266 described later.

  When the process of S236 is executed, it is determined whether or not 1 msec has elapsed from the start of transmission of the inner frame release command (S237). If 1 msec has elapsed since the start of the inner frame release command transmission (S237: Yes), the transmission of the inner frame release command is terminated (S238). By the processes of S232, S237, and S238, the inner frame release command is transmitted to the sound lamp control device 113 for 1 msec. On the other hand, if 1 msec has not elapsed since the start of transmission of the inner frame release command (S237: No), the transmission of the inner frame release command is not ended (the transmission of the inner frame release command is continued), and the process of S251 Migrate to Whether or not 1 msec has elapsed since the start of transmission of the inner frame release command is determined by a counter (provided in MPU 201, not shown) that counts the elapsed time since the start of transmission of the inner frame release command. Judgment based on the timing of

  When the process of S238 is executed, the transmission of the inner frame release command to the sound lamp control device 113 is completed, so the inner frame release command transmission counter 203c is incremented by “1” (the inner frame release command transmission counter). 203c is set from "0 (zero)" to "1", S239). Thereafter, the inner frame closing command transmission counter 203d is set to “0 (zero)” (S240). The inner frame opening command has already been transmitted to the sound lamp control device 113 in the processing of S232 to S238, but the inner frame closing command has not yet been transmitted to the sound lamp control device 113. The closing command transmission counter 203d is set to “0 (zero)”.

  If the value of the inner frame release command transmission counter 203c is “1” in the processing of S231 (S231: No), an inner frame release command indicating that the inner frame 12 has been released is already sent to the audio lamp control device 113. Since the transmission is performed once, the processing of S232 to S240 is skipped, and the process proceeds to S251.

  Here, 1 μsec elapses from the start of transmission of the strobe signal SG3 (determined as “Yes” in the process of S235), and 1 msec elapses from the start of transmission of the inner frame release command (in the process of S237). In other words, until the inner frame release command transmission counter 203c becomes “1”, the determination in S231 continues to be made “Yes” (until “Yes” is determined). At this time, the processing of S232 to S234, which is executed after it is determined as “Yes” in the processing of S231, is configured to be skipped after being executed once for the first time. That is, until the inner frame release command transmission counter 203c becomes “1”, it is determined as “Yes” in the processing of S231, but in this case, if the processing of S232 to S234 has already started, S232 to S234. The processing is configured to skip this processing and shift to the processing of S235. Therefore, the processing of S232 to S234 is not repeatedly executed more than once until the inner frame release command transmission counter 203c becomes “1”.

  Next, in the process of S230, when it is determined that the inner frame release flag 203a is off (S230: No), the power of the pachinko machine of the ninth embodiment is turned on and the inner frame 12 is Since it is closed, the process proceeds to S241 and subsequent processes, which are processes for transmitting the inner frame closing command and the strobe signal SG3 to the sound lamp control device 113. In the process of S241, it is determined whether or not the value of the inner frame closing command transmission counter 203d is “0 (zero)”. If the value of the inner frame closing command transmission counter 203d is “0 (zero)” (S241: Yes), the inner frame closing command has not yet been transmitted to the sound lamp control device 113 after the inner frame 12 is closed. In order to transmit this, transmission of an inner frame closing command is started (S242). Thereafter, processing is waited for 1 μsec (S243), and transmission of the strobe signal SG3 is started (S244). When the strobe signal SG3 is received by the sound lamp control device 113, the sound lamp control device 113 starts receiving an inner frame closing command. The reason for starting the transmission of the inner frame closing command, waiting for the processing for 1 μs in the processing of S243 and then starting the transmission of the strobe signal SG3 is the same as in the case of the inner frame opening command. By (command stabilization).

  After the processing of S244, it is determined whether 1 μsec has elapsed from the start of transmission of the strobe signal SG3 (from the start of processing of S244) (S245). If 1 μs has elapsed since the start of transmission of the strobe signal SG3 (S245: Yes), the transmission of the strobe signal SG3 is terminated (S246). Through the processing of S243 to S246, the transmission of the strobe signal SG3 is started 1 μsec after the start of the transmission of the inner frame closing command, and the strobe signal SG3 that has started transmission is transmitted to the audio lamp control device 113 for 1 μsec. (The pulse width of the strobe signal SG3 is 1 μsec).

  On the other hand, if 1 μs has not elapsed since the start of transmission of the strobe signal SG3 (S245: No), the transmission of the strobe signal SG3 is not terminated (the transmission of the strobe signal SG3 is continued), and the process proceeds to S251. .

  When the process of S246 is executed, it is determined whether 1 msec has elapsed from the start of transmission of the inner frame closing command (S247). If 1 msec has elapsed from the start of transmission of the inner frame closing command (S247: Yes), the transmission of the inner frame closing command is terminated (S248). By the processes of S242, S247, and S248, the inner frame closing command is transmitted to the sound lamp control device 113 for 1 msec. On the other hand, if 1 msec has not elapsed since the start of transmission of the inner frame closing command (S247: No), the processing of S251 is performed without terminating the transmission of the inner frame closing command (while continuing to transmit the inner frame closing command). Migrate to Whether or not 1 msec has elapsed from the start of transmission of the inner frame closing command is determined by a counter (provided in MPU 201, not shown) that counts the elapsed time from the start of transmission of the inner frame closing command. Judgment based on the timing of

  When the process of S248 is executed, the transmission of the inner frame closing command to the sound lamp control device 113 is completed, so the inner frame closing command transmission counter 203d is incremented by “1” (the inner frame closing command transmission counter). 203d is set from “0 (zero)” to “1”, S249). Thereafter, the inner frame release command transmission counter 203c is set to “0 (zero)” (S250). The inner frame closing command has already been transmitted to the audio lamp control device 113 in the processing of S242 to S248, but the inner frame opening command has not been transmitted to the audio lamp control device 113 yet. The release command transmission counter 203c is set to “0 (zero)”.

  If the value of the inner frame closing command transmission counter 203d is “1” in the processing of S241 (S241: No), an inner frame closing command indicating that the opened inner frame 12 is closed is sent to the voice lamp control device. Since the data has already been transmitted once to 113, the processing of S242 to S250 is skipped and the processing proceeds to S251.

  Here, 1 μsec elapses from the start of transmission of the strobe signal SG3 (determined as “Yes” in the processing of S245) and until 1 msec elapses from the start of transmission of the inner frame closing command (in the processing of S247). In other words, until the inner frame closing command transmission counter 203d becomes “1”, it is determined as “Yes” in the process of S241. At this time, the processing of S242 to S244 executed after the determination of “Yes” in the processing of S241 is skipped after being executed once for the same time as the processing of S232 to S234 described above. Processing is configured. Therefore, the processing of S242 to S244 is not repeatedly executed more than once until the inner frame closing command transmission counter 203d becomes “1”.

  Next, it is determined whether or not the front frame opening flag 203b is on (S251). The front frame opening flag 203b is switched on and off by a timer interrupt process (not shown) of the pachinko machine according to the ninth embodiment. As described above, the timer interrupt process of the pachinko machine of the ninth embodiment is exactly the same as the timer interrupt process (see FIG. 28) of the pachinko machine 500 of the fourth embodiment. Therefore, in the timer interrupt process of the pachinko machine of the ninth embodiment, as described in the timer interrupt process of the pachinko machine 500 shown in FIG. 28, when the power of the pachinko machine of the ninth embodiment is turned on, When the front frame 14 is opened and the output of the front frame input / output port output circuit 292b becomes 5 volts (see S511: Yes in FIG. 28), the front frame open flag 203b is set to ON (see S512 in FIG. 28). ). On the other hand, when the power of the pachinko machine of the ninth embodiment is on, the front frame 14 is closed and the output of the front frame input / output port output circuit 292b becomes zero volts (see S511: No in FIG. 28). The front frame release flag 203b is set to OFF (see S513 in FIG. 28).

  Returning to the description of FIG. If the front frame release flag 203b is on (S251: Yes), the front frame 14 is opened while the power of the pachinko machine of the ninth embodiment is turned on, so the front frame release command and the strobe signal SG3. Is transferred to the audio lamp control device 113, and the process proceeds to S252 and subsequent steps. In the process of S252, it is determined whether or not the value of the front frame opening command transmission counter 203e is “0 (zero)”. If the value of the front frame opening command transmission counter 203e is “0 (zero)” (S252: Yes), the front frame opening command has not yet been transmitted to the audio lamp control device 113 after the front frame 14 is opened. In order to transmit this, transmission of a front frame opening command is started (S253). Thereafter, processing is waited for 1 μsec (S254), and transmission of the strobe signal SG3 is started (S255). When the strobe signal SG3 is received by the sound lamp control device 113, the sound lamp control device 113 starts receiving a front frame opening command. The reason for starting the transmission of the front frame opening command, waiting for the processing for 1 μs in the processing of S254, and starting the transmission of the strobe signal SG3 thereafter is the same as in the case of the inner frame opening command. By (command stabilization).

  After the process of S255, it is determined whether 1 μsec has elapsed from the start of transmission of the strobe signal SG3 (from the start of the process of S255) (S256). If 1 μsec has elapsed since the start of transmission of the strobe signal SG3 (S256: Yes), the transmission of the strobe signal SG3 is terminated (S257). By the processing of S254 to S257, transmission of the strobe signal SG3 is started 1 μsec after the start of transmission of the front frame opening command, and the strobe signal SG3 that has started transmission is transmitted to the audio lamp control device 113 for 1 μsec. The

  On the other hand, if 1 μs has not elapsed since the start of transmission of the strobe signal SG3 (S256: No), the transmission of the strobe signal SG3 is not ended (while the transmission of the strobe signal SG3 is continued), and the door command transmission process (S222). ) Ends.

  When the process of S257 is executed, it is determined whether or not 1 msec has elapsed from the start of transmission of the front frame opening command (S258). If 1 msec has elapsed from the start of transmission of the front frame opening command (S258: Yes), transmission of the front frame opening command is terminated (S259). By the processes of S253, S258, and S259, the front frame opening command is transmitted to the sound lamp control device 113 for 1 msec. On the other hand, if 1 msec has not elapsed since the start of transmission of the front frame opening command (S258: No), the transmission of the door command is terminated without terminating the transmission of the front frame opening command (while continuing to transmit the front frame opening command). The process (S222) ends. Note that a counter (provided in MPU 201, not shown) that counts the elapsed time from the start of transmission of the front frame opening command is whether 1 msec has elapsed from the start of transmission of the front frame opening command. Judgment based on the timing of

  When the process of S259 is executed, the transmission of the front frame opening command to the audio lamp control device 113 is completed, so the front frame opening command transmission counter 203e is incremented by “1” (front frame opening command transmission counter). 203e is set from "0 (zero)" to "1", S260). Thereafter, the front frame closing command transmission counter 203f is set to “0 (zero)” (S261). The front frame opening command has already been transmitted to the sound lamp control device 113 in the processes of S253 to S259, but the front frame closing command has not yet been transmitted to the sound lamp control device 113. Therefore, in the process of S261, the front frame The closing command transmission counter 203f is set to “0 (zero)”. In addition, after the process of S261 is complete | finished, this door command transmission process (S222) is complete | finished.

  If the value of the front frame release command transmission counter 203e is “1” in the processing of S252 (S252: No), a front frame release command indicating that the front frame 14 has been released is already sent to the sound lamp control device 113. Since it has transmitted once, the process of S253-S261 is skipped and this door command transmission process (S222) is complete | finished.

  Here, 1 μsec elapses from the start of transmission of the strobe signal SG3 (determined as “Yes” in the process of S256) and until 1 msec elapses from the start of transmission of the front frame opening command (in the process of S258). In other words, until “Yes” is determined, in other words, “Yes” is continuously determined in the processing of S252 until the front frame opening command transmission counter 203e becomes “1”. At this time, the processing of S253 to S255, which is executed after it is determined as “Yes” in the processing of S252, is skipped after being executed once for the same time as the processing of S232 to S234 described above. Processing is configured. Therefore, the processing of S253 to S255 is not repeatedly executed more than once until the front frame opening command transmission counter 203e becomes “1”.

  Next, if it is determined in the process of S251 that the front frame release flag 203b is off (S251: No), the power of the pachinko machine of the ninth embodiment is turned on and the front frame 14 is Since it is closed, the process proceeds to S262 and subsequent processes, which are processes for transmitting the front frame closing command and the strobe signal SG3 to the sound lamp control device 113. In the process of S262, it is determined whether or not the value of the front frame closing command transmission counter 203f is “0 (zero)”. If the value of the front frame closing command transmission counter 203f is “0 (zero)” (S262: Yes), the front frame closing command has not yet been transmitted to the sound lamp control device 113 after the front frame 14 is closed. In order to transmit this, transmission of a front frame closing command is started (S263). Thereafter, processing is waited for 1 μsec (S264), and transmission of the strobe signal SG3 is started (S265). When the strobe signal SG3 is received by the sound lamp control device 113, the sound lamp control device 113 starts receiving a front frame closing command. Note that, after the transmission of the front frame closing command is started, the processing waits for 1 μsec in the processing of S264, and the transmission of the strobe signal SG3 is started after the standby, as in the case of the inner frame opening command. For reasons (command stabilization).

  After the process of S265, it is determined whether or not 1 μs has elapsed from the start of transmission of the strobe signal SG3 (from the start of the process of S265) (S266). If 1 μsec has elapsed since the start of transmission of the strobe signal SG3 (S266: Yes), the transmission of the strobe signal SG3 is terminated (S267). Through the processing of S264 to S267, transmission of the strobe signal SG3 is started 1 μsec after the start of transmission of the front frame closing command, and the strobe signal SG3 that has started transmission is transmitted to the audio lamp control device 113 for 1 μsec. The

  On the other hand, if 1 μs has not elapsed since the start of transmission of the strobe signal SG3 (S266: No), the transmission of the strobe signal SG3 is not ended (while the transmission of the strobe signal SG3 is continued), and the door command transmission process (S222). ) Ends.

  When the process of S267 is executed, it is determined whether 1 msec has elapsed from the start of transmission of the front frame closing command (S268). If 1 msec has elapsed since the start of transmission of the front frame closing command (S268: Yes), transmission of the front frame closing command is terminated (S269). Through the processes of S263, S268, and S269, the front frame closing command is transmitted to the sound lamp control device 113 for 1 msec. On the other hand, if 1 msec has not elapsed since the start of transmission of the front frame closing command (S268: No), the transmission of the door command is performed without terminating the transmission of the front frame closing command (while continuing to transmit the front frame closing command). The process (S222) ends. Whether or not 1 msec has elapsed from the start of transmission of the front frame closing command is determined by a counter (provided in the MPU 201, not shown) that counts the elapsed time since the transmission of the front frame closing command has started. Judgment based on the timing of

  When the process of S269 is executed, the transmission of the front frame closing command to the sound lamp control device 113 is completed, so the front frame closing command transmission counter 203f is incremented by “1” (front frame closing command transmission counter). 203f is set from "0 (zero)" to "1" (S270). Thereafter, the front frame open command transmission counter 203e is set to “0 (zero)” (S271). The front frame closing command has already been transmitted to the sound lamp control device 113 in the processes of S263 to S269, but the front frame opening command has not yet been transmitted to the sound lamp control device 113. Therefore, in the process of S271, the front frame is closed. The release command transmission counter 203e is set to “0 (zero)”. After the process of S271 ends, the door command transmission process (S222) ends.

  If the value of the front frame closing command transmission counter 203f is “1” in the processing of S262 (S262: No), a front frame closing command indicating that the opened front frame 14 is closed is sent to the voice lamp control device. Since it has already transmitted once to 113, the process of S263-S271 is skipped and this door command transmission process (S222) is complete | finished.

  Here, 1 μsec elapses from the start of transmission of the strobe signal SG3 (determined as “Yes” in the process of S266), and 1 msec elapses from the start of transmission of the front frame close command (in the process of S268). In other words, until the front frame closing command transmission counter 203f becomes “1”, the determination in S262 continues to be “Yes” (until “Yes” is determined). At this time, the processing of S263 to S265, which is executed after it is determined as “Yes” in the processing of S262, is skipped after being executed once for the same time as the processing of S232 to S234 described above. Processing is configured. Therefore, the processing of S263 to S265 is not repeatedly executed more than once until the front frame closing command transmission counter 203f becomes “1”.

  Thus, in the door command transmission process (S222), the inner frame 12 is opened while the power of the pachinko machine of the ninth embodiment is turned on, and the inner frame release command indicating the opening has not been transmitted yet. In this case, the main controller 110 transmits the inner frame opening command only once to the sound lamp controller 113 for 1 msec. Further, when 1 μsec has elapsed from the start of transmission of the inner frame release command, main controller 110 transmits strobe signal SG3 to audio lamp controller 113 only once for 1 μsec.

  Similar to the inner frame opening command, the inner frame closing command, the front frame opening command, and the front frame closing command are transmitted only once from the main controller 110 to the sound lamp controller 113 only when the commands have not been transmitted yet. Sent. Therefore, the pachinko machine of the ninth embodiment is compared with the pachinko machine 500 of the fourth embodiment that repeatedly transmits the inner frame opening command, the inner frame closing command, the front frame opening command, and the front frame closing command to the audio lamp control device 113. The machine can reduce the processing load in the main process by reducing the number of command transmissions of the main controller 110.

  Next, referring to the flowcharts of FIGS. 65 to 67, main processing, external interrupt processing, and door opening notification processing (indicated by the MPU 221 provided in the sound lamp control device 113 of the pachinko machine according to the ninth embodiment ( The process in the main process will be described. For convenience of explanation, first, the external interrupt process of FIG. 66 will be described, then the main process of FIG. 65 will be described, and finally the door opening notification process of FIG. 67 will be described.

  FIG. 66 is a flowchart showing an external interrupt process executed by the MPU 221 provided in the sound lamp control device 113 of the pachinko machine according to the ninth embodiment, and receives the strobe signal SG3 output from the main control device 110. (If strobe signal SG3 is 5 volts). When the external interrupt process is executed, since various commands are started to be transmitted from the main controller 110 to the sound lamp controller 113, the various commands are received and the received various commands are stored in the command reception memory 223c. (S820). Thereafter, the external interrupt process is terminated.

  Next, with reference to FIG. 65, the main process performed by MPU221 provided in the audio | voice lamp control apparatus 113 of the pachinko machine of 9th Embodiment is demonstrated. FIG. 65 is a flowchart showing main processing executed by the MPU 221 in the sound lamp control device 113.

  The main processing executed by the MPU 221 provided in the sound lamp control device 113 of the pachinko machine according to the ninth embodiment shown in FIG. 65 is provided in the sound lamp control device 113 of the pachinko machine 500 according to the fourth embodiment. The main processing (see FIG. 30) executed by the MPU 221 is performed by making the following two changes.

  First, in the main process executed by the sound lamp control device 113 of the pachinko machine of the ninth embodiment, the door opening notification process (S813) executed by the sound lamp control device 113 of the pachinko machine 500 of the fourth embodiment. The execution position of FIG. 30 is changed after the processing of S809, and the processing content of the door opening notification processing is changed (this is executed by the sound lamp control device 113 of the pachinko machine of the ninth embodiment). The door opening notification process is “S818”). Secondly, in the main process executed by the sound lamp control device 113 of the pachinko machine of the ninth embodiment, the main process from the main control device 110 executed by the sound lamp control device 113 of the pachinko machine 500 of the fourth embodiment. Command reception (S811, see FIG. 30) is deleted.

  Except for these two changes, the main processing (see FIG. 65) executed by the audio lamp control device 113 of the pachinko machine according to the ninth embodiment and the audio lamp control device 113 of the pachinko machine 500 according to the fourth embodiment. The main process to be executed (see FIG. 30) is the same process. Therefore, in the main process executed by the audio lamp control device 113 of the pachinko machine of the ninth embodiment shown in FIG. 65, the same part as the main process of the audio lamp control device 113 of the pachinko machine 500 described above with reference to FIG. The same number is attached | subjected and the description is abbreviate | omitted and only a different part is demonstrated. The start-up process (not shown) executed by the MPU 221 provided in the sound lamp control device 113 of the pachinko machine according to the ninth embodiment is performed in the sound lamp control device 113 of the pachinko machine 500 according to the fourth embodiment. This is the same processing as the startup processing (see FIG. 29) executed by the MPU 221 provided in FIG.

  In the main process executed by the sound lamp control device 113 of the pachinko machine of the ninth embodiment, first, it is determined whether or not 1 msec or more has elapsed since the main process was started (S801), and the main process is started. If it is determined that 1 msec or more has passed since the start (S801: Yes), the processing of S802 to S809 is executed, and then either the inner frame 12 or the front frame 14 is opened, or the inner frame is opened. When both the frame 12 and the front frame 14 are opened, a door opening notification process (S818) for performing notification using the audio output device 226 and the lamp display device 227 is executed. After the door opening notification process (S818) is executed, the process proceeds to S810.

  On the other hand, if it is determined in step S801 that the main process has not started for more than 1 msec (S801: No), the processes in S802 to S809 and S818 are skipped, and the process in S810 is performed. Migrate to

  After the process of S810, if the occurrence information of the power interruption is not stored in the RAM 223 in the process of S812 (S812: No), it is determined whether or not the RAM 223 is destroyed based on the keyword stored in the RAM 223 (S814). If the RAM 223 is not destroyed (S814: No), the process returns to the process of S801, and the main process is repeatedly executed.

  In the process of S812, each process of S815 to S817 that is executed when the information on the occurrence of power interruption is stored in the RAM 223 (when it is determined “Yes” in the process of S812) is the fourth embodiment. Since it is the same process as each process of S815-S817 in the main process performed with the audio | voice lamp control apparatus 113 of the pachinko machine 500 of a form, description is abbreviate | omitted.

  Finally, with reference to FIG. 67, the door opening notification process (S818) will be described. FIG. 67 is a flowchart showing a door opening notification process executed by the MPU 221 provided in the audio lamp control device 113. This door opening notification process determines whether or not four commands of an inner frame opening command, a front frame opening command, an inner frame closing command, or a front frame closing command are received by the sound lamp control device 113, and according to the determination. This is a process for performing notification.

  In the door opening notification process (S818), it is first determined whether or not the inner frame opening command reception flag 223a is ON indicating that the inner frame opening command has been received (S950). If the inner frame release command reception flag 223a is off (S950: No), the voice lamp control device 113 has not received the inner frame release command from the main control device 110 until this time, so the inner frame 12 Is determined to be closed. Therefore, in order to determine whether the inner frame 12 is still closed (to determine whether the inner frame 12 is not opened after this time), the command stored in the command reception memory 223c is It is determined whether the command is an inner frame release command (S951).

  If it is determined that the command stored in the command reception memory 223c is an inner frame release command (S951: Yes), the inner frame 12 is displayed while the pachinko machine according to the ninth embodiment is turned on. Since it is released and the inner frame release command is transmitted from the main controller 110, the inner frame release command reception flag 223a is turned on (S952), and the inner frame release notification process is started (S953). In the inner frame release notification process, the voice output device 226 is used to notify, for example, an electronic sound that “the inner frame is open” or the inner frame 12 is opened using the lamp display device 227. For example, blinking is performed four times per second. Thereby, it is possible to notify an unspecified number of persons (players, shop assistants, etc.) that the inner frame 12 has been opened. In the process of S952, although not shown, after the inner frame release command reception flag 223a is turned on, the inner frame release command is transmitted once to the display control device 114. When this inner frame opening command is received by the display control device 114, a display indicating that the inner frame 12 has been opened is executed by the third symbol display device 81.

  After the inner frame release notification process is started (S953), the inner frame release command stored in the command reception memory 223c is cleared (S954), and then the process proceeds to S956.

  If it is determined in the process of S950 that the inner frame release command reception flag 223a is on (S950: Yes), the voice lamp control device 113 has already received the inner frame release command, Since the frame release notification process (S953) is being executed, the executed inner frame release notification process is continued (S955).

  If it is determined in S951 that the command stored in the command reception memory 223c is not an inner frame release command (S951: No), the inner frame 12 has not been released (inner frame). 12 is closed), the process of S952 to S954 is skipped, and the process proceeds to S956.

  Next, in the process of S956, it is determined whether or not the front frame release command reception flag 223b is ON indicating that the front frame release command has been received (S956). If the front frame release command reception flag 223b is off (S956: No), the voice lamp control device 113 has not received the front frame release command from the main control device 110 until this time, so the front frame 14 Is determined to be closed. Therefore, in order to determine whether the front frame 14 is still closed (to determine whether the front frame 14 is not opened after this time), the command stored in the command reception memory 223c is It is determined whether it is a front frame release command (S957).

  If it is determined that the command stored in the command reception memory 223c is the front frame opening command (S957: Yes), the front frame 14 is turned on while the power of the pachinko machine of the ninth embodiment is turned on. Since the front frame release command is transmitted from the main controller 110, the front frame release command reception flag 223b is turned on (S958), and the front frame release notification process is started (S959). In this front frame opening notification process, the voice output device 226 is used to notify, for example, an electronic sound that “the front frame is open” or the front frame 14 is opened using the lamp display device 227. For example, blinking is performed once per second. Thereby, it is possible to notify an unspecified number of people that the front frame 14 has been opened. In the process of S958, although not shown, the front frame opening command reception flag 223b is turned on, and then the front frame opening command is transmitted once to the display control device 114. When the front frame opening command is received by the display control device 114, a display indicating that the front frame 14 has been opened is executed by the third symbol display device 81.

  After starting the front frame release notification process (S959), the front frame release command stored in the command reception memory 223c is cleared (S960), and then the process proceeds to S962.

  If it is determined in step S956 that the front frame opening command reception flag 223b is on (S956: Yes), the voice lamp control device 113 has already received the front frame opening command, Since the frame release notification process (S959) is being executed, the front frame release notification process being executed is continued (S961).

  If it is determined in step S957 that the command stored in the command reception memory 223c is not a front frame release command (S957: No), the front frame 14 is not opened (front frame). 14 is closed), the process of S958 to S960 is skipped and the process proceeds to S962.

  Next, in the process of S962, it is determined whether or not the inner frame release command reception flag 223a is ON indicating that the inner frame release command has been received (S962). If the inner frame release command reception flag 223a is on (S962: Yes), the audio lamp control device 113 has received the inner frame release command from the main control device 110 until this time, but the main control device. The inner frame closing command from 110 has not been received. That is, until this time, it is determined that the inner frame 12 is open. Therefore, in order to determine whether or not the inner frame 12 is still open (to determine whether the inner frame 12 is not closed after this time), the command stored in the command reception memory 223c is It is determined whether or not it is an inner frame closing command (S963).

  If it is determined that the command stored in the command reception memory 223c is an inner frame closing command (S963: Yes), the opened inner frame 12 is closed, and the inner frame closing command is sent from the main controller 110. Therefore, the inner frame release command reception flag 223a is turned off (S964), and the inner frame release notification process is terminated (S965). In the process of S964, although not shown, the inner frame closing command reception flag 223a is turned off, and then the inner frame closing command is transmitted once to the display control device 114. When this inner frame closing command is received by the display control device 114, the open display of the inner frame 12 executed by the third symbol display device 81 is terminated.

  After the process of S965, the inner frame closing command stored in the command reception memory 223c is cleared, and the process proceeds to S967 (S966).

  If it is determined in S962 that the inner frame release command reception flag 223a is off (S962: No), the inner frame release command has not been received, and the inner frame 12 has not been released. Therefore (because the inner frame 12 is closed), the process of S963 to S966 is skipped, and the process proceeds to S967.

  If it is determined in S963 that the command stored in the command reception memory 223c is not an inner frame closing command (S963: No), the opened inner frame 12 is not closed. (Because the inner frame 12 remains open), the processing of S964 to S966 is skipped, and the processing proceeds to S967.

  Next, in the process of S967, it is determined whether or not the front frame release command reception flag 223b is ON indicating that the front frame release command has been received (S967). If the front frame release command reception flag 223b is on (S967: Yes), the audio lamp control device 113 has received the front frame release command from the main control device 110 until this time, but the main control device. The front frame closing command from 110 has not been received. That is, until this time, it is determined that the front frame 14 is open. Therefore, in order to determine whether or not the front frame 14 is still open (to determine whether the front frame 14 is not closed after this time), the command stored in the command reception memory 223c is It is determined whether it is a front frame closing command (S968).

  When it is determined that the command stored in the command reception memory 223c is a front frame closing command (S968: Yes), the opened front frame 14 is closed, and the front frame closing command is sent from the main controller 110. Has been transmitted, the front frame release command reception flag 223a is turned off (S969), and the front frame release notification process is terminated (S970). In the process of S969, although not shown, the front frame closing command reception flag 223a is turned off, and then the front frame closing command is transmitted once to the display control device 114. When this front frame closing command is received by the display control device 114, the open display of the front frame 14 executed by the third symbol display device 81 is terminated.

  After the process of S970, the front frame closing command stored in the command reception memory 223c is cleared (S971), and the door opening notification process is terminated.

  If it is determined in step S967 that the front frame release command reception flag 223b is off (S967: No), the front frame release command has not been received and the front frame 14 has not been opened. Therefore (because the front frame 14 is closed), the processing of S968 to S971 is skipped, and this door opening notification processing is terminated.

  If it is determined in S968 that the command stored in the command reception memory 223c is not a front frame closing command (S968: No), the opened front frame 14 is not closed. (Because the front frame 14 remains open), the processing of S969 to S971 is skipped, and this door opening notification processing is terminated.

  As described above, in the door opening notification process (S818), when the sound lamp control device 113 receives the inner frame opening command in the external interrupt processing (see FIG. 66), the inner frame opening command reception flag 223a is set. Turn on to indicate that the inner frame release command has been received (S952), and start the inner frame release notification process (S953). Since the inner frame opening notification process (S953) is continuously performed until the opened inner frame 12 is closed, an unspecified number of persons (players, salespeople, etc.) indicate that the inner frame 12 is being opened. ). Similarly, when the front lamp opening command is received in the external interrupt process (see FIG. 66), the sound lamp control device 113 sets the front frame opening command reception flag 223b to ON indicating that the front frame opening command has been received. Then, the front frame opening notification process is started (S959). Since the front frame opening notification process (S959) is also continuously performed until the opened front frame 14 is closed, it is possible to notify an unspecified number of people that the front frame 14 is being opened. .

  Further, in the door opening notification process (S818), when the sound lamp control device 113 receives the inner frame closing command in the external interrupt process (see FIG. 66), the voice lamp control device 113 displays the inner frame opening command reception flag 223a. The information indicating that the close command has been received is turned off (S964), and the executed inner frame release notification process is terminated (S965). Similarly, when the front lamp close command reception flag 223b is received in the external lamp interrupt process (see FIG. 66), the sound lamp control device 113 sets the front frame open command reception flag 223b to OFF indicating that the front frame close command has been received. In step S969, the front frame opening notification process that has been executed is terminated (S970).

  As described above, according to the pachinko machine of the ninth embodiment, the inner frame 12 is opened when power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power supply DC1. The inner frame opening detection circuit 290 detects the opening, and the main control device 110 transmits an inner frame opening command once to the sound lamp control device 113 within the main process. Similarly, when power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power source DC1, when the front frame 14 is opened, the front frame frame open detection circuit 292 Upon detection of opening, the main control device 110 transmits a front frame opening command once to the sound lamp control device 113 within the main process.

  As described above, in the pachinko machine according to the ninth embodiment, when the inner frame 12 or the front frame 14 is opened, an inner frame opening command or a front frame opening command is sent from the main controller 110 to the sound lamp control device. It transmits to 113 only once. Therefore, when the inner frame 12 or the front frame 14 is released, the inner frame release command or the front frame release command is repeatedly transmitted from the main control device 110 to the sound lamp control device 113 during the opening period. Compared with the pachinko machine 500, in the pachinko machine of the ninth embodiment, the number of command transmissions of the main control device 110 can be reduced, and the processing load in the main process can be reduced.

  Further, when the inner frame 12 or the front frame 14 is released, the inner frame release command or the front frame release command is repeatedly transmitted to the sound lamp control device 113 every 4 milliseconds within the main process of the main control device 110. In contrast to the pachinko machine 500 of the embodiment, in the pachinko machine of the ninth embodiment, when the inner frame 12 or the front frame 14 is opened, an inner frame release command or a front frame release command is sent from the main controller 110 to the sound lamp. Since the data is transmitted only once to the control device 113, the repetition period (every 4 milliseconds) in the main process of the main control device 110 cannot be grasped. Thereby, it becomes impossible to grasp the update cycle of the first per-random number counter C1 used for the big hit lottery repeatedly performed in the main process of the main controller 110. Therefore, according to the pachinko machine of the ninth embodiment, it is possible to make it difficult to illegally acquire the update period of the first random number counter C1 or the like, for example, using a hanging board.

  Furthermore, according to the pachinko machine of the ninth embodiment, when the power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power supply DC1, the opened inner frame 12 is closed. Then, the inner frame opening detection circuit 290 detects the closing, and the main control device 110 transmits an inner frame closing command once to the sound lamp control device 113 within the main process in accordance with the detection. Similarly, when power is supplied to the pachinko machine and a DC voltage of 12 volts is supplied from the DC power source DC1, if the opened front frame 14 is closed, the front frame frame open detection circuit 292 detects the closing, and the main control device 110 transmits a front frame closing command once to the sound lamp control device 113 within the main process in accordance with the detection.

  As described above, in the pachinko machine according to the ninth embodiment, when the opened inner frame 12 or the opened front frame 14 is closed, an inner frame closing command or a front frame closing command is issued to the main control device along with the closing. 110 is transmitted to the sound lamp control device 113 only once. Therefore, when the opened inner frame 12 or the opened front frame 14 is closed, the inner frame closing command or the front frame closing command is repeatedly transmitted from the main control device 110 to the sound lamp control device 113 during the closing period. Compared with the pachinko machine 500 according to the fourth embodiment, the pachinko machine according to the ninth embodiment can reduce the number of command transmissions of the main control device 110 and reduce the processing load in the main process.

  Further, when the inner frame 12 or the front frame 14 is closed, the inner frame closing command or the front frame closing command is repeatedly transmitted to the sound lamp control device 113 every 4 milliseconds within the main process of the main control device 110. In contrast to the pachinko machine 500 of the embodiment, in the pachinko machine of the ninth embodiment, when the inner frame 12 or the front frame 14 is closed, an inner frame close command or a front frame close command is sent from the main controller 110 to the sound lamp. Since the data is transmitted only once to the control device 113, the repetition period (every 4 milliseconds) in the main process of the main control device 110 cannot be grasped. Thereby, it becomes impossible to grasp the update cycle of the first per-random number counter C1 used for the big hit lottery repeatedly performed in the main process of the main controller 110. Therefore, according to the pachinko machine of the ninth embodiment, it is possible to make it difficult to illegally acquire the update period of the first random number counter C1 or the like, for example, using a hanging board.

  Note that the pachinko machine of the ninth embodiment is similar to the pachinko machine 500 of the fourth embodiment, for example, when the business hours of the amusement hall are over and the power supply to the pachinko machine is shut off, and 12 volts from the DC power supply DC1. When either the inner frame 12 or the front frame 14 is opened, the hall computer 262 is pulsed even when the DC voltage is not supplied, that is, when the control of the main controller 110 is stopped. Signals can be output separately. Therefore, it is possible to identify whether the inner frame 12 has been opened, the front frame 14 has been opened, or both have been opened by the pulse signal stored in the hall computer 262.

  In the pachinko machine according to the ninth embodiment, the main controller 110 to the sound lamp controller 113, in addition to the inner frame opening command, inner frame closing command, front frame opening command, and front frame closing command, as described above. Then, a variation pattern command, a stop symbol command, a stop command, an effect time addition command, etc. necessary for the variation display of the third symbol by the third symbol display device 81 are transmitted. In the pachinko machine of the ninth embodiment, these variation pattern command, stop symbol command, stop command, effect time addition command, etc. are the same as the inner frame release command, inner frame close command, front frame open command and front frame close command. The main controller 110 is configured to transmit the sound lamp controller 113 only once via the bus line BL1. In the pachinko machine according to the ninth embodiment, the strobe signal SG3 is transmitted from the main controller 110 to the sound lamp controller 113 via the bus line BL2 in accordance with the variation pattern command transmitted from the main controller 110. It is comprised so that.

  Specifically, this configuration is, for example, S231 to S240 of the door command transmission process in accordance with commands (variation pattern command, stop symbol command, stop command, effect time addition command, etc.) transmitted to the sound lamp control device 113. A new process using the concept of each process (see FIG. 64) is added to the door command transmission process (see FIG. 64).

  Here, an example of transmission of the fluctuation pattern command will be described. The transmission of the stop symbol command, the stop command, the effect time addition command, and the like may be configured in the same manner as the transmission of the variation pattern command, and the description thereof is omitted. Regarding the transmission of the variation pattern command, first, a variation pattern command transmission counter indicating whether or not the variation pattern command has been transmitted is provided in the RAM 203. In the door command transmission process (S222) shown in FIG. 64, for example, after execution of the process of S261 or S271, whether or not the “variation pattern command transmission counter is“ 0 (zero) ”using the concept of the process of S231”. Is determined. After the process, the door command transmission process is provided with a “change pattern command transmission start” process using the concept of the process of S232. Further, after the process, the door command transmission process is provided with a process using the processes of S233 to 236 as they are. After the process, the door command transmission process is provided with a determination process of “whether 1 msec has elapsed since the start of the transmission of the variation pattern command” using the concept of the process of S237. After the process, the door command transmission process is provided with a “variation pattern command transmission end” process using the concept of the process of S238. Then, after the process, the door command transmission process is provided with a process of “counting up the variation pattern command transmission counter by 1” using the concept of the process of S239. When a variation pattern command different from the variation pattern command transmitted earlier is transmitted, the variation pattern command transmission counter is set to “0 (zero)” before the transmission (concept of the processing of S240). Is provided in the door command transmission process.

  With the configuration described above, in the pachinko machine according to the ninth embodiment, a variation pattern command, a stop symbol command, a stop command, an effect time addition command, and the like are sent from the main controller 110 to the sound lamp controller 113 via the bus line BL1. The strobe signal SG3 is transmitted from the main control device 110 to the sound lamp control device 113 via the bus line BL2 in accordance with the transmitted command.

  Further, in the pachinko machine according to the ninth embodiment, the inner frame opening command, the inner frame closing command, the front frame opening command, or the front frame closing command is transmitted from the sound lamp control device 113 to the display control device 114 without the strobe signal SG3. However, it is not limited to this. The inner frame opening command, the inner frame closing command, the front frame opening command, and the front frame closing command are transmitted to the voice lamp control device 113 by the main control device 110, and the inner frame opening command is displayed in the process of S952. 114, the front frame opening command is transmitted to the display controller 114 in the process of S958, the inner frame closing command is transmitted to the display controller 114 in the process of S964, and the front frame closing command is transmitted in the process of S969. Is transmitted to the display control device 114, the sound lamp control device 113 may transmit the strobe signal SG3 to the display control device 114 in accordance with the command to be transmitted.

  In this case, a bus line for transmitting the strobe signal SG3 from the input / output port 225 of the sound lamp control device 113 to the input port 237 of the display control device 114 is newly provided, and S952 executed by the sound lamp control device 113 is performed. After each process of S958, S964, and S969, door command transmission processing (S222) for transmitting the inner frame opening command, the front frame opening command, the inner frame closing command, or the front frame closing command together with the strobe signal SG3 to the display control device 114. , See FIG. 64), the processing configuration of the door opening notification process (S818, see FIG. 67) may be changed. When the door opening notification process (S818) has this processing configuration, the display control device 114 displays an inner frame opening command, a front frame opening command, an inner frame closing command, and a front frame closing command in the door command transmission process. Therefore, it is not necessary to transmit these commands to the display control device 114 in each process of S952, S958, S964, and S969. Thereby, the sound lamp control device 113 can transmit the strobe signal SG3 to the display control device 114 in accordance with the transmission of the inner frame opening command, the inner frame closing command, the front frame opening command, or the front frame closing command. In the case of this configuration, when receiving the strobe signal SG3, the display control device 114 receives the inner frame opening command, inner frame closing command, front frame opening command, or front frame closing command transmitted from the sound lamp control device 113. Is configured to start receiving.

  The pachinko machine according to the ninth embodiment is a modification of the pachinko machine 500 according to the fourth embodiment. However, the pachinko machine according to the ninth embodiment may be applied to the pachinko machine 600 according to the fifth embodiment. . Further, the pachinko machine of the ninth embodiment may be applied to the pachinko machine 10x of the sixth embodiment, the pachinko machine of the seventh embodiment, and the pachinko machine of the eighth embodiment.

  Here, the case where the pachinko machine of 9th Embodiment is applied to the pachinko machine 10x of 6th Embodiment is demonstrated as a typical example. When the pachinko machine of the ninth embodiment is applied to the pachinko machine of the seventh embodiment and the pachinko machine of the eighth embodiment, the pachinko machine of the ninth embodiment is replaced with the pachinko machine 10x of the sixth embodiment. Since the configuration is the same as that applied to the above, description thereof is omitted. In addition, when the pachinko machine of the ninth embodiment is applied to the pachinko machine 600 of the fifth embodiment, the same change as the change made to the pachinko machine 500 of the fourth embodiment may be performed. Is omitted.

  When the pachinko machine of the ninth embodiment is applied to the pachinko machine 10x of the sixth embodiment, first, in the block diagram showing the electrical configuration of the pachinko machine 10x shown in FIG. 42, the input / output ports of the main controller 110x A bus line BL2x (not shown) that transmits a strobe signal to the input / output port 225x of the sound lamp control device 113x is connected to 205x (added). Accordingly, when an on-medium frame open command or an on-medium frame close command is started to be transmitted from the main control device 110x to the sound lamp control device 113x via the bus line (different from the bus line BL2x), the strobe A signal is output from the main controller 110x to the sound lamp controller 113x via the bus line BL2x.

  Further, an on-in-frame open command transmission counter and an on-in-frame closing command transmission counter are provided in the RAM 203x (see FIG. 42) of the main controller 110x. Further, a command reception memory is provided in the RAM 223x (see FIG. 42) of the sound lamp control device 113x.

  Whether the inner frame 12x or the front frame 14x is opened and whether or not the on frame release command is transmitted once from the main control device 110x to the sound lamp control device 113x. It is a counter that counts. The on-frame open command transmission counter is configured to open the inner frame 12x or the front frame 14x while the power is supplied to the pachinko machine 10x and a DC voltage of 12 volts is supplied from the DC power supply DC1x. When the on-in-frame release command is transmitted once by the control device 110x, “1” indicating that the on-in-frame release command has already been transmitted once is set. On the other hand, the on-frame open command transmission counter is turned on while the power is supplied to the pachinko machine 10x and a DC voltage of 12 volts is supplied from the DC power supply DC1x, or the opened inner frame 12x or the opened front frame. When the frame 14x is closed and the on-in-frame closing command is transmitted once by the main controller 110x, it is set to “0 (zero)” again.

  The on-in-frame closing command transmission counter is configured such that the opened inner frame 12x or the opened front frame 14x is closed, and an on-in-frame closing command 1 is sent from the main controller 110x to the sound lamp controller 113x. It is a counter that counts whether or not it has been transmitted once. The on-in-frame closing command transmission counter is configured to open the inner frame 12x or the opened front frame when power is supplied to the pachinko machine 10x and a DC voltage of 12 volts is supplied from the DC power source DC1x. When 14x is closed and the on-in-frame closing command is transmitted once by the main controller 110x, the on-in-frame closing command is set to “1” indicating that it has already been transmitted once. On the other hand, the on-in-frame closing command transmission counter is closed when the power is supplied to the pachinko machine 10x and the DC voltage of 12 volts is supplied from the DC power source DC1x, or the closed inner frame 12x or the closed front surface. When the frame 14x is released and the on-in-frame release command is transmitted once by the main controller 110x, the on-in-frame release command is not transmitted, contrary to the on-in-frame release command transmission counter. 0 (zero) ".

  The command reception memory is a memory for storing various commands transmitted from the main controller 110x via the bus line. In this command reception memory, in addition to the on-in-frame release command, on-in-frame close command, and off-in-frame release command, the fluctuation pattern command and stop symbol command necessary for the third symbol display by the third symbol display device 81 are displayed. , Stop command, production time addition command, etc. are stored. Note that the MPU 221x of the sound lamp control device 113x decodes the command stored in the command reception memory and performs control according to the decoded command.

  Next, the main process executed by the MPU 201x of the main controller 110x shown in FIG. 48 is changed. In the main process shown in FIG. 48, the ON middle frame release command transmission counter is set to “0 (zero)” at the execution position before “Yes” is determined in S214x and the process proceeds to S201x. A process of setting the middle frame closing command transmission counter to “1” is added (this process is added at the same position as the position where the process of S221 in FIG. 63 is executed). Further, the processes of S207x, S208x and S209x in the main process shown in FIG. 48 are deleted. At this time, if it is determined “No” in the process of S204x, the processing configuration is changed to shift to the process of S210x. Then, a door command transmission process (S222) shown in FIG. 64 is added after the process of S219x or S220x. At this time, the processing configuration is changed so that the processing shifts to S213x after the processing of S222.

  Then, after adding the door command transmission process (S222) shown in FIG. 64 to the main process shown in FIG. 48, the following processing configuration is changed to the door command transmission process shown in FIG. First, the processing of S251 to S271 shown in FIG. 64 is deleted, and the processing configuration is changed so that the processing of S230 to S250 remaining without being deleted is executed. Then, the “inner frame release flag” described in the process of S230 is changed to the “on-frame release flag (203bx)”. Further, the “inner frame release command transmission counter” described in the processing of S231, S239, and S250 is changed to “on-frame release command transmission counter”. Further, the “inner frame release command” described in the processing of S232, S237, and S238 is changed to the “on-frame release command”.

  In addition, the “inner frame closing command transmission counter” described in the processing of S240, S241, and S249 is changed to “on middle frame closing command transmission counter”. In addition, the “inner frame closing command” described in the processing of S242, S247, and S248 is changed to the “on middle frame closing command”. The other processes (S233 to S236 and S243 to S246) use the process described in the door command transmission process (S222) shown in FIG. 64 as it is.

  Next, the main process executed by the MPU 221x of the audio lamp control device 113x shown in FIG. 55 is changed. In the main process of the audio lamp control device 113x shown in FIG. 55, first, the process of S1111x is changed to the external interrupt process shown in FIG. Note that the processing shown in FIG. 66 is used as it is without changing the processing contents of the external interrupt processing that is changed from S1111x.

  Finally, in the door opening notification process (S1113x) shown in FIG. 56, the “command received in the process of S1111x” described in each process of S1201x, S1203x, and S1205x in the door opening notification process (S1113x) is performed. Change to “command stored in command reception memory”. It should be noted that when an off-frame release command is stored in the command reception memory, a process for deleting the off-frame release command from the command reception memory is not shown. It may be configured as follows. That is, when the off-in-frame release flag 203ax is turned off in the start-up process of the main controller 110x (see the process of S116x in FIG. 47), the off-in-frame release flag from the main controller 110x to the sound lamp controller 113x. A command indicating that 203ax is turned off is transmitted. Then, the voice lamp control device 113x may be configured to delete the off-in-frame release command from the command reception memory when the command is received. Thereby, only when the off-in-frame release flag 203ax is turned off, the off-in-frame release command is erased from the command reception memory, and the notification performed by the audio output device 226x and the lamp display device 227x is terminated. Can do. In addition, when either the ON middle frame opening command or the ON middle frame closing command is stored in the command reception memory, the command reception memory is received every time a command opposite to the command stored in the command reception memory is received. Is changed (since either the on-in-frame release command or the on-in-frame release command stored in the command reception memory is erased), the on-in-frame release command or on from the command reception memory is changed. There is no need to consider how to delete the middle frame closing command.

  By applying the above-described changes to the pachinko machine 10x of the sixth embodiment, also in the pachinko machine 10x of the sixth embodiment, power is supplied to the pachinko machine 10x, and a DC voltage of 12 volts is supplied from the DC power supply DC1x. When the inner frame 12x or the front frame 14x is opened in the case where it is supplied, the opening is detected by the frame opening detection circuit 260x, and the main controller 110x detects the sound lamp in the main process. An on-frame opening command can be transmitted once to the control device 113x. Further, when power is supplied to the pachinko machine 10x and a DC voltage of 12 volts is supplied from the DC power source DC1x, when the opened inner frame 12x or the opened front frame 14x is closed, the frame The opening detection circuit 260x detects the closing, and the main control device 110x can transmit the ON middle frame closing command once to the sound lamp control device 113x within the main process in accordance with the detection.

  Therefore, when the inner frame 12x or the front frame 14x is opened, or when the opened inner frame 12x or the opened front frame 14x is closed, the on-in-frame opening command or the on-in-frame closing is performed during that period. Compared with the pachinko machine 500 of the fourth embodiment in which commands are repeatedly transmitted from the main control device 110 to the sound lamp control device 113, in the pachinko machine 10x of the sixth embodiment to which the pachinko machine of the ninth embodiment is applied, It is possible to reduce the processing load in the main process by reducing the number of command transmissions of the main controller 110x.

  When the pachinko machine according to the ninth embodiment is applied to the pachinko machine 10x according to the sixth embodiment, an on-in-frame opening command and an on-in-frame closing command are controlled from the main controller 110x together with a strobe signal. Although the description has been given of transmitting only once to the device 113x via the bus line, the present invention is not limited to this, and the off-line open command is also connected to the sound lamp control device 113x from the main controller 110x together with the strobe signal. Needless to say, the transmission may be performed only once.

  When the pachinko machine according to the ninth embodiment is applied to the pachinko machine 10x according to the sixth embodiment, the main controller 110x is switched on to the sound lamp controller 113x, similarly to the pachinko machine according to the ninth embodiment. In addition to the open frame command, the on frame close command, and the off frame open command, a variation pattern command, a stop symbol command, a stop command, an effect time addition command, etc. necessary for the variation display of the third symbol by the third symbol display device 81, etc. Is sent. When the pachinko machine of the ninth embodiment is applied to the pachinko machine 10x of the sixth embodiment, these variation pattern command, stop symbol command, stop command, effect time addition command, etc. Similar to the middle frame closing command, the main controller 110x is configured to transmit only one time to the sound lamp controller 113x via the bus line. When the pachinko machine of the ninth embodiment is applied to the pachinko machine 10x of the sixth embodiment, the main controller 110x to the sound lamp controller 113x in accordance with various commands transmitted from the main controller 110x. The strobe signal is configured to be transmitted via a bus line BL2x (not shown). In addition, about the specific structure in this case, since it is as having demonstrated with the pachinko machine of 9th Embodiment, the description is abbreviate | omitted.

  As described above, the present invention has been described based on each embodiment, but the present invention is not limited to the above-described embodiment, and various modifications can be easily made without departing from the spirit of the present invention. It can be guessed.

  For example, in the first to fifth embodiments and the ninth embodiment, each command is transmitted from the main control device 110 to the sound lamp control device 113, and the display control device 114 is transmitted from the sound lamp control device 113. However, it is also possible to send a command directly from the main control device 110 to the display control device 114. Further, an audio lamp control device may be connected to the display control device, and a command instructing the output of each sound and the lighting of the lamp may be transmitted from the display control device to the audio lamp control device. Furthermore, the sound lamp control device and the display control device may be configured as one control device.

  Further, for example, in the sixth to eighth embodiments, each command is transmitted from the main control device 110x to the sound lamp control device 113x and displayed from the sound lamp control device 113x to the display control device 114x. However, the command may be transmitted directly from the main control device 110x to the display control device 114x. Further, an audio lamp control device may be connected to the display control device, and a command instructing the output of each sound and the lighting of the lamp may be transmitted from the display control device to the audio lamp control device. Furthermore, the sound lamp control device and the display control device may be configured as one control device.

  Further, in the first to fifth embodiments and the ninth embodiment, each of the winnings to the first entrance 64 and the passage of the second entrance 67 is suspended up to 4 times each. However, the maximum number of holding times is not limited to four times, and may be set to three times or less, or five times or more (for example, eight times). In addition, the number of times the variable display is held based on the winning at the first entrance 64 is different for the part of the third symbol display device 81 by a number or by dividing the number of four divided areas by the number of times of the hold. It may be displayed in a mode (for example, color or lighting pattern), and a light emitting member such as a lamp is provided separately from the first symbol display device 37, and the number of holding times is notified by the light emitting member. You may do it.

  Moreover, in the said 6th Embodiment to 8th Embodiment, although it comprised so that the winning to the 1st entrance 64x and the passage of the 2nd entrance 67x were each suspended up to four times, The number of holding times is not limited to four times, but may be set to three times or less, or five times or more (for example, eight times). Further, the number of suspensions of the variable display based on the winning at the first entrance 64x is different in the third symbol display device 81x by a number or the number of regions divided into four by the number of suspensions. It may be displayed in a mode (for example, color or lighting pattern), and a light emitting member such as a lamp is provided separately from the first symbol display device 37x, and the number of holding times is notified by the light emitting member. You may do it.

  In addition, as shown in the above embodiment, the variable display, which is a kind of dynamic display, scrolls the symbol as identification information in the vertical direction on the display screen of the third symbol display device 81 (third symbol display device 81x). It is not limited to those to be performed, but may be performed by moving and displaying symbols along a predetermined route such as a horizontal direction or an L-shape. In addition, the dynamic display of the identification information is not limited to the display of variation of the symbol. For example, one or a plurality of characters may be displayed in various manners together with the symbol or displayed in a variety of manners separately from the symbol. The effect display etc. which are displayed are also included. In this case, one or more characters are used as the third symbol.

  You may implement this invention in the pachinko machine etc. of a type different from the said embodiment. For example, the present invention may be applied to a so-called second type pachinko gaming machine having a winning device having a special area such as a V zone. Further, in addition to the pachinko machine, the game machine may be implemented as another game machine such as an alepacchi or a sparrow ball.

  You may implement this invention in the pachinko machine etc. of a type different from the said embodiment. For example, once a big hit, a pachinko machine that raises the expected value of the big hit until a big hit state occurs (for example, two times or three times) including that (for example, a two-time right item, a three-time right item) May also be implemented. Further, after the jackpot symbol is displayed, it may be implemented as a pachinko machine that generates a special game that gives a player a predetermined game value on the condition that a ball is won in a predetermined area. Further, the present invention may be implemented in a pachinko machine that has a special area such as a V-zone and has a special gaming state as a necessary condition for winning a ball in the special area. Further, in addition to the pachinko machine, the game machine may be implemented as various game machines such as an alepatchi, a sparrow ball, a slot machine, a game machine in which a so-called pachinko machine and a slot machine are integrated.

  In the slot machine, for example, a symbol is changed by operating a control lever in a state where a symbol effective line is determined by inserting coins, and a symbol is stopped and confirmed by operating a stop button. Is. Accordingly, the basic concept of the slot machine is that it is provided with a display device for confirming and displaying the identification information after variably displaying the identification information string composed of a plurality of identification information, and resulting from the operation of the starting operation means (for example, the operation lever). The variation display of the identification information is started, and the variation display of the identification information is stopped and fixedly displayed due to the operation of the operation means for stop (for example, the stop button) or when a predetermined time elapses. It is a slot machine that generates a special game that gives a player a predetermined game value on the condition that the combination of identification information at the time is a specific condition. In this case, the game medium is typically a coin, medal, etc. Take as an example.

  In addition, as a specific example of a gaming machine in which a pachinko machine and a slot machine are fused, a display device is provided that displays a symbol after a symbol string composed of a plurality of symbols is variably displayed, and has a handle for launching a ball. What is not. In this case, after throwing a predetermined amount of spheres based on a predetermined operation (button operation), for example, the change of the symbol is started due to the operation of the operation lever, for example, due to the operation of the stop button, or With the passage of time, the variation of the symbol is stopped, and a special game that gives a predetermined game value to the player is generated on the condition that the determined symbol at the time of stoppage is a so-called jackpot symbol. In this case, a large amount of balls are paid out to the lower tray.

  Hereinafter, in addition to the gaming machine of the present invention, concepts of various inventions included in the various embodiments described above are shown. A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. Door opening detecting means for detecting opening of the body, and when the door opening detecting means detects the opening of the door body, if the door body is in the initial state, the door body is operated by the operation from the initial state to a specified time. A period adjusting means for outputting a signal that becomes a predetermined output period regardless of the opening period of the door, and a detection result by the door opening detecting means is output to the specific device based on the signal output by the period adjusting means. Output means, and power supply means for operating the output means and the period adjusting means by supplying electric power, and the door opening detecting means initially sets the period adjusting means when the closing of the door body is detected. The power supply means includes an off-operation means for supplying power to the output means and the period adjusting means when the gaming machine is powered off. A gaming machine A1 characterized by

  According to the gaming machine A1, when the opening of the door body is detected by the door opening detection means, the period adjusting means is determined in advance regardless of the opening time of the door body by the operation from the initial state to the specified time. Outputs a signal for the output period. Then, the output means outputs the detection result to the specific device based on the signal output from the period adjusting means. Here, the output period of the signal output by the period adjusting means is determined by the operation of the period adjusting means from the initial state to the specified time. In order to cause the period adjusting means to output a signal that is a predetermined output period regardless of the opening time of the door body, the initialization means includes a period adjusting means when the door opening detecting means detects the closing of the door body. To the initial state. Therefore, the period adjusting means can always operate from the initial state when the door opening detecting means detects the opening of the door body. Therefore, every time the door opening detection unit detects the opening of the door body, the period adjusting unit is operated normally and stably from the initial state to the specified time, thereby providing a predetermined output period for the period adjusting unit. The signal can be output normally and stably, and the detection result can be output normally and stably from the output means to the specific device.

  In addition, according to the gaming machine A1, in addition to the state where the power source of the gaming machine is turned on, even if the power source of the gaming machine is turned off and the control means is stopped, the door opening detection means detects the door body. When opening is detected, power is supplied to the output means and the period adjusting means by the off-operation means. Therefore, even when the gaming machine is turned off and the control means is stopped, when the door opening detection means detects the opening of the door body, a signal that becomes a predetermined output period by the period adjustment means Is output, and the output means outputs the detection result to the specific device based on the output signal. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  In addition, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side (including the back surface side of the main body) of the door body that cannot be touched by a hand when the door body is closed. The detection result output from the output means provided for each of the plurality of gaming machines may be received by one specific device, or a specific device is provided for each gaming machine, and the specific device is distributed to each gaming machine. May be installed. When a specific device is installed in each gaming machine, the box base and the box cover covering the opening of the box base are connected to each other, and the specific device is specified in the space formed by the box cover and the box base. Store the device. Then, the box cover and the box base are connected by the sealing unit so that they cannot be opened. Further, a seal seal is attached to the connecting portion between the box cover and the box base over the box cover and the box base. In addition, a specific device may be disposed on the back surface or the back surface side of the door body.

  In the gaming machine A1, the door opening detecting means includes a stopping means for stopping power supply to the period adjusting means by the power supply means when the closing of the door body is detected. A2.

  According to the gaming machine A2, when the door opening detection means detects the closing of the door body, the stop means stops the power supply by the power supply means to the period adjustment means. Therefore, the period adjusting means can be set to the initial state by the initializing means while the operation of the period adjusting means is stopped by the stopping means. Therefore, the period adjusting means can be in a normal and stable initial state.

  In the gaming machine A1 or A2, the period adjusting unit is configured using a power storage unit that stores a charge, and the charge stored in the power storage unit by the power supplied from the initial state to a specified time by the power source unit. The game machine A3 is characterized in that the voltage generated along with the above is output as a signal for the predetermined output period.

  According to the gaming machine A3, when power from the power supply means is supplied to the power storage means constituting the period adjusting means from the initial state to the specified time, electric charge is stored in the power storage means. The period adjusting means outputs a voltage generated with the electric charge stored in the power storage means as a signal that becomes a predetermined output period. In this way, by configuring the period adjusting unit with the power storage unit, a signal having a predetermined output period can be output with a simple configuration without using a complicated circuit as the period adjusting unit.

  In the gaming machine A3, the initialization means discharges the charge stored in the power storage means constituting the period adjusting means when the door opening detection means detects the closing of the door body, thereby A gaming machine A4, characterized by comprising discharging means for initializing the means.

  According to the gaming machine A4, when the door opening detecting means detects the closing of the door body, the discharging means discharges the charge stored in the power storage means constituting the period adjusting means. Therefore, when the door opening detection means detects the door opening, the electric charge stored in the power storage means is discharged to zero by the discharging means when the door opening detection means detects the door closing. can do. Thereby, when the door opening detection means detects the opening of the door body, the period adjusting means constituted by the power storage means can always operate from the initial state. Therefore, every time the door opening detection unit detects the opening of the door body, the period adjusting unit is operated normally and stably from the initial state to the specified time, thereby providing a predetermined output period for the period adjusting unit. The signal can be output normally and stably, and the detection result can be output normally and stably from the output means to the specific device. An example of a method for discharging the power storage means is to short-circuit the power storage means to the ground.

  In any one of the gaming machines A2 to A4, the stopping means is a releasing means for releasing the electrical connection between the power supply means and the period adjusting means when the door opening detecting means detects the closing of the door body. A gaming machine A5, comprising:

  According to the gaming machine A5, when the closing of the door body is detected by the door opening detecting means, the electrical connection between the power supply means and the period adjusting means is released by the releasing means. Therefore, the period adjusting means can be brought into the initial state by the initializing means or the discharging means in a state where the power supply to the period adjusting means is stopped by the releasing means. Therefore, the period adjusting means can be in a normal and stable initial state.

  In the gaming machine A5, when the door opening detection unit detects the opening of the door body, the initialization unit releases a short circuit caused by the discharging unit between the power storage unit and the ground constituting the period adjusting unit. A discharge release means, and the stop means stops the release of electrical connection by the release means between the power supply means and the period adjusting means when the door opening detection means detects the opening of the door body. Power supply restarting means for restarting power supply to the period adjusting means by the power supply means, and when the door opening detection means detects the opening of the door body, the power supply restarting means After the short circuit caused by the discharging means between the power storage means and the ground constituting the period adjusting means is released by the discharge releasing means, the electricity by the releasing means between the power supply means and the period adjusting means When the release of the connection is stopped, the power supply to the period adjusting means is restarted, and the door opening detecting means detects the closing of the door body, the discharging means is the power supply means. And after the electrical connection between the period adjusting means and the period adjusting means is released by the releasing means, the electric storage means constituting the period adjusting means is short-circuited to the ground, and the electric charge stored in the electric storage means is discharged. A gaming machine A6.

  According to the gaming machine A6, when the door opening detection means detects the opening of the door body, the power supply restarting means first uses a short circuit between the power storage means and the grant constituting the period adjustment means as the discharge release means. After the release, the power supply from the power supply means to the period adjusting means is resumed. On the other hand, when closing of the door body is detected by the door opening detecting means, the discharging means first causes the releasing means to release the electrical connection between the power supply means and the period adjusting means, and then configures the period adjusting means. The power storage means to be short-circuited to the ground discharges the charge stored in the power storage means. Therefore, neither the case where the door opening detection means detects the opening of the door body nor the case where the door opening detection means detects the closing of the door body will cause a short circuit between the power supply means and the ground. . Therefore, it is possible to reliably prevent damage to the power supply means and the like due to a short circuit between the power supply means and the ground.

  In any one of the gaming machines A1 to A6, the game machine includes an output period limiting unit that keeps one output period of the output unit within a predetermined period. The gaming machine A7 is configured to operate by supplying power to the output period limiting means.

  According to the gaming machine A7, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means and the period adjustment means, the output period limiting means operates by receiving power supply from the off-time operation means while the gaming machine is turned off. Can be kept within a predetermined period, and consumption of the off-operation means during the power-off of the gaming machine can be suppressed. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

  In any one of the gaming machines A1 to A7, the off-operation means is configured to be rechargeable by electric power supplied from a power source of the gaming machine.

  According to the gaming machine A8, the off-operation means is charged by the power supplied to the gaming machine while the gaming machine is powered on, so the gaming machine power is turned on in accordance with the business hours of the game hall. The operating means can be charged only during the off-state. Therefore, when the door is opened while the power of the gaming machine is turned off after the game hall is closed, the output means and the period adjusting means (and the output period limiting means) are operated by the off-operation means. The detection result by the door opening detection means can be reported to the specific device.

  In the gaming machine A7 or A8, the output means outputs a detection result to the specific device based on the output from the output period restriction means, and the output period restriction means causes the door opening detection means to detect the door body. A gaming machine A9 that outputs to the output means during the predetermined period when release is detected.

  According to the gaming machine A9, to the output means for outputting the detection result to the specific device based on the output from the output period limiting means, during the predetermined period when the door opening detection is detected by the door opening detection means, Output is performed by the output period limiting means. Therefore, the output operation to the output means by the output period limiting means can be stopped within a predetermined period for each opening of the door body. Accordingly, it is possible to suppress consumption of the off-operation means while the power of the gaming machine is turned off, and to increase the number of times that the output means can be operated, thereby increasing the number of times that the door body can be detected.

  In the gaming machine A9, the output period limiting unit stops output to the output unit when the door opening detection unit does not detect the opening of the door body.

  According to the gaming machine A10, the output of the output period limiting unit to the output unit that outputs the detection result to the specific device is stopped when the door opening detection unit does not detect the opening of the door body. Therefore, when the door opening detection means does not detect the opening of the door body, it is possible to suppress the power consumed by the output operation of the output period restriction means. Accordingly, it is possible to suppress consumption of the off-operation means while the power of the gaming machine is turned off, and to increase the number of times that the output means can be operated, thereby increasing the number of times that the door body can be detected.

  In any one of the gaming machines A7 to A10, the output period limiting means is configured using a monostable multivibrator, and the output period of the signal output to the monostable multivibrator by the period adjusting means is the door body. The gaming machine A11 is set to a period shorter than the predetermined period regardless of the opening period.

  According to the gaming machine A11, the signal input to the output period limiting means using the monostable multivibrator is a predetermined output period by the output means by the period adjusting means regardless of the door opening period. Adjusted to be shorter than the period. Here, the monostable multivibrator continues to output a signal unless the input period of the input signal is shorter than the output period of the output signal. For this reason, when a monostable multivibrator is used as the output period limiting means, it is input to the output period limiting means beyond the output period of the output signal, that is, the predetermined period limited by the output period limiting means. The signal input period, that is, the door opening period must be short. However, since it is completely unpredictable how long the door opening period will be, in order to keep the door opening period always shorter than the predetermined period limited by the output period limiting means, It is necessary to set the period with a sufficient margin. For example, if the door opening period is predicted to be several tens of seconds to several minutes, the predetermined period limited by the output period restriction means is set from several minutes to several tens of minutes with sufficient margin. Must. Then, during this predetermined period, power is continuously supplied to the output period limiting means and the output means from the off-state operation means, so that the off-state operation means is significantly consumed. Therefore, a special circuit configuration is required to suppress the consumption of the off-operation means while using a monostable multivibrator as the output period limiting means. However, according to the gaming machine A11, the signal input to the output period limiting means can be adjusted to be shorter than the predetermined period by the period adjusting means regardless of the door opening period. Therefore, since the output period limiting means can be operated normally regardless of the door opening period, one output period by the output means can be kept within a predetermined period by the output period limiting means. As described above, according to the gaming machine A11, by providing the period adjusting means, it is possible to suppress the consumption of the operating means during the off state, and to use the monostable multivibrator without adopting a special circuit configuration. Limiting means can be realized.

  In any one of the gaming machines A1 to A11, the output means is mounted on a substrate different from the control means.

  In any one of the gaming machines A1 to A12, the output means includes a photocoupler, and the detection result by the door opening detection means is output to the specific device by the output of the photocoupler. Machine A13.

  In any one of the gaming machines A1 to A13, the output means and the period adjusting means (further, the output period limiting means) are configured to be operable even at a voltage lower than the operating voltage of the control means. Characteristic gaming machine A14.

  According to the gaming machine A14, the output means and the period adjusting means (and the output period limiting means) are configured to be operable even at a voltage lower than the operating voltage of the control means. Even if the amount of charge decreases and the output voltage of the operating means during the off state becomes lower than the operating voltage of the control means, the output means and the period adjusting means (and the output period limiting means) are operated to open the door body. Can be reported to a specific device. That is, it is possible to detect the opening of the door body for a long time when the gaming machine is powered off.

  In any one of the gaming machines A1 to A14, the output means and the period adjusting means (further, the output period limiting means) are configured such that the operable range voltage is wider than the operable range voltage of the control means. A gaming machine A15.

  According to the gaming machine A15, the output means and the period adjusting means (further, the output period limiting means) are configured such that the operable range voltage is wider than the operable range voltage of the control means. Therefore, when the power of the gaming machine is turned off, the output means and the period adjusting means (moreover, the output period limiting means) can be operated for a long time by the off-time operating means. Can be detected for a long time.

  Any one of the gaming machines A7 to A15, wherein the output period limiting means includes a C-MOS semiconductor.

  According to the gaming machine A16, the output period limiting means includes a C-MOS semiconductor. Here, the C-MOS semiconductor generally has low power consumption during operation. Therefore, according to the gaming machine A16, it is possible to reduce the consumption of the off-operation means and to detect the opening of the door body for a long time when the gaming machine is powered off.

  In any one of the gaming machines A1 to A16, the period adjusting means is configured by using an integration circuit.

  According to the gaming machine A17, since the period adjusting means is configured by using the integration circuit, the signal input to the output period limiting means is adjusted to be shorter than the predetermined period without using a complicated circuit or signal processing. be able to. Further, by adjusting the resistance value of the resistor used in the integrating circuit and the capacitance value of the capacitor, the output period of the signal output by the period limiting means can be freely adjusted within a predetermined period.

  One of the gaming machines A1 to A17, wherein the gaming machine is a pachinko gaming machine. Among them, the basic configuration of a pachinko gaming machine is provided with an operation handle, and a ball is launched into a predetermined game area in accordance with the operation of the operation handle, and the ball is placed in an operation port disposed at a predetermined position in the game area. As a necessary condition for winning a prize (or passing through an operating port), the identification information that is dynamically displayed on the display device is confirmed and stopped after a predetermined time. In addition, when a special gaming state occurs, a variable winning device (specific winning port) disposed at a predetermined position in the gaming area is opened in a predetermined manner so that a ball can be won, and a value corresponding to the number of winnings is obtained. Examples include those to which values (including data written on magnetic cards as well as premium balls) are given.

  A gaming machine A19 according to any one of the gaming machines A1 to A17, wherein the gaming machine is a slot machine. Above all, the basic configuration of the slot machine is “equipped with variable display means for confirming and displaying the identification information after dynamically displaying an identification information string composed of a plurality of identification information, and for operating the starting operation means (for example, an operation lever). As a result, the dynamic display of the identification information is started, and the dynamic display of the identification information is stopped due to the operation of the stop operation means (stop button) or after a predetermined time has elapsed. The game machine is provided with special game state generating means for generating a special game state advantageous to the player on the condition that the confirmed identification information is specific identification information. In this case, examples of the game media include coins and medals.

  Any of the gaming machines A1 to A17, wherein the gaming machine is a combination of a pachinko gaming machine and a slot machine. Among them, the basic configuration of the merged gaming machine includes “a variable display means for confirming and displaying the identification information after dynamically displaying an identification information string composed of a plurality of identification information, and a starting operation means (for example, an operation lever). The identification information fluctuates due to the operation, and the dynamic display of the identification information is stopped due to the operation of the operation means for stopping (for example, the stop button) or after a predetermined time has passed. Special game state generating means for generating a special game state advantageous to the player on the condition that the fixed identification information at the time of stoppage is specific identification information, and using a ball as a game medium, and the identification information The game machine is configured such that a predetermined number of balls are required at the start of the dynamic display, and a large number of balls are paid out when the special gaming state occurs.

  In the gaming machines A1 to A20, the pachinko machine 10 corresponds to the gaming machine, the outer frame 11 corresponds to the main body, the inner frame 12 and the front frame 14 correspond to the door body, and the control means includes The main controller 110 corresponds. Further, the integration circuit 281 corresponds to the period adjusting means, and the inner frame opening detection circuit 300, the inner frame terminal board output circuit 300a, the inner frame external output terminal board 291 and the front frame opening are used as the output means. The detection circuit 302, the front frame terminal board output circuit 302a, the front frame external output terminal board 293, and the photocoupler PR1 correspond to each other. The power source means corresponds to the capacitor CD1 and the DC power source DC1, the off-time operation means corresponds to the capacitor CD1, the output period limiting means corresponds to the timer IC1, the door opening detection means, the stop means, and the release means. The switch SW3A and the switch SW4A correspond to the power supply restarting means, the initialization means, the discharging means, and the discharge releasing means.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detection means for detecting the opening of the body, and an output means for outputting the detection result to the specific device when the door opening detection means detects the opening of the door body, the output means, The gaming machine B1 is configured to output a detection result by the door opening detection means to the specific device when the power of the gaming machine is turned off and the control means is stopped.

  According to the gaming machine B1, even when the power of the gaming machine is turned off and the control means is stopped, when the door opening detection is detected by the door opening detection means, the detection result is specified by the output means. Output to the device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, an output means for outputting the detection result to the specific device when the door opening detecting means detects the opening of the door, and a one-time output by the output means. An output period limiting means for keeping the output period within a predetermined period, and an off-time operation means for operating the output period limiting means and the output means while the gaming machine is powered off. Machine B2.

  According to the gaming machine B2, when the door opening detection means detects the opening of the door body, the detection result is output to the specific device by the output means. Since the output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. The detection result can be output to a specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operation period of the output means by one opening of the door body is within a predetermined period. In other words, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, an output means for outputting the detection result to the specific device when the door opening detecting means detects the opening of the door, and a one-time output by the output means. An output period limiting unit that keeps the output period within a predetermined period; and an off-period operation unit that operates the output period limiting unit and the output unit while the gaming machine is powered off. A detection result is output to the specific device based on an output from the period limiting unit, and the output period limiting unit detects the opening of the door body by the door opening detection unit during the predetermined period. output Gaming machine B3 which is characterized in that the output of the stage.

  According to the gaming machine B3, when the door opening detection means detects the opening of the door body, the detection result is output to the specific device by the output means. Since the output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. The detection result can be output to a specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operation period of the output means by one opening of the door body is within a predetermined period. In other words, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

  Further, the output means for outputting the detection result to the specific device based on the output from the output period restriction means is output by the output period restriction means during a predetermined period when the door opening detection is detected by the door opening detection means. Output is done. Therefore, the output operation to the output means by the output period limiting means can be stopped within a predetermined period for each opening of the door body. Accordingly, it is possible to suppress consumption of the off-operation means while the power of the gaming machine is turned off, and to increase the number of times that the output means can be operated, thereby increasing the number of times that the door body can be detected.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, an output means for outputting the detection result to the specific device when the door opening detecting means detects the opening of the door, and a one-time output by the output means. An output period limiting unit that keeps the output period within a predetermined period; and an off-period operation unit that operates the output period limiting unit and the output unit while the gaming machine is powered off. The detection result is output to the specific device based on the output from the period limiting unit, and the output period limiting unit outputs to the output unit when the door opening detection unit does not detect the opening of the door body. Gaming machine B4, characterized in that the stop.

  According to the gaming machine B4, when the door opening detection means detects the opening of the door body, the detection result is output to the specific device by the output means. Since the output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. The detection result can be output to a specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operation period of the output means by one opening of the door body is within a predetermined period. In other words, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

  Further, the output of the output period limiting means to the output means for outputting the detection result to the specific device is stopped when the door opening detection means does not detect the opening of the door body. Therefore, when the door opening detection means does not detect the opening of the door body, it is possible to suppress the power consumed by the output operation of the output period restriction means. Accordingly, it is possible to suppress consumption of the off-operation means while the power of the gaming machine is turned off, and to increase the number of times that the output means can be operated, thereby increasing the number of times that the door body can be detected.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, an output means for outputting the detection result to the specific device when the door opening detecting means detects the opening of the door, and a one-time output by the output means. Output period limiting means using a monostable multivibrator that keeps the output period within a predetermined period, and connected to the output period limiting means, and when the door opening detection means detects the opening of the door body, the output An input period adjusting unit that adjusts a signal input to the period limiting unit to a period shorter than the predetermined period regardless of an opening period of the door body, and the output period limiting unit and the output unit are connected to the electric machine of the gaming machine. Gaming machine B5, characterized in that it comprises a and off during operation means for operating during the off.

  According to the gaming machine B5, when the door opening detection means detects the opening of the door body, the detection result is output to the specific device by the output means. Since the output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. The detection result can be output to a specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the output means is kept within a predetermined period by the output period limiting means. Similarly to the output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operation period of the output means by one opening of the door body is within a predetermined period. In other words, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine. Therefore, the frequency | count of operation | movement of an output means can be increased and the frequency | count of detection of opening of a door body can be increased.

  Further, the signal input to the output period limiting means using the monostable multivibrator is shorter than the predetermined period, which is one output period by the output means, regardless of the door opening period by the input period adjusting means. Adjusted. Here, the monostable multivibrator continues to output a signal unless the input period of the input signal is shorter than the output period of the output signal. For this reason, when a monostable multivibrator is used as the output period limiting means, it is input to the output period limiting means beyond the output period of the output signal, that is, the predetermined period limited by the output period limiting means. The signal input period, that is, the door opening period must be short. However, since it is completely unpredictable how long the door opening period will be, in order to keep the door opening period always shorter than the predetermined period limited by the output period limiting means, It is necessary to set the period with a sufficient margin. For example, if the door opening period is predicted to be several tens of seconds to several minutes, the predetermined period limited by the output period restriction means is set from several minutes to several tens of minutes with sufficient margin. Must. Then, during this predetermined period, power is continuously supplied to the output period limiting means and the output means from the off-state operation means, so that the off-state operation means is significantly consumed. Therefore, a special circuit configuration is required to suppress the consumption of the off-operation means while using a monostable multivibrator as the output period limiting means. However, according to the gaming machine B5, the input period adjusting unit can adjust the signal input to the output period limiting unit to be shorter than the predetermined period regardless of the door opening period. Therefore, since the output period limiting means can be operated normally regardless of the door opening period, one output period by the output means can be kept within a predetermined period by the output period limiting means. Thus, according to the gaming machine B5, by providing the input period adjusting means, the consumption of the operating means during the off state is suppressed, and the output is performed using the monostable multivibrator without adopting a special circuit configuration. Period limiting means can be realized.

  In the gaming machine B5, the input period adjusting means is configured by using an integrating circuit.

  According to the gaming machine B6, since the input period adjusting means is configured using the integration circuit, the signal input to the output period limiting means is adjusted to be shorter than the predetermined period without using a complicated circuit or signal processing. can do. Also, by adjusting the resistance value of the resistor used in the integrating circuit and the capacitance value of the capacitor, the input period of the signal input to the output period limiting means can be freely adjusted within a predetermined period.

  In the gaming machine B5 or B6, the input period adjusting means includes a constant voltage means for making a maximum voltage of a signal input to the output period limiting means constant.

  According to the gaming machine B7, since the constant voltage means is provided, the maximum voltage of the signal input to the output period limiting means is made constant, the signal input to the output period limiting means is stabilized, and the output means One output period can be stably kept within a predetermined period.

  In addition, when the input period adjustment means is configured using an integration circuit, electric charge is stored in the capacitor used in the integration circuit, and the voltage due to this charge is superimposed on the signal input to the output period restriction means. There is a possibility that an overvoltage that can destroy the output period limiting means is applied to the output period limiting means. However, according to the gaming machine 7, the constant voltage means makes the maximum voltage of the signal input to the output period limiting means constant, so that an overvoltage that can destroy the output period limiting means is not applied to the output period limiting means. . Therefore, destruction of the output period limiting unit can be prevented.

  In the gaming machine B7, the constant voltage means is constituted by a Zener diode, the gaming machine B8.

  According to the gaming machine B8, since the constant voltage means is constituted by the Zener diode, it is input to the output period limiting means with a simple configuration and at a lower cost than a constant voltage circuit constituted by a complicated circuit. The maximum signal voltage can be made constant. Therefore, using a simple and inexpensive Zener diode, the signal input to the output period limiting means is stabilized, and the output period is limited while the output period by the output means is stably kept within a predetermined period. It is possible to prevent an overvoltage that can destroy the means from being applied to the output period limiting means.

  In the gaming machines B1 to B8, the door body includes an inner frame that is opened and closed with respect to the main body, and a transparent plate support door that is opened and closed with respect to the inner frame, and the door opening detection means Are provided on the inner frame and the transparent plate support door, respectively, and are connected in parallel to the output means. The output means is configured to detect at least one of the inner frame or the transparent plate support door by the door opening detection means. A game machine B9, wherein when a release is detected, the detection result is output to the specific device.

  According to the gaming machine B9, the door opening detection means is provided on the inner frame and the transparent plate support door, and is connected in parallel to the output means. When at least one of the openings is detected, the detection result is output to the specific device by the output means. Therefore, even if one of the inner frame and the transparent plate support door constituting the door body is opened, the opening can be reported to the specific device by one output means.

  In any one of the gaming machines B1 to B9, the door opening detection means is configured to be turned on when the door body is opened, and blocked when the door body is closed. A gaming machine B10, which is characterized in that According to the gaming machine B10, the door opening detection means is turned on when the door body is opened, while it is blocked when the door body is closed, so that it is time for an illegal act. It is possible to keep the power consumption small by operating the output means only while the door is open.

  Any one of the gaming machines B1 to B10 is provided with an off-state operation means that is charged while the gaming machine is powered on, and the output means operates by the charge or power charged in the off-state operation means. A gaming machine B11 characterized by that. According to the gaming machine B11, the off-operation means is charged by the power supplied to the gaming machine while the gaming machine is powered on, so the gaming machine is turned on in accordance with the business hours of the game hall. It is possible to charge the operating means while off. Therefore, if the door is opened while the power of the gaming machine is turned off after the game hall is closed, the output means (and the output period restriction means) are operated by the off-operation means, and the door The detection result by the opening detection means can be reported to the specific device.

  In any of the gaming machines B1 to B11, the control means includes main control means for performing main control of the game, and the output means is mounted on the main control means. .

  In any one of the gaming machines B1 to B11, the output means is mounted on a different board from the control means.

  In any one of the gaming machines B1 to B13, the output means includes a photocoupler, and the detection result by the door opening detection means is output to the specific device by the output of the photocoupler. Machine B14.

  In any one of the gaming machines B2 to B14, the output period limiting means and the output means are configured to be operable even at a voltage lower than the operating voltage of the control means. . According to the gaming machine B15, the output period limiting means and the output means are configured to be operable even at a voltage lower than the operating voltage of the control means. Even when the output voltage of the off-operation means becomes lower than the operation voltage of the control means, it is possible to report the opening of the door to the specific device by operating the output period limiting means and the output means. That is, it is possible to detect the opening of the door body for a long time when the gaming machine is powered off.

  In any one of the gaming machines B2 to B15, the output period limiting means and the output means are configured such that the operable range voltage is wider than the operable range voltage of the control means. B16. According to the gaming machine B16, the output period limiting means and the output means are configured such that the operable range voltage is wider than the operable range voltage of the control means. Therefore, when the power of the gaming machine is turned off, the output period limiting means and the output means can be operated for a long time by the off-time operating means, so that the opening of the door body is detected for a long time when the gaming machine is powered off. Can do.

  In any one of the gaming machines B2 to B16, the output period limiting means includes a C-MOS semiconductor, and the gaming machine B17 is characterized in that: According to the gaming machine B17, the output period limiting means has a C-MOS semiconductor. Here, the C-MOS semiconductor generally has low power consumption during operation. Therefore, according to the gaming machine B17, it is possible to detect the opening of the door body for a long time when the power of the gaming machine is turned off by reducing the consumption of the off-operation means.

  Any of the gaming machines B1 to B17, wherein the gaming machine is a pachinko gaming machine.

  A gaming machine B19 according to any one of the gaming machines B1 to B17, wherein the gaming machine is a slot machine.

  A gaming machine B20 according to any one of the gaming machines B1 to B17, wherein the gaming machine is a fusion of a pachinko gaming machine and a slot machine.

  In the gaming machines B1 to B20, the pachinko machine 10 corresponds to the gaming machine, the outer frame 11 corresponds to the main body, the inner frame 12 and the front frame 14 correspond to the door body, and the transparent plate support door Corresponds to the front frame 14. The main controller 110 corresponds to the control means, the open frame detection circuits 260, 270, and 280, the external output terminal plate 261, and the photocoupler PR1 correspond to the output means, and the integration circuit corresponds to the input period adjustment means. 281 corresponds to capacitors CD1 and CD6 corresponding to the off-state operating means. The Zener diode D3 corresponds to the constant voltage means, the timer IC1 corresponds to the output period limiting means, and the switch SW1 and the switch SW2 correspond to the door opening detection means.

  A main body, a door body for opening and closing the front surface of the main body, a control means for controlling a game provided in a space formed by the door body and the main body, and an informing means for performing notification by control of the control means A door opening detecting means for detecting the opening of the door body with respect to the main body, and when the opening of the door body is detected by the door opening detecting means, the detection result is indicated by the control means. And output means for outputting the detection result to a specific device, and the output means is controlled by the control means when the gaming machine is turned on. If the door opening detection means outputs the detection result by the door opening detection means to the specific device, and the gaming machine is turned off and is not controlled by the control means, the door opening detection hand Gaming machine C1, characterized in that the detection result and to output to the specific device according to.

  According to the gaming machine C1, when the opening of the door body is detected by the door opening detection means when the power of the gaming machine is turned on and the control means is controlled, the detection result is controlled by the output means. The information is output to the means and the notification by the notification means is executed, and the detection result is output to the specific device by the output means. Therefore, for example, when the door is opened by an unauthorized act by someone while the game machine is turned on, it is possible to determine the gaming machine whose door has been opened by notification by the notification means. At the same time, it is possible to determine the gaming machine whose door is opened by the specific device. On the other hand, when the power of the gaming machine is turned off, control of the control means is stopped. In this case as well, when the door opening detection means detects the opening of the door body, the detection result is output. Is output to the specific device by the means. Therefore, even if the door is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door opened by the specific device can be determined. Therefore, regardless of whether the gaming machine is powered on or off, when the door is opened by an unauthorized act by somebody, the detection result is output to the specific device by one output means, and the game in which the door is opened The machine can be identified by a specific device.

  In the gaming machine C1, when the power source of the gaming machine is turned on, a power source unit that operates by supplying power to the output unit and a power source unit are provided separately, and the power source of the gaming machine is turned off. An off-state operating means for operating the output means by supplying power to the output means, and the output means is operated by the power supplied by the power supply means and the detection result by the door opening detection means is the control means. Control output means for outputting to the power supply means, and output means for specification for operating the electric power supplied by the power supply means or the off-operation means to output the detection result by the door opening detection means to the specific device. A gaming machine C2 characterized by that.

  According to the gaming machine C2, when the power source of the gaming machine is turned on, power is supplied from the power source means to the control output means and the specifying output means. Thus, when the door opening detection means detects the opening of the door body, the detection result is output to the control means by the control output means, the notification by the notification means is executed, and the detection result is output for specification. Is output to the specific device by the means. Therefore, for example, when the door is opened by an unauthorized act by someone while the game machine is turned on, it is possible to determine the gaming machine whose door has been opened by notification by the notification means. At the same time, it is possible to determine the gaming machine whose door is opened by the specific device. On the other hand, when the power of the gaming machine is turned off, power is supplied to the specifying output means by the off-operation means. Thus, when the door opening detection means detects the opening of the door body, the detection result is output to the specifying device by the specifying output means. Therefore, even if the door is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door opened by the specific device can be determined. Therefore, regardless of whether the gaming machine is powered on or off, if the door is opened by an unauthorized act by somebody, a detection result is output to the specific device by the specifying output means, and the game in which the door is opened The machine can be identified by a specific device.

  In the gaming machine C2, the game machine C2 further includes an output period limiting unit that keeps one output period of the specifying output unit within a predetermined period, and the off-time operation unit includes the output period limiting unit in addition to the specifying output unit Also, the gaming machine C3 is configured to be operated by supplying electric power.

  According to the gaming machine C3, one output period by the specifying output means is kept within a predetermined period by the output period limiting means. Similarly to the specifying output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operating period of the specifying output means by one opening of the door body Can be kept within a predetermined period, and consumption of the off-operation means during the power-off of the gaming machine can be suppressed. Therefore, it is possible to increase the number of times that the specifying output means can be operated and increase the number of times that the opening of the door body can be detected.

  In the gaming machine C2 or C3, the off-operation means is configured to be rechargeable by electric power supplied from a power source of the gaming machine.

  According to the gaming machine C4, the off-time operation means is charged by the power supplied to the gaming machine while the gaming machine is turned on, so the gaming machine is turned on in accordance with the business hours of the game hall. It is possible to charge the operating means while off. Therefore, when the door body is opened while the power of the gaming machine is turned off after the game hall is closed, the specifying output means and the output period limiting means are operated by the off-operation means, and the door The detection result by the opening detection means can be reported to the specific device.

  In any one of the gaming machines C2 to C4, a diode that allows a current supplied from the power supply means to flow in one direction is provided, and the off-operation means is configured using a capacitor or a secondary battery, and the door opening detection means Is configured to be turned on when the door is open, and cut off when the door is closed, and the power supply means is connected to the anode terminal of the diode. The cathode terminal of the diode is connected to one end of the off-state operation means, the other end of the off-state operation means is grounded, and the control output means is the power supply means. And the anode terminal of the diode via the door opening detecting means, and the output means for specifying is the cathode terminal of the diode and one end of the off-time operating means. Gaming machine C5, characterized in that it is connected through the door opening detection means.

  According to the gaming machine C5, since the control output means is connected to the power supply means and the anode terminal of the diode, when the door body is opened when the power supply of the gaming machine is turned on, the door opening detection means Becomes conductive, power is supplied from the power supply means to the control output means, and an operating state is established. On the other hand, when the power of the gaming machine is turned off, the supply of power by the power supply means is stopped, so even if the door body is opened and the door opening detection means is conducted, the control output means The electric power is not supplied from the power supply means and the vehicle is stopped. On the other hand, because the specifying output means is connected to the off-state operating means and the cathode terminal of the diode, when the door body is opened when the power of the gaming machine is turned on, the door opening detection means The power supply means is supplied to the specifying output means from the power supply means, and the operation state is set. When the power source of the gaming machine is turned off, the power supply by the power supply means to the specifying output means is stopped, but when the door body is opened and the door opening detecting means is turned on, the specifying operation is performed by the off-operation means. Since electric power is supplied to the output means, the specifying output means is in an operating state. Here, when the power source of the gaming machine is turned off and power is supplied from the off-operation means to the specifying output means, the power supply to the control output means can be cut off by the diode. Thereby, the consumption of the off-operation means during the power-off of the gaming machine can be suppressed. Therefore, it is possible to increase the number of times that the specifying output means can be operated and increase the number of times that the opening of the door body can be detected.

  In any one of the gaming machines C1 to C5, the door body includes an inner frame that is opened and closed with respect to the main body, and a transparent plate support door that is opened and closed with respect to the inner frame, and the door opening detection means includes: , An inner frame door opening detection means provided on the inner frame, and a transparent plate door opening detection means provided on the transparent plate support door, and the output means is provided by the inner frame door opening detection means. A first output means for outputting a detection result to the control means and executing a notification by the notification means when the opening of the inner frame is detected; and outputting the detection result to a specific device; and the transparent plate When the opening of the transparent plate support door is detected by the door opening detection means, the detection result is output to the control means, the notification by the notification means is executed, and the detection result is output to the specific device. With second output means Gaming machine C6, characterized by that.

  According to the gaming machine C6, when the power of the gaming machine is turned on and the control means is controlled, when the opening of the inner frame is detected by the inner frame door opening detection means, the detection result is the first. The output is output to the control means by one output means and the notification is executed by the notification means, and the detection result is output to the specific device by the first output means. Similarly, when the opening of the transparent plate support door is detected by the transparent plate door opening detection means when the power of the gaming machine is turned on, the detection result is output to the control means by the second output means. The notification by the notification unit is executed, and the detection result is output to the specific device by the second output unit. On the other hand, when the power of the gaming machine is turned off, the control of the control means is stopped. Even in this case, when the opening of the inner frame is detected by the inner frame door opening detection means, the detection is detected. The result is output to the specific device by the first output means. Similarly, when the power supply of the gaming machine is turned off and the opening of the transparent plate support door is detected by the transparent plate door opening detection means, the detection result is output to the specific device by the second output means. . As described above, the first output means for outputting the detection result when the inner frame is opened and the second output means for outputting the detection result when the transparent plate support door is opened are provided separately. Therefore, when either one or both of the inner frame and the transparent plate support door is opened, it is possible to determine which has been opened by the notification by the notification means and the specific device.

  In any one of the gaming machines C3 to C6, the specifying output means outputs a detection result to the specific device based on an output from the output period limiting means, and the output period limiting means includes the door opening detecting means When the opening of the door is detected by the above, an output to the specifying output means is performed during the predetermined period.

  According to the gaming machine C7, when the door opening detection means detects the opening of the door body, the detection result is output to the specific device by the specifying output means. Since the specifying output means operates by receiving power supply from the off-operation means while the gaming machine is turned off, the door opening detection means detects the opening of the door body even when the gaming machine is powered off. Then, the detection result can be output to the specific device. Therefore, for example, even if the door body is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be identified by the specific device.

  Moreover, one output period by the specifying output means is kept within a predetermined period by the output period limiting means. Similarly to the specifying output means, the output period limiting means operates by receiving power supply from the off-operation means while the gaming machine is turned off, so that the operating period of the specifying output means by one opening of the door body Can be kept within a predetermined period, and consumption of the off-operation means during the power-off of the gaming machine can be suppressed. Therefore, it is possible to increase the number of times that the specifying output means can be operated and increase the number of times that the opening of the door body can be detected.

  Further, to the output means for specifying that outputs the detection result to the specific device based on the output from the output period limiting means, the output period is limited during a predetermined period when the door opening detection is detected by the door opening detection means. Output is performed by means. Therefore, the output operation to the specifying output means by the output period limiting means can be stopped within a predetermined period for each opening of the door body. Therefore, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine, and increase the number of times that the specifying output means can be operated, thereby increasing the number of times that the door body can be detected.

  In the gaming machine C7, the output period limiting means stops the output to the specifying output means when the door opening detection means does not detect the opening of the door body.

  According to the gaming machine C8, the output of the output period limiting means to the specifying output means for outputting the detection result to the specific device is stopped when the door opening detection means does not detect the opening of the door body. Therefore, when the door opening detection means does not detect the opening of the door body, it is possible to suppress the power consumed by the output operation of the output period restriction means. Therefore, it is possible to suppress the consumption of the off-operation means during the power-off of the gaming machine, and increase the number of times that the specifying output means can be operated, thereby increasing the number of times that the door body can be detected.

  In any one of the gaming machines C3 to C8, the output period limiting means is configured using a monostable multivibrator, connected to the monostable multivibrator, and the door opening detection means opens the door body. And a period of time that is shorter than the predetermined period regardless of the opening time of the door body when the signal is detected. Machine C9.

  According to the gaming machine C9, the signal input to the output period limiting means using the monostable multivibrator is output once by the specifying output means by the input period adjusting means regardless of the door opening period. It is adjusted to be shorter than the predetermined period. Here, the monostable multivibrator continues to output a signal unless the input period of the input signal is shorter than the output period of the output signal. For this reason, when a monostable multivibrator is used as the output period limiting means, it is input to the output period limiting means beyond the output period of the output signal, that is, the predetermined period limited by the output period limiting means. The signal input period, that is, the door opening period must be short. However, since it is completely unpredictable how long the door opening period will be, in order to keep the door opening period always shorter than the predetermined period limited by the output period limiting means, It is necessary to set the period with a sufficient margin. For example, if the door opening period is predicted to be several tens of seconds to several minutes, the predetermined period limited by the output period restriction means is set from several minutes to several tens of minutes with sufficient margin. Must. Then, during this predetermined period, power is continuously supplied from the off-state operation means to the output period limiting means and the specifying output means, so that the consumption of the off-state operation means becomes significant. Therefore, a special circuit configuration is required to suppress the consumption of the off-operation means while using a monostable multivibrator as the output period limiting means. However, according to the gaming machine C9, the signal input to the output period limiting means can be adjusted to be shorter than the predetermined period by the input period adjusting means regardless of the door opening period. Therefore, the output period limiting means can be operated normally regardless of the door opening period, so that one output period by the specifying output means can be kept within a predetermined period by the output period limiting means. Thus, according to the gaming machine C9, by providing the input period adjusting means, the consumption of the operating means during the off state is suppressed, and the output is performed using the monostable multivibrator without adopting a special circuit configuration. Period limiting means can be realized.

  In any one of the gaming machines C1 to C9, the control means includes main control means for performing main control of the game, and the output means is mounted on the main control means. .

  In any one of the gaming machines C1 to C10, the output means is mounted on a different board from the control means.

  In any one of the gaming machines C1 to C11, the output means includes a photocoupler, and the detection result by the door opening detection means is output to the control means and the specific device by the output of the photocoupler. A gaming machine C12.

  In any one of the gaming machines C3 to C12, the output period limiting means and the specifying output means are configured to be operable even at a voltage lower than an operating voltage of the control means. Machine C13.

  According to the gaming machine C13, the output period limiting means and the specifying output means are configured to be operable even at a voltage lower than the operating voltage of the control means. Thus, even when the output voltage of the off-operation means becomes lower than the operation voltage of the control means, the output period limiting means and the specifying output means can be operated to report the opening of the door to the specific device. That is, it is possible to detect the opening of the door body for a long time when the gaming machine is powered off.

  In any one of the gaming machines C3 to C13, the output period limiting unit and the specifying output unit are configured such that the operable range voltage is wider than the operable range voltage of the control unit. Game machine C14.

  According to the gaming machine C14, the output period limiting means and the specifying output means are configured so that the operable range voltage is wider than the operable range voltage of the control means. Therefore, when the power of the gaming machine is turned off, the output period limiting means and the specifying output means can be operated for a long time by the off-time operating means. It can be carried out.

  In any one of the gaming machines C3 to C14, the output period limiting means is configured to include a C-MOS semiconductor.

  According to the gaming machine C15, the output period limiting means has a C-MOS semiconductor. Here, the C-MOS semiconductor generally has low power consumption during operation. Therefore, according to the gaming machine C15, it is possible to reduce the consumption of the off-operation means and detect the opening of the door body for a long time when the gaming machine is powered off.

  In any one of the gaming machines C9 to C15, the input period adjusting means is configured by using an integration circuit.

  According to the gaming machine C16, the input period adjusting means is configured by using the integration circuit, so that the signal input to the output period limiting means is adjusted to be shorter than the predetermined period without using a complicated circuit or signal processing. can do. Also, by adjusting the resistance value of the resistor used in the integrating circuit and the capacitance value of the capacitor, the input period of the signal input to the output period limiting means can be freely adjusted within a predetermined period.

  In any one of the gaming machines C9 to C16, the input period adjusting means includes constant voltage means for making the maximum voltage of a signal input to the monostable multivibrator as the output period limiting means constant. A gaming machine C17 to play.

  According to the gaming machine C17, since the constant voltage means is provided, the maximum voltage of the signal input to the output period limiting means is made constant, the signal input to the output period limiting means is stabilized, and the specific output One output period by means can be stably kept within a predetermined period.

  In addition, when the input period adjustment means is configured using an integration circuit, electric charge is stored in the capacitor used in the integration circuit, and the voltage due to this charge is superimposed on the signal input to the output period restriction means. There is a possibility that an overvoltage that can destroy the output period limiting means is applied to the output period limiting means. However, according to the gaming machine C17, since the maximum voltage of the signal input to the output period limiting unit is made constant by the constant voltage unit, an overvoltage that can destroy the output period limiting unit is not applied to the output period limiting unit. . Therefore, destruction of the output period limiting unit can be prevented.

  In the gaming machine C17, the constant voltage means is constituted by a Zener diode, the gaming machine C18.

  According to the gaming machine C18, since the constant voltage means is constituted by a Zener diode, it is input to the output period limiting means with a simple structure and at a lower cost than a constant voltage circuit constituted by a complicated circuit. The maximum signal voltage can be made constant. Therefore, the signal input to the output period limiting means is stabilized using a simple structure and an inexpensive Zener diode, and the output period of one output by the specifying output means is stably kept within a predetermined period, while outputting It is possible to prevent an overvoltage that can destroy the period limiting unit from being applied to the output period limiting unit.

  A gaming machine C19 according to any one of the gaming machines C1 to C18, wherein the gaming machine is a pachinko gaming machine.

  A gaming machine C20 according to any one of the gaming machines C1 to C18, wherein the gaming machine is a slot machine.

  Any of the gaming machines C1 to C18, wherein the gaming machine is a fusion of a pachinko gaming machine and a slot machine.

  A gaming machine comprising: a main body; a door body that opens and closes a front surface of the main body; and a control unit that is provided in a space formed by the door body and the main body and controls a game. A door opening detecting means for detecting the opening of the body, and an output means for outputting the detection result to a specific device when the door opening detecting means detects the opening of the door body, When the gaming machine is turned on and controlled by the control means, the detection result by the door opening detection means is output to the specific device, and the gaming machine is turned off and the control means The gaming machine C22 is configured to output a detection result by the door opening detection means to the specific device even when the control is not performed.

  According to the gaming machine C22, when the opening of the door body is detected by the door opening detection means when the power of the gaming machine is turned on and the control means is controlled, the detection result is specified by the output means. Output to the device. Therefore, for example, when the door is opened by an unauthorized act by someone during the opening of the store where the power of the gaming machine is turned on, the gaming machine with the door opened by the specific device can be determined. On the other hand, when the power of the gaming machine is turned off, control of the control means is stopped. In this case as well, when the door opening detection means detects the opening of the door body, the detection result is output. Is output to the specific device by the means. Therefore, even if the door is opened by an unauthorized act by someone after the store is closed with all the gaming machines turned off, the gaming machine with the door opened by the specific device can be determined. Therefore, regardless of whether the gaming machine is powered on or off, when the door is opened by an unauthorized act by somebody, the detection result is output to the specific device by one output means, and the game in which the door is opened The machine can be identified by a specific device.

  In any one of the gaming machines C1, C6, C10 to C12 or C19 to C22, a generating means for generating a signal output as the detection result from the output means, and the generating means of the gaming machine via a specific location A gaming machine C23, comprising: an on-supply supply means for supplying electric power while the power is on; and an off-supply supply means for supplying electric power to the specific location while the gaming machine is powered off.

  According to the gaming machine C23, while the gaming machine is powered on, power is supplied to the specific part of the generating means from the on-supplying means, while when the gaming machine is powered off, the power is supplied to the specific part of the generating means while being off. Power is supplied from the means. That is, power is supplied to the generating means regardless of the on / off state of the power supply of the gaming machine. Therefore, the generation means can generate a signal output as a detection result from the output means regardless of the on / off state of the power supply of the gaming machine.

  In the gaming machines C1 to C23, the pachinko machine 10 corresponds to the gaming machine, the outer frame 11 corresponds to the main body, the inner frame 12 and the front frame 14 correspond to the door body, and the transparent plate support A front frame 14 corresponds to the door. The main control device 110 corresponds to the control means and the main control means, the integration circuit 281 corresponds to the input period adjustment means, and an inner frame frame is included in a part of the output means and a part of the first output means. The opening detection circuit 290 corresponds, and the inner frame terminal board output circuit 290a corresponds to part of the output means and part of the output means for specification. Also, an inner frame input / output port output circuit 290b corresponds to a part of the output means and a part of the control output means, and a part of the output means, a part of the output means for specification, and one of the first output means. The external output terminal plate 291 for the inner frame corresponds to the part, the frame opening detection circuit 292 for the front frame corresponds to a part of the output means and a part of the second output means, and a part of the output means and for specification The front frame terminal board output circuit 292a corresponds to a part of the output means. Also, the front frame input / output port output circuit 292b corresponds to a part of the output means and a part of the control output means, and a part of the output means, a part of the specifying output means, and one of the second output means. The external output terminal plate 293 for the front frame corresponds to the part, the capacitor CD1 corresponds to the off-time operating means, and the Zener diode D3 corresponds to the constant voltage means. Further, the DC power source DC1 corresponds to the power source means, the timer IC1 corresponds to the output period limiting means, the photocoupler PR1 corresponds to a part of the output means, and a part of the door opening detection means and the inner frame The switch SW3 corresponds to the door opening detection means. Finally, the switch SW4 corresponds to a part of the door opening detection means and the transparent plate door opening detection means, and the processing of S904, S908, S1111, and S1113 corresponds to a part of the notification means.

  Needless to say, it is naturally possible to realize a gaming machine in which the above gaming machines A1 to A20, gaming machines B1 to B20, and gaming machines C1 to C23 are appropriately combined.

  In a gaming machine comprising a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing related to game control, door opening detection means for detecting the opening of the door body with respect to the main body, and Storage means for storing the opening detection of the door body by the door opening detection means, and when the opening of the door body is detected by the door opening detection means, the opening detection is stored based on the calculation processing of the calculation means. And when the door opening detection unit detects that the door is open while the gaming machine is powered off, the storage unit, the storage execution unit, and the calculation unit are activated for a predetermined period. The game machine D1 further comprises a startup unit that makes it possible to execute the storage of the release detection by the storage execution unit.

  According to the gaming machine D1, even when the power of the gaming machine is turned off and the computing means is stopped, if the door opening detection is detected by the door opening detecting means, the rising means is a storage means, The storage execution means and the calculation means are activated for a predetermined period of time, and the storage execution means can perform the detection of door opening detection. Thus, for example, even if the door body is opened due to an unauthorized act by someone after the store is closed with all the gaming machines turned off, the storage execution means stores the opening detection of the door body in the storage means. Can do. Therefore, it is possible to grasp the opening of the door even when the power of the gaming machine is turned off.

  In general, the calculation means is provided in a space formed by the door body and the main body. Furthermore, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side (including the back surface side of the main body) of the door body which cannot be touched by the hand when the door body is closed.

  The gaming machine D1 is provided with an off-operation means that is filled when the gaming machine is turned on and that enables the storage means, storage execution means, calculation means, and startup means to operate with the charged power. A gaming machine D2 characterized by this.

  According to the gaming machine D2, it is provided with the off-operation means that is filled when the gaming machine is powered on, and the storage means, the storage execution means, the calculation means, and the startup means are filled in the off-operation means. Operates with power. Therefore, the storage means, the storage execution means, the calculation means, and the start-up means can be operated even after the gaming machine is turned off.

  In the gaming machine D1 or D2, the start-up means is configured to store the storage means, the storage execution means, and the computing means when the door opening detection means detects that the door body is open while the gaming machine is powered off. An operation period determining means for setting the operation period as the first operation period, and when the first operation period determined by the operation period determining means is ended, the operation periods of the storage means, the storage execution means and the calculation means are set to the second operation period. An extension means for extending to an operation period, and the sum of a second operation period extended by the extension means and a first operation period determined by the operation period determination means is the predetermined period, The extending means is configured to be able to operate the storage means, the storage execution means, and the computing means with less power than the power consumed by the operation period determining means. .

  According to the gaming machine D3, when the first operation period determined by the operation period determining unit ends, that is, when the first operation period has elapsed, the extension unit stores the storage unit, the storage execution unit, and the calculation. The operation period of the means is extended to the second operation period. Here, the sum of the first operation period determined by the operation period determination unit and the second operation period extended by the extension unit is defined as a predetermined period during which the start-up unit starts up the storage unit, the storage execution unit, and the calculation unit. Yes. Therefore, of the predetermined period, the period during which the power charged in the off-operation means is consumed by the operation period determination means is kept in the first operation period, and thereafter the extension means that consumes less power than the operation period determination means. The storage means, the storage execution means, and the calculation means can be operated. Accordingly, it is possible to suppress the consumption of the electric power charged in the off-operation means, increase the operable number of times of the storage means, the storage execution means, the calculation means, and the rising means, and increase the number of detectable opening of the door body.

  In the gaming machine D3, the operation period determination unit is configured to store the storage unit, the storage execution unit, and the calculation unit when the door opening detection unit detects opening of the door body in a period shorter than the first operation period. The first operation period, which is an operation period of the first operation period, is set to the short operation period, and the extension unit is configured to store the storage unit, the storage execution unit, and the calculation unit after the short operation period determined by the operation period determination unit. The second operation period is extended to the second operation period, and the second operation period extended by the extension means is set to a period in which the storage execution means can perform the storage of the open detection. A gaming machine D4.

  According to the gaming machine D4, when the door opening detection unit detects the opening of the door body in a period shorter than the first operation period, the operation period determination unit operates the storage unit, the storage execution unit, and the calculation unit. The period is the short operation period. Then, after the end of the short operation period determined by the operation period determination unit, the extension unit extends the operation period of the storage unit, the storage execution unit, and the calculation unit to the second operation period. The second operation period is set to a period during which the storage execution means can store the door opening detection. Therefore, even if the door is opened within a short period, the detection of opening of the door can be reliably stored in the storage by the storage execution unit. In addition, when the door is opened within a short period, the period during which the power charged in the off-operation means is consumed by the operation period determination means can be kept short. Therefore, it is possible to suppress the consumption of the electric power charged in the off-operation means, increase the operable number of times of the storage means, the storage execution means, the calculation means, and the rising means, and increase the number of detectable opening of the door body. .

  In the gaming machine D3 or D4, the extension means operates when the operation period of the storage means, the storage execution means and the calculation means is within the first operation period determined by the operation period determination means. When the first operation period determined by the operation period determination unit is completed while being charged by the power supplied by the unit, the storage unit, the storage execution unit, and the calculation are performed by using the charged power. The gaming machine D5 is characterized in that power is supplied to the means and its operation period is extended to the second operation period.

  According to the gaming machine D5, when the operation period of the storage means, the storage execution means, and the calculation means is within the first operation period determined by the operation period determination means, the extension means is supplied by the off-time operation means. Filled with electric power. On the other hand, when the first operation period determined by the operation period determining means ends, the extension means supplies power to the storage means, the storage execution means, and the calculation means by using the charged power. Due to the power supply of the extension means, the operation periods of the storage means, the storage execution means, and the calculation means are extended to the second operation period. In this way, by reliably filling the extension means from the off-operation means, the extension means can reliably extend the operation period of the storage means, the storage execution means, and the calculation means to the second operation period. it can.

  In any one of the gaming machines D3 to D5, the arithmetic means inputs a driving voltage input means for inputting a driving voltage that enables the arithmetic means to start up and an operation signal that makes the arithmetic processing executable. Operating signal input means, and when the door opening detection means detects the opening of the door body while the gaming machine is powered off, the rising means is connected to the drive voltage input means. A drive voltage supply means for supplying a voltage, and an operation signal for outputting the operation signal to the operation signal input means when the opening of the door is detected by the door opening detection means while the gaming machine is powered off. Output means, and during the second operation period extended by the extension means, the operation signal output by the operation signal output means is stopped and then supplied by the drive voltage supply means. Gaming machine D6, characterized in that those stopping the driving voltage that.

  According to the gaming machine D6, when the door opening detection means detects the opening of the door body while the gaming machine is powered off, an operation signal is output from the operation signal output means of the start-up means to the operation signal input means of the arithmetic means. At the same time, the drive voltage is supplied from the drive voltage supply means of the rising means to the drive voltage input means of the calculation means. The rising means first stops the operation signal output by the operation signal output means during the second operation period extended by the extension means, and then drives the drive voltage supplied by the drive voltage supply means. To stop. Therefore, the calculation means is first set in a state where the calculation process cannot be performed, and then is lowered. Therefore, even if the door opening detection means detects the opening of the gaming machine while the gaming machine is turned off and the rising means starts the calculation means for a predetermined period, the calculation means is lowered during the second operation period. Can do.

  In the gaming machine D6, the calculation means is configured to be able to start up when the drive voltage input to the drive voltage input means is greater than or equal to a first value, and the operation signal output means is connected to the extension means. When connected and the voltage supplied by the extension means is greater than or equal to the second value exceeding the first value, the supplied voltage is output as the operation signal to the operation signal input means, When the voltage supplied by the extension means becomes less than the second value exceeding the first value, the operation signal output to the operation signal input means is stopped, and the drive voltage supply means is It is connected to the extension means and outputs the supplied voltage as the drive voltage to the drive voltage input means regardless of the voltage supplied by the extension means. Tricks machine D7.

  According to the gaming machine D7, the operation signal output means and the drive voltage supply means are both connected to the extension means. When the voltage supplied by the extension means is equal to or higher than the second value exceeding the first value, the operation signal output means of the start-up means uses the supplied voltage as the operation signal as an operation signal. Output to. On the other hand, the operation signal output means of the start-up means stops the operation signal output to the operation signal output means of the calculation means when the voltage supplied by the extension means is less than the second value. Unlike the operation of the operation signal output means, the drive voltage supply means outputs the supplied voltage as the drive voltage to the drive voltage input means of the calculation means regardless of the voltage supplied by the extension means. That is, even when the voltage supplied by the extension means becomes less than the second value, the drive voltage supply means continues to output the supplied voltage to the drive voltage input means of the calculation means as the drive voltage. Here, the calculation means is configured to be startable (operable) when the drive voltage input to the drive voltage input means is equal to or higher than the first value. Therefore, even if the drive voltage supplied from the drive voltage supply means of the start-up means to the drive voltage input means of the calculation means is less than the second value, if the drive voltage is greater than or equal to the first value, the calculation means is continuously started up. (Can continue to operate). As a result, the computing means is first set in a state in which the computation processing cannot be performed, and then lowered. Therefore, even if the door opening detection means detects the opening of the gaming machine while the gaming machine is turned off and the rising means starts the calculation means for a predetermined period, the calculation means can be lowered during the second period. it can.

  In a gaming machine comprising a main body, a door body that opens and closes the front surface of the main body, and arithmetic means that executes arithmetic processing related to game control, door opening detection means that detects the opening of the door body with respect to the main body, Storage means capable of holding the detection of opening of the door body by the door opening detection means even when the gaming machine is turned off, and opening of the door body is detected by the door opening detection means while the gaming machine is turned off. The storage means and the calculation means within a predetermined period, and an off-operation means for supplying power to the startup means, and the calculation processing executed by the calculation means A gaming machine E1 comprising a storage execution process for causing the storage means to hold the detection of the opening of the door when the arithmetic means is started up by the upper means within a predetermined period.

  According to the gaming machine E1, even when the power of the gaming machine is turned off and the calculation means is finished, when the door opening detection is detected by the door opening detection means, the electric power supplied by the off-operation means is used. The start-up means starts up the storage means and the calculation means within a predetermined period. Then, the computing means started up within a predetermined period executes the storage execution process, and causes the storage means to hold the door body opening detection. Therefore, for example, even if the door is opened due to an unauthorized act by someone after the store is closed with all the gaming machines turned off, the detection of the opening of the door is stored by the storage execution process executed by the computing means. The means can be held. Therefore, it is possible to grasp the opening of the door even when the power of the gaming machine is turned off.

  In the gaming machine E1, the calculation process executed by the calculation means includes an end process for ending the started calculation means. The end process and the storage execution process are started by the calculation means by the start-up means. A gaming machine E2 that is configured to complete processing within a predetermined period.

  According to the gaming machine E2, even if the opening of the door is detected by the door opening detection means while the gaming machine is powered off and the calculation means is started up by the start-up means, the calculation means performs the storage execution process and the end. The processing can be completed within a predetermined period. Therefore, even if the door is opened while the power of the gaming machine is turned off, the detection of the opening of the door can be held in the storage means by the storage execution process, and the calculation means that has been started up for a predetermined period of time It can be terminated by a termination process.

  The gaming machine E1 or E2 includes detection signal receiving means for receiving a detection signal indicating detection of opening of the door body by the door opening detection means, and the rising means opens the door body by the door opening detection means. Is detected signal output means for outputting a detection signal to the detection signal receiving means, and when the door opening detection is detected by the door opening detection means while the gaming machine is powered off. Is configured to start up the storage unit, the calculation unit, the detection signal output unit, and the detection signal reception unit within a predetermined period, and the calculation unit receives the detection signal by the detection signal reception unit. In this case, the gaming machine E3 is characterized by executing the storage execution process.

  According to the gaming machine E3, when the opening of the door is detected by the door opening detection means while the gaming machine is powered off, the rising means includes the storage means, the calculation means, and the detection signal output means for outputting the detection signal. A detection signal receiving means for receiving the detection signal is activated within a predetermined period. Then, when the detection signal output from the detection signal output means is received by the detection signal receiving means, the calculation means executes a storage execution process to hold the door body open detection in the storage means. That is, the calculation means executes the storage execution process for the first time when the detection signal receiving means receives the detection signal after being started up by the start-up means within a predetermined period. Therefore, the storage execution process by the computing means can be executed for the first time only when the door is reliably opened while the gaming machine is powered off.

  The gaming machine E1 or E2 includes a timing means for timing the operation period of the computing means, and the start-up means is detected by the door opening detection means that the opening of the door is detected while the gaming machine is powered off. In this case, the storage unit, the calculation unit, and the timing unit are started up within a predetermined period, and the calculation unit has an operation period measured by the timing unit within a predetermined second period. However, when the termination process is executed, the storage execution process is executed assuming that the door is opened while the gaming machine is powered off. .

  According to the gaming machine E4, when the opening of the door is detected by the door opening detection means while the gaming machine is powered off, the start-up means counts the storage means, the calculation means, and the operation period of the calculation means. Is launched within a predetermined period. In the case where the calculation means performs the end process even though the operation period timed by the time measuring means is within the predetermined second period, the door body was opened while the gaming machine was turned off. The memory execution process is executed. In other words, the computing means executes the storage execution process for the first time when the termination process is executed within the second period after being started up by the rising means within a predetermined period. Therefore, the storage execution process by the arithmetic means can be executed for the first time only when it is determined that the door body is reliably opened while the gaming machine is powered off by the operation period timed by the time measuring means.

  The gaming machine E3 or E4 includes backup means capable of holding data even after the gaming machine is powered off, and the arithmetic processing executed by the arithmetic means determines whether the data held in the backup means is valid. When it is determined to be valid by the determination process and the determination process, the data stored in the backup unit is used to return to the state before the power is turned off, and the determination process is determined to be invalid. In this case, an initialization process for initializing data held in the backup unit is provided, and the start of reception of the detection signal by the detection signal reception unit or the start of the measurement of the operation period by the timing unit is performed by the return process or the initial stage. A gaming machine E5, which is performed immediately after the execution of any one of the processes.

  According to the gaming machine E5, when the opening of the door body is detected by the door opening detecting means while the power of the gaming machine is turned off, and the calculating means is started up within a predetermined period by the rising means, after the return process or the initial stage Immediately after the conversion processing, that is, as soon as various settings of the calculation means are completed, the detection signal reception means starts receiving the detection signal or the time measurement means starts timing. Therefore, when the door is opened while the gaming machine is turned off, the opening of the door can be immediately detected.

  In the gaming machine E5, the gaming machine E5 is provided with a reporting means for performing a notification when the opening detection of the door is held in the storage means by the storage execution process, and the reporting means is provided when the gaming machine is turned on. On the other hand, while the game machine is powered off, even when the door opening detection means detects the opening of the door body, the startup by the rising means is not executed. A gaming machine E6 characterized by being a thing.

  According to the gaming machine E6, the notification means is activated when the power of the gaming machine is turned on, and notifies if the detection of opening of the door body is held in the storage means. On the other hand, when the door is detected to be opened by the door opening detection means while the gaming machine is powered off, the notification means is not activated by the rising means (even by the rising means) Is never). In other words, the notification means is started up when the power of the gaming machine is turned on, but the opening of the door body is detected by the door opening detection means while the power of the gaming machine is turned off, and is calculated by the startup means. Even if the means is started up within a predetermined period, the start-up means is not started up. Therefore, for example, even if the door is opened by an unauthorized person after closing the store where all the gaming machines are turned off and the detection of the opening of the door is held in the storage by the storage execution process, the notification means No notification will be made. Accordingly, the storage means can be held without the knowledge of the fraudster that the door has been opened while the power of the gaming machine is off. In addition, if the gaming machine is turned on and the detection of the opening of the door body is held in the storage means, the notification means will notify the game machine that the door body has been opened while the gaming machine is powered off. Can be specified.

  In the gaming machine E6, the gaming machine E6 includes erasing means for setting the detection of opening of the door held in the storage by the storage execution process to a state that can be erased, and the detection of opening of the door held in the storage is performed. The erasure means sets the release detection to an erasable state, and erasure is executed when the gaming machine is turned on and the arithmetic means is started up. A gaming machine E7.

  According to the gaming machine E7, the detection of the opening of the door held in the storage means is set in a state in which the detection of the opening of the door is erasable by the erasing means, and the arithmetic means is turned on when the gaming machine is turned on. When it is launched, it is erased. That is, firstly, when the opening detection of the door body is set to a state that can be erased by the erasing means, and secondly, when the gaming machine is turned on and the arithmetic means is started up, it is held in the memory means for the first time. The detected door opening detection is erased. Therefore, once the door opening detection is held in the storage means, the door opening detection cannot be erased from the storage means unless the above procedure is followed. Therefore, when the detection of the opening of the door is held in the storage means, it is possible to make it difficult to erase the detection of the opening of the door by an unauthorized person.

  In any one of the gaming machines E1 to E7, the game machine includes an output unit that outputs a predetermined signal to a specific device based on a calculation process of the calculation unit, and the rising unit is configured to open the door body by the door opening detection unit. When detected while the gaming machine is powered off, the output means is started up within a predetermined period, and the calculation process executed by the calculation means is the detection of opening of the door by the storage execution process. An output process for causing the output means to output detection of opening of the door as a predetermined signal when held in the storage means, and the output process is performed within a predetermined period during which the arithmetic means is started up by the rising means. A gaming machine E8 that is configured to complete the process.

  According to the gaming machine E8, when the door opening detection means detects the opening of the door body while the power of the gaming machine is turned off, the start-up means raises the output means within a predetermined period in addition to the storage means and the calculation means. . Then, the computing means started up within a predetermined period executes an output process, and causes the output means to output detection of opening of the door as a predetermined signal. Here, the predetermined signal is output to the specific device. Therefore, for example, even if the door body is opened due to an unauthorized act by somebody after the store is closed with all the gaming machines turned off, the gaming machine with the door body opened can be determined by the specific device. .

  In addition, a predetermined signal output from output means provided for each of a plurality of gaming machines may be received by one specific device, or a specific device is provided for each gaming machine, and the specific device is provided to each gaming machine. It may be arranged. When a specific device is installed in each gaming machine, the box base and the box cover covering the opening of the box base are connected to each other, and the specific device is specified in the space formed by the box cover and the box base. Store the device. Then, the box cover and the box base are connected by the sealing unit so that they cannot be opened. Further, a seal seal is attached to the connecting portion between the box cover and the box base over the box cover and the box base. In addition, a specific device may be disposed on the back surface or the back surface side of the door body.

  In a gaming machine comprising a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing related to game control, door opening detection means for detecting the opening of the door body with respect to the main body, and A gaming machine F1 comprising: a calculation start-up means for starting up the calculation means for a predetermined period when the door opening detection means detects the opening of the door body while the gaming machine is powered off. .

  According to the gaming machine F1, even when the power of the gaming machine is turned off and the calculation means is stopped, if the door opening detection is detected by the door opening detection means, the calculation start-up means Is launched for a predetermined period. Therefore, the computing means that has been started up for a predetermined time can be used, for example, to store the detection of door opening or to output the door opening detection to a specific device (specific device). it can.

  In a gaming machine comprising a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing related to game control, door opening detection means for detecting the opening of the door body with respect to the main body, and When the opening of the door is detected by the door opening detection means while the gaming machine is turned off, the calculation start-up means for starting up the calculation means for a predetermined period, and the calculation started by the calculation start-up means An gaming machine G1 comprising: output means for outputting detection of opening of the door body to a specific device based on arithmetic processing of the means.

  According to the gaming machine G1, even when the power of the gaming machine is turned off and the calculation means is stopped, if the door opening detection is detected by the door opening detection means, the calculation startup means Launched for a predetermined period. Then, based on the calculated calculation process of the calculation means, the output means outputs the door body opening detection to the specific device. Therefore, for example, even if the door is opened due to an unauthorized act by someone after the store is closed with all the gaming machines turned off, the detection of the opening of the door can be output to the specific device. Therefore, it is possible to grasp the opening of the door even when the power of the gaming machine is turned off.

  Needless to say, it is naturally possible to realize a gaming machine in which the gaming machines D1 to D7, the gaming machines E1 to E8, the gaming machine F1, and the gaming machine G1 are appropriately combined.

  In the above gaming machines D1 to D7, gaming machines E1 to E8, gaming machines F1 and gaming machines G1, the pachinko machine 10x corresponds to the gaming machine, the outer frame 11x corresponds to the main body, and the door body includes The inner frame 12 and the front frame 14 correspond. Further, the main control device 110x corresponds to the calculation means, the MPU 201x corresponds to the drive voltage input means and the operation signal input means, and the RAM 203x corresponds to the backup means. The storage means corresponds to the RAM 203x and the off-frame open flag 203ax, and the start-up means, drive voltage supply means, operation signal output means, and detection signal output means correspond to the frame open detection circuit 260x, The means corresponds to a capacitor CD1x. Further, the capacitor CD4x corresponds to the extension means, the timer IC 1x corresponds to the operation period determination means, and the processing of S112x and S226x corresponds to the storage execution means and the storage execution processing. Further, the switch SW1x and the switch SW2x correspond to the door opening detecting means, the RAM erasing switch 122x corresponds to the erasing means, and the power-on counter 203cx corresponds to the timing means. Further, the input / output port 205x corresponds to the detection signal receiving means and the output means, the sound output device 226x and the lamp display device 227x correspond to the notification means, and the processing of S107x corresponds to the determination processing. Finally, the process of S108x corresponds to the return process, the process of S116x corresponds to the initialization process, the process of S206x corresponds to the output process, and the processes of S221x to S224x correspond to the end process.

It is a front view of a pachinko machine. It is a front view of the game board of a pachinko machine. It is a rear view of a pachinko machine. It is a perspective view of the pachinko machine in the state where an inner frame, a front frame, and a lower plate unit were opened. It is the figure which showed the structure of the switch. It is a block diagram which shows the electric constitution of a pachinko machine. It is the block diagram which showed the electrical structure of the frame open detection circuit and the external output terminal board. 6 is a timing chart showing the relationship between the state of the inner frame, the state of the front frame, the TRG terminal voltage of the timer, the OUT terminal voltage of the timer, and the output of the external output terminal plate. (A) is the figure which showed typically the area division setting and effective line setting of the display screen, (b) is the figure which illustrated the actual display screen. It is a figure which shows the outline | summary of various counters. 3 is a flowchart showing start-up processing executed by an MPU 201 in the main control device 110. It is a flowchart which shows the main process performed by MPU in a main controller. It is a flowchart which shows the fluctuation | variation process performed in a main process. It is the flowchart which showed the change start process performed in a change process. It is a flowchart which shows a timer interruption process. It is a flowchart which shows the start winning process performed in a timer interruption process. It is a flowchart which shows a NMI interruption process. It is the block diagram which showed the electrical structure of the frame open detection circuit of 2nd Embodiment. It is the timing chart which showed the state of the state of the inner frame 12, the state of the front frame 14, the voltage of A of the frame open | release detection circuit of 2nd Embodiment, and the output of an external output terminal board. It is the block diagram which showed the electrical structure of the frame open detection circuit of 3rd Embodiment. It is the timing chart which showed the state of the state of an inner frame, the state of a front frame, the TRG terminal voltage of the timer of 3rd Embodiment, the OUT terminal voltage of the timer of 3rd Embodiment, and the output of an external output terminal board. It is a perspective view of the pachinko machine of a 4th embodiment in the state where an inner frame, a front frame, and a lower plate unit were opened. It is sectional drawing of switch SW3 used for the pachinko machine of 4th Embodiment. It is a block diagram which shows the electrical structure of the pachinko machine of 4th Embodiment. It is the block diagram which showed the electrical structure of the frame open detection circuit for inner frames, and the external output terminal board for inner frames. Power supply state of pachinko machine of the fourth embodiment, state of switch SW3-1 and switch SW3-2, timer TRG terminal voltage, timer OUT terminal voltage, output of inner frame external output terminal plate, and inner frame 4 is a timing chart showing the relationship of the output of the input / output port output circuit. It is the flowchart which showed the main process performed by MPU in the main control apparatus of 4th Embodiment. It is the flowchart which showed the timer interruption process performed by MPU in the main controller of 4th Embodiment. It is the flowchart which showed the starting process performed by MPU in the audio lamp control apparatus of 4th Embodiment. It is the flowchart which showed the main process performed by MPU in the audio lamp control apparatus of 4th Embodiment. It is the flowchart which showed the door opening alerting | reporting process performed by MPU in the audio | voice lamp control apparatus of 4th Embodiment. It is the flowchart which showed the main process performed by MPU in the display control apparatus of 4th Embodiment. It is the flowchart which showed the external interruption process performed by MPU in the display control apparatus of 4th Embodiment. It is sectional drawing of switch SW3A used for the pachinko machine of 5th Embodiment. It is the block diagram which showed the electrical structure of the frame open detection circuit for inner frames and the external output terminal board for inner frames used for the pachinko machine of 5th Embodiment. Power supply state, inner frame state, switch SW3-3 state, switch SW3-1 and switch SW3-2 state, voltage applied to capacitor CD7, timer TRG terminal voltage, 6 is a timing chart showing the relationship between the OUT terminal voltage of the timer, the output of the inner frame external output terminal plate, and the output of the inner frame input / output port output circuit. It is a front view of the pachinko machine of a 6th embodiment. It is a front view of the game board of the pachinko machine of 6th Embodiment. It is a rear view of the pachinko machine of a 6th embodiment. It is a perspective view of the pachinko machine of a 6th embodiment in the state where an inner frame, a front frame, and a lower plate unit were opened. It is the figure which showed the structure of the switch of 6th Embodiment. It is a block diagram which shows the electric constitution of the pachinko machine of 6th Embodiment. It is the circuit diagram which showed the electrical constitution of the frame open detection circuit of 6th Embodiment. State of inner frame, state of front frame, timer TRG terminal voltage, timer OUT terminal voltage, capacitor CD4x voltage, power supply output terminal voltage of frame open detection circuit, frame open of pachinko machine of sixth embodiment It is the timing chart which showed the relationship between the voltage of the reset signal output terminal of a detection circuit, and the voltage of the electric power interruption signal output terminal of a frame open detection circuit. (A) is the figure which showed typically the area division setting and effective line setting of the display screen, (b) is the figure which illustrated the actual display screen. It is a figure which shows the outline | summary of the various counters of the pachinko machine of 6th Embodiment. It is a flowchart which shows the starting process performed by MPU201x in the main control apparatus 110x of the pachinko machine of 6th Embodiment. It is a flowchart which shows the main process performed by MPU in the main control apparatus of the pachinko machine of 6th Embodiment. It is a flowchart which shows the fluctuation process performed in the main process of the pachinko machine of 6th Embodiment. It is the flowchart which showed the change start process performed in the change process of the pachinko machine of 6th Embodiment. It is a flowchart which shows the timer interruption process of the pachinko machine of 6th Embodiment. It is a flowchart which shows the start winning process performed in the timer interruption process of the pachinko machine of 6th Embodiment. It is a flowchart which shows the NMI interruption process of the pachinko machine of 6th Embodiment. It is the flowchart which showed the starting process performed by MPU in the audio | voice lamp control apparatus of the pachinko machine of 6th Embodiment. It is the flowchart which showed the main process performed by MPU of the audio | voice lamp control apparatus of the pachinko machine of 6th Embodiment. It is the flowchart which showed the door opening alerting | reporting process performed by MPU of the audio | voice lamp control apparatus of the pachinko machine of 6th Embodiment. It is the flowchart which showed the starting process performed with MPU in the main control apparatus of the pachinko machine of 7th Embodiment. It is a flowchart which shows the timer interruption process performed with MPU in the main control apparatus of the pachinko machine of 7th Embodiment. It is a flowchart which shows the main process performed with MPU in the main control apparatus of the pachinko machine of 7th Embodiment. It is the flowchart which showed the starting process performed with MPU in the main control apparatus of the pachinko machine of 8th Embodiment. It is the flowchart which showed the main process performed with MPU in the main control apparatus of the pachinko machine of 8th Embodiment. It is a block diagram which shows the electric constitution of the pachinko machine of 9th Embodiment. It is the flowchart which showed the main process performed with MPU in the main control apparatus of the pachinko machine of 9th Embodiment. It is the flowchart which showed the door command transmission process performed with MPU in the main control apparatus of the pachinko machine of 9th Embodiment. It is the flowchart which showed the main process performed with MPU in the audio | voice lamp control apparatus of the pachinko machine of 9th Embodiment. It is the flowchart which showed the external interruption process performed with MPU in the audio | voice lamp control apparatus of the pachinko machine of 9th Embodiment. It is the flowchart which showed the door opening alerting | reporting process performed with MPU in the audio | voice lamp control apparatus of the pachinko machine of 9th Embodiment.

Explanation of symbols

10 Pachinko machines (game machines)
11 Outer frame (main body)
12 Inner frame (part of door)
14 Front frame (transparent plate support door, part of door)
110 Main control device (part of control means, main control means)
281 Integration circuit (input period adjustment means)
290 Inner frame open frame detection circuit (part of output means, part of first output means)
290a Inner frame terminal board output circuit (part of output means, part of specifying output means)
290b I / O port output circuit for inner frame (part of output means, part of control output means)
291 External output terminal board for inner frame (part of output means, part of output means for specification, part of first output means)
292 Front frame opening detection circuit (part of output means, part of second output means)
292a Front frame terminal board output circuit (part of output means, part of output means for specification)
292b I / O port output circuit for front frame (part of output means, part of control output means)
293 External output terminal board for front frame (part of output means, part of output means for specification, part of second output means)
CD1 capacitor (operating means while off)
D1 Diode D3 Zener diode (constant voltage means)
DC1 DC power supply (power supply means)
IC1 timer (output period limiting means)
PR1 Photocoupler (part of output means)
SW3 switch (part of door opening detection means, door opening detection means for inner frame)
SW4 switch (part of door opening detection means, transparent plate door opening detection means)
S904, S908 Door open notification process (part of the notification means)
S1111, S1113 External interrupt processing (part of notification means)

Claims (5)

A main body, a door body for opening and closing the front surface of the main body, a control means for controlling a game provided in a space formed by the door body and the main body, and an informing means for informing by control of the control means In a gaming machine equipped with
Door opening detection means for detecting the opening of the door body with respect to the main body;
When the door opening detection means detects the opening of the door body, an output means for outputting the detection result to the control means to execute notification by the notification means and outputting the detection result to a specific device. With
The output means is
When the power of the gaming machine is turned on and control by the control means is performed, the detection result by the door opening detection means is output to the specific device,
A game configured to output the detection result by the door opening detection means to the specific device even when the power of the gaming machine is turned off and the control by the control means is not performed. Machine. Power supply means for supplying power to the output means to operate when the power of the gaming machine is on;
Provided separately from the power supply means, provided with an off-operation means for operating the gaming machine by supplying power to the output means when the gaming machine is powered off,
The output means includes
An output means for control that operates by electric power supplied from the power supply means and outputs a detection result by the door opening detection means to the control means;
2. A specifying output unit that operates by electric power supplied from the power source unit or the off-state operating unit and outputs a detection result by the door opening detection unit to the specific device. Game machines. An output period limiting means for keeping one output period by the specifying output means within a predetermined period;
The gaming machine according to claim 2, wherein the off-time operating means is configured to operate by supplying power to the output period limiting means in addition to the specifying output means.   4. The gaming machine according to claim 2, wherein the off-operation unit is configured to be rechargeable by electric power supplied from a power source of the gaming machine. Comprising a diode for passing a current supplied from the power supply means in one direction;
The off-operation means is configured using a capacitor or a secondary battery,
The door opening detection means is configured to be turned on when the door body is opened, and to be blocked when the door body is closed,
The power supply means is connected to the anode terminal of the diode;
The cathode terminal of the diode is connected to one end of the operating means during the off state,
The other end of the operating means during the off-state is grounded,
The control output means is connected to the power supply means and the anode terminal of the diode via the door opening detection means,
5. The game according to claim 2, wherein the specifying output means is connected to a cathode terminal of the diode and one end of the off-operation means via the door opening detection means. Machine.

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