JP2020108834A - Game machine - Google Patents

Abstract

To provide a game machine capable of grasping the opening of a door body in the case where the door body is opened while the electric power source of the game machine is off.SOLUTION: If an off-state frame opening flag 203a is on, an off-state frame opening command is transmitted to a voice/lamp control device 113 during startup processing, and a pulse signal whose pulse width is approximately 1 millisecond is output to a hall computer 262 thereafter. Accordingly, if an inner frame 12 or a front frame 14 is opened while a power of the Pachinko game machine is off, a frame opening detection circuit 260 immediately recognizes that an MPU 201 has been temporarily started up when the power of the Pachinko game machine is turned on next time.SELECTED DRAWING: Figure 26

Description

The present invention relates to a gaming machine represented by a pachinko machine, a spinning drum type gaming machine (for example, a slot machine), or a spinning drum type gaming machine using a game ball.

In the pachinko machine, when a ball hit in the game area enters the symbol working opening, a lottery is performed at the timing of the entrance. In a spinning machine using a slot machine or a game ball, when the start lever is operated, a lottery is performed at the timing of the operation. As a result of the lottery, for example, when a big hit is reached, a large amount of prize balls and coins can be paid out. Since the control for determining the lottery and the big hit is performed by the main control device, the main control device is likely to be the target of fraudulent activity.

Specific fraudulent acts include, for example, replacing the main control device with a fraudulent one that frequently causes jackpots, or connecting a fraudulent board (eg, "hanging board") to the main control device Are illegally generated. Further, in the case of a pachinko machine, there is also an illegal act in which a nail that is driven on the surface of the game board is illegally bent to make it easier for the ball to enter the winning opening or the symbol operating opening.
In the case of a pachinko machine, the main controller is mounted on the back surface of the game board. A frame body is provided on the back surface of the game board, and an inner frame on which the game board is mounted is provided on the front surface of the frame body. The inner frame can be opened and closed with respect to the frame body. A glass frame is provided on the front surface of the inner frame, and the glass frame can be opened and closed with respect to the inner frame. Therefore, if a cheating person commits a cheating on the game board surface or the main control device, the inner frame or the glass frame must be opened, but if the inner frame or the glass frame is opened, the Opening is detected by the sensor, and it is notified to the hall computer that manages the amusement hall.Also, by notifying the outside that the inner frame or the glass frame is opened by lighting the lamp or outputting audio, which pachinko machine It is possible to easily grasp whether or not a fraudulent act has been performed.

JP 2001-198332 A

However, when a fraudster invades, for example, at midnight after the amusement park is closed, and the intruder opens the inner frame or the glass frame and conducts a fraudulent act, the power of the pachinko machine is cut off at that time. Since the pachinko machine is stopped, the opening of the inner frame or the glass frame cannot be detected, and it is very difficult to grasp the opening.

The present invention has been made to solve the above-described problems and the like, and makes it possible to grasp the opening of a door when the door is opened while the power of the gaming machine is off. It is intended to provide a game machine capable of playing.

In order to achieve this object, the gaming machine according to claim 1, a main body, a door body for opening and closing the front surface of the main body, a main arithmetic means for executing arithmetic processing relating to game control, and an output from the main arithmetic means. A sub-computing means for performing a computation process relating to the control of the electric device based on the signal, and the main computing means, the sub-computing means and a power supply means for supplying driving power to the electric device, Door opening detection means for detecting opening of the door body with respect to the main body, and holding means capable of holding detection of opening of the door body by the door opening detection means even when drive power from the power supply means is not supplied. And when the opening of the door body is detected by the door opening detection means when the drive power from the power supply means is not supplied, the holding means and the main calculation means are activated for a predetermined period, and the door body is opened. Means for holding the opening detection in the holding means, and the rising means when drive power from the power supply means is not supplied and opening of the door body is detected by the door opening detection means. An off-state operating means for supplying drive power to the holding means and a holding means for holding detection of opening of the door body when drive power is supplied to the main computing means, the sub computing means and the electric device by the power supply means. An output unit that outputs a predetermined signal according to the holding state is provided. The main calculation means is generally provided in the space formed by the door body and the main body. Further, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side (including the back surface side of the main body) of the door body that cannot be touched when the door body is closed.

The gaming machine according to claim 2 is the gaming machine according to claim 1, wherein the main calculation means is executed once when drive power is supplied from the power supply means, and its start-up processing. The second predetermined signal is output from the output unit to the sub-calculation unit according to the normal process that is executed later and repeatedly executes a plurality of calculation processes and the holding state of the holding unit that holds the opening detection of the door body. An output control process is provided, the output control process is executed in the startup process, and then the normal process is performed.

The gaming machine according to claim 3 is the gaming machine according to claim 1 or 2, wherein the main computing means is provided separately from the main computing means, and a specific device for detecting an operating state of the gaming machine and an electric machine are provided. The opening means of the holding means when the opening of the door body is detected by the door opening detection means when the drive power from the power supply means is not supplied. The third output means for outputting the third predetermined signal to the specific device according to the holding state is started for a predetermined period. The electrical connection between the main processing means and the specific device means that the main processing means and the specific device are connected by a signal line, or an input/output port composed of a latch circuit or the like. It also includes the case of connecting via wireless communication and the case of connecting via wireless communication.

According to a fourth aspect of the present invention, in the gaming machine according to the third aspect, the main calculation means is specified by the third output means according to a holding state of a holding means that holds detection of opening of the door body. A third output control process for outputting a third predetermined signal to the apparatus is provided, the third output control process is executed in the startup process, and then the normal process is performed.

According to the gaming machine of claim 1, even when the driving power is not supplied from the power supply means to the main calculation means, the sub calculation means and the electric device, the opening of the door body is detected by the door opening detection means. The rising means starts up the holding means and the main calculation means for a predetermined time by the driving power supplied by the off-time operating means, and causes the holding means to hold the door opening detection. Then, when the driving power is supplied from the power supply means to the main calculation means, the sub calculation means and the electric device, the output means outputs a predetermined signal according to the holding state of the holding means. Therefore, for example, even if the door body is opened by a fraudulent act by somebody after the store is closed when the driving power is not supplied by the power source means in all gaming machines, the opening of the door body is held and the power source means is used. A predetermined signal can be output when drive power is supplied. Therefore, there is an effect that it is possible to grasp the opening of the door body performed when the driving power by the power supply means is not supplied, that is, when the power of the gaming machine is turned off.

According to the gaming machine of the second aspect, in addition to the effect of the gaming machine of the first aspect, the output means transfers the secondary operation means to the sub-calculation means according to the holding state of the holding means that holds the detection of opening the door. The output control processing for outputting the predetermined signal is executed within the startup processing of the main calculation means that is executed once when the driving power is supplied from the power supply means. In this way, when the driving power is supplied from the power supply means, the output control processing is immediately executed and the second predetermined signal is output to the sub-calculation means, so that it is performed when the power of the gaming machine is off. There is an effect that the opening of the opened door can be immediately grasped by the sub calculation means. When the second predetermined signal is output to the sub-calculation unit, the sub-calculation unit controls, for example, the electric device to give a notification. Further, since the output control processing is executed within the startup processing of the main processing means, it is possible to make the output control processing non-executable in the normal processing in which a plurality of arithmetic processings are repeatedly executed. ..

According to the gaming machine of claim 3, in addition to the effect of the gaming machine of claim 1 or 2, the opening of the door body is detected by the door opening detection means when the drive power from the power supply means is not supplied. Then, the rising means starts the third output means for a predetermined time. Then, the third output means outputs the third predetermined signal to the specific device in accordance with the holding state of the holding means that holds the detection of opening the door. Therefore, when the drive power from the power supply means is not supplied, that is, when the opening of the door body is detected by the door opening detection means when the power supply of the gaming machine is turned off, at that time, The specific device has an effect of being able to grasp the opening of the door body performed while the power of the game machine is turned off.
According to the gaming machine of claim 4, in addition to the effect of the gaming machine of claim 3, according to the holding state of the holding means for holding the opening detection of the door body, the third output means to the specific device. The third output control processing for outputting the three predetermined signals is executed within the startup processing of the main calculation means that is executed once when the driving power is supplied from the power supply means. In this way, when the driving power is supplied from the power supply means, the third output control process is immediately executed and the third predetermined signal is output to the specific device. Therefore, when the power of the gaming machine is off. There is an effect that the opening of the door body that has been performed can be immediately grasped by the specific device. Further, since the third output control processing is executed in the startup processing of the main processing means, it is possible to make the third output control processing non-executable in the normal processing in which a plurality of arithmetic processings are repeatedly executed. There is an effect.

It is a front view of a pachinko machine. It is a front view of the game board of the pachinko machine. It is a rear view of a pachinko machine. It is a perspective view of a pachinko machine in a state where an inner frame, a front frame, and a lower plate unit are opened. It is the figure which showed the structure of the switch. It is a block diagram which shows the electric constitution of a pachinko machine. It is a circuit diagram showing an electrical configuration of a frame open detection circuit. Inner frame state, front frame state, timer TRG terminal voltage, timer OUT terminal voltage, capacitor CD4 voltage, frame open detection circuit power supply output terminal voltage, frame open detection circuit reset signal output terminal 7 is a timing chart showing the relationship between the voltage and the voltage of the power failure signal output terminal of the frame open detection circuit. (A) is the figure which showed typically the area division setting and effective line setting of a display screen, (b) is the figure which illustrated the actual display screen. It is a figure which shows the outline of various counters. 7 is a flowchart showing a startup process executed by MPU 201 in main controller 110. It is a flow chart which shows the main processing performed by MPU in a main control unit. It is a flowchart which shows the fluctuation process performed in a main process. It is the flowchart which showed the fluctuation start processing which is executed in fluctuation processing. It is a flowchart which shows a timer interruption process. It is a flow chart which shows a starting winning a prize process performed in a timer interruption process. It is a flow chart which shows NMI interruption processing. It is the flowchart which showed the starting processing performed by MPU in a voice lamp control device. It is the flowchart which showed the main processing performed by MPU of a voice lamp control device. It is the flowchart which showed the door opening notification process performed by MPU of a voice lamp control device. It is the flowchart which showed the starting processing performed by MPU in the main controller of the pachinko machine of 2nd Embodiment. It is a flowchart which shows the timer interruption process performed by MPU in the main control device of the pachinko machine of 2nd Embodiment. It is a flow chart which shows the main processing performed by MPU in the main control device of the pachinko machine of a 2nd embodiment. It is the flowchart which showed the starting processing performed by MPU in the main controller of the pachinko machine of 3rd Embodiment. It is the flowchart which showed the main processing performed by MPU in the main control device of the pachinko machine of 3rd Embodiment. It is the flowchart which showed the starting processing performed by MPU in the main control device of the pachinko machine of 4th Embodiment. It is the flowchart which showed the main processing performed by MPU in the main control device of the pachinko machine of 4th Embodiment.

An embodiment of a pachinko gaming machine (hereinafter, simply referred to as "pachinko machine") will be described below with reference to the drawings. 1 is a front view of the pachinko machine 10, FIG. 2 is a front view of the game board 13 of the pachinko machine 10, and FIG. 3 is a rear view of the pachinko machine 10.

As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 in which an outer shell is formed by a wooden frame combined in a substantially rectangular shape, and an outer shape substantially the same as the outer frame 11 with respect to the outer frame 11. And an inner frame 12 that is openably and closably supported. To support the inner frame 12, metal hinges 18 are attached to the outer frame 11 at two upper and lower positions on the left side in front view (see FIG. 1), and the side on which the hinge 18 is provided serves as an opening/closing shaft. The frame 12 is supported openably and closably on the front side.

On the inner frame 12, a game board 13 (see FIG. 2) having a large number of nails, winning holes 63, 64, etc. is detachably mounted from the back side. A ball game is performed by the ball flowing down on the front surface of the game board 13. In addition, in the inner frame 12, a ball launching unit 112a (see FIG. 5) that launches a ball to the front area of the game board 13 and a launch that guides the ball launched from the ball launching unit 112a to the front area of the game board 13. Rails (not shown) and the like are attached.

On the front side of the inner frame 12, a front frame 14 that covers the upper side of the front and a lower plate unit 15 that covers the lower side thereof are provided. In order to support the front frame 14 and the lower plate unit 15, metal hinges 19 are attached at two upper and lower positions on the left side in a front view (see FIG. 1), and the side provided with the hinges 19 is used as an opening/closing shaft. The lower plate unit 14 and the lower plate unit 15 are supported openably and closably on the front side. The locking of the inner frame 12 and the locking of the front frame 14 are released by inserting a dedicated key into the keyhole 21 of the cylinder lock 20 and performing a predetermined operation.

The front frame 14 is assembled with a decorative resin component, an electrical component, and the like, and a window portion 14c having a substantially elliptical opening is provided at a substantially central portion thereof. A glass unit 16 having two glass plates is arranged on the back side of the front frame 14, and the front side of the game board 13 can be visually recognized on the front side of the pachinko machine 10 via the glass unit 16. An upper plate 17 for storing balls is formed in the front frame 14 in a substantially box-like shape having an open upper surface and protruding toward the front, and prize balls, rental balls, and the like are discharged to the upper plate 17. The bottom surface of the upper plate 17 is formed to be inclined downward to the right when viewed from the front (see FIG. 1), and the ball introduced into the upper plate 17 is guided to the ball firing unit 112a by the inclination. A frame button 22 is provided on the upper surface of the upper plate 17. The frame button 22 is operated by the player, for example, when changing the effect pattern of the variable display displayed on the third symbol display device 81 or when changing the effect contents during the reach effect.

In addition, the front frame 14 is provided with light emitting means such as various lamps around the front frame 14 (for example, a corner portion). These light emitting means change the light emitting mode by lighting or blinking according to the change of the game state at the time of a big hit or a predetermined reach, and play a role of enhancing the effect effect during the game. On the periphery of the window portion 14c, there are provided electric decoration portions 29 to 33 which incorporate a light emitting means such as an LED. In the pachinko machine 10, these illumination parts 29 to 33 function as a production lamp such as a jackpot lamp, and when a jackpot or a reach production is performed, each illumination portion 29 to 33 is turned on by turning on or blinking the built-in LED. Alternatively, it blinks to notify that the jackpot is in the midst of hitting, or that the reach is one step ahead of the jackpot.

Further, in the upper left portion of the front frame 14 when viewed from the front (see FIG. 1), a light emitting means such as an LED is provided, and a display lamp 34 capable of displaying during payout of a prize ball and when an error occurs is provided. In addition, a small window 35 is formed on the lower side of the right decorative portion 32 so that the back side of the front frame 14 can be visually recognized, and a small window 35 is formed. The certificate or the like attached to (see 2) is visible from the front of the pachinko machine 10. Further, in the pachinko machine 10, a plating member 36 made of ABS resin, which is plated with chrome, is attached to a region around the electric decorations 29 to 33 in order to bring out more brilliance.

A ball rental operation unit 40 is arranged below the window 14c. The ball lending operation unit 40 is provided with a frequency display unit 41, a ball lending button 42, and a return button 43. When the ball rental operation unit 40 is operated in a state where banknotes, cards, etc. are inserted into a card unit (ball lending unit) (not shown) arranged on the side of the pachinko machine 10, the ball is operated according to the operation. Lending is done. Specifically, the frequency display unit 41 is an area in which the balance information of a card or the like is displayed, and the built-in LED lights up to display the balance as a number as the balance information. The ball lending button 42 is operated to obtain a loan ball based on information recorded on a card or the like (recording medium), and the loan ball is supplied to the upper plate 17 as long as there is a balance on the card or the like. To be done. The return button 43 is operated when requesting return of a card or the like inserted in the card unit. It should be noted that the ball rental operation unit 40 is not necessary in a pachinko machine, which is a cash machine in which balls are lent directly to the upper plate 17 from a ball lending device or the like without using a card unit, but in this case, the ball rental operation unit 40 is used. It is also possible to add a decorative seal or the like to the installation portion of to make the parts configuration common. A pachinko machine using a card unit and a cash machine can be shared.

In the lower plate unit 15 located below the upper plate 17, a lower plate 50 for storing balls that cannot be stored in the upper plate 17 is formed in a central portion of the lower plate unit 15 in a substantially box shape with an open upper surface. There is. On the right side of the lower plate 50, an operation handle 51 operated by the player to drive the ball into the front surface of the game board 13 is provided, and inside the operation handle 51, the driving of the ball firing unit 112a is permitted. Sensor 51a for pressing, a push button type stop switch 51b for stopping the firing of the ball during the pressing operation, and a variable resistor for detecting the rotation operation amount of the operation handle 51 by the change of the electric resistance. (Not shown) and are built in. When the operation handle 51 is rotated clockwise by the player, the touch sensor is turned on and the resistance value of the variable resistor changes in accordance with the operation amount, and in accordance with the rotation operation amount of the operation handle 51. A ball is fired with a strength corresponding to the variable resistance value of the variable resistor, and thereby the ball is driven into the front surface of the game board 13 with a jump amount corresponding to the operation of the player. Further, when the operation handle 51 is not operated by the player, the touch sensor 51a and the stop switch 51b are off.

At the lower part of the front surface of the lower plate 50, a ball removing lever 52 for operating when the balls stored in the lower plate 50 are discharged downward is provided. This ball-pulling lever 52 is always biased to the right, and by sliding it to the left against the bias, the bottom opening formed on the bottom of the lower plate 50 opens, The sphere falls from the bottom opening and is discharged. The operation of the ball removing lever 52 is usually performed in a state in which a box (generally referred to as “thousand box”) for receiving the balls discharged from the lower plate 50 is placed below the lower plate 50. As described above, the operation handle 51 is arranged on the right side of the lower tray 50, and the ashtray 53 is attached on the left side of the lower tray 50.

As shown in FIG. 2, the game board 13 includes a wooden base plate 60 cut into a substantially square shape in a front view, a large number of nails for guiding balls, windmills and rails 61 and 62, a general winning opening 63, and a first winning opening 63. It is configured by assembling a ball entrance 64, a variable winning device 65, a variable display device unit 80, etc., and a peripheral portion thereof is attached to a back surface side of the inner frame 12. The general winning opening 63, the first winning opening 64, the variable winning device 65, and the variable display device unit 80 are arranged in through holes formed in the base plate 60 by router processing, and wood screws are applied from the front side of the game board 13. It is fixed by etc. Further, the central portion of the front surface of the game board 13 can be viewed from the front surface side of the inner frame 13 through the window portion 14c (see FIG. 1) of the front frame 14. The configuration of the game board 13 will be described below.

On the front surface of the game board 13, an outer rail 62 formed by bending a band-shaped metal plate into a substantially arc shape is planted. At the inner position of the outer rail 62, a band-shaped metal plate is formed like the outer rail 62. The arc-shaped inner rail 61 formed in step 1 is planted. The inner rail 61 and the outer rail 62 surround the outer periphery of the front surface of the game board 13, and the front and rear are surrounded by the game board 13 and the glass unit 16 (see FIG. 1), so that the front surface of the game board 13 has a ball. A game area in which a game is played is formed by the behavior of. The game area is a substantially circular area formed by partitioning the two rails 61 and 62 and the arc member 70 on the front surface of the game board 13 (where a winning opening or the like is provided, and a shot ball is It is the area that flows down.

The two rails 61 and 62 are provided to guide the ball fired from the ball firing unit 112a to the upper part of the game board 13. A return ball prevention member 68 is attached to the tip portion of the inner rail 61 (upper left portion in FIG. 2) to prevent the situation where the ball once guided to the upper part of the game board 13 returns to the ball guide passage again. To be done. At the tip of the outer rail 62 (upper right part in FIG. 2), a return rubber 69 is attached at a position corresponding to the maximum flight portion of the ball, and the ball launched with a momentum higher than a predetermined value hits the return rubber 69 to generate momentum. Is attenuated and bounces back toward the center. In addition, between the lower right end of the inner rail 61 and the upper right end of the outer rail 62, a resin arc member 70 formed by providing an arc connecting the rails on the inner surface side is a base. It is fixed by being driven into the plate 60.

A first symbol display device 37 provided with a plurality of LEDs 37a, which are light emitting means, and a 7-segment display 37b is disposed on the upper right side in the front view of the game area (upper right side in FIG. 2). The first symbol display device 37 is a display according to each control performed by the main control device 110, and mainly displays the gaming state of the pachinko machine 10. The plurality of LEDs 37a indicate whether the pachinko machine 10 is in a probability change, shortening time, or normal by a lighting state, indicate whether it is changing or not by a lighting state, and a stop symbol corresponding to a probability variation jackpot. Or, it is indicated by a lighting state whether it is a symbol corresponding to a normal jackpot or a deviating symbol, and the number of reserved balls is indicated by a lighting state. The 7-segment display device 37b is for displaying the number of rounds in a big hit and an error. The LEDs 37a are configured so that the light emission colors (for example, red, green, and blue) of the respective LEDs are different, and the combination of the light emission colors can suggest various game states of the pachinko machine 10 with a small number of LEDs. ..

In addition, the above-mentioned probability that the pachinko machine 10 is changing is a gaming state in which the jackpot probability increases and a special gaming state is likely to occur. Furthermore, during the probability change in the present embodiment, the probability of hitting the second symbol is increased, and the ball is easy to enter the first entrance 64. In addition, the pachinko machine 10 is in a game state in which it is easy for the ball to enter the first ball entrance 64 because the jackpot probability remains the same and only the second symbol hit probability increases. In addition, the pachinko machine 10 is in a normal state, which is a state of a game that is neither probable change nor time saving (a state in which neither the jackpot probability nor the winning probability of the second symbol is improved). It should be noted that, depending on the gaming state of the pachinko machine 10, the time for which the electric accessory (not shown) attached to the first ball inlet 64 is opened and the number of times the electric accessory is opened per one time are changed. Good as a thing.

Further, in the game area, a plurality of general winning openings 63 are provided in which 5 to 15 balls are paid out as prize balls when the balls are won. Further, a variable display device unit 80 is arranged in the center of the game area. In the variable display device unit 80, a third symbol display device 81 composed of a liquid crystal display (hereinafter simply referred to as “display device”) that variably displays the third symbol triggered by winning in the first ball entrance 64. And, a second symbol display device 82 including a light emitting diode (hereinafter, abbreviated as “LED”) that variably displays the second symbol with the passage of the sphere of the second ball entrance 67 as a trigger is provided. ..

The display content of the third symbol display device 81 is controlled by the display control device 114 described later, and, for example, three symbol columns of left, middle and right are displayed. Each symbol row is composed of a plurality of symbols, and these symbols are vertically scrolled for each symbol row so that the third symbol is variably displayed on the display screen of the third symbol display device 81. In addition, in the present embodiment, the third symbol display device 81 is composed of a large 8-inch liquid crystal display, and the variable display device unit 80 surrounds the outer periphery of the third symbol display device 81, and the center frame. 86 is provided. Third symbol display device 81 of the present embodiment, the display of the game state accompanied by the control of the main controller 110 is performed in the first symbol display device 37, the display of the first symbol display device 37 The decorative display is performed according to. Instead of the display device, for example, a reel or the like may be used to configure the third symbol display device 81.

In addition, when the ball enters the first ball entrance 64 until the stop symbol (one of the probability variation jackpot symbol, the ordinary jackpot symbol, and the deviation symbol) is displayed on the first symbol display device 37 The number of times the ball is entered is held up to a maximum of four times, and the number of times the ball is held is indicated by the first symbol display device 37 and the number of lights of the hold lamp 85. Four reserve lamps 85 are provided for the maximum reserve number, and are arranged symmetrically above the third symbol display device 81. In addition, in the present embodiment, the winning in the first entrance 64 is configured to be held up to 4 times, but the maximum number of holdings is not limited to 4 times, and 3 times or less. Alternatively, the number may be set to 5 times or more (for example, 8 times). In addition, the hold lamp 85 is deleted, and the number of times of variable display based on winning in the first entrance 64 is numerically displayed as a part of the third symbol display device 81, or an area divided into four is reserved. The display may be performed in a mode (for example, a color or a lighting pattern) different for the number of times. Further, since the number of times of holding is indicated by the first symbol display device 37, the holding lamp 85 may not perform the lighting display.

The second symbol display device 82 has a display unit 83 for the second symbol and a holding lamp 84, and each time the ball passes through the second entrance 67, as a display symbol (second symbol) on the display unit 83. The "○" symbol and the "X" symbol are alternately lit to perform a variable display, and when the variable display is stopped by a predetermined symbol ("○" symbol in the present embodiment), The 1 ball entrance 64 is configured to be activated (open) for a predetermined time. The number of times the ball has passed through the second entrance 67 is held up to a maximum of four times, and the number of times of holding is displayed by the first symbol display device 37 and the holding lamp 84 is also lit up. The variable display of the second symbol is performed by switching the lighting and non-lighting of a plurality of lamps on the display unit 83, as in the present embodiment, as well as the first symbol display device 37 and the third symbol display device. You may make it perform using a part of 81. Similarly, the holding lamp 84 may be turned on by a part of the third symbol display device 81. In addition, the maximum number of times of passing through the second entrance 67 is not limited to 4 as in the case of the first entrance 64, and is not more than 3 times or not less than 5 times (for example, (8 times). Further, since the number of times of holding is shown by the first symbol display device 37, the holding lamp 84 may not perform the lighting display.

Below the variable display device unit 80, a first ball entrance 64 into which a ball can enter is arranged. When a ball enters the first entrance 64, a first entrance switch (not shown) provided on the back side of the game board 13 is turned on, which is caused by turning on the first entrance switch. A lottery for the jackpot is made in the main controller 110, and a display corresponding to the lottery result is shown by the LED 37a of the first symbol display device 37. Further, the first ball entrance 64 is also one of the prize holes through which five balls are paid out as prize balls when the balls enter.

A variable winning device 65 is disposed below the first ball entrance 64, and a horizontally elongated rectangular specific winning opening (large opening) 65a is provided at a substantially central portion thereof. In the pachinko machine 10, when the lottery in the main controller 110 is a big hit, the LED 37a of the first symbol display device 37 is turned on so that a big hit stop pattern is lit after a predetermined time (variable time) has passed, and The stop symbol corresponding to the big hit is displayed on the third symbol display device 81, and the occurrence of the big hit is shown. After that, the game state transitions to a special game state (big hit) where the ball is easy to win. In this special game state, the specific winning opening 65a which is normally closed is opened for a predetermined time (for example, until 30 seconds elapse or 10 balls are won).

The specific winning opening 65a is closed after a predetermined time has passed, and after the closing, the specific winning opening 65a is opened again for a predetermined time. The opening/closing operation of the specific winning opening 65a can be repeated, for example, 16 times (16 rounds) at the maximum. The state in which this opening/closing operation is performed is one form of a special game state that is advantageous to the player, and the player is given a larger amount of prize balls than usual in order to give a game value (game value). Is done.

The variable winning device 65 is, specifically, a horizontally-long rectangular opening/closing plate that covers the specific winning opening 65a, and a large opening solenoid (not shown) for opening/closing the front side with the lower side of the opening/closing plate as an axis. It has and. The specific winning opening 65a is normally in a closed state in which the ball cannot be won or is difficult to win. At the time of a big hit, the large opening solenoid is driven to tilt the opening/closing plate to the lower side of the front surface to temporarily form an open state in which the ball easily wins the specific winning opening 65a, and the open state and the normal closing The state and the state operate alternately.

The special game state is not limited to the above-mentioned form. A large opening that is opened and closed separately from the specific winning opening 65a is provided in the game area, and when the LED 37a corresponding to the big hit on the first symbol display device 37 is turned on, the specific winning opening 65a is opened for a predetermined time, and the specific winning is achieved. A special game state is a game state in which a large opening provided separately from the specific winning opening 65a is opened for a predetermined time and a predetermined number of times when the ball wins into the specific winning opening 65a while opening the opening 65a. It may be formed.

Adhesive spaces K1 and K2 for adhering a certificate stamp, an identification label, etc. are provided in the left and right corners on the lower side of the game board 13, and the certificate stamp etc. affixed to the adhesive space K1 is the front frame 14 It can be seen through the small window 35 (see FIG. 1).

Further, the game board 13 is provided with an outlet 66. Balls that have not entered any of the winning openings 63, 64, 65a are guided to a ball discharge path (not shown) through the outlet 66. In the game board 13, a large number of nails are planted in order to appropriately disperse and adjust the falling direction of the balls, and various members (features) such as a wind turbine are arranged.

As shown in FIG. 3, control board units 90 and 91 and a back pack unit 94 are mainly provided on the back side of the pachinko machine 10. The control board unit 90 is a unit in which a main board (main control device 110), a voice lamp control board (voice lamp control device 113), and a display control board (display control device 114) are mounted. The control board unit 91 is unitized by mounting a payout control board (payout control device 111), a firing control board (firing control device 112), a power supply board (power supply device 115), and a card unit connection board 116.

The back pack unit 94 includes a back pack 92 forming a protective cover and a payout unit 93. In addition, each control board is used as an MPU as a one-chip microcomputer that controls each control, a port for communicating with various devices, a random number generator used in various lottery, time counting and synchronization. A clock pulse generating circuit and the like are installed as needed.

The main control device 110, the voice lamp control device 113 and the display control device 114, the payout control device 111 and the firing control device 112, the power supply device 115, and the card unit connection board 116 are housed in the board boxes 100 to 104, respectively. .. The board boxes 100 to 104 each include a box base and a box cover that covers an opening of the box base. The box base and the box cover are connected to each other to house each control device and each board.

Further, in the board box 100 (main controller 110) and the board box 102 (payout controller 111 and launch controller 112), a box base and a box cover are connected in an unopenable manner by a sealing unit (not shown) (caulking structure). (Consolidated by). In addition, a sealing seal (not shown) is attached to the connecting portion between the box base and the box cover, extending over the box base and the box cover. The seal sticker is made of a brittle material, and if the seal sticker is peeled off to open the board boxes 100 and 102, or if the board boxes 100 and 102 are forcibly opened, the box base side and the box cover are closed. To be cut into sides. Therefore, by checking the sealing unit or the sealing sticker, it is possible to know whether the substrate boxes 100 and 102 have been opened.

The payout unit 93 is located at the uppermost part of the back pack unit 94 and opens upward, a tank rail 131 connected below the tank 130 and gently inclined toward the downstream side, and a downstream side of the tank rail 131. A case rail 132 that is vertically connected to the side, and a payout device 133 that is provided at the most downstream portion of the case rail 132 and that pays out balls by a predetermined electrical configuration of the payout motor 216 (see FIG. 5). ing. The tank 130 is sequentially replenished with balls supplied from the island facility of the game hall, and the required number of balls are paid out by the payout device 133 as appropriate. A vibrator 134 for applying vibration to the tank rail 131 is attached to the tank rail 131.

The payout control device 111 is provided with a state return switch 120, the firing control device 112 is provided with a variable resistor operation knob 121, and the power supply device 115 is provided with a RAM erase switch 122. The state return switch 120 is operated to eliminate the ball clogging (return to the normal state) when a dispensing error occurs, such as a ball clogging of the dispensing motor 216 (see FIG. 4). The operation knob 121 is operated to adjust the firing force of the firing solenoid. The RAM erase switch 122 is operated when the power is turned on when it is desired to return the pachinko machine 10 to the initial state.

Next, an internal configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 4 is a perspective view of the pachinko machine 10 in a state where the inner frame 12, the front frame 14, and the lower plate unit 15 are opened.

The pachinko machine 10 is provided with an outer frame 11 forming an outer shell thereof, and an inner frame 12 is supported to the outer frame 11 so as to be openable and closable. In the game arcade, the outer peripheral surface of the outer frame 11 is fixed to an installation place called an island in the game arcade. The inner frame 12, the front frame 14, and the lower plate unit 15 are configured to be openable to the front side with respect to the outer frame 11, so that the inner side 12, the front side frame 14, and the lower dish unit 15 are not exposed from the front side of the pachinko machine 10. Inspection and adjustment are performed with the inner frame 12 and the like open to the front side with respect to the outer frame 11.

To support the inner frame 12, an upper hinge (not shown) and a lower hinge (not shown) made of metal are attached to the outer frame 11 at upper and lower portions on the left side in front view. The inner frame 12 is supported so as to be openable and closable with the side provided with the upper hinge and the lower hinge as an opening and closing shaft.

The inner frame 12 is mainly composed of an inner frame base 55 made of ABS resin and formed in a rectangular shape, and a substantially circular central window 55a is formed at the center of the inner frame base 55. A mounting portion for the game board 13 is provided on the back side of the inner frame base 55, and the game board 13 is detachably mounted.

The lower side of the central window 55a of the inner frame base 55 is formed in a concave shape with the front side open, and a flat mounting surface 52b is formed on the back side thereof. On the mounting surface 52b, a firing unit 140 for firing a ball to the front surface of the game board 13, a passage forming member 54 that forms a passage for discharging the ball to the upper plate 17 and the lower plate 50, and the like are attached.

A switch SW1 for detecting opening and closing of the inner frame 12 is provided between the outer frame 11 and the inner frame 12, and between the inner frame 12 and the front frame 14 the front frame 14 is opened and closed. A switch SW2 for detecting closing is provided.

Here, the structures of the switches SW1 and SW2 will be described with reference to FIG. Since the switches SW1 and SW2 have the same structure, the structure of the switch SW1 will be described, and the description of the switch SW2 will be omitted.

FIG. 5 is a sectional view of the switch SW1. FIG. 5A is a cross-sectional view showing a state (a cutoff state) of the switch SW1 when the inner frame 12 is closed. Further, FIG. 5B is a cross-sectional view showing a state (conduction state) of the switch SW1 in a state where the inner frame 12 is opened.

As shown in FIG. 5A, the switch SW1 disposed on the surface of the outer frame 11 facing the inner frame 12 includes a movable shaft SW1a that abuts the inner frame 12 in the closed state, and the movable shaft SW1a. A conductor plate SW1-1a made of a metal that is a conductive member arranged in SW1a, and a pair of terminal plates SW1-1b made of a metal arranged at a position facing the conductor plate SW1-1a. , The pair of terminal plates SW1-1b are respectively arranged on the support plate SW1-1c arranged on the housing SW1b and on the surface of the conductor plate SW1-1a opposite to the surface facing the pair of terminal plates SW1-1b. A pair of springs SW1c that are provided to generate a biasing force toward the pair of terminal plates SW1-1b with respect to the conductor plate SW1-1a are provided.

As shown in FIG. 5A, when the inner frame 12 is closed, the movable shaft SW1a comes into contact with the inner frame 12 and the movable shaft SW1a is pushed into the housing SW1b. Therefore, the contact between the conductor plate SW1-1a and the pair of terminal plates SW1-1b is prevented. Therefore, in the state where the inner frame 12 is closed, the switch SW1 is in a state in which conduction is cut off.

On the other hand, as shown in FIG. 5B, when the inner frame 12 is opened, the contact between the movable shaft SW1a and the inner frame 12 is released, so that the conductors are urged by the pair of springs SW1c. The board SW1-1a contacts the pair of terminal boards SW1-1b. Therefore, when the inner frame 12 is open, the switch SW1 is in a conductive state.

In this way, the switch SW1 is in the cutoff state when the inner frame 12 is closed, and is in the conductive state when the inner frame 12 is open. The structure of the switch SW1 is not limited to the shape shown in FIG. 5, and when the inner frame 12 is closed, the switch SW1 is in the cutoff state, while when the inner frame 12 is open, It is sufficient that the switch SW1 has a conductive state. The same applies to the structure of the switch SW2.

Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 6 is a block diagram showing an electrical configuration of the pachinko machine 10.

The power supply unit 115 is provided with a power supply unit 251 for supplying power to each unit of the pachinko machine 10, a power failure monitoring circuit 252 for monitoring power interruption due to power failure, etc., and a RAM erase switch 122 (see FIG. 3). The erase switch circuit 253 and the reset circuit 254 that outputs the reset signal SG3a that makes the arithmetic processing of the MPU 201 executable are included. The power supply unit 251 is a device that supplies a necessary operating voltage to each of the control devices 110 to 114 and the like through a power supply path (not shown). As an outline thereof, the power supply unit 251 takes in a voltage of 24 V AC supplied from the outside, and 12 V voltage for driving various switches such as various switches 208, solenoids such as the solenoid 209, and motors, A 5 volt voltage for logic, a backup voltage for RAM backup, and the like are generated, and the 12 volt voltage, the 5 volt voltage, and the backup voltage are supplied to the respective control devices 110 to 114 as necessary. The power supply unit 251 also outputs the drive voltage Va of 5 V to the input terminal I13 of the multiplexer MP1.

When a power failure occurs due to a power failure or the like while the pachinko machine 10 is powered on, the power failure monitoring circuit 252, at the time of the power interruption, to the input terminal I11 of the multiplexer MP1 and the NMI terminal of the MPU211 of the payout control device 111, It is a circuit for outputting the power failure signal SG1a which is a positive pulse signal. The power failure monitoring circuit 252 monitors the voltage of DC stable 24V which is the maximum voltage output from the power supply unit 251, and determines that a power failure (power cut, power cut) occurs when this voltage becomes less than 22V. Then, the power failure signal SG1a is output to the multiplexer MP1 and the payout control device 111. The main controller 110 and the payout controller 111 recognize the occurrence of the power failure by the output of the power failure signal SG1a, and execute the NMI interrupt processing. Note that the power supply unit 251 outputs the voltage of 5 V which is the drive voltage of the control system for a time sufficient to execute the NMI interrupt processing even after the voltage of DC stable 24 V becomes less than 22 V. Is maintained at a normal value. Therefore, the main controller 110 and the payout controller 111 can normally execute and complete the NMI interrupt process (see FIG. 17).

The RAM erase switch circuit 253 is a circuit for outputting a RAM erase signal SG2 for clearing the backup data to the main controller 110 when the RAM erase switch 122 is pressed. The main control device 110 and the payout control device 111 clear the respective backup data when the RAM erase signal SG2 is input when the pachinko machine 10 is powered on, and at the same time, the payout control device 111 clears the backup data. The payout initialization command is transmitted to the payout control device 111.

The reset circuit 254 is a circuit that outputs a reset signal SG3a that puts the MPU 201 in a state in which it is possible to execute arithmetic processing. The reset circuit 254 outputs the voltage of 5 volts output from the power supply unit 251 as the reset signal SG3a. When the reset signal SG3a is input to the MPU 201 via the multiplexer MP2, the MPU 201 enters a state in which arithmetic processing can be executed. On the other hand, when the output of the reset signal SG3a is stopped, the MPU 201 is in a state in which the arithmetic processing cannot be executed. Although not shown, the reset signal SG3a output from the reset circuit 254 is also input to the MPU 211 of the payout control device 111, the MPU 221 of the voice lamp control device 113, and the MPU 231 of the display control device 114.

In the pachinko machine 10, the power failure monitoring circuit 252, the RAM erase switch circuit 253, and the reset circuit 254 are provided in the power supply device 115, but the invention is not limited to this, and the power failure monitoring circuit 252, the RAM erase switch circuit 253, or Any of the reset circuits 254 may be provided in the main controller 110. Further, a combination of any two circuits of the power failure monitoring circuit 252, the RAM erase switch circuit 253, and the reset circuit 254 may be provided in the main controller 110. Further, three circuits, that is, the power failure monitoring circuit 252, the RAM erase switch circuit 253, and the reset circuit 254 may be provided in the main controller 110. When the RAM erase switch circuit 253 is provided in the main controller 110, the RAM erase switch 112 is also provided in the main controller 110.

The main controller 110 is equipped with an MPU 201 as a one-chip microcomputer which is an arithmetic unit. The MPU 201 includes a ROM 202 that stores various control programs executed by the MPU 201 and fixed value data, and a memory for temporarily storing various data when the control program stored in the ROM 202 is executed. In addition to a certain RAM 203, various circuits such as an interrupt circuit, a timer circuit, and a data transmission/reception circuit are built in. Note that various commands are transmitted from the main control device 110 to the sub control device by the data transmission/reception circuit in order to instruct the sub control devices such as the payout control device 111 and the voice lamp control device 113 to operate. Such a command is transmitted from the main control device 110 to the sub control device in only one direction.

The MPU 201 has a power supply terminal to which a drive voltage Va or a drive voltage Vb that enables the MPU 201 is input, and either a reset signal SG3a or a reset signal SG3b that enables the arithmetic processing of the MPU 201. Is provided, and an NMI terminal (non-maskable interrupt terminal) to which either the power failure signal SG1a or the power failure signal SG1b is input is provided.

The lower limit value of the voltage at which the MPU 201 can operate is about 4.0 volts. Therefore, when the drive voltage Va or the drive voltage Vb supplied to the power supply terminal of the MPU 201 exceeds about 4.0 V, the MPU 201 is in a startable state (operable state) while the MPU 201 power supply terminal is in a ready state. When the drive voltage Va or the drive voltage Vb supplied to the device is about 4.0 V or less, the MPU 201 becomes inoperable. In addition, the lower limit value of the voltage at which the MPU 201 is in a state in which it is possible to perform calculation is approximately 4.3 volts. Therefore, if the voltage (reset signal SG3a or reset signal SG3b) supplied to the reset terminal of the MPU 201 exceeds approximately 4.3 volts, the MPU 201 is in a state in which it can execute the arithmetic processing, while the MPU 201 receives the reset terminal. When the supplied voltage (reset signal SG3a or reset signal SG3b) is about 4.3 V or less, the MPU 201 is in a state in which the arithmetic processing cannot be executed. Further, the NMI terminal of the MPU 201 is configured to receive the power failure signal SG1a output from the power failure monitoring circuit 252 or the power failure signal SG1b output from the frame opening detection circuit 260, and the power failure signal SG1a or the power failure signal SG1a. When any of the SG1b is input to the MPU 201, the NMI interrupt processing (see FIG. 17) as the power failure processing is immediately executed.

An input/output port 205 is connected to the MPU 201 of the main controller 110 via a bus line 204 composed of an address bus and a data bus. In the input/output port 205, the payout control device 111, the voice lamp control device 113, the first symbol display device 37, the second symbol display device 82, various switches 208 including a switch group and a sensor group not shown, and a specific prize. A solenoid 209 including a large opening solenoid for driving to open and close forward with the lower side of the opening/closing plate of the opening 65a as an axis and a solenoid for driving an electric accessory is connected.

Further, the input/output port 205 is connected to a hall computer 262 which operates continuously for 24 hours. When the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on while the pachinko machine 10 is powered off, the frame opening detection circuit 260 described later temporarily starts up the MPU 201. The MPU 201 that has risen temporarily outputs a pulse signal having a pulse width of about 1 ms to the hall computer 262 via the input/output port 205. The pulse signal output via the input/output port 205 is stored in the hall computer 262. Therefore, by analyzing the pulse signal stored in the hall computer 262, it is possible to detect the opening of the inner frame 12 or the front frame 14 performed while the power of the pachinko machine 10 is turned off. Furthermore, the pachinko machine 10 with the inner frame 12 or the front frame 14 opened can be specified.

Main controller 110 is provided with a frame opening detection circuit 260 that detects opening of inner frame 12 when switch SW1 conducts and detects opening of front frame 14 when switch SW2 conducts. The frame opening detection circuit 260 is connected to a switch SW1 that detects the opening of the inner frame 12 and a switch SW2 that detects the opening of the front frame 14. Note that the switches SW1 and SW2 are connected to the frame opening detection circuit 260 via an input/output unit (not shown in the drawing, which is different from the input/output port 205 (latch circuit or the like)) that inputs and outputs signals. Is being done. Although details will be described with reference to FIG. 7, since the frame open detection circuit 260 is provided with the capacitor CD1 for supplying power, the inner frame 12 or the front surface is provided when the pachinko machine 10 is powered off. Even if the frame 14 is opened, the frame opening detection circuit 260 can detect the opening and temporarily start up the MPU 201. Further, when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered on, the frame open detection circuit 260 naturally operates. Here, when the power of the pachinko machine 10 is on, the MPU 201 has already started up, and it is not necessary to start up the MPU 201 by the frame opening detection circuit 260, so the inner frame 12 or the front frame 14 is opened at this time. In this case, the frame opening detection circuit 260 outputs only the reset signal SG3b to the input/output port 205 by the operation of the multiplexers MP1 to MP3, instead of raising the MPU 201.

Further, the frame open detection circuit 260 receives an input from the multiplexer MP1 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on when the pachinko machine 10 is powered off. The terminal I21 is provided with an interruption signal output terminal that outputs the power failure signal SG1b for about 4.4 seconds after the switch SW1 or the switch SW2 is turned on. The power failure signal output terminal of the frame open detection circuit 260 is connected to the input terminal I21 of the multiplexer MP1 whose output terminal O1 is connected to the NMI terminal of the MPU 201. The input terminal I11 of the multiplexer MP1 is connected to the power failure monitoring circuit 252, and the control terminal S1 of the multiplexer MP1 is connected to the power supply unit 251. Therefore, when the pachinko machine 10 is powered on, a voltage of 5 V for logic is input from the power supply unit 251 to the control terminal S1 of the multiplexer MP1. On the other hand, when the pachinko machine 10 is powered off, the power supply unit 251 does not operate, so no voltage is input to the control terminal S1 of the multiplexer MP1 (the voltage of the control terminal S1 of the multiplexer MP1 is zero volts). Become).

Here, regarding the relationship between the power failure signal SG1a output from the power failure monitoring circuit 252 and the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260, a case where the power of the pachinko machine 10 is turned on. The case where the power of the pachinko machine 10 is turned off will be separately described.

When the pachinko machine 10 is powered on, a voltage of 5 volts is input from the power supply unit 251 to the control terminal S1 of the multiplexer MP1. When a voltage of 5 volts is input to the control terminal S1, the multiplexer MP1 conducts conduction between the input terminal I11 of the multiplexer MP1 and the output terminal O1 of the multiplexer MP1 (the input terminal I21 of the multiplexer MP1 and the output terminal of the multiplexer MP1). When the power of the pachinko machine 10 is turned on, the power failure signal SG1a output from the power failure monitoring circuit 252 can be input to the NMI terminal of the MPU 201 (since it is not electrically connected to O1) (frame open detection). Even if the power failure signal SG1b is output from the power failure signal output terminal of the circuit 260, it is not input to the NMI terminal of the MPU 201). On the other hand, when the power of the pachinko machine 10 is off, a voltage of zero volt is input from the power supply unit 251 to the control terminal S1 of the multiplexer MP1. When a voltage of zero volt is input to the control terminal S1, the multiplexer MP1 conducts the input terminal I21 of the multiplexer MP1 and the output terminal O1 of the multiplexer MP1 (the input terminal I11 of the multiplexer MP1 and the output terminal O1 of the multiplexer MP1). When the power of the pachinko machine 10 is off, the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 can be input to the NMI terminal of the MPU 201. Becomes As described above, the multiplexer MP1 outputs the signal output to the NMI terminal of the MPU 201 to the power failure signal SG1a or the power failure according to the voltage input from the power supply unit 251 to the control terminal S1, that is, according to the on/off state of the power supply of the pachinko machine 10. Switch to any of the signals SG1b.

Further, the frame open detection circuit 260 receives an input from the multiplexer MP2 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on when the pachinko machine 10 is powered off. A reset signal output terminal for outputting the reset signal SG3b is provided to the terminal I22 and the input/output port 205 for about 9.4 seconds after the switch SW1 or the switch SW2 is turned on. The reset signal output terminal of the frame open detection circuit 260 is connected to the input terminal I22 of the multiplexer MP2 whose output terminal O2 is connected to the reset terminal of the MPU 201 and the input/output port 205. The input terminal I12 of the multiplexer MP2 is connected to the reset circuit 254, and the control terminal S2 of the multiplexer MP2 is connected to the power supply unit 251. Therefore, when the power of the pachinko machine 10 is on, a voltage of 5 V for logic is input from the power supply unit 251 to the control terminal S2 of the multiplexer MP2. On the other hand, when the power of the pachinko machine 10 is off, the power supply unit 251 does not operate, so no voltage is input to the control terminal S2 of the multiplexer MP2 (the voltage of the control terminal S2 of the multiplexer MP2 is zero volts). Become).

Here, regarding the relationship between the reset signal SG3a output from the reset circuit 254 and the reset signal SG3b output from the reset signal output terminal of the frame opening detection circuit 260, the case where the power of the pachinko machine 10 is turned on and the case of the pachinko machine are The case where the power of 10 is turned off will be described separately.

When the pachinko machine 10 is powered on, a voltage of 5 volts is input from the power supply unit 251 to the control terminal S2 of the multiplexer MP2. When a voltage of 5 volts is input to the control terminal S2, the multiplexer MP2 conducts the input terminal I12 of the multiplexer MP2 and the output terminal O2 of the multiplexer MP2 (the input terminal I22 of the multiplexer MP2 and the output terminal of the multiplexer MP2). When the pachinko machine 10 is powered on, the reset signal SG3a output from the reset circuit 254 can be input to the reset terminal of the MPU 201 (since it is not electrically connected to O2) (frame opening detection circuit). Even if the reset signal SG3b is output from the reset signal output terminal of 260, it is not input to the reset terminal of MPU 201). On the other hand, when the power of the pachinko machine 10 is off, a voltage of zero volt is input from the power supply unit 251 to the control terminal S2 of the multiplexer MP2. When a voltage of zero volts is input to the control terminal S2, the multiplexer MP2 conducts the input terminal I22 of the multiplexer MP2 and the output terminal O2 of the multiplexer MP1 (the input terminal I12 of the multiplexer MP2 and the output terminal O2 of the multiplexer MP1). Therefore, when the power of the pachinko machine 10 is off, the reset signal SG3b output from the reset signal output terminal of the frame opening detection circuit 260 can be input to the reset terminal of the MPU 201. Become. In this way, the multiplexer MP2 outputs the signal output to the reset terminal of the MPU 201 to the reset signal SG3a or the reset signal according to the voltage input from the power supply unit 251 to the control terminal S, that is, according to the on/off state of the power supply of the pachinko machine 10. Switch to any of the signals SG3b.

The reset signal output terminal of the frame opening detection circuit 260 is also connected to the input/output port 205 as described above. Therefore, when the inner frame 12 or the front frame 14 is opened, the reset signal SG3b is sent from the reset signal output terminal of the frame open detection circuit 260 to the input/output port 205 regardless of whether the power of the pachinko machine 10 is turned on. Is output. The MPU 201 can detect the opening of the inner frame 12 or the front frame 14 by the reset signal SG3b output to the input/output port 205.

The frame open detection circuit 260 includes an input terminal I13 of the multiplexer MP3 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on when the pachinko machine 10 is powered off. Is provided with a power supply output terminal for supplying a drive voltage Vb having a maximum value of about 5 volts for about 9.9 seconds after the switch SW1 or the switch SW2 is turned on. The power output terminal of the frame open detection circuit 260 is connected to the input terminal I23 of the multiplexer MP3 whose output terminal O3 is connected to the power terminal of the MPU 201. The input terminal I13 of the multiplexer MP3 is connected to the power supply unit 251, and the control terminal S3 of the multiplexer MP3 is also connected to the power supply unit 251. Therefore, when the pachinko machine 10 is powered on, a voltage of 5 V for logic is input from the power supply unit 251 to the control terminal S3 of the multiplexer MP3. On the other hand, when the power of the pachinko machine 10 is off, the power supply unit 251 does not operate, so no voltage is input to the control terminal S3 of the multiplexer MP3 (the voltage of the control terminal S3 of the multiplexer MP3 is zero volts). Become).

Here, regarding the relationship between the drive voltage Va output from the power supply unit 251 and the drive voltage Vb output from the power supply output terminal of the frame open detection circuit 260, which has a maximum value of about 5 volts, the power of the pachinko machine 10 is turned on. The case where the pachinko machine 10 is turned off and the case where the pachinko machine 10 is turned off will be described separately.

When the pachinko machine 10 is powered on, a voltage of 5 volts is input from the power supply unit 251 to the control terminal S3 of the multiplexer MP3. When a voltage of 5 volts is input to the control terminal S3, the multiplexer MP3 conducts the input terminal I13 of the multiplexer MP3 and the output terminal O3 of the multiplexer MP3 (the input terminal I23 of the multiplexer MP3 and the output terminal of the multiplexer MP3 are connected. When the pachinko machine 10 is powered on, the drive voltage Va output from the power supply unit 251 can be input to the power supply terminal of the MPU 201 (since it is not electrically connected to O3) (frame open detection circuit). Even if the drive voltage Vb is output from the power supply output terminal of 260, it is not input to the power supply terminal of MPU 201). On the other hand, when the power of the pachinko machine 10 is off, a voltage of zero volt is input from the power supply unit 251 to the control terminal S3 of the multiplexer MP3. When a voltage of zero volt is input to the control terminal S3, the multiplexer MP3 conducts the input terminal I23 of the multiplexer MP3 and the output terminal O3 of the multiplexer MP3 (the input terminal I13 of the multiplexer MP3 and the output terminal O3 of the multiplexer MP3). Therefore, when the power of the pachinko machine 10 is off, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 can be input to the power terminal of the MPU 201. .. In this way, the multiplexer MP3 outputs the voltage output from the power supply unit 251 to the power supply terminal of the MPU 201 according to the voltage input from the power supply unit 251 to the control terminal S, that is, according to the on/off state of the power supply of the pachinko machine 10. Either the output drive voltage Va or the drive voltage Vb output from the power supply output terminal of the frame open detection circuit 260 is switched.

Although not shown, the output terminal O3 of the multiplexer MP3 is also connected to the input/output port 205. Therefore, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is conducted while the power of the pachinko machine 10 is turned off, the power is output from the power output terminal of the frame open detection circuit 260. The drive voltage Vb that supplies the input/output port 205 is also supplied.

As described above, when the power of the pachinko machine 10 is turned on, various signals (power failure signal SG1a and reset signal SG3a) are output from each circuit (power supply unit 251, power failure monitoring circuit 252 and reset circuit 254) of the power supply device 115. And the drive voltage Va are output to each terminal (NMI terminal, reset terminal, and power supply terminal) of the MPU 201 via the multiplexers MP1 to MP3. Then, when the power of the pachinko machine 10 is turned on, the inner frame 12 or the front frame 14 is opened, and when the switch SW1 or the switch SW2 becomes conductive, only the reset signal SG3b is input from the frame opening detection circuit 260. It is output to the output port 205. On the other hand, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the switch SW1 or the switch SW2 is turned on, various signals (blackout signal SG1b) are output from the frame open detection circuit 260. The reset signal SG3b) and the drive voltage Vb are output to each terminal (NMI terminal, reset terminal, and power supply terminal) of the MPU 201 via the multiplexers MP1 to MP3 for a certain period. Therefore, even when the power of the pachinko machine 10 is turned off, the frame open detection circuit 260 causes the MPU 201 to temporarily (when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 becomes conductive (the present embodiment). Then, it can be started up for about 9.9 seconds.

As described above, the output terminal O3 of the multiplexer MP3 is also connected to the input/output port 205, though not shown. Therefore, when the power of the pachinko machine 10 is turned off and the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the power output terminal of the frame open detection circuit 260 to the input/output port 205. Also outputs the drive voltage Vb. Therefore, even when the power of the pachinko machine 10 is turned off, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 becomes conductive, the frame open detection circuit 260 also causes the input/output port 205 to be opened. It can be started up temporarily (about 9.9 seconds in this embodiment).

The RAM 203 is a stack area in which the contents of internal registers of the MPU 201 and the return address of the control program executed by the MPU 201 are stored, and a work area in which various flags, counters, I/O, and other values are stored. Area) and. Further, the RAM 203 has an OFF inside frame opening flag 203a and an ON inside frame opening flag 203b. Note that the RAM 203 is configured to be able to retain (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is cut off, and all the data stored in the RAM 203 is backed up. ..

When the power is cut off due to the occurrence of a power failure or the like, the RAM 203 stores the stack pointer when the power is cut off (including the occurrence of a power failure; the same applies hereinafter) and the value of each register. On the other hand, at the time of power-on (including power-on by elimination of power failure. The same applies hereinafter), the state of the pachinko machine 10 is restored to the state before the power-off, based on the information stored in the RAM 203. Writing to the RAM 203 is executed when the power is shut off by the main processing (see FIG. 12), and restoration of each value written to the RAM 203 is executed in the startup processing when the power is turned on (see FIG. 11).

When the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the frame opening detection circuit 260 causes the frame opening detection circuit 260 to turn off the MPU 201. It is a flag that is turned on when it is temporarily started up (the process of S112 of the startup process of the main control device 110 described later). By turning on the off-frame open flag 203a, the MPU 201 can detect that the inner frame 12 or the front frame 14 has been opened while the pachinko machine 10 is powered off. When the pachinko machine 10 is turned on while the off-inside frame open detection flag 203a is turned on, the MPU 201 uses the audio output device 226 and the lamp display device 227 to make a notification. As a result, the pachinko machine 10 can notify an unspecified number of persons (a clerk, a player, etc.) that the inner frame 12 or the front frame 14 was opened while the power of the pachinko machine 10 was turned off. On the other hand, the off-in-frame opening flag 203a is turned off when the RAM erase switch 122 is operated and the used RAM area is cleared in the processing of S116 of the startup processing of the main controller 110 (see FIG. 11). .. Therefore, once the off-inside frame open flag 203a is turned on, the off-inside frame open flag 203a cannot be turned off unless the RAM erase switch 122 is operated to clear the used RAM area in the processing of S116. Therefore, when the power of the pachinko machine 10 is turned on, the pachinko machine 10 certainly does not confirm that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. It is possible to notify a specified number of people.

The on-frame opening flag 203b is a reset signal for the frame opening detection circuit 260 when the pachinko machine 10 is powered on, the inner frame 12 or the front frame 14 is opened, and the switch SW1 or the switch SW2 is turned on. This is a flag that is turned on when the reset signal SG3b is output from the output terminal to the input/output port 205 (the process of S219 of the main process). This on-frame opening flag 203b is turned off in the process of S220 of the main process when the opened inner frame 12 or the opened front frame 14 is closed. By turning on the on-frame opening flag 203b, the MPU 201 can detect that the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered on. When the pachinko machine 10 is powered on and the on-frame opening detection flag 203b is turned on, the MPU 201 uses the audio output device 226 and the lamp display device 227 to make a notification. As a result, the pachinko machine 10 can notify an unspecified number of persons that the inner frame 12 or the front frame 14 has been opened while the pachinko machine 10 is powered on.

The payout control device 111 drives the payout motor 216 to perform payout control of prize balls and rental balls. The MPU 211, which is an arithmetic unit, has a ROM 212 that stores a control program executed by the MPU 211, fixed value data, and the like, and a RAM 213 that is used as a work memory and the like.

The RAM 213 of the payout control device 111, like the RAM 203 of the main control device 110, has a stack area in which the contents of the internal registers of the MPU 211 and the return address of the control program executed by the MPU 211 are stored, and various flags and counters. , I/O, and the like are stored in a work area (work area). The RAM 213 is configured to be able to retain (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is cut off, and all the data stored in the RAM 213 is backed up. The NMI terminal of the MPU 211 is configured to receive the power failure signal SG1a from the power failure monitoring circuit 252 when the power is shut off due to the occurrence of a power failure or the like. When the power failure signal SG1a is input to the MPU 211, the power failure occurs. The NMI interrupt process (see FIG. 17) as a process is immediately executed.

An input/output port 215 is connected to the MPU 211 of the payout control device 111 via a bus line 214 composed of an address bus and a data bus. The main controller 110, the payout motor 216, the firing controller 112, etc. are connected to the input/output port 215, respectively. Further, although not shown, the payout control device 111 is connected to a prize ball detection switch for detecting the paid prize balls. The prize ball detection switch is connected to the payout control device 111, but is not connected to the main control device 110.

The firing control device 112 controls the ball firing unit 112a so that when the main control device 110 gives an instruction to fire a sphere, the sphere launching unit 112a has a launching strength corresponding to the rotational operation amount of the operation handle 51. The ball firing unit 112a includes a firing solenoid and an electromagnet, which are not shown, and the firing solenoid and the electromagnet are permitted to be driven when a predetermined condition is satisfied. Specifically, the touch sensor 51a detects that the player is touching the operation handle 51, and the stop switch 51b for stopping the firing of the ball is turned off (not operated) on condition that the operation handle is not operated. The firing solenoid is excited according to the amount of rotation of 51, and the ball is fired with a strength corresponding to the amount of operation of the operation handle 51.

The voice lamp control device 113 outputs the voice output from the voice output device (such as a speaker not shown) 226, the light output from the lamp display device (such as the illumination parts 29 to 33 and the display lamp 34), and the display control device 114. It is for controlling setting of the display mode of the third symbol display device 81 that is performed. The MPU 221 as an arithmetic unit has a ROM 222 that stores a control program executed by the MPU 221 and fixed value data, and a RAM 223 used as a work memory.

An input/output port 225 is connected to the MPU 221 of the audio lamp control device 113 via a bus line 224 composed of an address bus and a data bus. The main control device 110, the display control device 114, the audio output device 226, the lamp display device 227, etc. are connected to the input/output port 225, respectively.

The display control device 114 controls the variable display of the third symbol on the third symbol display device (LCD) 81. The display control device 114 includes an MPU 231, a ROM (program ROM) 232, a work RAM 233, a video RAM 234, a character ROM 235, an image controller 236, an input port 237, an output port 238, bus lines 239 and 240. have. The input side of the input port 237 is connected to the output side of the audio lamp controller 113, and the output side of the input port 237 is connected to the MPU 231, the ROM 232, the work RAM 233, and the image controller 236. A video RAM 234 and a character ROM 235 are connected to the image controller 236, and an output port 238 is connected via a bus line 240. The third symbol display device 81 is connected to the output side of the output port 238. It should be noted that the pachinko machine 10 is a model having a completely same design as the symbol configuration displayed on the third symbol display device 81, even if it is a different model having a different winning probability for the jackpot or the number of prize balls paid out in one jackpot. Therefore, the display control device 114 is made into a common component to reduce the cost.

The MPU 231 of the display control device 114 controls the display content of the third symbol display device 81 based on the symbol display command input from the voice lamp control device 113. The ROM 232 is a memory for storing various control programs executed by the MPU 231 and fixed value data. The work RAM 233 is a memory for temporarily storing work data and flags used when the MPU 231 executes various programs. The character ROM 235 is a memory that stores data for effects such as symbols (background symbols and third symbols) displayed on the third symbol display device 81. The video RAM 234 is a memory for storing effect data displayed on the third symbol display device 81, and by rewriting the contents of the video RAM 234, the display content of the third symbol display device 81 is changed.

The image controller 236 adjusts the timing of each of the MPU 231, the video RAM 234, and the output port 238 to intervene in reading and writing of data, and reads the display data stored in the video RAM 234 at a predetermined timing to read the third symbol display device 81. To be displayed on.

Next, the frame open detection circuit 260 will be described with reference to FIG. FIG. 7 is a circuit diagram showing an electrical configuration of the frame open detection circuit 260. A frame opening detection circuit 260 for detecting opening of the inner frame 12 or opening of the front frame 14 includes a DC power supply DC1 that supplies a DC voltage of 12 V, diodes D1 to D5, capacitors CD1 to CD4, and resistors R1 to R5. And a timer IC1 (LMC555 manufactured by National Semiconductor) which is a C-MOS timer, a transistor TR1, FET1 to FET3, a reset IC2 (BD4843 manufactured by ROHM Co., Ltd.), and a NOTIC3 which is a logic negation circuit. doing.

In order to detect the opening of the inner frame 12 by the conduction of the switch SW1 and the opening of the front frame 14 by the conduction of the switch SW2, the frame opening detection circuit 260 has the above-mentioned components shown in FIG. Connected according to the circuit diagram. Since the switch SW1 and the switch SW2 are connected in parallel and then connected to the frame opening detection circuit 260, if either one of the switches is turned on, the frame opening detection circuit 260 causes the inner frame 12 or the front frame. The opening of 14 can be detected.

The DC power supply DC1 is a power supply that supplies a DC voltage of 12 V to the frame open detection circuit 260. Electric power (power supply) to the DC power supply DC1 is supplied from a power supply unit 251 provided in the power supply device 115 through a power supply path (not shown). The DC power supply DC1 is connected to the anode terminal of the diode D1. One end of a 1F (farad) capacitor CD1 is connected to the cathode terminal of the diode D1. The other end of the capacitor CD1 is grounded. Further, one end of the capacitor CD1 is connected to one end of the switch SW1, one end of the switch SW2, the VDD terminal of the timer IC1 and the RES terminal of the timer IC1.

The capacitor CD1 functions as a rechargeable battery that supplies a DC voltage to the frame open detection circuit 260 when the power supply to the pachinko machine 10 is cut off and the DC voltage of 12 V is not supplied from the DC power supply DC1. It is a part.

This is because the capacitor CD1 is applied to the capacitance 1F (farad) of the capacitor CD1 and the capacitor CD1 when the pachinko machine 10 is supplied with power and the DC voltage of 12 V is supplied from the DC power supply DC1. And a DC voltage (about 11.3 V obtained by subtracting about 0.7 V of the voltage drop in the diode D1 from 12 V supplied from the DC power supply DC1) are stored.

On the other hand, the capacitor CD1 is stored in the capacitor CD1 when the DC power of DC 12 DC is not supplied from the DC power supply DC1, for example, when power supply to the pachinko machine 10 is cut off after the business hours of the game arcade are over. Electric power based on the generated charges is supplied to the frame open detection circuit 260.

Therefore, the frame open detection circuit 260 naturally operates when the pachinko machine 10 is supplied with power and a DC voltage of 12 V is supplied from the DC power supply DC1, and further, for example, a game hall business. Even when the power supply to the pachinko machine 10 is cut off after the end of time and the DC voltage of 12 V is not supplied from the DC power supply DC1, the power is supplied by the capacitor CD1 to operate the inner frame. The opening of 12 and the opening of the front frame 14 can be detected. In the present embodiment, the capacitor CD1 is used as a component that supplies power to the frame open detection circuit 260 when a DC voltage of 12 V is not supplied from the DC power supply DC1. However, the present invention is not limited to this, and the capacitor CD1 may be a secondary battery (rechargeable battery) having a larger amount of stored electricity or a primary battery that does not need to be charged.

In addition, when the cathode terminal of the diode D1 is connected to one end of the capacitor CD1 and this diode D1 fulfills the function of preventing backflow of current, when the power is supplied from the capacitor CD1 to the frame open detection circuit 260. However, the voltage generated by the power is not applied to the DC power supply DC1, and the DC power supply DC1 is not damaged.

The timer IC1 is a C-MOS timer, and the inner frame 12 or the front frame 14 is opened by connecting the resistor R1 of 200 kΩ, the resistor R2 of 100 kΩ, the capacitor CD2 of 22 μF, and the capacitor CD3 of 0.1 μF. To function as a circuit for making the transistor TR1 conductive for about 4.4 seconds. When the transistor TR1 is turned on, a drive voltage Vb having a maximum value of about 5 volts is output from the power supply output terminal, a reset signal SG3b is output from the reset signal output terminal, and a power failure is output from the power interruption signal output terminal. The output of the signal SG1b is started.

The timer IC1 is supplied with electric power by the capacitor CD1, for example, when the power supply to the pachinko machine 10 is cut off after the business hours of the amusement hall are finished and the DC voltage of 12 V is not supplied from the DC power supply DC1. The case where the power is supplied to the pachinko machine 10 and the case where the DC voltage of 12 V is supplied from the DC power supply DC1 is shared. Therefore, naturally, the timer IC 1 can operate with a DC voltage of 12 V or less supplied to the frame open detection circuit 260 when power is being supplied to the pachinko machine 10. Further, since the timer IC1 is a timer composed of a C-MOS semiconductor, it is possible to suppress power consumption during operation and operate for a long time.

The VDD terminal of the timer IC1 is a terminal for inputting the DC voltage supplied to the timer IC1, and is connected to one end of the switch SW1, one end of the switch SW2, one end of the capacitor CD1 and the RES terminal of the timer IC1. The RES terminal of the timer IC1 is a terminal for activating a reset function that forcibly brings the voltage output from the OUT terminal into an output stopped state (zero volt) when a pulse signal is input to the RES terminal. However, since the frame open detection circuit 260 does not use this reset function, the RES terminal of the timer IC1 is connected to the VDD terminal of the timer IC1 so that the reset function does not operate. Since the VDD terminal of the timer IC1 and the RES terminal of the timer IC1 are connected to one end of the capacitor CD1 as described above, a DC voltage of about 11.3 volts is applied to the VDD terminal and the RES terminal of the timer IC1. Is applied.

When the switch SW1 and the switch SW2 are cut off (when the inner frame 12 and the front frame 14 are closed), the TRG terminal of the timer IC1 outputs about the voltage output from the OUT terminal of the timer IC1. While setting to 10.6 volts, when either the switch SW1 or the switch SW2 or both the switch SW1 and the switch SW2 become conductive (either the inner frame 12 or the front frame 14, or When both the inner frame 12 and the front frame 14 are open), the voltage output from the OUT terminal of the timer IC 1 is set to about 10.6 volts to zero volts about 4.4 seconds after the conduction. It is a terminal for doing. The TRG terminal of the timer IC1 is connected to the other end of the resistor R2.

The resistor R2 connected to the TRG terminal of the timer IC1 has a timer when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is in a conductive state (see FIG. 5B). This is a resistor for applying a DC voltage (about 11.3 V) to the TRG terminal of IC1. Since the input impedance of the TRG terminal of the timer IC1 is sufficiently larger than the resistance value of the resistor R2 (100 kΩ), the voltage drop due to the resistor R2 hardly occurs. Therefore, when the switch SW1 or the switch SW2 becomes conductive, a voltage of about 11.3 volts supplied from one end of the capacitor CD1 is applied to the TRG terminal of the timer IC1.

With the above connection, when the switch SW1 and the switch SW2 are in the cutoff state (when the inner frame 12 and the front frame 14 are in the closed state), no voltage is supplied to the resistor R2, so that the voltage is applied to the TRG terminal of the timer IC1. The voltage will be zero volts. At this time, the voltage output from the OUT terminal of the timer IC1 is about 10.6 volts.

On the other hand, when either the switch SW1 or the switch SW2, or both the switch SW1 and the switch SW2 are in the conductive state (either the inner frame 12 or the front frame 14, or both the inner frame 12 and the front frame 14 are Since the voltage is supplied to the resistor R2 (in the open state), the voltage applied to the TRG terminal of the timer IC1 is about 11.3 volts which is the same as the voltage applied to one end of the capacitor CD1. At this time, the voltage output from the OUT terminal of the timer IC1 is about 10.6 for about 4.4 seconds after either the switch SW1 or the switch SW2 or both the switch SW1 and the switch SW2 become conductive. Volts, then zero volts.

As described above, the voltage applied to the TRG terminal of the timer IC1 can set the voltage output from the OUT terminal of the timer IC1 to either about 10.6 volts or zero volts. When the switch SW1 or the switch SW2 is turned on (the inner frame 12 or the front frame 14 is opened) and the voltage applied to the TRG terminal of the timer IC 1 changes from zero volt to about 11.3 volt, as described above, After a delay of about 4.4 seconds from the rise of the voltage, the voltage of about 10.6 volts output from the OUT terminal of the timer IC1 falls to zero volts. Then, as will be described in detail later, the transistor is caused by the time difference (about 4.4 seconds) between the rise of the voltage applied to the TRG terminal of the timer IC1 and the fall of the voltage output from the OUT terminal of the timer IC1. TR1 conducts for about 4.4 seconds.

When the switch SW1 and the switch SW2 are cut off (the inner frame 12 and the front frame 14 are closed) and the voltage applied to the TRG terminal of the timer IC1 becomes zero volts, the OUT terminal of the timer IC1 has a voltage of about 10.6 volts. When the switch SW1 or the switch SW2 is turned on (the inner frame 12 or the front frame 14 is opened) and the voltage applied to the TRG terminal of the timer IC1 rises to about 11.3 volts, It is a terminal that sets the output voltage of about 10.6 volts to zero volts with a delay of 4.4 seconds. The OUT terminal is connected to the gate terminal G of FET1 and the gate terminal G of FET2.

The FET1 is an N-MOS switching element that switches between conduction and interruption by the voltage output from the OUT terminal of the timer IC1, and the drain terminal D of the FET1 is connected to the other end of the resistor R3 of 100 kΩ and the base terminal b of the transistor TR1. Connected. The emitter terminal e of the transistor TR1 is connected to one end of the resistor R3, one end of the resistor R2 and the input terminal of the NOTIC3. The collector terminal c of the transistor TR1 is connected to one end of the capacitor CD4, one end of the resistor R4, the anode terminal of the diode D3, and the anode terminal of the diode D4. Further, the source terminal S of the FET1 is connected to the cathode terminal of the Zener diode D2. The anode terminal of this Zener diode D2 is grounded.

When the voltage output from the OUT terminal of the timer IC1 is about 10.6 volts, the FET1 (when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds after the opening, When the inner frame 12 and the front frame 14 are closed), the drain terminal D and the source terminal S of the FET 1 are brought into conduction. On the other hand, when the voltage output from the OUT terminal of the timer IC1 is zero volt (when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed after the opening), the FET1 is FET1. The drain terminal D and the source terminal S of the above are cut off.

Here, three scenes of the operation of the FET1 and the operation of the transistor TR1 will be described in time series. First, the operation of the FET1 and the operation of the transistor TR1 from the opening of the inner frame 12 or the front frame 14 to the elapse of about 4.4 seconds will be described. When the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is in a conductive state, and therefore, until about 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened (the switch Until about 4.4 seconds have passed since the switch SW1 or the switch SW2 was turned on), the current supplied from the DC power source DC1 or the capacitor CD1 was passed through the resistor R3 to the drain terminal D and the source terminal S of the FET1. Between the zener diode D2 and the cathode terminal of the zener diode D2. Here, the limiting voltage of the Zener diode D2 is about 5.7 volts. When the drain terminal D and the source terminal S of the FET 1 are in a conductive state, the impedance between the drain terminal D and the source terminal S of the FET 1 is about several Ω. Therefore, the voltage of the base terminal b of the transistor TR1 becomes about 5.7 volts which is almost the same voltage as the limiting voltage of the Zener diode D2. When a voltage is generated in the resistor R3, a bias voltage is applied to the base terminal b of the transistor TR1 and the emitter terminal e of the transistor TR1. Therefore, the emitter terminal e and the collector terminal c of the transistor TR1 are also electrically connected, and the current supplied from the DC power supply DC1 or the capacitor CD1 flows from the emitter terminal e of the transistor TR1 to the collector terminal c. Here, when the base terminal b and the collector terminal c of the transistor TR1 are in a conductive state, the impedance between the base terminal b and the collector terminal c of the transistor TR1 is about several Ω. Therefore, the voltage of the collector terminal c of the transistor TR1 is approximately the same as the limiting voltage of the Zener diode D2, approximately 5.7, until approximately 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened. It becomes a bolt. By this operation, until about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened, a voltage of about 5.7 volts is applied to the capacitor CD4, the capacitor CD4 is charged, and the power source is turned on. A drive voltage Vb having a maximum value of about 5 V (a voltage obtained by subtracting 0.7 V of the voltage drop of the diode D3 from the voltage of about 5.7 V applied to the capacitor CD4) is started from the output terminal, and the reset signal output terminal outputs. The reset signal SG3b is started to be output, and the power failure signal SG1b is started to be output from the power failure signal output terminal.

Next, the operation of the FET1 and the operation of the transistor TR1 when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed from the opening will be described. When the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds have passed since the opening, the drain terminal D and the source terminal S of the FET 1 are cut off. Therefore, even if the switch SW1 or the switch SW2 is conductive, the current supplied from the DC power supply DC1 or the capacitor CD1 does not flow into the resistor R3, and the voltage generated in the resistor R3 becomes zero. Therefore, the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off. Therefore, when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have passed after the opening, the voltage of the collector terminal c of the transistor TR1 becomes zero volts. By this operation, the inner frame 12 or the front frame 14 is opened, and when about 4.4 seconds elapses from the opening, the voltage applied to the capacitor CD4 becomes zero volt, and the electric power stored in the capacitor CD4 is discharged. ..

Finally, the operation of the FET1 and the operation of the transistor TR1 when the inner frame 12 and the front frame 14 are closed will be described. When the inner frame 12 and the front frame 14 are closed, the voltage output from the OUT terminal of the timer IC1 becomes about 10.6 volts, and the drain terminal D and the source terminal S of the FET1 become conductive, but the switch SW1 and the switch SW1 SW2 is in the cutoff state. Therefore, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET1 become conductive, but no current is supplied from the DC power source DC1 or the capacitor CD1 and the transistor TR1 is The voltage between the base terminal b and the emitter terminal e is zero volt. As a result, the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off. Therefore, when the inner frame 12 and the front frame 14 are closed, no voltage is applied to the collector terminal c of the transistor TR1 and the voltage of the collector terminal c of the transistor TR1 becomes zero volts. By this operation, even when the inner frame 12 and the front frame 14 are closed, the voltage applied to the capacitor CD4 becomes zero volt, and the electric power stored in the capacitor CD4 is discharged.

Returning to the explanation of FIG. The capacitor CD4 charges the electric power supplied via the transistor TR1 and discharges the charged electric power to supply the electric power to the power supply output terminal and the reset IC 2 except the power interruption signal output terminal. Farad) capacitors. One end of the capacitor CD4 is connected to the collector terminal c of the transistor TR1, one end of the resistor R4, the anode terminal of the diode D3 and the anode terminal of the diode D4. On the other hand, the other end of the capacitor CD4 is grounded.

By this connection, in the capacitor CD4, the drain terminal D and the source terminal S of the FET1 become conductive and the emitter terminal of the transistor TR1 remains until about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened. The electric power supplied from the DC power supply DC1 or the capacitor CD1 is stored via the transistor TR1. Then, in the capacitor CD4, the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds after the opening (the drain terminal D and the source terminal S of the FET1 are cut off and the emitter terminal of the transistor TR1 is cut off). (Since e and the collector terminal c are cut off), the stored electric power is discharged and the electric power is supplied to the power output terminal and the reset IC 2. When the drain terminal D and the source terminal S of the FET1 are in the cutoff state, the conduction between the drain terminal D and the source terminal S of the FET2 is naturally cutoff, so that the current accompanying the power discharged by the capacitor CD4 is generated. It does not flow into the resistor R5. Therefore, the voltage associated with the electric power discharged from the capacitor CD4 is not output to the power failure signal output terminal. Therefore, the capacitor CD4 does not supply power to the power failure signal output terminal, but supplies power to the power supply output terminal and the reset IC 2.

The discharge time until the electric power stored in the capacitor CD4 becomes zero depends on the input impedance of the input terminal I23 of the multiplexer MP3 connected to the power output terminal and the power terminal of the MPU 201 connected to the output terminal O3 of the multiplexer MP3. , The input impedance of the input terminal IN of the reset IC2, the input impedance of the input terminal I22 of the multiplexer MP2 connected to the reset signal output terminal, and the input impedance of the reset terminal of the MPU201 connected to the output terminal O2 of the multiplexer MP2. Etc. In this embodiment, when the capacitor CD4 is fully charged, the discharge time until the fully charged electric power becomes zero is set to about 20 seconds. However, when the capacitor CD4 is fully charged, the discharge time until the fully charged power becomes zero is shorter than about 20 seconds or longer than about 20 seconds by adjusting the impedance described above. You may set it.

The electric power stored in the capacitor CD4 is discharged even when the inner frame 12 or the front frame 14 is opened, about 4.4 seconds elapses from the opening, and the inner frame 12 and the front frame 14 are closed. continue. In addition, when the inner frame 12 and the front frame 14 are closed, the voltage output from the OUT terminal of the timer IC1 becomes about 10.6 volts, and the drain terminal D and the source terminal S of the FET1 become conductive. , The switch SW1 and the switch SW2 are in a cutoff state. Therefore, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET1 are conducted, but no current is supplied from the DC power supply DC1 or the capacitor CD1 and the base of the transistor TR1 is not supplied. The voltage between terminal b and emitter terminal e is zero volts. Therefore, since the emitter terminal e and the collector terminal c of the transistor TR1 are cut off, the inner frame 12 or the front frame 14 is opened, and the capacitor CD4 is stored in the same manner as when about 4.4 seconds have passed since the opening. The discharged power is discharged to supply power to the power output terminal and the reset IC 2. Here, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET2 become conductive as in the FET1, and the power failure signal SG1b is output from the power failure signal output terminal. In this case, the power failure signal SG1b is not output from the power failure signal output terminal because the drain terminal D and the source terminal S of the FET3, which will be described later, become conductive. This description will be described later.

It should be noted that when the electric power stored in the capacitor CD4 becomes zero, the discharge naturally ends (stops). As a result, the power supplied from the capacitor CD4 to the power output terminal and the reset IC 2 is also stopped.

Like the FET1, the FET2 is an N-MOS switching element that switches between conduction and interruption by the voltage output from the OUT terminal of the timer IC1, and the drain terminal D of the FET2 is connected to the other end of the resistor R4 of 100 kΩ. It One end of the resistor R4 is connected to one end of the capacitor CD4, the collector terminal c of the transistor TR1, the anode terminal of the diode D3 and the anode terminal of the diode D4. Further, the source terminal S of the FET2 is connected to the anode terminal of the diode D5 for backflow prevention and one end of the resistor R5 of 100 MΩ. The other end of the resistor R5 is grounded. The cathode terminal of the diode D5 is connected to the power failure signal output terminal.

When the voltage output from the OUT terminal of the timer IC1 is about 10.6 volts, the FET2 (when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds after the opening) When the inner frame 12 and the front frame 14 are closed), the drain terminal D and the source terminal S of the FET 2 are brought into conduction. On the other hand, when the voltage output from the OUT terminal of the timer IC1 is zero volt (when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed after the opening), the FET2 is FET2. The drain terminal D and the source terminal S of the above are cut off.

NOTIC3 is a logical NOT circuit that applies a voltage to the gate terminal G of the FET3. The input terminal of the NOTIC3 is connected to the other end of the switch SW1, the other end of the switch SW2, one end of the resistor R1, one end of the resistor R2 and one end of the resistor R3. The power supply terminal of the NOTIC3 is connected to one end of the capacitor CD1 although not shown. Therefore, when the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and a voltage of about 11.3 volts is applied to the input terminal of the NOTIC3, zero voltage is applied from the output terminal of the NOTIC3. Is output. On the other hand, when the inner frame 12 and the front frame 14 are closed, the switches SW1 and SW2 are cut off, and when zero volt is applied to the input terminal of the NOTIC3, a voltage of about 11.3 volts is output from the output terminal of the NOTIC3. Is output.

The FET 3 is an N-MOS switching element that controls the power failure signal SG1b output from the power interruption signal output terminal. The gate terminal G of the FET3 is connected to the output terminal of the NOTIC3. Further, the drain terminal D of the FET3 is connected to the anode terminal of the diode D5, and the source terminal S of the FET3 is grounded. Therefore, when zero volt is output from the output terminal of the NOTIC3, that is, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 becomes conductive, the drain terminal D and the source terminal S of the FET3 are The connection with is cut off. Therefore, when the inner frame 12 or the front frame 14 is opened, the power failure signal SG1b can be output from the power failure signal output terminal. On the other hand, when a voltage of about 11.3 V is output from the output terminal of NOTIC3, that is, when the inner frame 12 and the front frame 14 are closed and the switches SW1 and SW2 are cut off, the drain of the FET3 The terminals D and the source terminal S are electrically connected to each other. Therefore, when the inner frame 12 or the front frame 14 is closed, the power failure signal SG1b cannot be output from the power failure signal output terminal.

Here, as for the operation of the FET2 and the FET3, three scenes will be described in time series as in the case of the FET1. First, the operation of the FET 2 and the FET 3 from when the inner frame 12 or the front frame 14 is opened until a lapse of about 4.4 seconds will be described. When the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is in a conductive state. Therefore, until about 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened (the switch Until about 4.4 seconds have passed since the switch SW2 or the switch SW2 was turned on), the current supplied from the DC power supply DC1 or the capacitor CD1 is supplied to the drain terminal D of the FET2 and the source of the FET2 via the resistor R4. It passes through between the terminals S and flows into the resistor R5. At this time, as described above, the voltage at the collector terminal c of the transistor TR1 is about 5.7 volts, so the voltage applied to one end of the resistor R4 is also about 5.7 volts. Here, when the drain terminal D and the source terminal S of the FET 2 are in a conductive state, the impedance between the drain terminal D and the source terminal S of the FET 2 is about several Ω. On the other hand, since the inner frame 12 or the front frame 14 is open, the conduction between the drain terminal D and the source terminal S of the FET 3 is cut off. Therefore, the voltage of about 5.7 volts applied to one end of the resistor R4 is divided by the resistors R4 and R5. The resistance ratio of the resistors R4 and R5 is 1:1000. Therefore, until about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened, the voltage applied to the resistor R5 is about 5.7 volts which is almost the same as the limit voltage of the Zener diode D2. Becomes By this operation, the power failure signal SG1b is output from the power failure signal output terminal until about 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened. At this time, the power failure signal SG1b output from the power interruption signal output terminal is about 5.0 V obtained by subtracting about 0.7 V of the voltage drop at the diode D5 from about 5.7 V applied to the resistor R5. Becomes

In addition, until about 4.4 seconds have passed since the inner frame 12 or the front frame 14 was opened (until about 4.4 seconds have passed since the switch SW1 or the switch SW2 became conductive), the DC power supply DC1 Alternatively, the voltage supplied from the capacitor CD1 is applied to the power supply signal output terminal via the diode D3 and is applied to the input terminal IN of the reset IC via the diode D4. Therefore, the drive voltage is output from the power supply signal output terminal, and the reset signal SG3b is also output from the reset signal output terminal.

Next, the operation of the FET 2 and the FET 3 when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed from the opening will be described. When the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed after the opening, the drain terminal D and the source terminal S of the FET 2 are cut off. At this time, as described above, since the conduction between the drain terminal D and the source terminal S of the FET1 is also cut off, even if the switch SW1 or the switch SW2 is in the conduction state, the emitter terminal e and the collector terminal of the transistor TR1 are c is cut off. As a result, the voltage supply from the DC voltage DC1 or the capacitor CD1 is stopped. By stopping this voltage supply, the discharge of the capacitor CD4 is started. Here, if the drain terminal D and the source terminal S of the FET 2 are in the cutoff state, even if the conduction between the drain terminal D and the source terminal S of the FET 3 is in the cutoff state, the voltage due to the discharge of the capacitor CD4 is not charged. No signal is applied to the signal output terminal. Therefore, the power failure signal SG1b output from the power failure signal output terminal is in a stopped state. On the other hand, the voltage accompanying the discharge of the capacitor CD4 is applied to the power supply output terminal via the diode D3, and is also applied to the input terminal IN of the reset IC via the diode D4. By this operation, the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds after the opening, the power failure signal SG1b output from the power interruption signal output terminal is in the stopped state, while it is output from the power supply output terminal. The drive voltage Vb and the reset signal SG3b output from the reset signal output terminal are continuously output. When the power stored in the capacitor CD4 becomes zero due to discharge, the drive voltage Vb and the reset signal SG3b output from the power supply output terminal are stopped.

Finally, the operation of the FET2 and FET3 when the inner frame 12 and the front frame 14 are closed will be described. When the inner frame 12 and the front frame 14 are closed, the voltage output from the OUT terminal of the timer IC1 becomes about 10.6 volts, and the drain terminal D and the source terminal S of the FET2 become conductive, but the switch SW1 and the switch SW1 SW2 is in the cutoff state. Therefore, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 2 are electrically connected, but no power is supplied from the DC power source DC1 or the capacitor CD1 and the capacitor CD4 The discharge is continued. Here, since the drain terminal D and the source terminal S of the FET2 are electrically connected, a path is generated in which a current accompanying the discharge of the capacitor CD4 flows into the resistor R5. However, in this case, since the inner frame 12 and the front frame 14 are closed, the terminals between the drain terminal D and the source terminal S of the FET 3 are also in a conductive state. When the drain terminal D and the source terminal S of the FET 3 are brought into conduction, the impedance between the drain terminal D and the source terminal S of the FET 3 becomes about several Ω, which is more than the resistance value of the resistor R5 of 100 MΩ. It is a sufficiently small value. Therefore, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 2 are electrically connected to each other to generate a path in which a current accompanying the discharge of the capacitor CD4 flows into the resistor R5. The current accompanying the discharge of CD4 flows into the drain terminal D of the FET3, so that no current also flows into the resistor R5. As a result, the power failure signal SG1b is not output from the power failure signal output terminal. Therefore, when the inner frame 12 and the front frame 14 are closed, the power failure signal SG1b output from the power interruption signal output terminal is in a stopped state, while the drive voltage Vb and the reset signal output terminal output from the power supply output terminal are stopped. The reset signal SG3b output from is continuously output. As described above, when the electric power stored in the capacitor CD4 becomes zero due to discharging, the drive voltage Vb and the reset signal SG3b output from the power supply output terminal are stopped.

If the voltage input to the input terminal IN exceeds 4.3 V, the reset IC 2 outputs the voltage input to the input terminal IN as it is from the output terminal OUT, while the voltage input to the input terminal IN The reset semiconductor circuit stops the voltage output from the output terminal OUT (sets the output voltage of the output terminal OUT to zero volt) when the voltage becomes 4.3 V or less. The input terminal IN of the reset IC 2 is connected to the cathode terminal of the diode D4 for backflow prevention. The anode terminal of the diode D4 is connected to the anode terminal of the diode D3 for backflow prevention, and is also connected to one end of the resistor R4, one end of the capacitor CD4 and the collector terminal c of the transistor TR1. The cathode terminal of the diode D3 is connected to the power output terminal. The output terminal OUT of the reset IC 2 is connected to the reset signal output terminal.

Although the output terminal OUT of the reset IC 2 is directly connected to the reset signal output terminal, a backflow prevention diode may be connected to the output terminal OUT of the reset IC 2. In this case, the anode terminal of the backflow prevention diode may be connected to the output terminal OUT of the reset IC 2, and the cathode terminal of the backflow prevention diode may be connected to the reset signal output terminal.

Here, the operation of the reset IC 2 will be described. When the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds have passed after the opening, the capacitor CD4 discharges the stored power and starts supplying power to the power output terminal and the reset IC 2. Since the electric power supplied from the capacitor CD4 decreases with the discharging time, the voltage generated by the discharging of the capacitor CD4 also decreases with the discharging time. Since only the backflow preventing diode D3 is connected between the power supply output terminal and the capacitor CD4, the voltage (driving voltage Vb) output to the power supply output terminal is generated by discharging the capacitor CD4. The voltage drops from the voltage by the forward voltage of the diode D3 (about 0.7 V). On the other hand, a reset IC 2 is connected between the reset signal output terminal and the capacitor CD4 in addition to the diode D4 for backflow prevention. As a result, the voltage output to the reset signal output terminal (reset signal SG3b) is about 4. The voltage dropped by the forward voltage of the diode D4 (about 0.7 V) from the voltage generated by the discharge of the capacitor CD4 is about 4. If the voltage exceeds 3 volts, that is, if the voltage input to the input terminal IN of the reset IC 2 exceeds approximately 4.3 volts, the voltage itself is input. On the other hand, when the voltage dropped by the forward voltage of the diode D4 from the voltage generated by the discharge of the capacitor CD4 is about 4.3 V or less, that is, the voltage input to the input terminal IN of the reset IC2. Is about 4.3 volts or less, the voltage output to the reset signal output terminal is zero volts.

Thus, if the voltage input to the input terminal IN exceeds about 4.3 volts, the reset IC 2 outputs the voltage input to the input terminal IN as it is from the output terminal OUT to the reset signal output terminal. While the voltage is being output (while the reset signal SG3b is being output), when the voltage input to the input terminal IN is about 4.3 V or less, the voltage output from the output terminal OUT is stopped and the reset signal output terminal is output. The output voltage is set to zero volt (the reset signal SG3b is stopped). Since the voltage (driving voltage Vb) output to the power supply output terminal can be 4.3 volts or less, the voltage generated by discharging the capacitor CD4 even after the voltage output from the reset signal output terminal becomes zero volts. Is continuously output until the voltage reaches zero volt.

Here, in order to normally terminate the MPU 201, when the driving voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, first, the MPU 201 is reset during the period of 10 clocks of the operation clock of the MPU 201. The reset signal SG3b input to the terminal is stopped to make the operation processing inexecutable, and then the drive voltage supplied to the power supply terminal of the MPU 201 is set to about 4.0 V or less to make the operation inoperable. There is a need. For example, if the operation clock of the MPU 201 is 100 MHz, in order to normally terminate the MPU 201, when the drive voltage Vb of 5 V is supplied to the power supply terminal of the MPU 201, first, the MPU 201 is input to the reset terminal of the MPU 201. The reset signal SG3b is stopped for at least 100 n seconds to make the arithmetic processing inexecutable, and then the drive voltage Vb supplied to the power supply terminal of the MPU 201 is set to about 4.0 V or less to make it inoperable. There is a need to. In order to realize this, in the frame opening detection circuit 260, first, the voltage input to the input terminal IN of the reset IC 2 is set to about 4.3 V or less, and the reset signal SG3b output from the reset signal output terminal is stopped. As a result, the MPU 201 is set in a state in which the arithmetic processing cannot be executed, and then the drive voltage Vb output from the power supply output terminal is set to about 4.0 V or less to set the MPU 201 in an inoperable state. Here, in the frame open detection circuit 260, after the reset signal SG3b output from the reset signal output terminal is stopped, the drive voltage Vb output from the power supply output terminal is reduced to about 4.0 volts or less. The period of 0.5 seconds is secured. As a result, even when the MPU 201 is temporarily activated by the frame opening detection circuit 260 when the pachinko machine 10 is powered off, the frame opening detection circuit 260 normally terminates the MPU 201 that has started up. You can

Further, when the voltage input to the input terminal IN of the reset IC 2 exceeds 4.3 volts, when the voltage is input to the input terminal IN of the reset IC 2, a delay of about 40 μsec occurs from the input of the voltage. Then, a voltage is output from the output terminal OUT. Due to the delay characteristic of the reset IC 2, the reset signal SG3b output to the reset signal output terminal is output about 40 μsec later than the drive voltage Vb output to the power supply output terminal.

Here, in order to normally start up the MPU 201, first, a drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201 to make the MPU 201 operable, and thereafter, at least 10 operating clocks of the MPU 201 are used. It is necessary to input the reset signal SG3b to the reset terminal of the MPU 201 after a period of (2) to make the arithmetic processing executable. For example, in order to normally start up the MPU 201 in which the operation clock of the MPU 201 is 100 MHz, first, the drive voltage Vb of 5 V is supplied to the power supply terminal of the MPU 201 to make the MPU 201 operable, and then at least 100 nsec. It is necessary to input the reset signal SG3b to the reset terminal of the MPU 201 after a period of (2) to make the arithmetic processing executable. In order to realize this, the frame open detection circuit 260 first outputs the drive voltage Vb of about 5 V from the power supply output terminal, and outputs the reset signal SG3b from the reset signal output terminal about 40 μsec after the output. As a result, even when the MPU 201 is temporarily activated by the frame opening detection circuit 260 when the power of the pachinko machine 10 is off, the activation can be normally performed.

The TH terminal of the timer IC1 is a terminal for measuring the voltage applied to the TH terminal, and is connected to the other end of the resistor R1, one end of the capacitor CD2, and the DCH terminal of the timer IC1. The DCH terminal of the timer IC1 has a voltage (about 7.5 volts) that is 2/3 of the DC voltage (about 11.3 volts) applied to the VDD terminal of the timer IC1 when the voltage applied to the TH terminal of the timer IC1. In this case, the impedance of the DCH terminal is switched from the infinite state to the zero state. When the impedance of the DCH terminal becomes zero (ground state), the voltage cannot be applied to the capacitor CD2. On the other hand, when the impedance of the DCH terminal is infinite, a voltage can be applied to the capacitor CD2.

The resistor R1 and the capacitor CD2 connected to the TH terminal of the timer IC1 and the DCH terminal of the timer IC1 open the inner frame 12 or the front frame 14 based on the time constant which is the product of the resistance value of the resistor R1 and the capacitor CD2. In this case, it is a part for determining a period of about 4.4 seconds until the voltage of about 10.6 V output from the OUT terminal of the timer IC 1 is switched to zero V. One end of the resistor R1 is connected to the other end of the switch SW1, the other end of the switch SW2, one end of the resistor R2, the input terminal of the NOTIC3, one end of the resistor R3 and the emitter terminal e of the transistor TR1. The other end of the resistor R1 is connected to the TH terminal of the timer IC1, the DCH terminal of the timer IC1, and one end of the capacitor CD2. The other end of the capacitor CD2 is grounded.

Here, the resistor R1 and the capacitor CD2 will be described together with the TRG terminal of the timer IC1, the TH terminal of the timer IC1, the DCH terminal of the timer IC1 and the OUT terminal of the timer IC1.

Since the voltage is not supplied to the resistor R1 when the inner frame 12 and the front frame 14 are in the closed state (when the switch SW1 and the switch SW2 are in the cutoff state), the voltage applied to the TH terminal of the timer IC1 is zero volt (about 7.5 volt). Less than) and the impedance of the DCH terminal of the timer IC1 is set to infinity. Therefore, a voltage can be applied to the capacitor CD2, and the capacitor CD2 is in a chargeable state (a state in which electric charge can be stored). However, when the switches SW1 and SW2 are cut off, the connection between the one end of the capacitor CD1 and the resistor R1 is cut off, so that no voltage is applied to the capacitor CD2 and the voltage applied to the capacitor CD2 is zero volt. Becomes Thus, the capacitor CD2 is in a chargeable state but is not charged. At this time, the voltage of the OUT terminal of the timer IC1 is about 10.6 volts, and the voltage between the drain terminal D and the source terminal S of the FET1 and the voltage between the drain terminal D and the source terminal S of the FET2 is reduced. There is continuity. However, since the switches SW1 and SW2 are in the cutoff state, no voltage is generated in the resistor R3 (between the base terminal b and the emitter terminal e of the transistor TR1), and the emitter terminal e and the collector terminal c of the transistor TR1 are not generated. And are cut off. Since the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal D of the FET 3 are electrically connected. Therefore, the power from the capacitor CD4 can be supplied to the power supply output terminal and the reset IC 2 excluding the power failure signal output terminal (when the power stored in the capacitor CD4 becomes zero due to discharge, No supply).

Next, when the inner frame 12 or the front frame 14 is opened (see FIG. 5B) and the switch SW1 or the switch SW2 is turned on, the voltage applied to the TRG terminal of the timer IC1 starts from zero volt. Switch to about 11.3 volts. At this time, the voltage of the OUT terminal of the timer IC1 is about 10.6 volts, and the drain terminal D and the source terminal S of the FET1 and the drain terminal D and the source terminal S of the FET2 are electrically connected. doing. Then, a voltage is generated in the resistor R3 (between the base terminal b and the emitter terminal e of the transistor TR1), and the emitter terminal e and the collector terminal c of the transistor TR1 are electrically connected. As a result, a voltage of about 5.7 volts is generated at the collector terminal c of the transistor TR1, and the generated voltage becomes about 5.0 volts via the diode D3 and is output to the power output terminal. The voltage of about 5.7 volts generated at the collector terminal c of the transistor TR1 becomes about 5.0 volts via the diode D4 and the reset IC2 and is output to the reset signal output terminal. In addition, since the inner frame 12 or the front frame 14 is in an open state and the drain terminal D and the source terminal D of the FET 3 are in a cutoff state, the voltage of about 5.7 volts generated at the collector terminal c of the transistor TR1 is generated. The voltage becomes about 5.0 V through the diode D5 and is output to the power interruption signal output terminal. Further, the capacitor CD4 is started to be charged by the voltage of about 5.7 volts generated at the collector terminal c of the transistor TR1.

Further, at the same time that the voltage applied to the TRG terminal of the timer IC1 is switched from zero volt to about 11.3 volt, the voltage is applied to the capacitor CD2 and the charging of the capacitor CD2 is started. At this time, the voltage applied to the TH terminal of the timer IC1 starts rising.

Regarding the voltage of the OUT terminal of the timer IC1, the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD2) is 2/the voltage (approximately 11.3 volts) input to the VDD terminal of the timer IC1. Continue to hold about 10.6 volts until it equals a voltage of 3, ie about 7.5 volts. When the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD2) rises and becomes equal to about 7.5 volts, the impedance of the DCH terminal of the timer IC1 changes from an infinite state to a zero state (ground). State). Then, the voltage applied to the capacitor CD2 is in a zero volt state, and the electric charge stored in the capacitor CD2 is discharged. As a result, the voltage applied to the TH terminal of timer IC1 switches from about 7.5 volts to zero volts. Due to the switching of the voltage applied to the TH terminal of the timer IC1, the voltage of the OUT terminal of the timer IC1 switches from about 10.6 volt to zero volt. Then, conduction between the drain terminal D and the source terminal S of the FET1 and between the drain terminal D and the source terminal S of the FET2 is cut off, and the resistance R3 (the base terminal b and the emitter terminal e of the transistor TR1 is disconnected). The voltage generated between the terminals) becomes zero volts. As a result, the capacitor CD4 discharges the stored power and supplies the power to the power output terminal and the reset IC2.

In this way, when the inner frame 12 or the front frame 14 is in the open state and the switch SW1 or the switch SW2 is in the conductive state (see FIG. 5B), it is output from the OUT terminal of the timer IC1. A period until the voltage of about 10.6 V is switched to zero V, that is, a period until the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD2) changes from zero V to about 7.5 V. , 4.4 seconds based on the time constant which is the product of the resistance value of the resistor R1 and the capacitance of the capacitor CD2. Then, the frame open detection circuit 260 outputs a voltage to the power supply output terminal, the reset signal output terminal, and the power failure signal output terminal for about 4.4 seconds when the inner frame 12 or the front frame 14 is opened. To do. Then, when about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened, the frame open detection circuit 260 detects the voltage of about 10.6 volts output from the OUT terminal of the timer IC 1. The voltage is switched to zero volt, the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off, the voltage output to the power interruption signal output terminal is stopped, and the discharge of the capacitor CD4 is started. As a result, the frame open detection circuit 260 causes the power supply output terminals other than the power failure signal output terminal due to the discharge of the capacitor CD4 when about 4.4 seconds have elapsed after the inner frame 12 or the front frame 14 was opened. And outputs a voltage to the reset signal output terminal. As described above, when the voltage input to the input terminal IN of the reset IC 2 becomes approximately 4.3 V or less due to the discharge of the capacitor CD4, the reset IC 2 outputs the voltage output from the output terminal OUT, that is, the reset signal output. Set the terminal voltage to zero volts. On the other hand, the voltage of the power output terminal is output until the discharge by the capacitor CD4 is stopped. Therefore, when about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened, the frame open detection circuit 260 first outputs the voltage (power failure signal SG1b) output to the power interruption signal output terminal. Then, the voltage output to the reset signal output terminal (reset signal SG3b) is stopped, and finally the voltage output to the power supply output terminal (drive voltage Vb) is stopped. Therefore, the frame opening detection circuit 260 can normally end the started MPU 201 even if the MPU 201 is temporarily started while the pachinko machine 10 is powered off.

After about 4.4 seconds have passed since the inner frame 12 or the front frame 14 was opened, the inner frame 12 and the front frame 14 are changed from the open state to the closed state (switch SW1 and switch SW2 are disconnected from the conductive state). State), that is, when the voltage applied to the TRG terminal of the timer IC1 switches from about 11.3 volts to zero volts, the voltage of the OUT terminal of the timer IC1 switches from zero volts to about 10.6 volts. In this state, as described above, the terminals between the drain terminal D and the source terminal S of the FET1 and the terminals between the drain terminal D and the source terminal S of the FET2 are in conduction, but the switches SW1 and SW2 are cut off. Since it is in the state, no electric power is supplied from the DC power source CD1 or the capacitor CD1, and the discharging state of the capacitor CD4 continues. When the inner frame 12 or the front frame 14 is closed, the drain terminal D and the gate terminal S of the FET 3 are electrically connected, so that the voltage due to the discharge of the capacitor CD4 is the power output terminal and the power output terminal except the power interruption signal output terminal. It is applied to the input terminal IN of the reset IC 2.

Here, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and before the elapse of about 4.4 seconds from the opening, the inner frame 12 and the front frame 14 are closed, When the switch SW1 and the switch SW2 are cut off, the voltage of the OUT terminal of the timer IC1 does not switch to zero volt and remains about 10.6 volt. However, also in this case, the frame open detection circuit 260 can stop the power failure signal SG1b, then the reset signal SG3b, and finally the drive voltage Vb. This case will be described. First, when the inner frame 12 or the front frame 14 is in the open state and the switch SW1 or the switch SW2 is conductive, the frame open detection circuit 260 causes the power supply output terminal, the reset signal output terminal, and the power failure signal output as in the above description. The voltage is output to the terminal and the capacitor CD4 is charged. When the inner frame 12 and the front frame 14 are closed within about 4.4 seconds from the open state, the switch SW1 and the switch SW2 are switched from the conductive state to the cutoff state, so that the emitter terminal e and the collector terminal c of the transistor TR1 are closed. Then, the conduction with and is cut off, and the discharge of the capacitor CD4 is started. Here, since the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 3 are electrically connected. Therefore, when the inner frame 12 and the front frame 14 are closed, the voltage due to the discharge of the capacitor CD4 is not applied to the power interruption signal output terminal, and the power failure signal SG1b is stopped. On the other hand, the voltage generated by discharging the capacitor CD4 is applied to the power supply output terminal and the input terminal IN of the reset IC 2. After that, the voltage accompanying the discharge of the capacitor CD4 decreases with the passage of time, the reset signal SG3b output from the reset signal output terminal is stopped, and finally the drive voltage Vb output from the power supply output terminal is stopped. .. By this operation, even if the inner frame 12 and the front frame 14 are closed within about 4.4 seconds after the inner frame 12 or the front frame 14 is opened, the frame open detection circuit 260 first detects It is possible to stop the power failure signal SG1b, then the reset signal SG3b, and finally the drive voltage Vb. Therefore, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds after the opening, the inner frame 12 and the front frame 14 are closed, and the switch is turned on. Even when the switch SW1 and the switch SW2 are cut off, the frame opening detection circuit 260 can normally end the started MPU 201 even if the MPU 201 is temporarily started.

Returning to the explanation of FIG. The CNT terminal of the timer IC1 is a terminal that adjusts the output period of the voltage output from the OUT terminal of the timer IC1 according to the signal input to the CNT terminal. The CNT terminal of the timer IC1 is connected to one end of the capacitor CD3. The other end of this capacitor CD3 is grounded. In the frame opening detection circuit 260, the output period of the voltage output from the OUT terminal of the timer IC1 is not adjusted (the output period of the voltage output from the OUT terminal of the timer IC1 is fixed to about 4.4 seconds). The CNT terminal of the timer IC1 is grounded in an alternating current by the capacitor CD3.

As described above, when the power of the pachinko machine 10 is off, the frame opening detection circuit 260 opens the inner frame 12 or the front frame 14 and turns on the switch SW1 or the switch SW2 (FIG. 5(b)), the power supply output terminal, the reset signal output terminal and the power failure signal output terminal. On the other hand, the frame open detection circuit 260 first stops the voltage (power failure signal SG1b) output to the power interruption signal output terminal when about 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened. At the same time, the capacitor CD4 is started to discharge, after that, the voltage (reset signal SG3b) output to the reset signal output terminal is stopped, and finally the drive voltage Vb output to the power supply output terminal is stopped. Therefore, even if the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started up when the power of the pachinko machine 10 is off, the frame open detection circuit 260 does not restart the MPU 201 that has started up. It can be terminated normally.

Although the details will be described later, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame opening detection circuit 260, so that the pachinko machine 10 is activated. 10 turns on the open-middle frame open flag 203a. By turning on the off-frame open flag 203a, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off. Further, as will be described later in detail, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame open detection circuit 260. In addition to turning on the in-off-frame flag 203a, the switch 10 outputs a pulse signal having a pulse width of 1 msec to the hall computer 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours.

Here, there is a case where the game hall has a crime prevention contract with a private security company, and in this case, when there is an intruder in the game hall, the guard of the security company immediately rushes to the game hall. However, since fraudulent acts are carried out in a short time, in most cases the intruder has already escaped from the playground when the guards rush. Therefore, even if a security contract is made with a private security company, it is impossible to determine which pachinko machine 10 has been fraudulent. The pachinko machine 10 that has been cheated must return to a normal state, but if you do not know which pachinko machine 10 has been cheated, the inner frame 12 and the front frame 14 of all the pachinko machines 10 must be removed. It had to be opened and inspected one by one, and performing this work at a game hall where a large number of pachinko machines 10 were installed was a considerable heavy labor.

However, according to the pachinko machine 10 of the present embodiment, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame open detection circuit 260. Then, in addition to turning on the off-inside frame open flag 203a, a pulse signal having a pulse width of 1 msec is output to the hall computer 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours. Therefore, the pachinko machine 10 in which the inner frame 12 or the front frame 14 has been opened can be specified also by the pulse signal stored in the hall computer 262. Furthermore, by storing the pulse signal output from the pachinko machine 10 to the hall computer 262 and storing the output time of the output pulse signal, the opening time of the inner frame 12 or the front frame of the specified pachinko machine 10 is stored. The opening time of 14 can be detected.

However, as described above, when the power of the pachinko machine 10 is off, when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily activated by the frame open detection circuit 260, the open middle frame is opened. Since the flag 203a is turned on, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off, without using the hall computer 262. is there. Therefore, according to the pachinko machine 10 of this embodiment, the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off, even in a game hall where the hall computer 262 is not operated for 24 hours. Then, the pachinko machine 10 can be specified.

Further, as described above, since the frame open detection circuit 260 is provided with the 1F capacitor CD1, the frame open detection circuit 260 supplies power to the pachinko machine 10, and the DC power supply DC1 supplies 12V. When the DC voltage is supplied, the operation is naturally performed, and further, for example, after the business hours of the amusement park are finished, the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12V is supplied from the DC power supply DC1. Even when the opening is not performed, the opening of the inner frame 12 and the opening of the front frame 14 can be detected and the MPU 201 can be started up for a certain period of time.

In addition, for example, when the power supply to the pachinko machine 10 is cut off after the business hours of the amusement hall are finished and the DC voltage is supplied from the capacitor CD1 to the frame open detection circuit 260, the inner frame 12 or the front frame 14 is When the total supply period of the current from the capacitor CD1 associated with opening is extended or the number of times the opening of the inner frame 12 or the front frame 14 is detected is increased, the capacity of the capacitor CD1 is increased (for example, the capacitor The capacity of CD1 is set to 10 F), and the capacitor CD1 may be changed to a secondary battery having a large amount of stored electricity.

However, the power consumption of the capacitor CD1 by the frame opening detection circuit 260 when the power of the pachinko machine 10 is off and the inner frame 12 and the front frame 14 are closed is the standby power of the timer IC1 and the power consumption of the NOTIC3. However, it does not cause a significant reduction in the amount of charge of the capacitor CD1. Moreover, since a voltage is only applied to each gate terminal G of the FET1 to FET3, the power consumed by the FET1 to FET3 is very small. Therefore, by setting the capacity of the capacitor CD1 to 1F which is widely used, the frame open detection circuit 260 can be manufactured at low cost.

Further, in the door opening detection circuit 260, a circuit for detecting the opening of the inner frame 12 or the opening of the front frame 14 and making the transistor TR1 conductive for about 4.4 seconds is realized by using the LMC555 for the timer IC1. It is not limited to. That is, by using another integrated circuit or the like for the timer IC 1, a circuit that generates one pulse signal for one opening of the inner frame 12 or one opening of the front frame 14 is realized. It is sufficient that the transistor TR1 is energized for a predetermined period based on the pulse signal.

Next, referring to FIG. 8, when one of the inner frame 12 or the front frame 14 is opened and both the inner frame 12 and the front frame 14 are opened while the pachinko machine 10 is powered off. The case will be described. FIG. 8 shows the voltage of the TRG terminal of the timer IC1 and the voltage of the OUT terminal of the timer IC1, which change depending on the state of the switch SW1 (state of the inner frame 12) and the state of the switch SW2 (state of the front frame 14). , The voltage of the capacitor CD4, the voltage of the power supply output terminal of the frame open detection circuit 260 (output voltage to the multiplexer MP3), and the voltage of the reset signal output terminal of the frame open detection circuit 260 (to the multiplexer MP2 and the input/output port 205). 7 is a timing chart showing the relationship between the output voltage) and the voltage of the power failure signal output terminal of the frame open detection circuit 260 (output voltage to the multiplexer MP1). 8A is an enlarged view of the voltage of the reset signal output terminal of the frame open detection circuit 260, which changes from t1 time to about 0.01 seconds later. In A of FIG. 8(f), the voltage of the reset signal output terminal from t1 time to about 0.01 seconds is illustrated, but from t3 time to about 0.01 seconds, from t5 time to about 0.01 seconds. The voltage of the reset signal output terminal from after t7 to about 0.01 seconds after t7 has the same waveform as the voltage of the reset signal output terminal from t1 after about 0.01 seconds, and therefore is not shown. doing.

First, as shown in FIG. 8A, when the switch SW1 is turned on (the inner frame 12 is opened) at t1, the TRG terminal voltage of the timer IC1 is t1 as shown in FIG. 8C. At times, it switches from zero volts to about 11.3 volts. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds elapse from t1. As a result, the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7) are brought into conduction, and charging of the capacitor CD4 (see FIG. 7) is started (at t1), as shown in FIG. 8(e). .. Note that this charging is completed in about 0.01 seconds after the switch SW1 becomes conductive as shown in FIG. 8(e). When the charging of the capacitor CD4 is completed, the voltage of the capacitor CD4 becomes about 5.7 volts as shown in FIG. 8(e). It takes about 0.01 seconds to charge the capacitor CD4, but it is physically impossible to open and close the inner frame 12 or the front frame 14 within about 0.01 seconds. Therefore, when the inner frame 12 or the front frame 14 is opened, the charging of the capacitor CD4 is always completed.

Further, the voltage at the power output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I23 of the multiplexer MP3) starts rising at t1 and is about 0 from t1 as shown in FIG. 8(f). It will be about 5.0 volts after 0.01 seconds. As a result, the drive voltage Vb of about 5.0 V is started to be output from the power supply output terminal of the frame open detection circuit 260. Further, the voltage of the reset signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I22 of the multiplexer MP2 and the input/output port 205) is as shown in A of FIGS. 8(g) and 8(f). , About 40 μsec after t1 and starts to rise, and reaches about 5.0 volts about 0.01 sec after t1. As a result, the reset signal SG3b is started to be output from the reset signal output terminal of the frame opening detection circuit 260. The voltage rise at the reset signal output terminal of the frame open detection circuit 260 is about 40 μs after t1 due to the delay characteristic of the reset IC 2 (see FIG. 7) described above. As shown in FIGS. 8F and 8G, the voltage rise at the power supply output terminal of the frame opening detection circuit 260 is about 40 μsec earlier than the voltage rise at the reset signal output terminal of the frame opening detection circuit 260. , The drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, and then the reset signal SG3b is input to the reset signal output terminal of the MPU 201. Therefore, when the pachinko machine 10 is powered off, the frame opening detection circuit 260 can normally start up the MPU 201 when it is temporarily started up.

Although the details will be described later, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame opening detection circuit 260, so that the pachinko machine 10 is activated. 10 turns on the open-middle frame open flag 203a. By turning on this off-inside frame opening flag 203a, the pachinko machine 10 in which the inner frame 12 or the front frame 14 has been opened can be specified. Further, as will be described later in detail, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame opening detection circuit 260, so that the pachinko machine 10 is activated. 10 outputs a pulse signal having a pulse width of 1 msec to the hall computer 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours.

Further, as shown in FIG. 8E, when the voltage of the capacitor CD4 becomes about 5.7 volts, the voltage of the power failure signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I21 of the multiplexer MP1). As shown in FIG. 8(h), the voltage starts rising at t1 and reaches about 5.0 volts approximately 0.01 seconds after t1. Here, since the switch SW1 is in the conducting state (the inner frame 12 is in the open state), the drain terminal D and the source terminal S of the FET3 are cut off from each other. As a result, the power failure signal SG1b is started to be output from the power failure signal output terminal of the frame opening detection circuit 260.

Then, when about 4.4 seconds elapse from the time t1, the timer IC1 switches the voltage of the OUT terminal from about 10.6 volts to zero volts, as shown in FIG. Then, the conduction between the drain terminal D and the source terminal S of the FET1 is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7) is cut off, so that the charging of the capacitor CD4 is completed. To do. Then, since the discharge of the capacitor CD4 is started, the voltage of the capacitor CD4 starts to drop (after elapse of about 4.4 seconds from t1) as shown in FIG. 8(e). Following this, as shown in FIG. 8(f), the voltage of the power output terminal of the frame open detection circuit 260 (driving voltage Vb with a maximum value of about 5.0 volts) starts to drop (from t1). After about 4.4 seconds). Further, as shown in FIG. 8G, the voltage (reset signal SG3b) at the reset signal output terminal of the frame opening detection circuit 260 starts to drop (after about 4.4 seconds have elapsed from t1).

Note that when about 4.4 seconds have elapsed from the time t1, the conduction between the drain terminal D and the source terminal S of the FET2 is cut off, so that no current is supplied to the power failure signal output terminal of the frame open detection circuit 260. Therefore, as shown in FIG. 8(h), the voltage at the power failure signal output terminal of the frame open detection circuit 260 (power failure signal SG1b) becomes zero volts when about 4.4 seconds have elapsed from t1. Therefore, when about 4.4 seconds elapse after the inner frame 12 is opened and the switch SW1 is turned on, the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 to the NMI terminal of the MPU 201 is first , Stopped.

Next, when about 9.4 seconds have passed since t1 (about 4.4 seconds after t1 and about 5.0 seconds have passed), the voltage of the capacitor CD4 is changed as shown in FIG. 8(e). Drops to about 5.0 volts. Then, as shown in FIG. 8(f), the voltage of the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.3 volts (from t1). After about 9.4 seconds). As shown in FIG. 8(g), the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 drops to about 4.3 volts, and then the reset IC 2 operates to zero volts. (Approx. 9.4 seconds after t1). Therefore, when about 9.4 seconds have passed since the inner frame 12 was opened and the switch SW1 was turned on, the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 to the reset terminal of the MPU 201 is the power failure signal. Next to SG1b, it is stopped. As a result, the MPU 201 is set in a state in which execution of arithmetic processing is impossible (after 9.4 seconds have elapsed from t1).

Further, when about 9.9 seconds have passed from t1 (about 9.4 seconds after t1 and about 0.5 seconds have passed), the voltage of the capacitor CD4 is changed as shown in FIG. 8(e). It drops to about 4.7 volts. Then, as shown in FIG. 8(f), the voltage at the power output terminal of the frame open detection circuit 260 (driving voltage Vb with a maximum value of about 5.0 volts) drops to about 4.0 volts (from t1 time). After about 9.9 seconds). Here, the lower limit of the operating voltage of the MPU 201 is about 4.0 volts. Therefore, when about 9.9 seconds have passed since the inner frame 12 was opened and the switch SW1 was turned on, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 to the power terminal of the MPU 201 was finally changed to The MPU 201 is stopped and becomes inoperable. That is, the MPU 201 is set to the inoperable state (after about 9.4 seconds from t1 o'clock) after being set to the state in which the arithmetic processing cannot be executed (about 9.9 seconds from t1 o'clock). After the passage). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

It should be noted that, when about 20 seconds have elapsed from t1, the voltage of the capacitor CD4 becomes zero volts as shown in FIG. 8(e). Following this, the voltage of the power supply output terminal of the frame open detection circuit 260 (also the drive voltage Vb) becomes zero volts (about 20 seconds before t1). Therefore, when about 20 seconds elapse from t1, the charge amount of the capacitor CD4 becomes zero.

Finally, as shown in FIG. 8A, at time t2, when the switch SW1 is turned off (the inner frame 12 is closed), as shown in FIG. 8C, the TRG terminal voltage of the timer IC1 becomes about At the same time as switching from 11.3 volts to zero volts, the OUT terminal voltage of the timer IC1 switches from zero volts to about 10.6 volts (at t2). When the switch SW1 is turned off (the inner frame 12 is closed) at t2, the drain terminal D and the source terminal S of the FET3 are brought into conduction. As a result, the frame open detection circuit 260 is again set to a state in which the inner frame 12 and the front frame 14 can be detected.

Next, as shown in FIG. 8B, at time t3, when the switch SW2 is turned on (the front frame 14 is opened), the TRG terminal voltage of the timer IC1 becomes as shown in FIG. 8C. At t3, the voltage switches from zero volt to about 11.3 volt. At this time, as shown in FIG. 8(d), the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds elapse from t3. This causes conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7), and charging of the capacitor CD4 (see FIG. 7) is started (see FIG. 8E). t3). Note that this charging is completed in about 0.01 seconds after the switch SW2 becomes conductive as shown in FIG. 8(e). When the charging of the capacitor CD4 is completed, the voltage of the capacitor CD4 becomes about 5.7 volts as shown in FIG. 8(e).

In addition, the voltage at the power output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I2 of the multiplexer MP3) starts rising at t3 and reaches about 0 from t3, as shown in FIG. 8(f). It will be about 5.0 volts after 0.01 seconds. As a result, the drive voltage Vb having a maximum value of about 5.0 volts starts to be output from the power supply output terminal of the frame open detection circuit 260. Further, the voltage at the reset signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I2 of the multiplexer MP2 and the input/output port 205) is about 40 μs after t3 as shown in FIG. 8(g). The voltage starts to rise (see A in FIG. 8F), and becomes about 5.0 volts about 0.01 seconds after t3. As a result, the reset signal SG3 is started to be output from the reset signal output terminal of the frame opening detection circuit 260. The voltage increase at the reset signal output terminal of the frame open detection circuit 260 is about 40 μs after t3 because of the delay characteristic of the reset IC 2 (see FIG. 7) as described above. As shown in FIGS. 8F and 8G, the voltage rise at the power supply output terminal of the frame opening detection circuit 260 is about 40 μsec earlier than the voltage rise at the reset signal output terminal of the frame opening detection circuit 260. , The drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, and then the reset signal SG3b is input to the reset signal output terminal of the MPU 201. Therefore, when the pachinko machine 10 is powered off and the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily booted, the boot can be normally performed.

Further, as shown in FIG. 8E, when the voltage of the capacitor CD4 becomes about 5.7 volts, the voltage of the power failure signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I2 of the multiplexer MP1). As shown in FIG. 8(h), the voltage starts rising at t3 and reaches about 5.0 volts about 0.01 seconds after t3. Here, since the switch SW2 is in the conducting state (the front frame 14 is in the open state), the drain terminal D and the source terminal S of the FET3 are cut off from each other. As a result, the power failure signal SG1b is started to be output from the power failure signal output terminal of the frame opening detection circuit 260.

Then, when about 4.4 seconds elapse from t3, the timer IC1 switches the voltage of the OUT terminal from about 10.6 volts to zero volts as shown in FIG. 8(d). Then, the conduction between the drain terminal D and the source terminal S of the FET1 is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7) is cut off. Charging to CD4 is completed. Then, the discharge of the capacitor CD4 is started, so that the voltage of the capacitor CD4 starts to drop (after about 4.4 seconds have elapsed from t3) as shown in FIG. 8(e). Following this, as shown in FIG. 8(f), the voltage of the power supply output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) starts to drop (from t3 o'clock). After about 4.4 seconds). Further, as shown in FIG. 8G, the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 starts to drop (after about 4.4 seconds have elapsed from t3).

Note that when about 4.4 seconds elapse from t3, the conduction between the drain terminal D and the source terminal S of the FET2 is cut off, so that a current is supplied to the power failure signal output terminal of the frame open detection circuit 260. Not done. Therefore, as shown in FIG. 8(h), the voltage at the power interruption signal output terminal of the frame opening detection circuit 260 (power failure signal SG1b) becomes zero volts when about 4.4 seconds have elapsed from t3. Therefore, when about 4.4 seconds elapse after the front frame 14 is opened and the switch SW2 is turned on, the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 to the NMI terminal of the MPU 201 is first , Stopped.

Next, when about 9.4 seconds elapses from t3 o'clock (about 4.4 seconds elapses from t3 o'clock and further about 5.0 seconds elapses), as shown in FIG. Drops to about 5.0 volts. Then, as shown in FIG. 8F, the voltage of the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.3 volts (from t3 o'clock). After about 9.4 seconds). As shown in FIG. 8(g), the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 drops to about 4.3 volts, and then the reset IC 2 operates to zero volts. (After about 9.4 seconds have passed since t3). Therefore, when about 9.4 seconds have passed since the front frame 14 was opened and the switch SW2 was turned on, the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 to the reset terminal of the MPU 201 is the power failure signal. Next to SG1b, it is stopped. As a result, the MPU 201 is set in a state in which the arithmetic processing cannot be executed (after about 9.4 seconds have elapsed from t3).

Further, when about 9.9 seconds have passed from t3 o'clock (after about 9.4 seconds have passed from t3 o'clock, another 0.5 seconds have passed), the voltage of the capacitor CD4 is changed as shown in FIG. 8(e). It drops to about 4.7 volts. Then, as shown in FIG. 8F, the voltage at the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.0 volts (from t3). After about 9.9 seconds). Here, as described above, the lower limit of the operating voltage of the MPU 201 is about 4.0 volts. Therefore, when about 9.9 seconds have passed since the front frame 14 was opened and the switch SW2 was turned on, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 to the power terminal of the MPU 201 was finally changed to The MPU 201 is stopped and becomes inoperable. In other words, the MPU 201 is set to the inoperable state (after about 9.4 seconds from t3 o'clock) after being set to the state in which the arithmetic processing cannot be executed (about 9.9 seconds from t3 o'clock). After the passage). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

It should be noted that when about 20 seconds have elapsed from the time t3, the voltage of the capacitor CD4 becomes zero volts as shown in FIG. 8(e). Following this, the voltage at the power output terminal of the frame open detection circuit 260 (also the drive voltage) becomes zero volts (about 20 seconds before t3). Therefore, when about 20 seconds have passed from t3, the charge amount of the capacitor CD4 becomes zero.

Finally, as shown in FIG. 8A, at time t4, when the switch SW2 is turned off (the front frame 14 is closed), the TRG terminal voltage of the timer IC1 becomes about as shown in FIG. At the same time as switching from 11.3 volts to zero volts, the OUT terminal voltage of the timer IC1 switches from zero volts to about 10.6 volts (at t4). When the switch SW2 is turned off (the front frame 14 is closed) at t4, the drain terminal D and the source terminal S of the FET 3 are electrically connected. As a result, the frame open detection circuit 260 is again set to a state in which the inner frame 12 and the front frame 14 can be detected.

As described above, the frame open detection circuit 260 resets after outputting the drive voltage Vb and the power failure signal SG1b when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off. The signal SG3b is output. Therefore, when the pachinko machine 10 is powered off, when the MPU 201 is temporarily started up, it can be normally started up. In addition, the frame opening detection circuit 260 opens the inner frame 12 or the front frame 14 and turns on the switch SW1 or the switch SW2 when the power of the pachinko machine 10 is turned off, and about 4.4 times after the turning on. When the second has elapsed, first, the power failure signal SG1b is stopped. Then, the frame opening detection circuit 260 stops the reset signal SG3b when about 9.4 seconds have elapsed after the switch SW1 or the switch SW2 was turned on. Further, the frame open detection circuit 260 reduces the drive voltage Vb output to the power supply terminal of the MPU 201 to about 4.0 volts when about 9.9 seconds have elapsed after the switch SW1 or the switch SW2 was turned on. Therefore, even when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off, and the MPU 201 is temporarily started by the frame opening detection circuit 260, the MPU 201 that has started is normally operated. Can be ended.

As described above, the operation of the frame opening detection circuit 260 is the same when the inner frame 12 is opened and when the front frame 14 is opened. Therefore, the operation of the frame opening detection circuit 260 from t5 to t6, which will be described next, will be described only when the inner frame 12 is opened.

As shown in FIG. 8A, when the switch SW1 is in the conducting state (the inner frame 12 is in the open state) at time t5, the TRG terminal voltage of the timer IC1 is at time t5 as shown in FIG. 8C. Switching from zero volts to about 11.3 volts. At this time, as shown in FIG. 8D, the timer IC 1 continues to output a voltage of about 10.6 volts from the OUT terminal. This causes conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7), and charging of the capacitor CD4 (see FIG. 7) is started (see FIG. 8E). t5). When the charging of the capacitor CD4 is completed, the voltage of the capacitor CD4 becomes about 5.7 volts as shown in FIG. 8(e) (about 0.01 seconds after t5).

In addition, the voltage at the power output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I23 of the multiplexer MP3) starts rising at t5 and is about 0 from t5 as shown in FIG. 8(f). It will be about 5.0 volts after 0.01 seconds. As a result, the drive voltage Vb of about 5.0 V is started to be output from the power supply output terminal of the frame open detection circuit 260. The voltage at the reset signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I22 of the multiplexer MP2 and the input/output port 205) is about 40 μs after t5 as shown in FIG. 8(g). The voltage starts to rise (see A in FIG. 8F), and becomes about 5.0 volts about 0.01 seconds after t5. As a result, the reset signal SG3b is started to be output from the reset signal output terminal of the frame opening detection circuit 260. The voltage increase at the reset signal output terminal of the frame open detection circuit 260 is about 40 μs after t5 due to the delay characteristic of the reset IC 2 (see FIG. 7) as described above. As shown in FIGS. 8F and 8G, the voltage rise at the power supply output terminal of the frame opening detection circuit 260 is about 40 μsec earlier than the voltage rise at the reset signal output terminal of the frame opening detection circuit 260. , The drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, and then the reset signal SG3b is input to the reset signal output terminal of the MPU 201. Therefore, when the pachinko machine 10 is powered off and the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily booted, the boot can be normally performed.

Further, as shown in FIG. 8E, when the voltage of the capacitor CD4 becomes about 5.7 volts, the voltage of the power failure signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I21 of the multiplexer MP1). As shown in FIG. 8(h), the voltage starts rising at t5 and reaches about 5.0 volts about 0.01 seconds after t5. Here, since the switch SW1 is in the conducting state (the inner frame 12 is in the open state), the drain terminal D and the source terminal S of the FET3 are cut off from each other. As a result, the power failure signal SG1b is started to be output from the power failure signal output terminal of the frame opening detection circuit 260.

When the inner frame 12 is closed before the elapse of about 4.4 seconds from t5 o'clock (when the inner frame 12 is closed at t6 when about 3.0 seconds elapses from t5 o'clock), FIG. As shown, the timer IC1 continues to output the voltage of about 10.6 volts without switching the voltage of the OUT terminal to about 10.6 volts. At this time, the drain terminal D and the source terminal S of the FET1 remain electrically connected, but the switch SW1 is cut off as the inner frame 12 is closed, so that the emitter of the transistor TR1 (see FIG. 7) is closed. The voltage is not applied to the terminal e and the base terminal b, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off. As a result, the charging of the capacitor CD4 is completed (at t6). Then, since the discharge of the capacitor CD4 is started, the voltage of the capacitor CD4 starts to drop (at t6) as shown in FIG. 8D. Following this, as shown in FIG. 8F, the voltage of the power supply output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) starts to drop (at t6). .. Further, as shown in FIG. 8G, the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 starts to drop (at t6).

Note that when the inner frame 12 is closed and the switch SW1 is cut off (at t6), the discharge of the capacitor CD4 is started, but the voltage generated by this discharge is not supplied to the power interruption signal output terminal of the frame open detection circuit 260. Not supplied. As described above, when the inner frame 12 is closed, the switch SW1 is turned off, so that the drain terminal D and the source terminal S of the FET3 are electrically connected to each other and the capacitor CD4 is discharged. This is because the current does not flow in the resistor R5 but flows in the drain terminal D of the FET3. Therefore, as shown in FIG. 8(h), the voltage (power failure signal SG1b) at the power interruption signal output terminal of the frame open detection circuit 260 becomes zero volts at t6. Therefore, when the inner frame 12 is opened, and the switch SW1 is shut off by closing the inner frame 12 before about 4.4 seconds have passed from the opening, when the switch SW1 is shut off, the frame open detection circuit is opened. The power failure signal SG1b output from the power failure signal output terminal of 260 to the NMI terminal of the MPU 201 is first stopped.

Next, when about 5.0 seconds elapse from t6, the voltage of the capacitor CD4 drops to about 5.0 volts as shown in FIG. 8(e). Then, as shown in FIG. 8(f), the voltage at the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.3 volts (from t6 o'clock). After about 5.0 seconds). Further, as shown in FIG. 8(g), the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 drops to about 4.3 volts, and thereafter, the voltage of the reset IC 2 is reduced to zero volts. (About 5.0 seconds after t6). Therefore, about 5.0 seconds after the inner frame 12 is closed and the switch SW1 is shut off, the reset signal SG3b output from the reset signal output terminal of the frame opening detection circuit 260 to the reset terminal of the MPU 201 is the power failure signal. Next to SG1b, it is stopped. As a result, the MPU 201 is set in a state in which the arithmetic processing cannot be executed (after a lapse of about 5.0 seconds from t6).

Further, when about 5.5 seconds have passed since t6 (about 5.0 seconds after t6, and then about 0.5 seconds have passed), the voltage of the capacitor CD4 changes as shown in FIG. 8(e). It drops to about 4.7 volts. Then, as shown in FIG. 8F, the voltage at the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.0 volts (from t6 o'clock). After about 5.5 seconds). Here, the minimum operating voltage of MPU 201 is about 4.0 volts. Therefore, when approximately 5.5 seconds have passed after the inner frame 12 was closed and the switch SW1 was cut off, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 to the power terminal of the MPU 201 was finally stopped. Then, the MPU 201 becomes inoperable. That is, the MPU 201 is set to the inoperable state (after about 5.0 seconds from t6 o'clock) after being set to the state in which the arithmetic processing cannot be executed (about 5.5 seconds from t6 o'clock). After the passage). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

Note that when about 20 seconds have passed from t5, the voltage of the capacitor CD4 becomes zero volts as shown in FIG. 8(e). Following this, the voltage of the power supply output terminal of the frame open detection circuit 260 (also the drive voltage Vb) becomes zero volts (about 20 seconds before the time t5). Therefore, when about 20 seconds have passed from t5, the charged amount of the capacitor CD4 becomes zero.

Here, in the operation of the frame opening detection circuit 260 from t5 to t6, the capacitor CD4 is discharged even after the inner frame 12 is closed at t6. Even in this case, when the inner frame 12 is closed at t6 and the switch SW1 is cut off, the frame open detection circuit 260 causes conduction between the drain terminal D and the source terminal S of the FET3. The current generated by the discharge of CD4 does not flow through the resistor R5 but flows through the drain terminal D of the FET3. Therefore, when the inner frame 12 is closed at t6, as shown in FIG. 8(h), the voltage (power failure signal SG1b) at the power interruption signal output terminal of the frame opening detection circuit 260 can be set to zero volt.

After the power failure signal SG1b output from the power interruption signal output terminal of the frame opening detection circuit 260 is stopped, the voltage accompanying the discharge of the capacitor CD4 decreases with the passage of time, and the reset signal output terminal outputs the reset signal. The signal SG3b is stopped, and finally the drive voltage Vb output from the power supply output terminal is stopped. By this operation, even if the inner frame 12 is closed before the elapse of about 4.4 seconds from the time t5 at which the inner frame 12 is opened (the inner frame 12 is closed at t6 at about 3.0 seconds after t5). It is possible to stop the power failure signal SG1b first, then the reset signal SG3b, and finally the drive voltage Vb even if it is closed. Therefore, when the power of the pachinko machine 10 is turned off, the inner frame 12 is opened, and within about 4.4 seconds until the voltage output from the OUT terminal of the timer IC 1 is switched, the inner frame 12 is released. Even if the frame 12 is closed, the MPU 201 can be temporarily activated by the frame opening detection circuit 260, and the activated MPU 201 can be normally terminated.

After the inner frame 12 is closed at t6, the voltage of the capacitor CD4 decreases to about 4.7 volts as shown in FIG. 8(e), and the power source becomes as shown in FIG. When the drive voltage Vb output from the output terminal to the end becomes about 4.0 V and the MPU 201 ends normally, the frame open detection circuit 260 sets the state in which the inner frame 12 or the front frame 14 can be detected again. To be done.

Finally, the case where the switch SW2 is in the conductive state (the front frame 14 is in the open state) while the switch SW1 is in the conductive state (the inner frame 12 is in the open state) will be described. As shown in FIG. 8A, at time t7, the switch SW1 is in the conductive state (the inner frame 12 is in the open state), and as shown in FIG. 8B, at time t8, the switch SW2 is in the conductive state (front surface). When the frame 14 is opened, the TRG terminal voltage of the timer IC 1 switches from zero volt to about 11.3 volt at t7 as shown in FIG. 8C. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds elapse from t7. This causes conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7), and charging of the capacitor CD4 (see FIG. 7) is started (see FIG. 8E). t7). Note that this charging is completed in about 0.01 seconds after the switch SW1 becomes conductive as shown in FIG. 8(e). When the charging of the capacitor CD4 is completed, the voltage of the capacitor CD4 becomes about 5.7 volts as shown in FIG. 8(e).

Further, the voltage at the power output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I23 of the multiplexer MP3) starts rising at t7 and is about 0 from t7, as shown in FIG. 8(f). It will be about 5.0 volts after 0.01 seconds. As a result, the drive voltage Vb of about 5.0 V is started to be output from the power supply output terminal of the frame open detection circuit 260. The voltage at the reset signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I22 of the multiplexer MP2 and the input/output port 205) is about 40 μs after t7 as shown in FIG. 8(g). It starts to rise and reaches about 5.0 volts about 0.01 seconds after t7. As a result, the reset signal SG3b is started to be output from the reset signal output terminal of the frame opening detection circuit 260. The voltage increase at the reset signal output terminal of the frame open detection circuit 260 is about 40 μs after t7 because of the delay characteristic of the reset IC 2 (see FIG. 7) as described above. As shown in FIGS. 8F and 8G, the voltage rise at the power supply output terminal of the frame opening detection circuit 260 is about 40 μsec earlier than the voltage rise at the reset signal output terminal of the frame opening detection circuit 260. , The drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, and then the reset signal SG3b is input to the reset signal output terminal of the MPU 201. Therefore, when the pachinko machine 10 is powered off and the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily booted, the boot can be normally performed.

Further, as shown in FIG. 8E, when the voltage of the capacitor CD4 becomes about 5.7 volts, the voltage of the power failure signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I21 of the multiplexer MP1). As shown in FIG. 8(h), the voltage starts rising at t7 and reaches about 5.0 volts about 0.01 seconds after t7. Here, since the switch SW1 is in the conducting state (the inner frame 12 is in the open state), the drain terminal D and the source terminal S of the FET3 are cut off from each other. As a result, the power failure signal SG1b is started to be output from the power failure signal output terminal of the frame opening detection circuit 260.

Then, when about 4.4 seconds elapse from t7, as shown in FIG. 8D, the timer IC 1 switches the voltage of the OUT terminal from about 10.6 volt to zero volt. Then, the conduction between the drain terminal D and the source terminal S of the FET1 is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7) is cut off. Charging to CD4 is completed. Then, since the discharge of the capacitor CD4 is started, the voltage of the capacitor CD4 starts to drop (after about 4.4 seconds have elapsed from t7), as shown in FIG. 8(e). Following this, as shown in FIG. 8(f), the voltage of the power supply output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) starts to drop (from t7). After about 4.4 seconds). Further, as shown in FIG. 8G, the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 starts to drop (after about 4.4 seconds have elapsed from t7).

When about 4.4 seconds elapse from t7, the conduction between the drain terminal D and the source terminal S of the FET2 is cut off, so that the current is supplied to the power failure signal output terminal of the frame open detection circuit 260. Not done. Therefore, as shown in FIG. 8(h), the voltage at the power interruption signal output terminal of the frame open detection circuit 260 (power failure signal SG1b) becomes zero volts when approximately 4.4 seconds have elapsed from t7. Therefore, when about 4.4 seconds elapse after the inner frame 12 is opened and the switch SW1 is turned on, the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 to the NMI terminal of the MPU 201 is first , Stopped.

Next, when about 9.4 seconds elapses from t7 o'clock (about 4.4 seconds elapses from t7 o'clock and further about 5.0 seconds elapses), as shown in FIG. Drops to about 5.0 volts. Then, as shown in FIG. 8(f), the voltage of the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.3 volts (from t7 o'clock). After about 9.4 seconds). As shown in FIG. 8(g), the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 drops to about 4.3 volts, and then the reset IC 2 operates to zero volts. (After about 9.4 seconds from t7). Therefore, when about 9.4 seconds have passed since the inner frame 12 was opened and the switch SW1 was turned on, the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 to the reset terminal of the MPU 201 is the power failure signal. Next to SG1b, it is stopped. As a result, the MPU 201 is set in a state in which the arithmetic processing cannot be executed (after about 9.4 seconds have elapsed from t7).

Further, when about 9.9 seconds have passed from t7 o'clock (after about 9.4 seconds have passed from t7 o'clock and about 0.5 seconds have passed), the voltage of the capacitor CD4 is changed as shown in FIG. 8(e). It drops to about 4.7 volts. Then, as shown in FIG. 8F, the voltage at the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.0 volts (from t7). After about 9.9 seconds). Here, as described above, the lower limit of the operating voltage of the MPU 201 is about 4.0 volts. Therefore, when about 9.9 seconds have passed since the inner frame 12 was opened and the switch SW1 was turned on, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 to the power terminal of the MPU 201 was finally stopped. Then, the MPU 201 becomes inoperable. That is, the MPU 201 is set to the inoperable state (after about 9.4 seconds from t7 o'clock) after being set to the state in which the arithmetic processing cannot be executed (about 9.9 seconds from t7 o'clock). After the passage). Therefore, even when the MPU 201 is temporarily activated by the frame opening detection circuit 260 while the pachinko machine 10 is powered off, the frame opening detection circuit 260 can normally terminate the MPU 201 that has been started. it can.

It should be noted that, when about 20 seconds have passed from t7, the voltage of the capacitor CD4 becomes zero volts as shown in FIG. 8(e). Following this, the voltage of the power output terminal of the frame open detection circuit 260 (also the drive voltage Vb) becomes zero volts (about 20 seconds before t7). Therefore, when about 20 seconds have passed from t7, the charged amount of the capacitor CD4 becomes zero.

Finally, as shown in FIG. 8A, at time t9, the switch SW1 is turned off (the inner frame 12 is closed), and as shown in FIG. 8B, at time t10, the switch SW2 is turned off. When the state (front frame 14 is closed) is reached, as shown in FIG. 8C, at time t10, the TRG terminal voltage of the timer IC1 is switched from about 11.3 volts to zero volts and the OUT terminal voltage of the timer IC1 is changed. Switches from zero volts to about 10.6 volts. When the switch SW2 is turned off (the front frame 14 is closed) at t10, the drain terminal D and the source terminal S of the FET 3 are brought into conduction. As a result, the frame open detection circuit 260 is again set to a state in which the inner frame 12 and the front frame 14 can be detected.

As described above, even when the switch SW2 is in the conductive state (the front frame 14 is in the open state) when the switch SW1 is in the conductive state (the inner frame 12 is in the open state), the timer IC1 does not operate in the conductive period of the switch SW1. Of the switch SW1 or the switch SW2, regardless of the length of the switch SW2 (the length of the open period of the inner frame 12) and the length of the conductive period of the switch SW2 (the length of the open period of the front frame 14). When about 4.4 seconds elapse from the time when either the inner frame 12 or the front frame 14 is opened, the voltage of the OUT terminal is switched from about 10.6 volt to zero volt. As a result, the frame opening detection circuit 260 stops the power failure signal SG1b and starts discharging the capacitor CD4 after about 4.4 seconds have elapsed from the time when either the switch SW1 or the switch SW2 becomes conductive. .. After that, the frame opening detection circuit 260 stops the reset signal SG3b after about 9.4 seconds have elapsed from the time when either the switch SW1 or the switch SW2 becomes conductive, and the frame open detection circuit 260 selects either the switch SW1 or the switch SW2. The drive voltage Vb is stopped after about 9.9 seconds have passed from the time when one of them becomes conductive. Therefore, when the power of the pachinko machine 10 is off, the switch SW1 is in the conductive state (the inner frame 12 is in the open state), and then the switch SW2 is in the conductive state (the front frame 14 is in the open state). Even if the frame open detection circuit 260 temporarily starts up the MPU 201, the frame open detection circuit 260 can normally end the started up MPU 201.

As described above, the frame opening detection circuit 260 drives when one of the inner frame 12 or the front frame 14 and both the inner frame 12 and the front frame 14 are opened when the power of the pachinko machine 10 is off. After outputting the voltage Vb and the power failure signal SG1b, the reset signal SG3b is output. Therefore, even if the pachinko machine 10 is powered off, the MPU 201 can be temporarily started up normally. Although details will be described later, when the power of the pachinko machine 10 is off, when the MPU 201 is temporarily activated by the frame opening detection circuit 260, the pachinko machine 10 turns on the off-frame opening flag 203a. To do. When the off-inside frame opening flag 203a is turned on, the pachinko machine 10 uses the voice output device 226 and the lamp display device 227 to display the inner frame 12 or the front frame when the power of the pachinko machine 10 is turned on next time. Notify that 14 has been opened. Therefore, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off.

Further, as will be described in detail later, when the pachinko machine 10 is powered off and the MPU 201 is temporarily activated by the frame opening detection circuit 260, the pachinko machine 10 turns on the off-frame opening flag 203a. In addition, a pulse signal having a pulse width of 1 msec is output to the hall computer 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours. Therefore, by analyzing the pulse signal stored in the hall computer 262, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. You can

Further, in the frame open detection circuit 260, when the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 becomes conductive, and about 4.4 seconds after the conduction, first, the power failure signal SG1b is stopped ( If the open inner frame 12 or the open front frame 14 is closed before the switch SW1 or the switch SW2 is turned on and about 4.4 seconds have passed after the turn-on, a stop signal is issued when the switch is closed. Stop SG1b). Next, the frame opening detection circuit 260 stops the reset signal SG3b when about 9.4 seconds have passed after the switch SW1 or the switch SW2 was turned on (about 4.4 seconds passed after the switch SW1 or the switch SW2 was turned on). When the opened inner frame 12 or the opened front frame 14 is closed before, the reset signal SG3b is stopped about 5.0 seconds after the closing). Then, the frame opening detection circuit 260 reduces the drive voltage Vb output to the power supply terminal of the MPU 201 to about 4.0 volts when about 9.9 seconds have elapsed after the switch SW1 or the switch SW2 was turned on (the switch SW1 or the switch SW1 or If the opened inner frame 12 or the opened front frame 14 is closed before about 4.4 seconds have passed after the switch SW2 is turned on, the drive is performed about 5.5 seconds after the closing. The voltage Vb is reduced to about 4.0 volts). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily activated by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

In addition, even if the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is conducted, the frame open detection circuit 260 detects that the inner frame 12 or the front frame is still in operation for about 4.4 seconds. Regardless of the open period of 14, the transistor TR1 stops the output of the driving voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4, which are performed by the electric power supplied from the capacitor CD1. After the stop by the transistor TR1, the frame open detection circuit 260 outputs the drive voltage Vb and the reset signal SG3b by discharging the capacitor CD4. Therefore, the frame opening detection circuit 260, for example, when the business hours of the game hall is finished and the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1 to the frame opening detection circuit 260. That is, that is, when the DC voltage of about 11.3 volts is supplied from the capacitor CD1 to the frame open detection circuit 260, the period during which the power is supplied from the capacitor CD1 is the open period of the inner frame 12 or the front frame 14. Regardless, it can be held for about 4.4 seconds. Therefore, the frame opening detection circuit 260 can suppress the consumption of the electric power charged in the capacitor CD1 and detect the opening of the inner frame 12 or the front frame 14 multiple times.

Even if the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the frame open detection circuit 260 is opened before about 4.4 seconds elapses from the time when the switch SW1 or the switch SW2 is turned on. When the frame 12 or the opened front frame 14 is closed, the switch SW1 or the switch SW2 is cut off, and the output of the drive voltage Vb, the output of the reset signal SG3b, and the power failure signal SG1b performed by the power supplied from the capacitor CD1. And the charging of the capacitor CD4 are stopped. After the inner frame 12 and the front frame 14 are closed, the drive voltage Vb and the reset signal SG3 are output by discharging the capacitor CD4.

In this way, when the charging of the capacitor CD4 is completed, after that, the driving voltage Vb and the reset signal SG3b can be output by discharging the capacitor CD4, so that the opening period of the inner frame 12 or the front frame 14 is about. If it is within 4.4 seconds, the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4, which are performed by the power supply from the capacitor CD1, are further shortened. Can be kept at. Therefore, the power consumption of the capacitor CD1 due to the opening of the inner frame 12 or the front frame 14 can be further suppressed.

Here, since the capacitance of the capacitor CD1 is 1F and the voltage applied to the capacitor CD1 is about 11.3 volts, the charge accumulated in the capacitor CD1 is the product of the capacitance of the capacitor CD1 and the applied voltage of the capacitor CD1. To about 11.3 C (coulomb). The electric charge of about 11.3C stored in the capacitor CD1 is about during each period of the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b and the charging of the capacitor CD4 which are performed by the power supply from the capacitor CD1. In the case of 4.4 seconds, the number of times power is supplied corresponds to about 11 times. Therefore, for example, when the power supply to the pachinko machine 10 is cut off after the business hours of the game arcade and the DC voltage of 12 V is not supplied from the DC power supply DC1, the inner frame 12 is opened (the switch SW1 is turned on). Even when the front frame 14 is opened (conduction) or the front frame 14 is opened (conduction of the switch SW2) for a plurality of times, the frame open detection circuit 260 opens the inner frame 12 or opens the front frame 14 (conduction of the switch SW1 or It is possible to reliably detect that the switch SW2 is turned on up to about 11 times each time, temporarily start the MPU 201 normally, and turn on the off-inside frame open flag 203a. At this time, when the inner frame 12 is opened or the front frame 14 is opened about 11 times, the electric power stored in the capacitor CD1 decreases, and the driving voltage Vb decreases, the reset signal SG3b decreases, and the power failure signal SG1b decreases. A decrease and a decrease in the charge amount of the capacitor CD4 occur. However, when the inner frame 12 or the front frame 14 is opened, the voltage of the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 exceeds about 4.3 V and the frame open detection circuit 260 is released. If the voltage of the drive voltage Vb output from the power output terminal of the power supply and the voltage of the power failure signal SG1b output from the power failure signal output terminal of the frame open detection circuit 260 exceeds about 4.0 volts, the power of the pachinko machine 10 is Even if it is turned off, the MPU 201 can be temporarily started up normally and the off-inside frame open flag 203a can be turned on. Furthermore, a pulse signal having a pulse width of 1 msec can be output to the hall computer 262.

In the frame open detection circuit 260, the capacities of the capacitors CD1 and CD4 are set to 1F, respectively. However, the capacitor CD1 is displayed when the power of the pachinko machine 10 is turned off and the inner frame 12 or the front frame 14 is opened. Since it is a capacitor that serves as a power source for operating the open circuit detection circuit 260, the capacitance value may be larger than that of the capacitor CD4. By making the capacitance value of the capacitor CD1 larger than 1F, opening of the inner frame 12 or the front frame 14 while the power of the pachinko machine 10 is turned off can be detected more than 11 times.

In the frame opening detection circuit 260, when the inner frame 12 and the front frame 14 are closed (when the switches SW1 and SW2 are cut off), the OUT terminal voltage of the timer IC1 is about 10.6 volts. Therefore, the drain opening D and the source terminal S of the FET1 and the drain terminal D and the source terminal S of the FET2 of the frame opening detection circuit 260 are in a conductive state. Since the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 3 are electrically connected. However, at this time, since the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off, the drain terminal D and the source terminal S of the FET1 and the drain terminal D and the source terminal of the FET2 are cut off. The current from the capacitor CD1 does not flow between the terminals S and S3 and between the drain terminal D and the source terminal S of the FET3. Therefore, when the inner frame 12 and the front frame 14 are closed, the electric power charged in the capacitor CD1 is generated between the drain terminal D and the source terminal S of the FET1 and between the drain terminal D and the source terminal S of the FET2. It does not flow between the terminals and between the drain terminal D and the source terminal S of the FET 3 and are not consumed.

Further, the power consumption of the capacitor CD1 by the frame opening detection circuit 260 when the pachinko machine 10 is powered off and the inner frame 12 and the front frame 14 are closed is determined by the standby power of the timer IC1 and the power consumption of the NOTIC3. It is a degree. Moreover, since a voltage is only applied to each gate terminal G of the FET1 to FET3, the power consumed by the FET1 to FET3 is very small. Therefore, the consumption of these powers does not cause a significant reduction in the amount of charge of the capacitor CD1.

Next, the display content of the third symbol display device 81 will be described with reference to FIG. FIG. 9 is a drawing for explaining the display screen of the third symbol display device 81, and FIG. 9A is a diagram schematically showing the area division setting and the effective line setting of the display screen, FIG. 9B is a diagram exemplifying an actual display screen.

The third symbol is composed of ten types of main symbols numbered from "0" to "9" and one type of petal-shaped sub-symbol formed smaller than the main symbol. Each main symbol is formed by attaching numbers from "0" to "9" on the rear symbol made of a wooden box, of which the main symbols with odd numbers (1, 3, 5, 7, 9) are , A large number is added to almost the front of the wooden box. On the other hand, the main designs with even numbers (0, 2, 4, 6, 8) are protected almost entirely on the front of the wooden box, and additional designs imitating characters such as furoshiki and helmet are added. An even number is small in green on the lower right side of the attached design, and is added so as to be displayed on the front side of the attached design.

Further, in the pachinko machine 10 of the present embodiment, when the lottery result by the main controller 110 is a big hit, a variable display in which the same main symbols are arranged is displayed, and a big hit occurs after the fluctuation display ends. Is configured to. When transitioning to a high probability state (probability change state) after the end of a big hit, a variable display in which main symbols (corresponding to “high probability symbols”) to which odd numbers are added are displayed. On the other hand, when transitioning to the low-probability state after the end of the big hit, a variable display in which main symbols (corresponding to “low-probability symbols”) to which even numbers are added are arranged is performed. Here, the high-probability state refers to a state in which the subsequent jackpot probability increases as an added value after the jackpot ends, that is, when the probability changes (probability change). The normal state (low-probability state) refers to a time when there is no probability change, and a state where the jackpot probability is normal, that is, a state where the jackpot probability is lower than during the probability change.

As shown in FIG. 9(a), the display screen of the third symbol display device 81 is roughly divided into upper and lower parts, and the lower 2/3 is the main display area Dm in which the third symbol is variably displayed, other than that. The upper third ⅓ is the sub display area Ds for displaying the notice effect and the character.

In the main display area Dm, three symbol columns Z1, Z2, Z3 of left, middle and right are displayed. In each of the symbol columns Z1 to Z3, the above-mentioned third symbol is displayed in a prescribed order. That is, in each of the symbol columns Z1 to Z3, main symbols are arranged in ascending or descending order of numbers, and one sub symbol is arranged between each main symbol. Therefore, a total of 20 third symbols of 10 main symbols and 10 sub symbols are set in each symbol column, and scrolls from top to bottom with periodicity for each symbol column Z1 to Z3. Variable display is performed. In particular, in the left symbol column Z1, the numbers of the main symbols are arranged in descending order, and in the middle symbol column Z2 and the right symbol column Z3, the numbers of the main symbols are arranged in ascending order.

Further, in the main display area Dm, the third symbols are displayed in the upper, middle, and lower three rows for each of the symbol columns Z1 to Z3. Therefore, the third symbol display device 81 displays a total of nine third symbols in three rows and three columns. Five effective lines, that is, an upper line L1, a middle line L2, a lower line L3, a rightward rising line L4, and a leftward rising line L5 are set in the main display area Dm. Then, in each game, the variable display is stopped in the order of the left symbol column Z1→the right symbol column Z3→the middle symbol column Z2, and at the time of stopping, a combination of the jackpot symbols on any of the activated lines (in the present embodiment, A combination of the same main symbols) will be displayed as a jackpot and a jackpot video will be displayed.

The sub display area Ds is provided horizontally longer than the main display area Dm, and is further divided into three notice areas Ds1 to Ds3 in the left-right direction. Here, the notice areas Ds1 and Ds3 on the left and right are normally covered with a double-opening opaque door that is electrically opened and closed by a solenoid (not shown), and sometimes the solenoid is excited to bring the door to the front side. It is a display area that can be viewed by the player when opened. The notice area Ds2 at the center is a display area which is always visible without being covered by the door.

As shown in FIG. 9B, in the actual display screen, a total of nine main symbols and sub symbols of the third symbol are displayed in the main display area Dm. In the sub display area Ds, the left and right doors are closed, and the left and right notice areas Ds1 and Ds3 are covered and the display screen is invisible. When one or both of the left and right doors are opened in the middle of the variable display, a moving image is displayed in the left and right notice areas Ds1 and Ds3, and it is easier for the player to make a transition to a big hit than usual. It is suggested. In the central notice area Ds2, usually, a predetermined character (in this embodiment, a boy with a hachimaki) performs a predetermined motion, sometimes performs a special motion different from the predetermined motion, or another character A notice production is performed by appearing. The display screen of the third symbol display device 81 is divided into upper and lower display areas Dm and Ds in principle, but the third symbol and characters are displayed in a larger size across the respective display areas Dm and Ds. Display effect can be performed.

Next, with reference to FIG. 10, a counter and the like provided in the RAM 203 of the main controller 110 will be described. These counters and the like are used in the MPU 201 of the main control device 110 in order to perform jackpot lottery, setting of display of the first symbol display device 37, lottery of display result of the second symbol display device 82, and the like.

To set the jackpot lottery and the display of the first symbol display device 37, the first random number counter C1 used for the jackpot lottery, the first hit type symbol counter C2 used for the jackpot symbol selection, and the stop pattern selection counter C3, a first initial value random number counter CINI1 used for setting an initial value of the first random number counter C1, and fluctuation type counters CS1, CS2, CS3 used for selecting a fluctuation pattern are used. The second random number counter C4 is used for the lottery of the second symbol display device 82, and the second initial value random number counter CINI2 is used for the initial value setting of the second random number counter C4. Each of these counters is a loop counter in which 1 is added to the previous value each time it is updated, and after reaching the maximum value, it returns to 0.

Each counter is updated at an interval of 4 ms which is an execution interval of the main process (see FIG. 12) or at an interval of 2 ms which is an execution interval of the timer interrupt process (see FIG. 15), and the updated value is a predetermined area of the RAM 203. It is appropriately stored in the counter buffer set to. The RAM 203 is provided with a holding ball storage area consisting of one execution area and four holding areas (holding first to fourth areas), and each of these areas is provided with a first ball entrance 64. Values of the first random number counter C1, the first hit type counter C2, and the stop pattern selection counter C3 are stored in accordance with the winning timing of the ball.

Each counter will be described in detail. The first random number counter C1 is configured to be sequentially incremented by 1 in the range of 0 to 738, for example, and after reaching the maximum value (that is, 738), returns to 0. In particular, when the first random number counter C1 makes one round, the value of the first initial value random number counter CINI1 at that time is read as the initial value of the first random number counter C1. Further, the first initial value random number counter CINI1 is configured as a loop counter that is updated within the same range as the first random number counter C1 (value=0 to 738), and each time the timer interrupt process (see FIG. 15) is executed. It is updated once and is repeatedly updated within the remaining time of the main process (see FIG. 12). The value of the first random number counter C1 is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the reserved ball is stored in the RAM 203 at the timing when the ball wins the first ball entrance 64. Stored in the area. There are two types of random number values for jackpots, one for low probability and one for high probability. The number of random number values for jackpot in low probability is 2, and the value is "373,727". The number of random numbers that are a big hit at high probability is 14, and the value is “59,109,163,211,263,317,367,421,479,523,631,683,733”.

The first hit type counter C2 determines the display mode of the first symbol display device 37 at the time of a big hit, and in the present embodiment, 1 is sequentially added within the range of 0 to 4, and the maximum value ( In other words, it is configured to return to 0 after reaching 4). The value of the first hit type counter C2 is updated, for example, regularly (in this embodiment, once for each timer interrupt process), and the reserved ball is stored in the RAM 203 at the timing when the ball wins the first ball entrance 64. Stored in the area. In addition, the value of the random number which becomes a high probability state after the big hit is "1, 2, 3", and the value of the random number which becomes a low probability state after the big hit is "0, 4", and two kinds of hit types are determined. It Therefore, the display mode corresponding to the stop symbol displayed on the first symbol display device 37 is a display mode corresponding to two types of jackpots of a high-probability state and a low-probability state, and one type of display mode corresponding to the deviation. Any one of the three display modes in total is selected.

The stop pattern selection counter C3 is configured to be incremented by 1 in the range of 0 to 238, for example, and return to 0 after reaching the maximum value (that is, 238). In the present embodiment, the stop pattern selection counter C3 selects the effect pattern displayed on the third symbol display device 81, and after the reach occurs, the final stop symbol is shifted by one before and after the reach symbol. A "rear out-of-front-reach" (for example, a range of 0 to 8) that stops, and a "reach other than out-of-front-rear" (for example, a range of 9 to 38) that stops after the last stop symbol occurs other than before and after the reach symbol. , Three stop (effect) patterns of "completely disengaged" (for example, a range of 39 to 238) in which reach is not generated are selected. The value of the stop pattern selection counter C3 is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the reserved ball storage area of the RAM 203 at the timing when the ball wins the first ball entrance 64. Stored in.

Further, the stop pattern selection counter C3 is provided with a plurality of tables having different ranges of random number values for which stop patterns are selected. This depends on whether the current state of the pachinko machine 10 is a high-probability state or a low-probability state, in which area of the reserved ball storage area each random number value is stored (that is, the number of reserved pieces), and the like. This is for changing the selection ratio of the stop pattern.

For example, in the high-probability state, a large table is selected with a range of random number values of 10 to 238 corresponding to the stop pattern of “complete deviation” so that the reach effect is not unnecessarily selected because a jackpot is likely to occur. It is easy to select "Completely missed". In this table, the "front-rear outreach" is narrowed to 0 to 5, and the "reach other than front-rear outreach" is also narrowed to 6 to 9, which makes it difficult to select "rear-rear outreach" or "reach other than front-rear-reach". Further, if each random number value is not stored in the reserved ball storage area in the low probability state, the disturbance corresponding to the "completely missed" stop pattern in order to secure the time for the ball to enter the first entrance 64. A table with a narrow range of numerical values of 51 to 238 is selected, and it becomes difficult to select “complete deviation”. In this table, the range of the random number value corresponding to the stop pattern of "reach other than out of front/back" is widened to 9 to 50, and "reach other than out of front/rear" is easily selected. Therefore, in the low probability state, it is possible to secure the time for the ball to enter the first ball entrance 64, so that the variable display by the third symbol display device 81 can be easily continued.

Of the two fluctuation type counters CS1 and CS2, one of the fluctuation type counters CS1 is sequentially incremented by 1 in the range of 0 to 198, for example, and reaches a maximum value (that is, 198) and then returns to 0. However, the other variation type counter CS2 is configured to be incremented by 1 in the range of, for example, 0 to 240, and returns to 0 after reaching the maximum value (that is, 240). In the following description, CS1 is also referred to as a "first variation type counter" and CS2 is also referred to as a "second variation type counter".

The first variation type counter CS1 determines a rough display mode such as so-called normal reach, super reach, and premium reach. Specifically, the determination of the display mode is determination of the variation time of the symbol variation. Further, the second variation type counter CS2 determines the variation time (in other words, the variation symbol number) until the final stop symbol (in the present embodiment, the medium symbol) is stopped after the reach is generated. Based on the variation time determined by the variation type counters CS1, CS2, the display control device 114 determines the reach type and the detailed symbol variation mode of the third symbol displayed on the third display device 81. Therefore, by combining these fluctuation type counters CS1 and CS2, it is possible to easily realize a variety of fluctuation patterns. Further, it is also possible to determine the symbol variation mode only by the first variation type counter CS1 or similarly determine the symbol variation aspect by the combination of the first variation type counter CS1 and the stopped symbol. The values of the fluctuation type counters CS1 and CS2 are updated once every time a main process (see FIG. 12) described later is executed, and are repeatedly updated even within the remaining time in the main process.

For example, the value of the fluctuation type counter CS3 is incremented by 1 in the range of 0 to 162, and returns to 0 after reaching the maximum value (that is, 162). In the following description, CS3 is also referred to as a “third fluctuation type counter”. The third symbol display device 81 of the present embodiment is for performing a decorative effect according to the display mode of the first symbol display device 37, and in addition to the variation of the symbol, sliding the varying symbol or A notice effect is given such as passing a notice character for notifying the occurrence of the reach effect. The effect pattern of the notice effect is selected by the variation type counter CS3. Specifically, a production pattern is selected in which the time required for the notice production is added to the variation time, on the contrary, the variation time is subtracted in order to reduce the variation display time, and the variation time is not added or subtracted. .. As with the stop pattern selection counter C3, the variation type counter CS3 is provided with a plurality of tables having different ranges of random number values for which the effect patterns are selected, and whether the current state of the pachinko machine 10 is the high probability state. The selection ratio of each effect pattern is configured to be different depending on the low probability state, which area of the reserved ball storage area each random value is stored, and the like.

As described above, the variation type counters CS1 and CS2 determine the variation time of the symbol variation, and the variation type counter CS3 determines the time to be added to and subtracted from the variation time. Therefore, the final change time until the final stop symbol stops is determined by the change type counters CS1, CS2, CS3.

The second random number counter C4 is configured as a loop counter that is incremented by 1 in the range of 0 to 250, for example, and returns to 0 after reaching the maximum value (that is, 250). In the present embodiment, the value of the second random number counter C4 is updated, for example, periodically for each timer interrupt process, and it is determined that the ball has passed the second entrance (through gate) 67 on either the left or the right. It is acquired when it is detected. The number of random number values to be won is 149, and the range is “5 to 153”. The second initial value random number counter CINI2 is configured as a loop counter that is updated in the same range as the second random number counter C4 (value=0 to 250), and is once for each timer interrupt process (see FIG. 15). It is updated and is repeatedly updated within the remaining time of the main process (see FIG. 12).

Next, each control process executed by the MPU 201 in the main controller 110 will be described with reference to the flowcharts of FIGS. 11 to 17. The process of the MPU 201 is roughly classified into a startup process that is started when the power is turned on, a main process that is executed after the startup process, and a regular process (in this embodiment, a cycle of 2 msec). There are a timer interrupt process and an NMI interrupt process activated by the input of the power failure signal SG1 to the NMI terminal. For convenience of explanation, first, the timer interrupt process and the NMI interrupt process will be described, and then the startup process. The main processing will be described.

FIG. 15 is a flowchart showing the timer interrupt process. The timer interrupt process is executed by the MPU 201 of the main control device 110, for example, every 2 msec. In the timer interrupt process, first, a process of reading various winning switches is executed (S501). That is, the states of various switches connected to the main controller 110 are read, the states of the switches are determined, and the detection information (winning detection information) is stored.

Next, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S502). Specifically, the first initial value random number counter CINI1 is incremented by 1, and is cleared to 0 when the counter value reaches the maximum value (738 in this embodiment). Then, the updated value of the first initial value random number counter CINI1 is stored in the corresponding buffer area of the RAM 203. Similarly, the second initial value random number counter CINI2 is incremented by 1, and when the counter value reaches the maximum value (250 in the present embodiment), it is cleared to 0 and the second initial value random number counter CINI2 is updated. The value is stored in the corresponding buffer area of the RAM 203.

Further, the first per random number counter C1, the first per type counter C2, the stop pattern selection counter C3, and the second per random number counter C4 are updated (S503). Specifically, each of the first per random number counter C1, the first per type counter C2, the stop pattern selection counter C3, and the second per random number counter C4 is incremented by 1, and the counter values thereof reach the maximum value (in the present embodiment). Then, when each reaches 738, 4, 238, 250), it is cleared to 0. Then, the updated values of the counters C1 to C4 are stored in the corresponding buffer areas of the RAM 203.

After that, the start winning process (see FIG. 16) associated with the winning in the first ball entrance 64 is executed (S504), the firing control process is executed (S505), and the timer interrupt process is ended. The firing control process detects that the player is touching the operation handle 51 with the touch sensor 51a, and turns on the firing of the ball on condition that the stop switch 51b for stopping the firing is not operated. This is a process for determining ON/OFF. The main controller 110 instructs the launch controller 112 to launch a sphere when the launch of the sphere is on.

Here, with reference to the flowchart of FIG. 16, the start winning process executed in the process of S504 will be described. FIG. 16 is a flowchart showing a start winning process (S504) executed in the timer interrupt process (see FIG. 15).

When this start winning process is executed, it is first determined whether or not the ball has won the first ball entrance 64 (starting prize) (S601). When it is determined that the ball has won the first ball entrance 64 (S601: Yes), whether or not the number N of operation-holding balls of the first symbol display device 37 is less than the upper limit value (4 in the present embodiment). It is determined (S602). If there is a winning in the first ball entrance 64 and the number N of operation-holding balls is <4 (S602: Yes), the number N of operation-holding balls is incremented by 1 (S603), and further updated in step S503. The respective values of the first hit random number counter C1, the first hit type counter C2, and the stop pattern selection counter C3 are stored in the first area of the empty hold areas of the hold ball storage area of the RAM 203 (S604). On the other hand, whether or not there is a prize in the first ball entrance 64 (S601: No), or even if there is a prize in the first ball entrance 64 but the number N of operation-holding balls is not N<4 (S602: No) , S603 and S604 are skipped, the start winning process is ended, and the process returns to the timer interrupt process.

FIG. 17 is a flowchart showing the NMI interrupt processing. In the NMI interrupt processing, the power of the pachinko machine 10 is turned on, and the power of the pachinko machine 10 is cut off due to the occurrence of a power failure while the power is on, and the power failure signal output from the power failure monitoring circuit 252. In addition to the case where SG1a falls from 5 V to zero V, the power of the pachinko machine 10 is turned off. While the power is off, the inner frame 12 or the front frame 14 is opened, and the frame open detection circuit 260 causes This is a process executed by the MPU 201 of the main controller 110 when the MPU 201 is started up and the power failure signal SG1b output from the frame opening detection circuit 260 falls from 5 volts to zero volts. When the MPU 201 detects the fall of the power failure signal SG1a or the fall of the power failure signal SG1b, it interrupts the control being executed and starts the NMI interrupt processing, and sets the power failure occurrence information as the power failure occurrence information. Is stored in the RAM 203 (S701), and the NMI interrupt processing ends.

It should be noted that the above NMI interrupt processing is similarly executed in the payout launch control device 111 when the power of the pachinko machine 10 is turned on, and the power failure occurrence information is stored in the RAM 213 by the NMI interrupt processing. It That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like while the power of the pachinko machine 10 is turned on, the power failure signal SG1a (falling) is output from the power failure monitoring circuit 252 in the payout emission control device 111. Is output to the NMI terminal of the MPU 211, and the MPU 211 interrupts the control being executed and starts the NMI interrupt processing.

Next, with reference to FIG. 11, a startup process when the main controller 110 is powered on will be described. FIG. 11 is a flowchart showing a startup process executed by the MPU 201 in the main controller 110. This start-up process is started by a reset when the power is turned on, and when the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened, and the frame open detection circuit 260 The drive voltage Vb and the reset signal SG3b are output, the drive voltage Vb enables the MPU 201 to operate, and then the reset signal SG3b activates the MPU 201 when it can execute the arithmetic processing. In the start-up process, first, an initial setting process accompanying power-on is executed (S101). Specifically, the stack pointer is set to a predetermined value, and the sub-side control devices (peripheral control devices such as the voice lamp control device 113 and the payout control device 111) are activated. In order to wait, a wait process (1 second in this embodiment) is executed. Then, access to the RAM 203 is permitted (S103). Due to this weight process, the main control unit 110 shifts to the main process after the payout control unit 111, the voice lamp control unit 113, and the display control unit 114 shift to the main process. Therefore, the payout control device 111, the voice lamp control device 113, and the display control device 114 can reliably receive the command transmitted from the main control device 110 (the payout control device 111, the voice lamp control device 113, and the display control. It is possible to prevent the device 114 from erroneously receiving a command from the main control device 110).

After that, it is determined whether or not the RAM erase switch 122 (see FIG. 3) provided in the power supply device 115 is turned on (S104), and if it is turned on (S104: Yes), the process proceeds to S115. On the other hand, if the RAM erase switch 122 is not turned on (S104: No), it is further determined whether or not the power-off occurrence information is stored in the RAM 203 (S105), and if it is not stored (S105: No). Since there is a possibility that the previous process at the time of power-off was not completed normally, the process proceeds to S115 in this case as well.

If the power failure occurrence information is stored in the RAM 203 (S105: Yes), the RAM determination value is calculated (S106), and the calculated RAM determination value is not normal (S107: No), that is, the calculated RAM. If the determination value does not match the RAM determination value saved when the power is shut off, the backed up data has been destroyed, and in such a case also the process proceeds to S115. Note that the RAM determination value is, for example, a checksum value at the work area address of the RAM 203, as will be described later in the process of S223 of FIG. Instead of this RAM judgment value, the validity of the backup may be judged by whether or not the keyword written in a predetermined area of the RAM 203 is correctly stored. The pachinko machine 10 is determined to be No in the process of S107 because the RAM determination value is always abnormal when the pachinko machine 10 is shipped from the production factory and the power is first turned on. Also in this case, the process proceeds to S115.

In the process of S115, a payout initialization command is transmitted to initialize the payout control device 111, which is a sub-side control device (peripheral control device) (S115). Upon receipt of this payout initialization command, the payout control device 111 clears areas (work areas) other than the stack area of the RAM 213, sets initial values, and enters a state in which game ball payout control can be started. After transmitting the payout initialization command, main controller 110 executes initialization processing (S116, S117) of RAM 203.

As described above, in the pachinko machine 10, when the RAM data is initialized when the power is turned on, for example, at the start of business at the game arcade, the power is turned on while pressing the RAM erase switch 122. Therefore, if the RAM erase switch 122 is pressed during the start-up process, the RAM initialization process (S116, S117) is executed. In addition, the initialization processing (S116, S117) of the RAM 203 is executed in the same manner when the power-off occurrence information is not set or when a backup abnormality is confirmed by the RAM determination value (checksum value or the like). .. In the RAM initialization processing (S116, S117), the used area of the RAM 203 is cleared to 0, the off-inside frame open flag 203a is turned off (S116), and then the initial value of the RAM 203 is set (S117). After the initialization processing of the RAM 203 is executed, the process proceeds to S110.

On the other hand, if the RAM erase switch 122 is not turned on (S104: No), the information on the occurrence of power failure is stored (S105: Yes), and if the RAM determination value (checksum value or the like) is normal ( (S107: Yes), the power-off occurrence information is cleared while the data backed up in the RAM 203 is held (S108), a payout return command is sent to the payout control device 111 (S109), and the process proceeds to S110. ..

In the process of S110, the voltage (reset signal SG3b) output from the frame open detection circuit 260 to the input/output port 205 is read (S110). Then, it is determined whether or not the output (reset signal SG3b) from the frame opening detection circuit 260 to the input/output port is high (S111). If the output from the frame open detection circuit 260 to the input/output port is high (S111: Yes), the off-in-frame open flag 203a is turned on (S112). On the other hand, if the output from the frame open detection circuit 260 to the input/output port is not high (S111: No), the process of S112 is skipped. Whether the output from the frame opening detection circuit 260 to the input/output port (reset signal SG3b) is high or not depends on whether the voltage output from the frame opening detection circuit 260 to the input/output port exceeds about 4.3 volts. It is determined by whether or not there is.

Here, when the output from the frame opening detection circuit 260 to the input/output port is determined to be high (S111: Yes), the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off. In addition to the case where the switch SW1 or the switch SW2 is turned on, the drive voltage Vb, the power failure signal SG1b and the reset signal SG3b are output from the frame opening detection circuit 260 and the MPU 201 is temporarily turned on, two other patterns are considered. To be The first pattern is when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off, and the power of the pachinko machine 10 is turned on within about 9.4 seconds from the opening, that is, the pachinko machine. When the power of 10 is off, the inner frame 12 or the front frame 14 is opened, and the frame open detection circuit 260 outputs the drive voltage Vb, the power failure signal SG1b, and the reset signal SG3b. This is the case when the power is turned on. The second pattern is a case where the power of the pachinko machine 10 is turned on, the inner frame 12 or the front frame 14 is opened, and the frame open detection circuit 260 outputs the reset signal SG3b before the processing of S110. Even when the pattern corresponds to the first pattern or the second pattern, there is no problem even if the off-inside frame open flag 203a is turned on (S112). In order to correspond to the first pattern or the second pattern, it is indispensable that the power of the pachinko machine 10 is turned on, and the first pattern and the second pattern are clerk before the business hours of the game hall This is because it is performed by. That is, when the first pattern or the second pattern is performed by the store clerk, at least the store clerk opens the inner frame 12 or the front frame 14 by himself when the pachinko machine 10 is powered off, It is recognized that the pachinko machine 10 has been turned on by itself within about 9.4 seconds after the opening (first pattern), or the pachinko machine 10 is turned on itself and immediately after that (the process of S110). This is because it recognizes that the inner frame 12 or the front frame 14 is opened by itself (second pattern). That is, even if the off-inside-frame opening flag 203a is turned on, the clerk opens the inner frame 12 or the front frame 14 after recognizing that the off-inside frame opening flag 203a is turned on. is there. Further, it is because the clerk can perform an operation to turn off the off-inside frame open flag 203a again. Therefore, even if the output from the frame open detection circuit 260 to the input/output port is determined to be high in the above two patterns (S111: Yes), there is no problem. That is, the above two patterns cannot occur in normal use of the pachinko machine 10, and therefore, there is no problem even if they are not considered.

As described above, while the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 becomes conductive, and the frame open detection circuit 260 outputs the drive voltage Vb, the power failure signal SG1b, and the reset. In addition to the case where the signal SG3b is output and the MPU 201 is temporarily started up, the output from the frame open detection circuit 260 to the input/output port is also determined to be high in the above two patterns (S111: Yes). ), the off-inside frame open flag 203a is turned on (S112).

When it is determined No in S111 or when the process of S112 is executed, a payout return command at power recovery for returning the sub-side control device (peripheral control device) to the game state when the drive power is cut off Is transmitted (S113), and the process proceeds to S114. When the payout control device 111 receives this payout return command, the payout control device 111 is ready to start the payout control of the game balls while holding the data stored in the RAM 213. In the process of S114, the interrupt is permitted, and the process proceeds to the main process described later.

As described above, the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is turned off, and the drive voltage Vb, the power failure signal SG1b and the reset signal SG3b are output from the frame open detection circuit 260. When the MPU 201 is temporarily started up, the output from the frame opening detection circuit 260 to the input/output port 205 becomes high (S111: Yes), and the off frame opening flag 203a is turned on (S112). ..

The processes of S110 to S112 are executed immediately after the process of S109 is completed or immediately after the process of S117 is completed. That is, the processes of S110 to S112 are executed immediately after the various settings of the MPU 201 are completed. Therefore, if the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off, the opening can be immediately detected by the processing of S110 to S112.

Next, with reference to FIG. 12, a main process executed after the above-described startup process will be described. FIG. 12 is a flowchart showing a main process executed by the MPU 201 in the main controller 110. In this main processing, the main processing of the game is executed. As an outline thereof, each process of S201 to S212 is executed as a regular process of 4 msec cycle, and each process of S215 to S220 is executed in the remaining time.

In the main process, first, output data such as a command updated in the previous process is transmitted to each sub-side control device (peripheral control device) (S201). Specifically, the presence/absence of winning detection information detected in the switch reading process of S501 is determined, and if there is winning detection information, a prize ball command corresponding to the number of acquired balls is transmitted to the payout control device 111. Further, by this external output processing, the variable pattern command, the stop symbol command, the stop command, the effect time addition command and the like necessary for the variable display of the third symbol by the third symbol display device 81 are transmitted to the voice lamp control device 113. Furthermore, when a ball is to be launched, a ball launch signal is transmitted to the launch control device 112.

Next, the respective values of the fluctuation type counters CS1, CS2, CS3 are updated (S202). Specifically, the fluctuation type counters CS1, CS2, CS3 are incremented by 1, and when the counter values reach the maximum values (198, 240, 162 in the present embodiment), they are cleared to 0 respectively. Then, the updated values of the fluctuation type counters CS1, CS2, CS3 are stored in the corresponding buffer area of the RAM 203.

When the variation type counters CS1, CS2, CS3 are updated, the prize ball count signal and the payout abnormality signal received from the payout control device 111 are read (S203). After that, it is determined whether the off-inside frame open flag 203a is on (S204). If the off-frame open flag 203a is on (S204: Yes), the inner frame 12 or the front frame 14 is open while the power of the pachinko machine 10 is off, or the two patterns described above are applicable. An off-inside frame open command is transmitted to the control device 113 (S205). When the voice lamp control device 113 receives the OFF-time frame open command, it controls the voice output device 226 and the lamp display device 227 to start notification that the inner frame 12 or the front frame 14 has been opened. Then, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 (S206). The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours. In addition, when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off and the MPU 201 is temporarily started up, power is not supplied to the audio lamp control device 113. Even if the OFF-in-frame opening command is transmitted to the audio lamp control device 113, the audio output device 226 and the lamp display device 227 do not give notification. Therefore, even if the inner frame 12 or the front frame 14 is opened by a fraudulent person while the power of the pachinko machine 10 is turned off, the pachinko machine 10 sets the off middle frame open flag 203a without being recognized by the fraudster. Can be used to store the opening of the inner frame 12 or the front frame 14 (without the notification by the audio output device 226 and the lamp display device 227, the off-in-frame open flag 203a is used to open the inner frame 12 or the front frame). Only open storage of frame 14 can be done).

On the other hand, if the OFF inside frame opening flag 203a is OFF (S204: No), it is determined whether the ON inside frame opening flag 203b is ON (S207). If the on-in-frame opening flag 203b is on (S207: Yes), the on-in-frame opening command is transmitted to the voice lamp control device 113 (S208). When the voice lamp control device 113 receives the on-frame opening command, it controls the voice output device 226 and the lamp display device 227 to start the notification that the inner frame 12 or the front frame 14 has been opened. On the other hand, if the on-inside frame opening flag 203b is off (S207: No), an on-inside frame closing command is transmitted to the voice lamp control device 113 (S209). When the voice lamp control device 113 receives the on-frame closing command, the voice lamp control device 113 ends the notification performed by the voice output device 226 and the lamp display device 227. When the on-frame opening flag 203b is on (S207: Yes), a pulse signal having a pulse width of about 1 msec may be output to the hall computer 262 after the process of S208. In this case, since the output pulse signal is stored in the hall computer 262 that continues to operate for 24 hours, the hall computer 262 also specifies the pachinko machine 10 in which the inner frame 12 or the front frame 14 has been opened. be able to.

After the processing of S206, S208 or S209 is completed, the processing for displaying by the first symbol display device 37 and the variation processing for setting the variation pattern of the third symbol by the third symbol display device 81 and the like are executed (S210). The details of the fluctuation process will be described later with reference to FIG.

After the end of the variation process, a large opening opening/closing process for opening or closing the specific winning opening (large opening) 65a of the variable winning device 65 in the case of a big hit state is executed (S211). That is, the specific winning opening 65a is opened for each round of the jackpot state, and it is determined whether the maximum opening time of the specific winning opening 65a has passed or whether a specified number of balls have been won in the specific winning opening 65a. Then, if any of these conditions is established, the specific winning opening 65a is closed. The opening and closing of the specific winning opening 65a is repeatedly executed for a predetermined number of rounds.

Next, the display control process of the second symbol (for example, a symbol of "○" or "x") by the second symbol display device 82 is executed (S212). Briefly described, on the condition that the sphere has passed through the second entrance (through gate) 67, the value of the second random number counter C4 is acquired at the timing of the passage, and the second symbol display device 82 is also acquired. The variable display of the second symbol is carried out on the display section 83 of. Then, the lottery for the second symbol is carried out by the value of the second hit random number counter C4, and when the second symbol is hit, the electric accessory attached to the first entrance 64 is opened for a predetermined time.

After that, it is determined whether or not the power-off occurrence information is stored in the RAM 203 (S213). If the power-off occurrence information is not stored in the RAM 203 (S213: No), the frame open detection circuit 260 causes the MPU 201 to operate. Has not been started up temporarily. Further, the trailing edge of the power failure signal SG1a output from the power failure monitoring circuit 252 is not detected, and the power of the pachinko machine 10 is not shut off. Therefore, in such a case, it is determined whether or not the execution timing of the next main processing has been reached, that is, whether or not a predetermined time (4 ms in the present embodiment) has elapsed since the start of the previous main processing (S214). ). If the predetermined time has already passed (S214: Yes), the process proceeds to S201, and the above-described respective processes after S201 are repeatedly executed.

On the other hand, if the power-off occurrence information is stored in the RAM 203 (S213: Yes), the power of the pachinko machine 10 is off, and the inner frame 12 or the front frame 14 is opened during the power-off, The MPU 201 is temporarily activated by the frame opening detection circuit 260 and the power failure signal SG1b output from the frame opening detection circuit 260 falls, and as a result, the NMI interrupt process of FIG. 17 has been executed, or the pachinko machine 10 When the power is turned on, the power is shut off due to the occurrence of a power failure or the power is turned off, and the power failure signal SG1a output from the power failure monitoring circuit 252 falls. As a result, the NMI interrupt processing of FIG. 17 is executed. Therefore, the processing at the time of power shutdown after S221 is executed. First, the generation of each interrupt process is prohibited (S221), and a power-off command indicating that the power is cut off is sent to other control devices (peripheral control devices such as the payout control device 111 and the voice lamp control device 113). And transmits (S222). Then, the RAM judgment value is calculated, the value is stored (S223), access to the RAM 203 is prohibited (S224), and the infinite loop is continued until the power is completely cut off and the processing cannot be executed. Here, the RAM determination value is, for example, a checksum value in the stack area and work area of the RAM 203 that are backed up.

In the process of S214, if the predetermined time has not yet passed from the start of the previous main process (S214: No), the predetermined time is reached, that is, the remaining time until the execution timing of the next main process is reached. In, the first initial value random number counter CINI1, the second initial value random number counter CINI2, and the variation type counters CS1, CS2, CS3 are repeatedly updated (S215, S216).

First, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S215). Specifically, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are incremented by 1, and when the counter value reaches the maximum value (738 and 250 in this embodiment), it is cleared to 0. To do. Then, the updated values of the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are stored in the corresponding buffer areas of the RAM 203, respectively.

Next, the fluctuation type counters CS1, CS2, CS3 are updated (S216). Specifically, the fluctuation type counters CS1, CS2, CS3 are incremented by 1, and when the counter values reach the maximum values (198, 240, 162 in the present embodiment), they are cleared to 0 respectively. Then, the updated values of the fluctuation type counters CS1, CS2, CS3 are stored in the corresponding buffer areas of the RAM 203, respectively.

Here, since the execution time of each processing of S201 to S212 changes according to the state of the game, the remaining time until the execution timing of the next main processing is not constant but fluctuates. Therefore, by repeatedly updating the first initial value random number counter CINI1 and the second initial value random number counter CINI2 using the remaining time, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 (that is, , The initial value of the first random number counter C1 and the initial value of the second random number counter C4) can be randomly updated, and similarly, the fluctuation type counters CS1, CS2, CS3 can also be randomly updated.

After the processing of S216, the voltage (reset signal SG3b) output from the frame opening detection circuit 260 to the input/output port 205 is read (S217). Then, it is determined whether the output from the frame opening detection circuit 260 to the input/output port (reset signal SG3b) is high (S218). If the output from the frame open detection circuit 260 to the input/output port is high (S218: Yes), the on-frame open flag 203b is turned on (S219). On the other hand, if the output from the frame open detection circuit 260 to the input/output port is not high (S218: No), the on-frame open flag 203b is turned off (S220). After the processing of S219 or the processing of S220, the processing shifts to the processing of S213, and the processing of S213 and thereafter is executed.

Note that the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened while the power is off, and the frame open detection circuit 260 causes the MPU 201 to be temporarily started up. When the reset signal SG3b is output from 260, the on-medium frame release flag 203b is also turned on in addition to the off-medium frame release flag 203a. It takes about 4.4 seconds after the power failure signal SG1b becomes 5 volts until the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 falls from 5 volts to zero volts ( It takes about 4.4 seconds until it is determined to be “Yes” in the processing of S213), and during that time, the processing of S218 is executed in addition to the startup processing, and it is determined to be “Yes” in this processing. Is.

However, even if the on-inside frame opening flag 203b is turned on in addition to the off-inside frame opening flag 203a, if the power of the pachinko machine 10 is next turned on, it is determined as “Yes” in the process of S204. Then, the process does not shift to the process of S207 for determining the state of the on-frame opening flag 203b. Therefore, main controller 110 can transmit only the OFF-in-frame opening command to voice lamp controller 113. Therefore, when the MPU 201 is temporarily activated by the frame open detection circuit 260, the on-in-frame open flag 203b is turned on in addition to the off-in-frame open flag 203a, but this does not cause any problem. is there.

On the other hand, when the inner frame 12 and the front frame 14 are not opened while the power of the pachinko machine 10 is off (when the inner frame 12 and the front frame 14 are closed), naturally, The OFF middle frame release flag 203a is never turned ON. Therefore, when the pachinko machine 10 is powered on next time, it is determined as “No” in the process of S204 and the process of S207 for determining the state of the on-frame opening flag 203b is executed. Naturally, the process of S218 is also executed. Therefore, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned on, the opening is detected by the processing of S217 and the processing of S218, and the processing of S208 executed thereafter. Then, main controller 110 can send only the on-frame open command to voice lamp controller 113.

As described above, when the off-inside frame opening flag 203a is turned on (S204: Yes), the pachinko machine 10 transmits an off-inside frame opening command to the voice lamp control device 113 (S205) and also to the hall computer 262. A pulse signal having a pulse width of about 1 msec is output (S206).

Note that the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened while the power is off, and the drive voltage Vb, the power failure signal SG1b, and the reset signal SG3b are output from the frame open detection circuit 260. The process of S201 to S213: Yes to S224, which is the process executed when the MPU 201 is temporarily started up, is at least the reset signal of the frame open detection circuit 260 due to the discharge of the capacitor CD4 (see FIG. 7). A program is set up so that execution is completed while the reset signal SG3b output from the output terminal drops to about 4.3 volts, that is, about 5.0 seconds (see FIG. 8). ing. The period of about 5.0 seconds is irrespective of the opening time of the inner frame 12 or the front frame 14 (the inner frame 12 or the front frame 14 is opened, and the inner frame 12 or the front frame 14 is immediately opened). (Although is closed), it is a period which is always generated by discharging the capacitor CD4 (see FIG. 8). Therefore, even when the MPU 201 is temporarily started up, the pachinko machine 10 temporarily turns on the off-inside frame opening flag 203a regardless of the opening time of the inner frame 12 or the front frame 14 and then temporarily. The MPU 201 that has started up can be normally terminated.

Note that the processing of S213 is at the timing when the series of processing corresponding to the game state change performed at S201 to S212 ends, or the end of one cycle of the processing of S215 to S220 performed within the remaining time. It is running. Therefore, in the main processing of the main controller 110, since the power-off occurrence information is confirmed at the timing when each setting is completed, when returning from the power-off state, the processing is performed after the start-up processing is completed. The process can be started from S201. That is, the process can be started from the process of S201 as in the case where the process is initialized in the startup process. Therefore, even if the contents of the registers used by the MPU 201 are not saved in the stack area or the stack pointer value is not saved in the power-off process, the stack pointer is not saved in the initial setting process (S101). By setting to a predetermined value (initial value), the process of S201 can be started. Therefore, the control load on the main control device 110 can be reduced, and accurate control can be performed without causing the main control device 110 to malfunction or run away.

Next, the variation process (S204) will be described with reference to FIG. FIG. 13 is a flowchart showing the variation process (S204) executed in the main process (see FIG. 12). In this variation process, first, it is determined whether or not a big hit is currently being made (S301). The jackpot includes the jackpot game displayed on the third symbol display device 81 and the first symbol display device 37 during the jackpot and the predetermined time period after the jackpot game ends. If the result of the determination is that the jackpot is in progress (S301: Yes), this processing is ended.

If it is not a big hit (S301: No), it is determined whether the display mode of the first symbol display device 37 is changing (S302), and if the display mode of the first symbol display device 37 is not changing. (S302: No), it is determined whether or not the number N of operation-holding balls is larger than 0 (S303). If the number N of operation-holding balls is 0 (S303: No), this process is terminated. If the number N of operation-holding balls> 0 (S303: Yes), the number N of operation-holding balls is subtracted by 1 (S304), and the data stored in the holding ball storage area is shifted (S305). This data shift process is a process of sequentially shifting the data stored in the holding first to fourth areas of the holding sphere storage area to the execution area side, that is, the holding first area→the execution area, the holding second area→ The data in each area is shifted such as the first reserved area, the third reserved area→the second reserved area, the fourth reserved area→the third reserved area. After the data shift process, the variation start process of the first symbol display device 37 is executed (S306). The fluctuation start process will be described later with reference to FIG.

In the process of S302, when it is determined that the display mode of the first symbol display device 37 is changing (S302: Yes), it is determined whether the changing time has elapsed (S307). The display time during change of the first symbol display device 37 is determined according to the change pattern selected by the change type counters CS1 and CS2 and the addition time selected by the change type counter CS3, and this change time is If not elapsed (S307: No), the display of the first symbol display device 37 is updated (S308).

In the present embodiment, among the LEDs 37a of the first symbol display device 37, until the variation time elapses after the variation is started, for example, if the currently lit LED is red, the red LED is Turn off the green LED and turn on the green LED. If the green LED is turned on, turn off the green LED and turn on the blue LED. If the blue LED is turned on, turn on the blue LED. A display mode is set in which the LED is turned off and the red LED is turned on.

The variation process is executed every 4 ms, but if the LED lighting color is changed every time the variation process is executed, the player cannot confirm the change in the LED lighting color. Therefore, a counter (not shown) is counted by 1 each time the variation process is executed so that the player can confirm the change in the LED lighting color, and when the counter reaches 100, the LED Change the lighting color of. That is, the lighting color of the LED is changed every 0.4 seconds. The value of the counter is reset to 0 when the lighting color of the LED is changed.

On the other hand, if the variation time of the first symbol display device 37 has elapsed (S307: Yes), the display mode corresponding to the stopped symbol of the first symbol display device 37 is set (S309). The setting of the stop symbol is determined whether or not it is a big hit depending on the value of the first random number counter C1, and in the case of a big hit, a symbol which becomes a high probability state after the big hit by the value of the first hit type counter C2. It is determined whether or not the symbol becomes a low probability state. In the present embodiment, the red LED is turned on when the high probability state is reached after the jackpot, the green LED is turned on when the low probability state is reached, and the blue LED is turned on when the probability is off. .. It should be noted that the display of each LED is turned off when the next change display is started, but may be turned on only for a few seconds after the change is stopped.

When the display mode of the first symbol display device 37 corresponding to the stopped symbol is set in the process of S309, the stop of the fluctuation of the third symbol display device 81 is stopped in order to synchronize with the lighting of the LED in the first symbol display device 37. The command is set (S310). Upon receiving this stop command, the voice lamp control device 113 gives a stop instruction to the display control device 114. The third symbol display device 81 stops the variation when the variation time elapses, and by receiving the stop command, the variation effect of 1 in the third symbol display device 81 ends.

Next, the fluctuation start process will be described with reference to FIG. FIG. 14 is a flowchart showing the fluctuation start process (S306) executed in the fluctuation process (see FIG. 13). In the fluctuation start process (S306), first, it is determined whether or not it is a big hit based on the value of the first winning random number counter C1 stored in the execution area of the reserved ball storage area (S401). Whether or not it is a big hit is determined based on the relationship between the value of the first random number counter C1 and the mode at that time. As described above, "373,727" of the numerical values 0 to 738 of the first random number counter C1 is the winning value at the normal low probability, and "59,109,163,211,263,317,367," at the high probability. "421, 479, 523, 631, 683, 733" is the winning value.

When it is determined that it is a big hit (S401: Yes), the value of the first hit type counter C2 stored in the execution area of the reserved ball storage area is confirmed, and the display mode at the time of a big hit is set (S402). ). In the process of S402, whether to shift to the high-probability state or the low-probability state after the big hit is set based on the value of the first hit type counter C2. When the transition state after the big hit is set, the display mode of the first symbol display device 37 (the lighting state of the LED 37a) is set. Also, based on the transition state after the big hit, the big hit stop symbol that is stopped and displayed on the third symbol display device 81 is set by the voice lamp control device 113 and the display control device 114. That is, the stop symbol in the third symbol display device 81 is set by setting the transition state after the big hit by the process of S402. In addition, among the numerical values 0 to 4 of the first hit type counter C2, in the case of "0, 4", the state shifts to the low probability state thereafter, and in the case of "1, 2, 3", the state shifts to the high probability state. ..

Next, the variation pattern at the time of a big hit is determined (S403). When the variation pattern is set in the process of S403, the display time of the first symbol display device 37 is set, and the variation time of the third symbol until the big symbol symbol stops on the third symbol display device 81 is determined. R. At this time, the values of the fluctuation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and based on the value of the first fluctuation type counter CS1, normal reach, super reach, premium reach, and other rough symbol fluctuations While determining the variation time, the variation time (in other words, variation symbol number) until the final stop symbol (in the present embodiment, the medium symbol Z2) is stopped after the reach is generated based on the value of the second variation type counter CS2 decide.

Note that the relationship between the numerical value of the first fluctuation type counter CS1 and the fluctuation time and the relationship between the numerical value of the second fluctuation type counter CS2 and the fluctuation time are preliminarily defined by a table or the like. However, the fluctuation time can be set using only the value of the first fluctuation type counter CS1 without using the value of the second fluctuation type counter CS2, and is set only by the value of the first fluctuation type counter CS1. Whether to set or to set with both values of both fluctuation type counters CS1 and CS2 is appropriately determined according to the value of the first fluctuation type counter CS1 and the game condition at each time.

When it is determined in the processing of S401 that the jackpot is not the big hit (S401: No), the display mode at the time of the deviation is set (S404). In the process of S404, the display mode of the first symbol display device 37 is set to a display mode corresponding to the out-of-design, and based on the value of the stop pattern selection counter C3 stored in the execution area of the reserved ball storage area, The effect displayed on the third symbol display device 81 is set to be a front/rear outreach, a reach other than the front/rear outreach, or a complete outreach. In the present embodiment, as described above, the range of values corresponding to each stop pattern of the stop pattern selection counter C3 is determined according to the high-probability state, the low-probability state, and the number N of operation suspensions. The tables are set differently.

Next, the variation pattern at the time of detachment is determined (S405), the display time of the first symbol display device 37 is set, and the variation time of the third symbol until it stops at the detachment symbol on the third symbol display device 81. Is determined. At this time, similarly to the processing of S403, the values of the fluctuation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and the normal reach, super reach, and premium reach are determined based on the values of the first fluctuation type counter CS1. While determining the variation time of the rough symbol variation such as, the variation time until the final stop symbol (the middle symbol Z2 in the present embodiment) stops after the reach is generated based on the value of the second variation type counter CS2 (in other words, For example, determine the number of variable symbols).

When the process of S403 or the process of S405 ends, the effect time that is added to or subtracted from the fluctuation time determined by the first and second type counters CS1 and CS2 is determined (S406). At this time, addition/subtraction of the effect time is determined based on the value of the third type counter CS3 stored in the counter buffer of the RAM 203, the display time of the first symbol display device 37 is set, and the third symbol display is performed. The variation time of the device 81 is set. In the present embodiment, the addition/subtraction of the effect time is determined by changing the variable display time by 2 when the variable display time is not changed and when the variable display time is added by 1 second according to the value of the third fluctuation type counter CS3. When adding seconds, four types of addition values are determined, which are the case where the variable display time is subtracted by 1 second.

In addition, when the variable display time is added or subtracted, a notice effect that the expected value of the big hit in the third symbol display device 81 becomes high (for example, a sliding effect in which the variation time of the variable symbol is made longer than usual to cause slippage, The effect of displaying the advance notice character, the effect of making the fluctuation time of the fluctuation pattern 1 shorter than usual and immediately stopping) are performed. Further, when the value of the first random number counter C1 is a big hit, the probability that the additional value of 2 seconds is selected is set high, so the player should expect a big hit by confirming the notice effect. You can

Next, the variation pattern command is set according to the variation pattern (variation time) determined in the processing of S403 or S405 (S407), and the stop symbol command is set according to the stop symbol set in the processing of S402 or S404. Yes (S408). Then, an effect time addition command is set according to the added value of the effect time determined in the process of S406 (S409), and the process returns to the variation process.

Next, with reference to FIGS. 18 to 20, the processing performed by the audio lamp control device 113 will be described. FIG. 18 is a flowchart showing a startup process executed by the MPU 221 in the voice lamp control device 113. This startup process is started when the power is turned on.

When the start-up process is executed, first, an initial setting process accompanying power-on is executed (S1001). Specifically, the stack pointer is set to a predetermined value. After that, depending on whether or not the power-off processing in progress flag is turned on, the power-up processing of S1115 (see FIG. 19) occurs due to a momentary voltage drop (instantaneous power failure, so-called “instantaneous stop”) in the startup processing of this time. It is determined whether or not the process is started during the execution of () (S1002). As will be described later with reference to FIG. 19, when the voice lamp control device 113 receives a power-off command from the main control device 110 (see S1112 of FIG. 19), the power-off process of S1115 is executed. The power-off processing flag is turned on before the power-off processing is executed, and the power-off processing flag is turned off after the power-off processing is completed. Therefore, whether or not the power-off processing in S1115 is being executed can be determined by the state of the power-off processing in progress flag.

If the power-off processing in progress flag is off (S1002: No), the startup processing of this time is started after the power is completely cut off, or after a momentary power failure occurs and the power-off in S1115 is performed. It is started after the execution of the process is completed, or is started (without receiving the power-off command from the main control unit 110) only on the MPU 221 of the voice lamp control unit 113 due to noise or the like. is there. Therefore, in these cases, it is confirmed whether or not the data in the RAM 223 is destroyed (S1003).

The confirmation of the data destruction of the RAM 223 is performed as follows. That is, the data as the keyword “55AAh” is written in the specific area of the RAM 223 by the processing of S1006. Therefore, it is possible to check the data stored in the specific area, and if the data is "55AAh", there is no data destruction in the RAM 223, and conversely, if it is "55AAh", it is possible to confirm the data destruction in the RAM 223. If the data destruction of the RAM 223 is confirmed (S1003: Yes), the process proceeds to S1004 and the initialization of the RAM 223 is started. On the other hand, if the data destruction of the RAM 223 is not confirmed (S1003: No), the process proceeds to S1008.

If the power-on process is started after the power is completely cut off, the keyword "55AAh" is not stored in the specific area of the RAM 223 (the memory of the RAM 223 is lost due to the power-off). Therefore, it is determined that the data in the RAM 223 has been destroyed (S1003: Yes), and the process proceeds to S1004. On the other hand, the startup process of this time was started after the momentary power failure occurred and after the execution of the power-off process of S1115 was completed, or only the MPU 221 of the audio lamp control device 113 was reset due to noise or the like. If it is started due to the trouble, the keyword “55AAh” is stored in the specific area of the RAM 223, so that the data of the RAM 223 is determined to be normal (S1003: No), and the process proceeds to S1008.

If the power-off processing in progress flag is on (S1002: Yes), the start-up processing this time is after the momentary power failure has occurred and during the execution of the power-off processing of S1115, the voice lamp control device 113 is executed. The MPU 221 has been reset and started. In such a case, since the power-off process is being executed, the storage state of the RAM 223 is not always correct. Therefore, in such a case, control cannot be continued, so the process moves to S1004, and initialization of the RAM 223 is started.

In the process of S1004, the entire storage area of the RAM 223 is checked (S1004). As a check method, first, “0FFh” is written for each byte, and it is read for each byte to check whether it is “0FFh”. If “0FFh”, it is determined to be normal. Such writing and confirmation for each byte is performed in the order of “55h”, “0AAh”, and “00h” after “0FFh”. By this read/write check of the RAM 223, all storage areas of the RAM 223 are cleared to 0.

If the read/write check is determined to be normal for all the storage areas of the RAM 223 (S1005: Yes), the keyword “55AAh” is written in the specific area of the RAM 223 to set the RAM destruction check data (S1006). By checking the keyword "55AAh" written in this specific area, it is checked whether or not there is data destruction in the RAM 223. On the other hand, if a read/write check abnormality is detected in any of the storage areas of the RAM 223 (S1005: No), the abnormality of the RAM 223 is notified (S1007), and an infinite loop is performed until the power is cut off. The abnormality of the RAM 223 is notified by the display lamp 34. The voice output device 226 may output voice to notify the abnormality of the RAM 223.

In the processing of S1008, it is determined whether or not the power-off flag is turned on (S1008). Since the power-off flag is turned on when the power-off process of S1115 is executed (see S1114 of FIG. 19), the power-off flag is turned on by the process of S1114, as described later with reference to FIG. That is, since the power-off flag is turned on before the power-off process of S1115 is executed, the process of S1008 with the power-off flag turned on is that the startup process of this time is instantaneous. This is the case after the power failure has occurred and the power-off process of S1115 is started without being completed. Therefore, in such a case (S1008: Yes), the work area of the RAM is cleared to initialize each process of the voice lamp control device 113 (S1009), the initial value of the RAM 223 is set (S1010), and then the interruption is performed. The permission is set (S1011), and the process proceeds to the main process. The work area of the RAM 223 is an area other than the area for storing commands and the like received from the main controller 110.

On the other hand, the reason why the process of S1008 is reached with the power-off flag turned off is that the present startup process is started after the power has been completely cut off, for example, and the process of S1004 to S1006 is followed to the process of S1008. This is the case when the processing has been started, or only the MPU 221 of the audio lamp control device 113 has been reset due to noise or the like (without receiving the power-off command from the main control device 110) and started. Therefore, in such a case (S1008: No), S1009 which is a work area clearing process of the RAM 223 is skipped, the process proceeds to S1010, the initial value of the RAM 223 is set (S1010), and then the interrupt permission is set. Then (S1011), the process proceeds to the main process.

It should be noted that the clear processing of S1009 is skipped because all the storage areas of the RAM 223 have already been cleared by the processing of S1004 when the processing of S1004 is passed through the processing of S1004 to the processing of S1008. When only the MPU 221 of the voice lamp control unit 113 is reset due to noise or the like and the start-up process is started, the data in the work area of the RAM 223 is saved without being cleared. This is because the control of can be continued.

Next, with reference to FIG. 19, a main process executed after the startup process of the voice lamp control device 113 will be described. FIG. 19 is a flowchart showing the main processing executed by the MPU 221 of the voice lamp control device 113. When the main process is executed, first, it is determined whether or not 1 msec or more has elapsed from the start of the main process (S1101), and if 1 msec or more has not elapsed (S1101: No), S1102 to S1109. The process shifts to S1110 without performing the process. In the process of S1101, determining whether 1 msec has elapsed is a process related to display (effect) in S1102 to S1109, and it is not necessary to edit in a short cycle (within 1 msec). This is because it is preferable to execute the updating process of each counter and the command receiving process of S1111 in a short cycle. As a result, it is possible to prevent omission of reception of commands transmitted from main controller 110.

If 1 ms or more has elapsed in the process of S1101 (S1101: Yes), the output of each lamp is set so that the lighting mode of the display lamp 34 is set or the lighting mode of the lamp edited in the process of S1107 described later is set. (S1102), and then the power-on notification process is executed (S1103). The power-on notification processing is to notify that the power is turned on for a predetermined time (for example, 30 seconds) when the power is turned on, and the notification is performed by the voice output device 226 or the lamp display device 227. Be seen. Further, a command may be transmitted to the display control device 114 so as to notify that the power is supplied on the screen of the third symbol display device 81. If it is not when the power is turned on, the process proceeds to the process of S1104 without performing the notification by the power-on notification process.

In the process of S1104, the customer waiting effect is executed, and then the retained quantity display update process is executed (S1105). In the customer waiting production, when the pachinko machine 10 is not played by the player for a predetermined time, the setting of switching the display of the third symbol display device 81 to the title screen is performed, and the setting is a command as a display control device. Sent to 114. In the retained quantity display updating process, a process of turning on the retaining lamp 85 according to the operation retaining ball N is performed.

Thereafter, frame button input monitoring/effect processing is executed (S1106). In this frame button input monitoring/production process, the input of whether or not the frame button 22 operated by the player in order to enhance the production effect is pressed is monitored, and it corresponds to the case where the input of the frame button 22 is confirmed. It is a process of setting to produce an effect. For example, when the notice character appears at the start of the variable display, pressing the frame button 22 displays the expected value of the jackpot due to this change, or by pressing the frame button 22 during the reach production, the expectation for the jackpot is displayed. It may be changed to a production that can be held or may be an enter button for selecting one of the reach productions. If the frame button 22 is not provided, the process of S1106 is omitted.

When the frame button input monitoring/effect process is finished, the ramp edit process is executed (S1107), and then the sound edit/output process is executed (S1108). In the lamp editing process, the lighting patterns of the illumination portions 29 to 33 are set so as to correspond to the display performed on the third symbol display device 81. In the sound editing/output process, the output pattern of the voice output device 226 is set so as to correspond to the display performed on the third symbol display device 81, and the sound is output from the voice output device 226 according to the setting.

Thereafter, the liquid crystal effect execution management process is executed (S1109), and the process proceeds to S1110. In the liquid crystal effect execution management process, time synchronized with the time required for the variable display performed on the third symbol display device 81 is set based on the variable pattern command and the effect time addition command transmitted from the main control device 110. Based on the time set in the liquid crystal effect execution monitoring process, the effect time of the lamp edit process of S1107 and the sound edit/output process of S1108 is set.

In the process of S1110, the variable display process of the third symbol display device 81 is executed. In this variable display processing, a plurality of counters (a counter for setting a stop symbol at the time of jackpot, a counter for selecting a stop symbol at the time of disengagement, etc.) mounted on the voice lamp control device 113 are updated, and the value of the counter and the main value are updated. Based on the variation pattern command and the stop symbol command transmitted from the control device 110, the symbol which is stopped and displayed on the third symbol display device 81 is set, and the pattern of the variable display (front/rear outreach, reach other than front/rear out, complete detachment) Etc. are set. The stop symbol and the variation pattern are transmitted to the display control device 114 as a command.

In the process of S1110, for example, when the command of the variation pattern transmitted from the main control device 110 is "completely missed", the completely missed A pattern is selected from among a plurality of patterns corresponding to the perfect miss, and the third symbol display is performed. A command is transmitted to the display control device 110 so that the device 81 produces the effect of the completely separated A pattern. Therefore, for one variation pattern determined by the main control device 110, the detailed variation pattern displayed on the third symbol display device 81 is determined by the voice lamp control device 113, so that the control of the main control device 110 is performed. The burden can be reduced. Furthermore, since the patterns of each effect determined in main controller 110 can be reduced, the storage capacity of ROM 202 can be reduced, and the cost can be reduced.

Then, the command from the main controller 110 is received (S1111). When the command from the main controller 110 is received, if the command is used by the voice lamp controller 113 according to the command, the process corresponding to the command is performed, the processing result is stored in the work RAM 233, and the display controller 114. If it is a command to be used, the command is transmitted to the display control device 114.

After the processing of S1111 is completed, it is determined whether or not the power-off occurrence information is stored in the work RAM 233 (S1112). The power-off occurrence information is stored when a power-off command is received from main controller 110. If the power-off occurrence information is stored in the process of S1112 (S1112: Yes), both the power-off flag and the power-off process in progress flag are turned on (S1114), and the power-off process is executed (S1115). After the power-off process is executed, the power-off process in progress flag is turned off (S1116), and then the process is infinitely looped. In the power-off process, the generation of the interrupt process is prohibited, each output port is turned off, and the outputs from the audio output device 226 and the lamp display device 227 are turned off. Also, the storage of the information on the occurrence of power failure is erased.

On the other hand, if the power-off occurrence information is not stored in the process of S1112 (S1112: No), either the inner frame 12 or the front frame 14 is opened, or both the inner frame 12 and the front frame 14 are opened. If there is, a door opening notification process (S1113) for performing notification using the voice output device 226 and the lamp display device 227 is executed.

Here, the door opening notification process (S1113) will be described with reference to FIG. FIG. 20 is a flowchart showing a door opening notification process executed by the MPU 221 of the voice lamp control device 113. This door opening notification processing determines whether or not the voice lamp control device 113 has received any one of an off-inside frame opening command, an on-inside frame opening command, and a frame closing command, and makes a notification according to the determination. This is a process that starts or ends execution.

In the door open notification process, first, in the process of S1111 (see FIG. 19 ), an OFF middle frame open command indicating that the inner frame 12 or the front frame 14 is open while the power of the pachinko machine 10 is turned off is received. It is determined whether or not (S1201). When the off-frame opening command is received (S1201: Yes), the audio output device 226 and the lamp display device indicate that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off. Notification is started using 227 (S1202). Specifically, in this notification, for example, the lamp display device 227 is used to indicate that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. Blinking is started once per second, and the voice output device 226 is used to start an electronic sound "Please check". As a result, it is possible to notify an unspecified number of people that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off.

After the processing of S1202, the frame opening notification processing ends. When the notification in the process of S1202 has already been executed, if the off-inside frame open command is received again in the process of S1111 (S1201: Yes), the process of S1202 is not performed again. The processing of S1202 that has already been executed is continuously executed.

On the other hand, in the process of S1111 (see FIG. 19), when the off-inside frame open command is not received (S1201: No), the power of the pachinko machine 10 is turned on in the process of S1111 (see FIG. 19). It is determined whether or not an on-frame opening command indicating that the inner frame 12 or the front frame 14 has been opened is received during the period (S1203). When an on-frame opening command is received (S1203: Yes), the audio output device 226 and the lamp display device indicate that the inner frame 12 or the front frame 14 has been opened while the pachinko machine 10 is powered on. Notification is started using 227 (S1204). Specifically, in this notification, for example, the lamp display device 227 is used to indicate that the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered on. Blinking is started once per second, or the voice output device 226 is used to start notification by electronic sound that the door is open. Thereby, it is possible to notify an unspecified number of people that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned on.

Furthermore, in the process of S1111 (see FIG. 19), if the on-frame open command is not received (S1203: No), the power of the pachinko machine 10 is turned on in the process of S1111 (see FIG. 19). It is determined whether or not an ON-inside frame closing command indicating that the inner frame 12 and the front frame 14 are closed while being received is received (S1205). When the on-frame closing command is received (S1205: Yes), the notification started in the process of S1204 ends (S1206). After that, the frame opening notification process ends. In the process of S1111 (see FIG. 19), if the on-frame closing command has not been received (S1205: No), the frame opening notification process ends.

As described above, when the voice lamp control device 113 receives the OFF-inside frame opening command in the process of S1111 (see FIG. 19), the inner frame 12 or the front frame is turned on while the pachinko machine 10 is powered off. Notification of the opening of 14 is started using the voice output device 226 and the lamp display device 227 (S1202). This notification is performed by operating the RAM erasing switch 122, turning on the power of the pachinko machine 10, and by the process of S116 of the startup process of the main control device 110 until the off middle frame open flag 203a is turned off. It will continue.

As described above, in order to turn off the off-inside frame opening flag 203a that has been turned on, unless the RAM erase switch 122 is operated and the pachinko machine 10 is powered on and the used RAM area is cleared in the processing of S116. , OFF The open frame flag 203a cannot be turned off. Therefore, when the power of the pachinko machine 10 is turned on, the pachinko machine 10 certainly does not confirm that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. It is possible to notify a specified number of people.

Further, as described above, when the voice lamp control device 113 receives the ON-in-frame opening command in the processing of S1111 (see FIG. 19), the inner frame 12 or while the pachinko machine 10 is powered on. Notification that the front frame 14 has been opened is started using the voice output device 226 and the lamp display device 227 (S1204). Since this notification is continuously performed until the inner frame 12 and the front frame 14 are closed and the ON-in-frame close command is received, the inner frame 12 or the front frame 12 is turned on while the pachinko machine 10 is powered on. It is possible to notify an unspecified number of people that the frame 14 is open.

Returning to the explanation of FIG. After the door opening notification process (S1113) is executed, it is determined whether or not the RAM 223 is destroyed based on the keyword stored in the RAM 223 (S1117). If the RAM 223 is not destroyed (S1117: No), S1101 is executed. Returning to the processing, the main processing is repeatedly executed. On the other hand, if the RAM 223 is destroyed (S1117: Yes), the process is infinitely looped to stop the execution of the subsequent processes. Here, if it is determined that the RAM is destroyed and the loop is infinite, the main process is not executed, and thereafter the display by the third symbol display device 81 does not change. Therefore, since the player can know that the abnormality has occurred, he can call a clerk in the hall or the like to request the pachinko machine 10 to be repaired. Further, when it is confirmed that the RAM 223 is destroyed, the voice output device 226 or the lamp display device 227 may be used to notify the RAM destruction.

As described above, according to the pachinko machine 10, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off, the frame open detection circuit 260 causes the frame open detection circuit 260 to detect the drive voltage Vb and After outputting the power failure signal SG1b, the reset signal SG3b is output. Therefore, even if the pachinko machine 10 is powered off, the MPU 201 can be temporarily started up normally. It should be noted that when the pachinko machine 10 is powered off and the MPU 201 is temporarily activated by the frame opening detection circuit 260, the pachinko machine 10 turns on the in-off frame opening flag 203a. When the off-inside frame opening flag 203a is turned on, the pachinko machine 10 uses the voice output device 226 and the lamp display device 227 to display the inner frame 12 or the front frame when the power of the pachinko machine 10 is turned on next time. Notify that 14 has been opened. Therefore, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. Therefore, even in a game hall where the hall computer 262 is not operated for 24 hours, it is possible to detect that the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off.

Further, the off-in-frame opening flag 203a is turned off when the RAM erasing switch 122 is operated to clear the used RAM area in the process of S116 of the startup process of the main controller 110. Therefore, once the off-inside frame open flag 203a is turned on, the off-inside frame open flag 203a cannot be turned off unless the RAM erase switch 122 is operated to clear the used RAM area in the processing of S116. Therefore, when the inner frame 12 or the front frame 14 is opened and the off-inside frame open flag 203a is turned on when the power of the pachinko machine is turned off, after that, the cheating person turns off the off-inside frame. It may be impossible to turn off the open flag 203a. Further, since the off-in-frame opening flag 203a cannot be turned off unless the RAM erasing switch 122 is operated to clear the used RAM area in S116, when the pachinko machine 10 is powered on, The pachinko machine 10 can reliably notify the unspecified number of people that the inner frame 12 or the front frame 14 has been opened while the power of the pachinko machine 10 is off.

Further, when the pachinko machine 10 is powered off and the MPU 201 is temporarily activated by the frame open detection circuit 260, the pachinko machine 10 turns on the off-time frame open flag 203a, and also in addition to the hall computer. A pulse signal having a pulse width of 1 msec is output to 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours. Therefore, by analyzing the pulse signal stored in the hall computer 262, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. You can Furthermore, by storing the pulse signal output from the pachinko machine 10 to the hall computer 262 and storing the output time of the output pulse signal, the opening time of the inner frame 12 or the front frame of the specified pachinko machine 10 is stored. The opening time of 14 can be detected.

Further, in the frame open detection circuit 260, when the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 becomes conductive, and about 4.4 seconds after the conduction, first, the power failure signal SG1b is stopped ( If the open inner frame 12 or the open front frame 14 is closed before the switch SW1 or the switch SW2 is turned on and about 4.4 seconds have passed after the turn-on, a stop signal is issued when the switch is closed. Stop SG1b). Next, the frame opening detection circuit 260 stops the reset signal SG3b when about 9.4 seconds have passed after the switch SW1 or the switch SW2 was turned on (about 4.4 seconds passed after the switch SW1 or the switch SW2 was turned on). When the opened inner frame 12 or the opened front frame 14 is closed before, the reset signal SG3b is stopped about 5.0 seconds after the closing). Then, the frame opening detection circuit 260 reduces the drive voltage Vb output to the power supply terminal of the MPU 201 to about 4.0 volts when about 9.9 seconds have elapsed after the switch SW1 or the switch SW2 was turned on (the switch SW1 or the switch SW1 or If the opened inner frame 12 or the opened front frame 14 is closed before about 4.4 seconds have passed after the switch SW2 is turned on, the drive is performed about 5.5 seconds after the closing. The voltage Vb is reduced to about 4.0 volts). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily activated by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

In addition, even if the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is conducted, the frame open detection circuit 260 detects that the inner frame 12 or the front frame is still in operation for about 4.4 seconds. Regardless of the open period of 14, the transistor TR1 stops the output of the driving voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4, which are performed by the electric power supplied from the capacitor CD1. After the stop by the transistor TR1, the frame open detection circuit 260 outputs the drive voltage Vb and the reset signal SG3b by discharging the capacitor CD4. Therefore, the frame opening detection circuit 260, for example, when the business hours of the game hall is finished and the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1 to the frame opening detection circuit 260. That is, that is, when the DC voltage of about 11.3 volts is supplied from the capacitor CD1 to the frame open detection circuit 260, the period during which the power is supplied from the capacitor CD1 is the open period of the inner frame 12 or the front frame 14. Regardless, it can be held for about 4.4 seconds. Therefore, the frame opening detection circuit 260 can suppress the consumption of the electric power charged in the capacitor CD1 and detect the opening of the inner frame 12 or the front frame 14 multiple times.

Even if the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the frame open detection circuit 260 is opened before about 4.4 seconds elapses from the time when the switch SW1 or the switch SW2 is turned on. When the frame 12 or the opened front frame 14 is closed, the switch SW1 or the switch SW2 is cut off, and the output of the drive voltage Vb, the output of the reset signal SG3b, and the power failure signal SG1b performed by the power supplied from the capacitor CD1. And the charging of the capacitor CD4 are stopped. After the inner frame 12 and the front frame 14 are closed, the drive voltage Vb and the reset signal SG3b are output by discharging the capacitor CD4.

In this way, when the charging of the capacitor CD4 is completed, after that, the driving voltage Vb and the reset signal SG3b can be output by discharging the capacitor CD4, so that the opening period of the inner frame 12 or the front frame 14 is about. If it is within 4.4 seconds, the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4, which are performed by the power supply from the capacitor CD1, are further shortened. Can be kept at. Therefore, the power consumption of the capacitor CD1 due to the opening of the inner frame 12 or the front frame 14 can be further suppressed.

Here, since the capacitance of the capacitor CD1 is 1F and the voltage applied to the capacitor CD1 is about 11.3 volts, the charge accumulated in the capacitor CD1 is the product of the capacitance of the capacitor CD1 and the applied voltage of the capacitor CD1. To about 11.3 C (coulomb). The electric charge of about 11.3C stored in the capacitor CD1 is about during each period of the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b and the charging of the capacitor CD4 which are performed by the power supply from the capacitor CD1. In the case of 4.4 seconds, the number of times power is supplied corresponds to about 11 times. Therefore, for example, when the power supply to the pachinko machine 10 is cut off after the business hours of the game arcade and the DC voltage of 12 V is not supplied from the DC power supply DC1, the inner frame 12 is opened (the switch SW1 is turned on). Even when the front frame 14 is opened (conduction) or the front frame 14 is opened (conduction of the switch SW2) for a plurality of times, the frame open detection circuit 260 opens the inner frame 12 or opens the front frame 14 (conduction of the switch SW1 or It is possible to reliably detect that the switch SW2 is turned on up to about 11 times each time, temporarily start the MPU 201 normally, and turn on the off-inside frame open flag 203a. At this time, when the inner frame 12 is opened or the front frame 14 is opened about 11 times, the electric power stored in the capacitor CD1 decreases, and the driving voltage Vb decreases, the reset signal SG3 decreases, and the power failure signal SG1 decreases. A decrease and a decrease in the charge amount of the capacitor CD4 occur. However, when the inner frame 12 or the front frame 14 is opened, the voltage of the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 exceeds about 4.3 V and the frame open detection circuit 260 is released. If the voltage of the drive voltage Vb output from the power output terminal of the power supply and the voltage of the power failure signal SG1b output from the power failure signal output terminal of the frame open detection circuit 260 exceeds about 4.0 volts, the power of the pachinko machine 10 is Even if it is turned off, the MPU 201 can be temporarily started up normally and the off-inside frame open flag 203a can be turned on. Furthermore, a pulse signal having a pulse width of 1 msec can be output to the hall computer 262.

In the frame opening detection circuit 260, when the inner frame 12 and the front frame 14 are closed (when the switches SW1 and SW2 are cut off), the OUT terminal voltage of the timer IC1 is about 10.6 volts. Therefore, the drain opening D and the source terminal S of the FET1 and the drain terminal D and the source terminal S of the FET2 of the frame opening detection circuit 260 are in a conductive state. Since the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 3 are electrically connected. However, at this time, since the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off, the drain terminal D and the source terminal S of the FET1 and the drain terminal D and the source terminal of the FET2 are cut off. The current from the capacitor CD1 does not flow between the terminals S and S3 and between the drain terminal D and the source terminal S of the FET3. Therefore, when the inner frame 12 and the front frame 14 are closed, the electric power charged in the capacitor CD1 is generated between the drain terminal D and the source terminal S of the FET1 and between the drain terminal D and the source terminal S of the FET2. It does not flow between the terminals and between the drain terminal D and the source terminal S of the FET 3 and are not consumed.

Further, the power consumption of the capacitor CD1 by the frame opening detection circuit 260 when the pachinko machine 10 is powered off and the inner frame 12 and the front frame 14 are closed is determined by the standby power of the timer IC1 and the power consumption of the NOTIC3. It is a degree. Moreover, since a voltage is only applied to each gate terminal G of the FET1 to FET3, the power consumed by the FET1 to FET3 is very small. Therefore, the consumption of these powers does not cause a significant reduction in the amount of charge of the capacitor CD1.

In the pachinko machine 10 of the present embodiment, the notification that the inner frame 12 or the front frame 14 has been opened is performed using the audio output device 226 and the lamp display device 227 controlled by the audio lamp control device 113. However, it is not limited to this. Instead of using the voice output device 226 and the lamp display device 227 controlled by the voice lamp control device 113 to notify that the inner frame 12 or the front frame 14 has been opened, it becomes possible to operate when the MPU 201 starts up. It is of course possible to use an audio output device or a lamp display device controlled by the MPU 201. However, in this case, when the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened by a cheating person, and the frame open detection circuit 260 temporarily starts up the MPU 201. Then, the voice output device and the lamp display device controlled by the MPU 201 also start up, and when the off-inside frame open flag 203a is turned on, the fraudulent person is notified. Here, it is executed when the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened while the power is off, and the frame open detection circuit 260 temporarily starts up the MPU 201. The processing of S201 to S213: Yes to S224 (see FIG. 12), which is the processing performed, is such that at least the reset signal SG3b output from the reset signal output terminal of the frame opening detection circuit 260 by the discharge of the capacitor CD4 is about 4. The program is designed so that the execution is completed in the period until the voltage drops to 3 volts, that is, in the period of about 5.0 seconds (see FIG. 8). When making use of this identification to notify by the audio output device or the lamp display device that the MPU 201 controls, the time after the power of the pachinko machine 10 is turned on is measured by a counter, and for example, the power of the pachinko machine 10 is The notification may be started 30 seconds after being turned on (after the counter measures 30 seconds). Then, when the MPU 201 is temporarily activated by the frame opening detection circuit 260, 30 seconds after the power of the pachinko machine 10 is turned on, that is, before the counter counts 30 seconds. , Since the MPU 201 has been shut down (because it has ended), the notification is not executed, but when the power of the pachinko machine 10 is turned on normally and the MPU 201 is started, the notification is performed. It is possible to perform notification when the power of the pachinko machine 10 is normally turned on while preventing notification to the actor.

In the pachinko machine 10 of the present embodiment, when the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened, and the switch SW1 or the switch SW2 is electrically connected. The output of the voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4 are started, but the present invention is not limited to this. That is, when the connection of each component mounted in the frame opening detection circuit 260 of the pachinko machine 10 is changed, the inner frame 12 or the front frame 14 is opened, and the opened inner frame 12 or the front frame 14 is closed. In addition, the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4 may be started from the time of closing.

However, in the frame opening detection circuit 260 of the pachinko machine 10 of the present embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is conducted, the output of the reset signal SG3b is started. With this configuration, the opening of the inner frame 12 or the front frame 14 can be quickly detected. Therefore, particularly during business hours when the power of the pachinko machine 10 is turned on, before the inner frame 12 or the front frame 14 is opened and a fraudulent act is performed on the main controller 110 or the game board 13, the inner frame 12 is opened. Alternatively, the opening of the front frame 14 can be detected. Therefore, it is possible to prevent abnormal operation due to fraudulent behavior that occurs when power is supplied to the pachinko machine 10.

It should be noted that the main frame opening detection circuit 260 is used to separately store which of the inner frame 12 and the front frame 14 is opened by using a flag, and to notify the opening of the inner frame 12 or the front frame 14 separately. When it is desired to separately store which of the inner frame 12 and the front frame 14 is opened in the hall computer 262, the following configuration may be adopted. First, one frame opening detection circuit 260 used in the present embodiment is newly added, the switch SW2 connected in parallel to the switch SW1 is cut off, and the cut switch SW2 is added to the newly added frame opening detection circuit 260. Connecting. Specifically, one end of the disconnected switch SW2 is connected to one end of the capacitor CD1 of the newly added frame opening detection circuit 260, the VDD terminal of the timer IC1 and the RES terminal of the timer IC1, and the other of the disconnected switch SW2 is connected. The end may be connected to one end of the resistor R1 of the newly provided frame opening detection circuit 260, one end of the resistor R2, the input terminal of the NOTIC3, one end of the resistor R3, and the emitter terminal e of the transistor TR1.

The power output terminal, the reset signal output terminal, and the power failure signal output terminal of the added frame opening detection circuit 260 are replaced by the power supply output terminal, the reset signal output terminal, and the power failure signal output of the existing frame opening detection circuit 260. Connect in parallel to the terminals. Further, the reset signal output terminal of the added frame opening detection circuit 260 is connected to an input port different from the input port to which the reset signal output terminal of the existing frame opening detection circuit 260 is connected to the input/output port 205. As a result, the MPU 201 can be temporarily activated separately when the switch SW1 is conducted (the inner frame 12 is opened) and when the switch SW2 is conducted (the front frame 14 is opened). Further, when there is conduction of the switch SW1 (opening of the inner frame 12), there is conduction of the reset signal SG3b output from the existing frame opening detection circuit 260 and conduction of the switch SW2 (opening of the front frame 14). In addition, the reset signal SG3b output from the newly added frame opening detection circuit 260 can be separately output to the input/output port 205.

In addition, the RAM 203 is provided with four flags: an inside-off-frame opening flag, an off-front-side frame opening flag, an on-inside frame opening flag, and an on-front frame opening flag. Then, in the process of S110 of the start-up process (see FIG. 11), the voltage (reset signal SG3b) output from the existing frame open detection circuit 260 to the input/output port 205 is read and the newly added frame open detection is performed. The voltage (reset signal SG3b) output from the circuit 260 to the input/output port 205 may be read. In accordance with the read result, in the process of S112, the OFF inner frame opening flag or the OFF front frame opening flag is individually turned ON.

Then, in the process of S205 of the main process (see FIG. 12), when the OFF inner frame opening flag is turned ON, the MPU 201 transmits an “OFF inner frame opening command” to the voice lamp control device 113 to turn OFF. When the middle front frame opening flag is turned on, the MPU 201 transmits an “off middle front frame opening command” to the voice lamp control device 113. Then, when the voice lamp control device 113 receives each command transmitted from the MPU 201 when the power of the pachinko machine 10 is turned on, the voice lamp control device 113 receives the off-time inner frame opening command and the off-time. Notification is made in a different mode from when the front frame opening command is received. For example, different warning sounds are output from the audio output device 226, and the lighting mode of the lamp display device 227 is changed.

In addition, the pulse width of the pulse signal transmitted from the pachinko machine 10 to the hall computer 262 may be changed in the processing of S206 in accordance with the ON state of each flag of the OFF inner frame opening flag or the OFF front frame opening flag. For example, when the inner frame open flag during off is on, a pulse signal having a pulse width of about 1 msec is transmitted to the hall computer 262, and when the front frame open flag during off is on, the pulse width is about 2 msec. The pulse signal may be transmitted to the hall computer 262. Accordingly, when the power of the pachinko machine 10 is turned off, the pachinko machine 10 can separately notify whether the inner frame 12 has been opened or the front frame 14 has been opened, and the hall It can be stored separately in the computer 262.

Further, in the processing of S217 of the main processing (see FIG. 12), the voltage (reset signal SG3b) output from the existing frame opening detection circuit 260 to the input/output port 205 is read, and the newly added frame opening detection circuit is added. The voltage (reset signal SG3b) output from 260 to the input/output port 205 may be read. In accordance with the read result, in the processing of S219 or S220, the on-inside inner frame opening flag or the on-inside front frame opening flag is individually turned on.

Then, in the process of S208 of the main process (see FIG. 12), when the on-inside inner frame opening flag is turned on, the MPU 201 transmits an “on-inside inner frame opening command” to the voice lamp control device 113 to turn on. When the middle front frame opening flag is turned on, the MPU 201 transmits an "on middle front frame opening command" to the voice lamp control device 113. Then, when the voice lamp control device 113 receives each command transmitted from the MPU 201, the voice lamp control device 113 differs depending on whether an on-inside inner frame opening command is received or an on-inside front frame opening command. A form is notified. For example, different warning sounds are output from the audio output device 226, and the lighting mode of the lamp display device 227 is changed. Accordingly, when the pachinko machine 10 is powered on, the pachinko machine 10 can separately notify whether the inner frame 12 has been opened or the front frame 14 has been opened.

In the present embodiment, the pulse signal output from the pachinko machine 10 is output to the hall computer 262, which is installed at a location different from that of the pachinko machine 10, but the present invention is not limited to this. A dedicated storage device having the function of the hall computer 262 may be provided for each pachinko machine 10, and the dedicated storage device may be provided on the back side of each pachinko machine 10 in which the main controller 110 and the like are provided. In this case, better, the main controller 110, the payout controller 111, and the launch controller 112 store a dedicated storage device in the board box, and the box base and the box cover provided in the board box. And are connected by a sealing unit (not shown) so that they cannot be opened (connection by a caulking structure). Then, a seal sticker (not shown) is attached to the connecting portion between the box base and the box cover across the box cover and the box base.

Next, a pachinko machine according to the second embodiment will be described with reference to FIGS. 21 to 23. The pachinko machine of the second embodiment is a modification of the pachinko machine 10 startup process, timer interrupt process, and main process of the first embodiment. Specifically, the pachinko machine according to the second embodiment is provided with a power-on counter 203c (not shown) in the RAM 203, which starts clocking when the MPU 201 is started up, and the power-on counter 203c can measure the time period. If there is power-off occurrence information within the predetermined period (5.0 seconds or less in the present embodiment), the inner frame 12 or the front frame is displayed when the pachinko machine is powered off. 14 is opened, and the frame open detection circuit 260 determines that the MPU 201 has been temporarily started up, and the off-in-frame open flag 203a is turned on.

According to the pachinko machine of the second embodiment, whether the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off is determined according to the time period of the power-on counter 203c. To do. Therefore, when the inner frame 12 or the front frame 14 is opened while the pachinko machine is powered off, power is supplied from the frame opening detection circuit 260 to the input/output port 205 to open the frame opening detection circuit 260. It is not necessary for the MPU 201 to detect whether the output from the input to the input/output port 205 is high. Therefore, according to the pachinko machine of the second embodiment, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is off, the power is supplied from the frame open detection circuit 260 to the input/output port 205. Compared to the pachinko machine 10 of the first embodiment (power is supplied from the frame opening detection circuit 260 to the input/output port 205 to output from the frame opening detection circuit 260 to the input/output port 205. It is possible to suppress the power consumption stored in the capacitor CD1 by comparing with the pachinko machine 10 of the first embodiment in which the MPU 201 detects whether or not is high.

The power-on counter 203c (not shown) is powered on for the pachinko machine 10 to execute the start-up process (FIG. 21), and a predetermined period (see FIG. 21) from the process (see FIG. 21) of the start-up process described later. In this embodiment, it is a counter that counts whether or not 5.0 seconds has elapsed. The power-on counter 203c is set to "0 (zero)" in the start-up process, starts counting up, and every time the timer interrupt process (see FIG. 22) is executed (every 2 ms). ) The count is incremented by one. When the count-up exceeds "2500 (5.0 seconds)" and becomes "2501", the count-up ends. Therefore, the power-on counter 203c can measure whether or not 5.0 seconds have elapsed since S119 of the startup processing.

Next, with reference to FIG. 21, a startup process executed by the MPU 201 of the pachinko machine according to the second embodiment will be described. FIG. 21 is a flowchart showing a startup process executed by the MPU 201 of the pachinko machine according to the second embodiment. The same parts as those in the startup process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the pachinko machine startup process of the second embodiment, the processes of S110 to S112 of the pachinko machine startup process of the first embodiment are deleted and the processes of S118 and S119 are added. In the pachinko machine startup process of the second embodiment, after the process of S109 or S117, the power-on counter 203c is set to "0 (zero)" (S118). Then, the power-on counter 203c starts counting up (S119). Then, the process proceeds to S113.

The processes of S118 to S119 are executed immediately after the process of S109 is completed or immediately after the process of S117 is completed. That is, the processing of S118 to S119 is executed immediately after the various settings of the MPU 201 are completed. Therefore, when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off, the opening can be immediately detected by the processes of S118 to S119.

Next, with reference to FIG. 22, a timer interrupt process executed by the MPU 201 of the pachinko machine according to the second embodiment will be described. FIG. 22 is a flowchart showing the timer interrupt processing executed by the MPU 201 of the pachinko machine of the second embodiment. The timer interrupt process of the pachinko machine of the second embodiment is executed by the MPU 201 of the main control device 110, for example, every 2 msec, like the timer interrupt process of the pachinko machine 10 of the first embodiment. The same parts as those in the timer interrupt process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 15 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the pachinko machine timer interrupt process of the second embodiment, the processes of S506 and S507 are added to the pachinko machine 10 timer interrupt process of the first embodiment. In the timer interrupt process of the pachinko machine of the second embodiment, after the process of S503, it is determined whether the count value of the power-on counter 203c is larger than "2500" (S506). Since the timer interrupt process is executed every 2 msec, if the count value of the power-on counter 203c is “2500”, 2500 (count value)×2 msec is 5.0 sec, which is the process of S119. It indicates that 5.0 seconds have elapsed since the power-on counter 203c started counting up.

If the count value of the power-on counter 203c is equal to or less than "2500" (S506: No), 5.0 seconds have elapsed since the count-up of the power-on counter 203c was started (after the processing of S119 was started). Therefore, the count value of the power-on counter 203c is incremented by "1" (S507). On the other hand, if the count value of the power-on counter 203c is larger than "2500", that is, if the count value of the power-on counter 203c is "2501" (S506: Yes), the count-up of the power-on counter 203c is started. Since 5.0 seconds have elapsed (since the processing of S119 is started), the processing of S507 is skipped and the count-up of the power-on counter 203c is stopped.

It should be noted that if it is determined “Yes” in the process of S506 and if the process of S507 is completed, the process proceeds to the process of S504.

Next, with reference to FIG. 23, a main process executed by the MPU 201 of the pachinko machine according to the second embodiment will be described. FIG. 23 is a flowchart showing main processing executed by the MPU 201 of the pachinko machine of the second embodiment. The same parts as those of the main process of the pachinko machine 10 of the first embodiment described above with reference to FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the main process of the pachinko machine of the second embodiment, the processes of S225 and S226 are added to the main process of the pachinko machine 10 of the first embodiment. In the main processing of the pachinko machine of the second embodiment, after the processing of S222, whether or not the count value of the power-on counter 203c is "2500" or less (S225), that is, the power-on counter 203c is incremented by the processing of S119. It is determined whether or not 5.0 seconds have passed since the start. If the count value of the power-on counter 203c is "2500" or less (S225: Yes), the off-inside frame open flag 203a is turned on (S226), and the process proceeds to S223. Note that when the count value of the power-on counter 203c is "2500" or less, the following two patterns are conceivable, and the off-inside frame open flag 203a is turned on regardless of which pattern occurs.

The first pattern is a case where the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily activated by the frame opening detection circuit 260 while the power of the pachinko machine is turned off. In this case, since the falling edge of the power failure signal SG1b is input to the MPU 201 together with the drive voltage Vb and the reset signal SG3b from the frame open detection circuit 260, the NMI interrupt process (see FIG. 17) is executed, and thus the MPU 201 rises. After the raising process (FIG. 21), it is determined in the process of S213 that there is power-off occurrence information (S213: Yes), and the processes of S221 to S225 are executed. Here, when the MPU 201 is temporarily activated by the frame opening detection circuit 260, the power failure signal SG1b output from the frame opening detection circuit 260 is (the MPU 201 is started when the power failure signal SG1b starts to be output. Then, it will fall in about 4.4 seconds. Therefore, if the count value of the power-on counter 203c is set to "2500" (5.0 seconds), the process is performed before the count value of the power-on counter 203c becomes "2500". The process can be shifted to S225. Therefore, when the power of the pachinko machine is turned off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame opening detection circuit 260, the count value of the power-on counter 203c. Is "2500" or less (S225: Yes), it is determined that the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is off, and the off middle frame open flag 203a is turned on. This is done (S226).

The second pattern is that the power of the pachinko machine is turned on, and the power of the pachinko machine is turned off within about 4.4 seconds after the power is turned on. In this case, after the power of the pachinko machine is turned off (before the determination of S213), the power failure signal SG1a output from the power failure monitoring circuit 252 falls and the NMI interrupt processing (see FIG. 17) is executed, In the process of S213, it is determined that there is power-off occurrence information (S213: Yes), and the processes of S221 to S225 are executed. Here, since the count value of the power-on counter 203c is set to "2500" (since it is set to 5.0 seconds), the power of the pachinko machine is turned on, and about 4.4 after the power is turned on. Even when the power of the pachinko machine is turned off within a second, the count value of the power-on counter 203c is determined to be "2500" or less (S225: Yes), and the off-inside frame open flag 203a is turned on (S226).

In this second pattern, since it is necessary to turn on/off the power of the pachinko machine, it cannot be executed by a fraudulent person, and it is limited to the case where it is executed by a store clerk. Therefore, in the case of this second pattern, the clerk can recognize that the OFF inside frame opening flag 203a is turned on by his/her own action, and thus the turned off inside frame opening flag 203a is set to OFF again. can do. Therefore, even in the case of the second pattern, there is no problem even if the off-inside frame open flag 203a is turned on in the process of S226.

In the process of S225, if the count value of the power-on counter 203c is not "2500" or less (S225: No), at least 5.0 seconds have passed since the count-up of the power-on counter 203c was started in the process of S119. Since it does not correspond to any of the above two patterns, the process of S226 is skipped and the process proceeds to S223. Since the frequency with which the above-mentioned two patterns occur is low, 5.0 seconds have elapsed since the count-up of the power-on counter 203c was started in the processing of S119, that is, the count value of the power-on counter 203c is "2500". It is normal to determine that it is not less than or equal to (S225: No).

As described above, according to the pachinko machine of the second embodiment, whether the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off is determined by the power-on counter 203c. In response (determination is made according to whether 5.0 seconds have elapsed since the power-on counter 203c started counting up in S119). Therefore, when the power of the pachinko machine is turned off and the inner frame 12 or the front frame 14 is opened, power is supplied from the frame opening detection circuit 260 to the input/output port 205, and the frame opening detection circuit 260 is input/output port. The MPU 201 does not need to detect whether the output to 205 is high. Therefore, according to the pachinko machine of the second embodiment, when the power of the pachinko machine is turned off and the inner frame 12 or the front frame 14 is opened, power is supplied from the frame opening detection circuit 260 to the input/output port 205. It is not necessary to compare with the pachinko machine 10 of the first embodiment (power is supplied from the frame opening detection circuit 260 to the input/output port 205 so that the output from the frame opening detection circuit 260 to the input/output port 205 is high. (Compared with the pachinko machine 10 of the first embodiment in which the MPU 201 detects whether or not), it is possible to suppress the power consumption stored in the capacitor CD1.

Next, a pachinko machine according to the third embodiment will be described with reference to FIGS. 24 and 25. The pachinko machine of the third embodiment is a modification of the startup process and main process of the pachinko machine 10 of the first embodiment. Specifically, the pachinko machine of the third embodiment outputs a pulse signal having a pulse width of about 1 msec to the hall computer 262 every time the startup process is executed.

According to the pachinko machine of the third embodiment, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 every time the startup process is executed, so that the pachinko machine is powered off. At this time, the fact that the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started up by the frame opening detection circuit 260 can be stored in the hall computer 262 that continues to operate for 24 hours. Thus, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off, a pulse signal of about 1 msec is output to the hall computer 262 to open the hall. Since it is stored in the computer 262, the off-inside frame opening flag 203a that stores that the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off can be eliminated. Therefore, the memory capacity of the RAM 203 can be reduced. Furthermore, the determination regarding the off-inside frame open flag 203a (each process of S110 to S112 in FIG. 11 and S204 to S206 in FIG. 12) can be eliminated, and thus the determination regarding the off-inside frame open flag 203a is performed. The program capacity of can be reduced.

First, the startup process executed by the MPU 201 of the pachinko machine according to the third embodiment will be described with reference to FIG. FIG. 24 is a flowchart showing a startup process executed by the MPU 201 of the pachinko machine according to the third embodiment. The same parts as those in the startup process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the pachinko machine startup process of the third embodiment, the processes of S110 to S112 of the pachinko machine startup process of the first embodiment are deleted and the process of S120 is added. Further, in the pachinko machine startup processing of the third embodiment, the processing content of S116 of the pachinko machine startup processing of the first embodiment is changed to the processing of S121.

In the pachinko machine startup processing of the third embodiment, after the processing of S101, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 (S120). Then, the process proceeds to S102. In the process of S120, since a pulse signal having a pulse width of about 1 msec is output, if it is left as it is, at least about 1 msec is required to complete the process of S120. When shortening the time (about 1 msec) until the process of S120 is completed, the output of the pulse signal to the hall computer 262 is started in the process of S120, and then the process proceeds to S102 and the wait of S102 is performed. It is sufficient to stop the pulse signal being output about 1 msec after the processing of S120 is started within the time. Since the wait process of S102 waits for about 1.0 second, there is no problem even if the process of stopping the pulse signal that started the output in the wait process is executed.

Further, in the pachinko machine startup process of the third embodiment, after the process of S115, the used area of the RAM 203 is cleared to 0 (S121), and then the process proceeds to S117. Since the pachinko machine of the third embodiment does not require the off-inside frame open flag 203a, the process of turning off the off-inside frame open flag 203a performed in the startup process of the pachinko machine 10 of the first embodiment (S116: (Execution within processing) is unnecessary. Therefore, in the processing of S121, only the processing of clearing the used area of the RAM 203 to 0 is executed.

Next, the main processing executed by the MPU 201 of the pachinko machine according to the third embodiment will be described with reference to FIG. FIG. 25 is a flowchart showing main processing executed by the MPU 201 of the pachinko machine according to the third embodiment. The same parts as those of the main process of the pachinko machine 10 of the first embodiment described above with reference to FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the main processing of the pachinko machine of the third embodiment, the processing of S204 to S206 of the main processing of the pachinko machine 10 of the first embodiment is deleted. That is, in the main processing of the pachinko machine of the third embodiment, after the processing of S203, it is determined whether or not the on-frame opening flag 203b is on (S207). If the on-frame open flag 203b is on (S207: Yes), the inner frame 12 or the front frame 14 is open while the power of the pachinko machine is on, so the on-frame open to the voice lamp control device 113. The command is transmitted (S208), and the process proceeds to S210. On the other hand, when the on-frame opening flag 203b is off (S207: No), the inner frame 12 or the front frame 14 is not opened (because the inner frame 12 and the front frame 14 are closed), the voice lamp An on-frame closing command is transmitted to the control device 113 (S209), and the process proceeds to S210.

Here, there is no determination (processing in S204 to S206) for the off-inside frame open flag 203a provided in the pachinko machines of the first and second embodiments for the following reason. That is, in the pachinko machine of the third embodiment, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is off, the pulse width of the pulse to the hall computer 262 is about 1 msec. By outputting the signal, the fact that the inner frame 12 or the front frame 14 has been opened can be stored in the hall computer 262 which continues to operate for 24 hours. As a result, the pachinko machine of the third embodiment does not require the off-in-frame opening flag 203a for storing that the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is off. Become. For this reason, in the pachinko machine according to the third embodiment, there is no determination regarding the off-in-frame opening flag 203a.

As described above, according to the pachinko machine of the third embodiment, since the off-inside frame open flag 203a is unnecessary, the memory capacity of the RAM 203 can be reduced. Further, according to the pachinko machine of the third embodiment, the determination regarding the off-inside frame open flag 203a (the processes of S110 to S112 in FIG. 11 and S204 to S206 in FIG. 12) is not necessary, so the off-inside frame open is performed. It is possible to reduce the program capacity of the process of making the determination regarding the flag 203a.

Further, according to the pachinko machine of the third embodiment, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 every time the startup process is executed, so that the pachinko machine is powered off. The fact that the inner frame 12 or the front frame 14 is released while the frame is open and the MPU 201 is temporarily activated by the frame open detection circuit 260 can be stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pulse signal stored in the hall computer 262 can identify the pachinko machine in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is off. Furthermore, by storing the pulse signal output from the pachinko machine to the hall computer 262 and storing the output time of the output pulse signal, the opening time of the inner frame 12 or the front frame 14 of the specified pachinko machine is stored. The opening time can be detected.

Next, a pachinko machine according to the fourth embodiment will be described with reference to FIGS. 26 and 27. The pachinko machine of the fourth embodiment is a modification of the startup process and main process of the pachinko machine 10 of the first embodiment. Specifically, the pachinko machine of the fourth embodiment determines whether or not the off-inside frame opening flag 203a is on during the startup process, and if the off-inside frame opening flag 203a is on, the audio lamp control device. The off-frame opening command is transmitted to 113, and then a pulse signal having a pulse width of about 1 msec is output to the hall computer 262.

According to the pachinko machine of the fourth embodiment, if the off-inside frame open flag 203a is on, the off-inside frame open command is transmitted to the voice lamp control device 113 in the startup process, and then the hall computer. Since a pulse signal having a pulse width of about 1 msec is output to 262, the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off, and the MPU 201 is temporarily operated by the frame open detection circuit 260. The fact that the pachinko machine is powered on can be immediately recognized when it is turned on next time.

First, with reference to FIG. 26, a startup process executed by the MPU 201 of the pachinko machine according to the fourth embodiment will be described. FIG. 26 is a flowchart showing a startup process executed by the MPU 201 of the pachinko machine according to the fourth embodiment. The same parts as those in the startup process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the pachinko machine startup process of the fourth embodiment, the processes of S204 to S206 that were executed in the main process of the pachinko machine 10 of the first embodiment are the processes of S227 to S229, and are added before the process of S113. doing.

In the pachinko machine startup process of the fourth embodiment, it is determined whether or not the off-inside frame open flag 203a is on after it is determined as "No" in the process of S111 or after the process of S112 (S227). .. If the off-inside frame opening flag 203a is on (S227: Yes), an off-inside frame opening command is transmitted to the voice lamp control device 113 (S228). When the voice lamp control device 113 receives the OFF-time frame open command, it controls the voice output device 226 and the lamp display device 227 to start notification that the inner frame 12 or the front frame 14 has been opened. Then, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 (S229). In addition, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off and the MPU 201 is temporarily started up, power is not supplied to the voice lamp control device 113. Even if the off-frame opening command is transmitted to the voice lamp control device 113, the notification by the voice output device 226 and the lamp display device 227 is not performed. Therefore, even if the fraudulent person opens the inner frame 12 or the front frame 14 while the power of the pachinko machine is turned off, the pachinko machine uses the off-medium frame open flag 203a without being recognized by the fraudster. It is possible to store the opening of the inner frame 12 or the front frame 14 (without the notification by the voice output device 226 and the lamp display device 227, the off-inside frame open flag 203a is used to set the inner frame 12 or the front frame 14). Only open storage can be done).

On the other hand, if the OFF medium frame opening flag 203a is OFF (S227: No), the processes of S228 and S229 are skipped, and the process proceeds to S113.

Next, with reference to FIG. 27, a main process executed by the MPU 201 of the pachinko machine according to the fourth embodiment will be described. FIG. 27 is a flowchart showing main processing executed by the MPU 201 of the pachinko machine of the fourth embodiment. The same parts as those of the main process of the pachinko machine 10 of the first embodiment described above with reference to FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the main processing of the pachinko machine of the fourth embodiment, the processing of S204 to S206 of the main processing of the pachinko machine 10 of the first embodiment is deleted. That is, in the main processing of the pachinko machine of the fourth embodiment, after the processing of S203, it is determined whether or not the on-frame opening flag 203b is on (S207). If the on-frame open flag 203b is on (S207: Yes), the inner frame 12 or the front frame 14 is open while the power of the pachinko machine is on, so the on-frame open to the voice lamp control device 113. The command is transmitted (S208), and the process proceeds to S210. On the other hand, when the on-frame opening flag 203b is off (S207: No), the inner frame 12 or the front frame 14 is not opened (because the inner frame 12 and the front frame 14 are closed), the voice lamp An on-frame closing command is transmitted to the control device 113 (S209), and the process proceeds to S210.

As described above, according to the pachinko machine of the fourth embodiment, if the off-inside frame opening flag 203a is on, the off-inside frame opening command is transmitted to the voice lamp control device 113 within the startup process, and then Since a pulse signal having a pulse width of about 1 msec is output to the hall computer 262, the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off, and the MPU 201 is opened by the frame open detection circuit 260. The fact that the pachinko machine is powered up temporarily can be immediately recognized when the power of the pachinko machine is turned on next time.

Further, the processing of S228 for transmitting the OFF-in-frame opening command to the voice lamp control device 113 and the processing of S229 for outputting a pulse signal having a pulse width of 1 msec to the hall computer 262 are executed within the pachinko machine startup processing. Therefore, the processes of S228 and S229 can be unexecuted in the main process in which the updating of the fluctuation type counters CS1, CS2, CS3, etc. is repeatedly executed. Therefore, it is possible to prevent the off-frame opening command and the pulse signal from being repeatedly output.

It should be noted that the modification of deleting the processing of S204 to S206 in the main processing performed by the pachinko machine of the fourth embodiment and adding the deleted processing of S204 to S206 before S113 in the startup processing is as follows. You may apply to the pachinko machine of 2 embodiment. Specifically, in the pachinko machine of the second embodiment, the processing of S204 to S206 is deleted from the main processing (see FIG. 23) of the pachinko machine of the second embodiment. Then, the deleted processing of S204 to S206 may be added between S119 and S113 of the pachinko machine startup processing (see FIG. 21) of the second embodiment.

The present invention has been described above based on the embodiment, but the present invention is not limited to the above-mentioned embodiment, and various modifications and improvements are easily possible without departing from the spirit of the present invention. Can be inferred.

It goes without saying that the respective pachinko machines described in the first to fourth embodiments can be combined to realize a pachinko machine having the function of each embodiment.

In the first to fourth embodiments, when the off-inside frame open flag 203a is on, an off-inside frame open command is transmitted to the voice lamp control device 113, and a pulse having a pulse width of 1 msec is sent to the hall computer 262. The signal is output, but is not limited to this. When the OFF middle frame release flag 203a is ON, the main control device 110 does not send a command to the voice lamp control device 113, unlike the pachinko machine according to the first to fourth embodiments, and the hall is opened. While the pulse signal is not output to the computer 262 as well, when the off-inside frame open flag 203a is off, the main control device 110 transmits a command to the voice lamp control device 113 and outputs the pulse signal to the hall computer 262. It may be configured to output. When the main controller 110 is configured in this way, the voice lamp controller 113 supplies the power to the pachinko machine when the command from the main controller 110 is not received within a predetermined time after the power to the pachinko machine is turned on. It may be configured to determine that the inner frame 12 or the front frame 14 is opened during the off state. Similarly, when the hall computer 262 does not receive the pulse signal from the main controller 110 within a predetermined time after the power of the pachinko machine is turned on, it is determined that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off. It may be configured to make a determination. With the above configuration, it is possible to realize a pachinko machine that does not transmit a command to the voice lamp control device 113 and does not output a pulse signal to the hall computer 262 when the off-inside frame open flag 203a is on.

In the first to fourth embodiments, the pachinko machine outputs a pulse signal having a pulse width of about 1 msec to the hall computer 262 to cause the hall computer 262 to store the opening of the inner frame 12 or the front frame 14. , But not limited to this. For example, a pachinko machine is provided with an EEPROM (Electronically Erasable and Programmable Read Only Memory) and a backup RAM. Then, the EEPROM or backup RAM and the input/output port 205 are connected via a bus line. With this configuration, the opening of the inner frame 12 or the front frame 14 can be stored in the EEPROM or the backup RAM. Then, when the power of the pachinko machine is turned on, the storage of the EEPROM or the backup RAM is confirmed by the MPU 201. Thereby, the opening of the inner frame 12 or the front frame 14 can be detected by using a pachinko machine without using the hall computer 262. That is, the role of the hall computer 262 can be assigned to the EEPROM or the backup RAM (the role of the "specific device" described in the claims can be assigned to the EEPROM or the backup RAM). The RAM 203 may be used as the backup RAM.

Further, in the first to fourth embodiments, the drive voltage, the reset signal SG3, and the power failure signal SG1 are output from the frame opening detection circuit 260 and the target to be temporarily started is the MPU 201, but the present invention is not limited to this. is not. For example, if a CPU (MPU) different from the MPU 201 and a RAM are provided in the main controller 110 and the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off, The CPU (MPU) and the RAM may be temporarily activated by the frame open detection circuit 260. Specifically, first, the off-inside-frame opening flag 203a is provided in the separately provided RAM. Then, the power supply output terminal, the reset signal output terminal, and the power failure signal output terminal of the frame opening detection circuit 260 are connected to a CPU (MPU) separately provided, and the RAM provided separately at the power supply output terminal of the frame opening detection circuit 260. Connect. Further, a separately provided CPU (MPU) and a separately provided RAM are connected. As a result, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off, the CPU (MPU) and RAM separately provided by the frame open detection circuit 260 temporarily rise. The off-inside frame open flag 203a provided in another RAM is turned on. Therefore, when the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off, the opening can be stored by the RAM provided separately. The frame open detection circuit 260, a CPU (MPU) provided separately, and a RAM provided separately may be integrated into a one-chip integrated circuit. In this case, the signals (driving voltage Vb, power failure signal SG1b, and reset signal SG3b) output from the frame opening detection circuit 260 are directly input to the CPU (MPU), so that the first to third embodiments can be used. The multiplexers MP1 to MP3 used in the pachinko machine are unnecessary. Further, the separately provided CPU (MPU) and the separately provided RAM may be provided inside the main control device 110, for example, inside the power supply device 115 outside the main control device 110.

Further, in the first to fourth embodiments, the voltage output from the OUT terminal of the timer IC1 provided in the frame open detection circuit 260 is the inner frame 12 or the front frame depending on the time constant of the resistor R1 and the capacitor CD2. It was set to zero volts about 14 seconds after 14 was opened, but it is not limited to this. For example, if the resistance value of the resistor R1 is set to 200 kΩ, the capacitance value of the capacitor CD2 is set to 10 μF, and the time constant is set to about 2 seconds, the voltage output from the OUT terminal of the timer IC1 is set to the inner frame 12 or the front surface. About 2 seconds after the frame 14 is opened, the voltage can be set to zero volt. Therefore, the startup process (see FIG. 11) which is a process executed when the MPU 201 is temporarily booted by the frame open detection circuit 260 and the processes of S201 to S213: Yes to S224 of the main process (see FIG. 12). ) Can be executed in a relatively short time (specifically, the above process is performed for about 2 seconds when the inner frame 12 or the front frame 14 is opened and a voltage is output from the OUT terminal of the timer IC 1). In the case where the reset signal SG3 output from the reset signal output terminal of the frame opening detection circuit 260 can be executed within a total of 7 seconds, which is about 5 seconds until the reset signal SG3 is reduced to about 4.3 volts), As described above, by setting the time constant to about 2 seconds, the output period of the voltage output from the OUT terminal of the timer IC 1 after the inner frame 12 or the front frame 14 is opened can be suppressed to about 2 seconds. .. Therefore, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is off, it is possible to suppress the power consumption stored in the capacitor CD1.

Further, in the first to fourth embodiments, when the inner frame 12 or the front frame 14 is opened, the notification is executed using the voice lamp control device 113, but the present invention is not limited to this. .. When the inner frame 12 or the front frame 14 is opened, the notification may be performed using the display control device 114 in addition to the notification using the voice lamp control device 113. In this case, when the audio lamp control device 113 receives the OFF inside frame opening command or the ON inside frame opening command, the audio lamp control device 113 receives the OFF inside frame opening command or the ON inside frame opening command received by the display control device 114. To send. Then, when the display control device 114 receives the off-inside frame opening command or the on-inside frame opening command, it starts displaying "Check" or "The door is open" on the third symbol display device 81. Just configure it. With this configuration, not only the notification of the voice lamp control device 113 but also the notification of the display control device 113 is performed. Therefore, it is possible to notify the unspecified number of people that the inner frame 12 or the front frame 14 has been opened more easily. it can.

Further, in the first to fourth embodiments, the signals (driving voltage Va, power failure signal SG1a and reset signal SG3a) output from the power supply device 115 and the signals (driving voltage Vb, The switching between the power failure signal SG1b and the reset signal SG3b) is performed using the multiplexers MP1 to MP3, but the invention is not limited to this. Switching between the signals (driving voltage Va, power failure signal SG1a and reset signal SG3a) output from the power supply device 115 and the signals (driving voltage Vb, power failure signal SG1b and reset signal SG3b) output from the frame opening detection circuit 260, Instead of the multiplexers MP1 to MP3, three OR circuits which are OR circuits may be used.

Further, in the first to fourth embodiments, in the processing of S218 for determining whether the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned on, and the processing of S218. Depending on the determination, the process of S219 for turning on the on-frame opening flag 203b and the process of S220 for turning off the on-frame opening flag 203b were executed in the remaining time of the main process, but this is not the only case. Not a thing. The processing of S218 to S220 may be executed within the regular processing of the 4 msec cycle of the main processing. Further, the processes of S218 to S220 may be executed within the timer interrupt process executed every 2 ms.

Further, in the first embodiment, the second embodiment, and the fourth embodiment, when the off-inside-frame opening flag 203a is on, the sound output device 226 and the lamp display device 227 are used to notify and the hall is displayed. A pulse signal of 1 msec was output to the computer 262, but the invention is not limited to this. That is, when the off-inside frame open flag 203a is on, a 1 msec pulse signal is not output to the hall computer 262, and only the notification is performed using the audio output device 226 and the lamp display device 227. May be. On the contrary, when the off-inside frame open flag 203a is on, the sound output device 226 and the lamp display device 227 are not used for notification, and only the pulse signal is output to the hall computer 262. It may be configured.

Further, for example, in each of the above-described embodiments, each command is transmitted from the main control device 110 to the voice lamp control device 113, and the display instruction is issued from the voice lamp control device 113 to the display control device 114. However, the command may be directly transmitted from the main controller 110 to the display controller 114. It is also possible to connect an audio lamp control device to the display control device, and to transmit a command for outputting each voice and lighting the lamp from the display control device to the audio lamp control device. Further, the voice lamp control device and the display control device may be configured as one control device.

Further, in the above-described embodiment, the winning of the first entrance 64 and the passage of the second entrance 67 are configured to be held up to four times at maximum, but the maximum number of holdings is four times. The number of times is not limited, and may be set to 3 times or less, or 5 times or more (for example, 8 times). In addition, the number of times the variable display is held based on the winning in the first entrance 64 is also changed by a number or the number of times the four divided areas are held even in a part of the third symbol display device 81. A mode (for example, a color or a lighting pattern) may be displayed, and a light emitting member such as a lamp is provided separately from the first symbol display device 37, and the number of holdings is notified by the light emitting member. You may do it.

Further, as shown in the above-mentioned embodiment, the variable display, which is a kind of dynamic display, is not limited to scrolling the symbol as the identification information in the vertical direction on the display screen of the third symbol display device 81, The symbols may be moved and displayed along a predetermined path such as a lateral direction or an L-shape. Further, the dynamic display of the identification information is not limited to the variable display of the symbols, and for example, one or a plurality of characters may be displayed together with the symbols, or may be displayed in various motions or changed in addition to the symbols. It also includes a display effect that is displayed. In this case, one or more characters are used as the third symbol.

The present invention may be applied to a pachinko machine or the like of a type different from the above embodiment. For example, it may be implemented in a so-called second-class pachinko gaming machine having a winning device having a special area such as a V zone. Further, in addition to a pachinko machine, it may be implemented as another game machine such as an arepachi or a sparrow ball.

The present invention may be applied to a pachinko machine or the like of a type different from the above embodiment. For example, once a big hit occurs, a pachinko machine (commonly called a 2nd right property, a 3rd right property, etc.) that can increase the jackpot expected value until a big hit state occurs multiple times (for example, 2 or 3 times) including that. It is also possible to carry out. Further, it may be implemented as a pachinko machine for generating a special game that gives a predetermined game value to a player on condition that a ball is won in a predetermined area after the jackpot pattern is displayed. Further, it may be implemented in a pachinko machine which is in a special game state, having a winning device having a special area such as a V zone and winning a ball in the special area as a necessary condition. Further, in addition to the pachinko machine, it may be implemented as various game machines such as arepaches, sparrow balls, slot machines, and game machines in which so-called pachinko machines and slot machines are integrated.

In the slot machine, for example, a symbol is changed by operating the operation lever in a state where a coin is inserted and the symbol effective line is determined, and by operating the stop button, the symbol is stopped and confirmed. It is a thing. Therefore, the basic concept of the slot machine is that "a display device for confirming and displaying the identification information after variably displaying the identification information sequence including a plurality of identification information is provided, which is caused by the operation of the starting operation means (for example, the operation lever). The variable display of the identification information is started by the operation of the stop operation means (for example, the stop button) or when a predetermined time elapses, the variable display of the identification information is stopped and confirmed, and then stopped. It becomes a slot machine that generates a special game that gives a predetermined game value to the player, provided that the combination of identification information at the time is specific".In this case, the game medium is typically a coin, medal, etc. As an example.

Further, as a specific example of a gaming machine in which a pachinko machine and a slot machine are fused, a display device for confirming and displaying the symbols after variably displaying a symbol row consisting of a plurality of symbols is provided, and a handle for ball launching is provided. Some are not. In this case, after throwing in a predetermined amount of balls based on a predetermined operation (button operation), the fluctuation of the symbol is started, for example, due to the operation of the operation lever, or due to, for example, the operation of the stop button, or By the passage of time, the fluctuation of the symbol is stopped, and a special game that gives a predetermined game value to the player is generated as a necessary condition that the definite symbol at the time of stop is a so-called jackpot symbol, and the player is caused to do so. Is a large amount of balls dispensed to the lower tray.

In the following, in addition to the gaming machine of the present invention, the concept of various inventions included in the above-described various embodiments will be shown. In a gaming machine including a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing relating to game control, a door opening detection means that detects opening of the door body with respect to the main body, and Storage means for storing detection of the opening of the door body by the door opening detection means; and when the opening of the door body is detected by the door opening detection means, the opening detection is stored based on the calculation processing of the calculation means. When the opening of the door body is detected by the door opening detecting means to be stored in the means during the power-off of the gaming machine, the storing means, the memory executing means, and the calculating means are activated for a predetermined period. And a start-up means for enabling storage of the release detection by the storage execution means, the gaming machine A1.

According to the gaming machine A1, even when the power of the gaming machine is turned off and the computing means is stopped, when the opening of the door is detected by the door opening detection means, the startup means is the storage means, The storage executing means and the calculating means are activated for a predetermined period of time so that the storage executing means can store the door open detection. Therefore, for example, even if the door body is opened by a person's fraudulent activity after the game is closed with all the game machines powered off, the storage execution means stores the door body open detection in the storage means. You can Therefore, the opening of the door can be grasped even when the power of the gaming machine is turned off.

The computing means is generally provided in the space formed by the door body and the main body. Further, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side (including the back surface side of the main body) of the door body that cannot be touched when the door body is closed.

The gaming machine A1 is provided with off-time operating means that is charged while the power of the gaming machine is on and that enables the memory means, the memory executing means, the computing means, and the rising means to operate with the charged electric power. A game machine A2 characterized by.

According to the gaming machine A2, the gaming machine A2 is provided with the off-time operating means to be charged while the power of the game machine is on, and the storage means, the memory executing means, the computing means and the startup means are charged to the off-time operating means. Operates on electricity. Therefore, the storage means, the storage execution means, the calculation means, and the startup means can be operated even after the power of the game machine is turned off.

In the gaming machine A1 or A2, the rising means is one of the storage means, the storage executing means, and the computing means when the opening of the door is detected by the door opening detecting means while the power of the gaming machine is off. An operation period determining unit that determines an operation period as a first operation period, and an operation period of the storage unit, the storage executing unit, and the calculating unit when the first operation period determined by the operation period determining unit ends And a second operation period extended by the extension unit and a first operation period determined by the operation period determination unit, the sum of the second operation period and the first operation period being the predetermined period. The extension means is configured to operate the storage means, the storage execution means, and the calculation means with less power than the power consumed by the operation period determination means.

According to the gaming machine A3, when the first operation period determined by the operation period determining means has ended, that is, when the first operation period has elapsed, the extending means causes the storage means, the storage executing means, and the calculation. The operating period of the means is extended to the second operating period. Here, the sum of the first operating period determined by the operating period determining unit and the second operating period extended by the extending unit is set as a predetermined period during which the rising unit starts up the storage unit, the storage execution unit and the calculation unit. There is. Therefore, of the predetermined period, the period in which the power filled in the off-time operating unit is consumed by the operating period determining unit is limited to the first operating period, and thereafter the extending unit that consumes less power than the operating period determining unit does. The storage means, the storage execution means, and the calculation means can be operated. Therefore, it is possible to suppress the consumption of the electric power charged in the off-time operating means, increase the operable number of times of the storage means, the storage executing means, the arithmetic means, and the rising means, and increase the detectable number of times the door body is opened.

In the gaming machine A3, the operation period determination means, when the door opening detection means detects the opening of the door body in a period shorter than the first operation period, the storage means, the storage execution means and the calculation means. The first operation period, which is the operation period, is set to the short operation period, and the extension means, after the end of the short operation period determined by the operation period determination means, the storage means, the storage execution means, and the calculation means. Is extended to a second operation period, and the second operation period extended by the extension means is set to a period in which the storage of the release detection by the storage execution means can be executed. A game machine A4.

According to the gaming machine A4, when the door opening detection means detects the opening of the door body in a period shorter than the first operation period, the operation period determination means operates the storage means, the storage execution means, and the operation means. Let the period be its short operating period. Then, after the short operation period determined by the operation period determination means ends, the extension means extends the operation period of the storage means, the storage execution means, and the calculation means to the second operation period. The second operation period is set to a period in which the storage executing means can store the door open detection. Therefore, even if the door is opened within a short period, the detection of opening the door can be surely stored in the storage means by the storage execution means. In addition, when the door is opened within a short period, the period during which the electric power charged in the off-time operating unit is consumed by the operating period determining unit can be limited to a short period. Therefore, it is possible to suppress the consumption of the electric power charged in the operating means during OFF, increase the number of operations of the storage means, the storage execution means, the calculation means, and the rising means, and increase the number of times the door can be opened. ..

In the gaming machine A3 or A4, the extension means operates in the off state when the operation period of the storage means, the storage execution means and the arithmetic means is within the first operation period determined by the operation period determination means. While being filled with the electric power supplied by the means, when the first operation period determined by the operation period determining means ends, the charged electric power is used to perform the storage means, the storage executing means, and the calculation. A gaming machine A5, characterized in that it supplies power to the means and extends its operation period to a second operation period.

According to the gaming machine A5, when the operation period of the storage unit, the storage execution unit and the calculation unit is within the first operation period determined by the operation period determination unit, the extension unit is supplied by the off-state operation unit. Filled with electric power. On the other hand, when the first operation period determined by the operation period determination means has ended, the extension means supplies electric power to the storage means, the storage execution means, and the calculation means by using the charged electric power. The power supply of the extension means extends the operation period of the storage means, the storage execution means, and the calculation means to the second operation period. As described above, by reliably executing the filling from the off-time operating means to the extending means, the extending means can reliably extend the operation period of the storage means, the storage executing means, and the calculating means to the second operation period. it can.

In any of the gaming machines A3 to A5, the arithmetic means inputs a drive voltage input means for inputting a drive voltage for enabling the arithmetic means and an operation signal for making the arithmetic processing executable. And an operation signal inputting means, wherein the rising means drives the driving voltage inputting means to the driving voltage inputting means when the opening of the door is detected by the door opening detecting means while the gaming machine is powered off. An operation signal for outputting the operation signal to the operation signal input means when the opening of the door body is detected by the door opening detection means for supplying a voltage while the power of the gaming machine is off. Output means for stopping the operation signal output by the operation signal output means during the second operation period extended by the extension means, and thereafter, the drive voltage supplied by the drive voltage supply means. A gaming machine A6, which stops the game.

According to the gaming machine A6, when the opening of the door is detected by the door opening detection means while the gaming machine is powered off, the operation signal is output from the operation signal output means of the rising means to the operation signal input means of the arithmetic means. At the same time, the drive voltage is supplied from the drive voltage supply means of the rising means to the drive voltage input means of the arithmetic means. Then, the rising means first stops the operation signal output by the operation signal output means during the second operation period extended by the extension means, and thereafter, the drive voltage supplied by the drive voltage supply means. To stop. Therefore, the calculation means is first set to a state in which the calculation processing cannot be executed, and then is stopped. Therefore, even if the opening of the door body is detected by the door opening detection means while the gaming machine is powered off and the calculation means is started by the startup means for a predetermined period, the calculation means is stopped during the second operation period. You can

In the gaming machine A6, the arithmetic means is configured to be able to start up when the drive voltage input to the drive voltage input means is a first value or more, and the operation signal output means is the extension means. When connected and the voltage supplied by the extension means is a second value or more that exceeds the first value, the supplied voltage is output to the operation signal input means as the operation signal, When the voltage supplied by the extension means becomes less than the second value that exceeds the first value, the operation signal output to the operation signal input means is stopped, and the drive voltage supply means, A gaming machine A7, which is connected to the extension means and outputs the supplied voltage as the drive voltage to the drive voltage input means regardless of the voltage supplied by the extension means. ..

According to the gaming machine A7, both the operation signal output means and the drive voltage supply means are connected to the extension means. When the voltage supplied by the extension means is a second value or more that exceeds the first value, the operation signal output means of the rising means uses the supplied voltage as an operation signal and the operation signal output means of the arithmetic means. Output to. On the other hand, the operation signal output means of the rising means stops the operation signal output to the operation signal output means of the arithmetic means when the voltage supplied by the extension means is less than the second value. Unlike the operation of the operation signal output means, the drive voltage supply means outputs the supplied voltage as a drive voltage to the drive voltage input means of the arithmetic means regardless of the voltage supplied by the extension means. That is, even when the voltage supplied by the extension means becomes less than the second value, the drive voltage supply means continues to output the supplied voltage as the drive voltage to the drive voltage input means of the arithmetic means. Here, the arithmetic means is configured to be able to start up (operable) when the drive voltage input to the drive voltage input means is equal to or higher than the first value. Therefore, even if the drive voltage supplied from the drive voltage supply means of the rising means to the drive voltage input means of the arithmetic means is less than the second value and is equal to or higher than the first value, the arithmetic means is kept activated. You can (can continue to operate). As a result, the calculation means is first set to a state in which the calculation processing cannot be executed, and then is stopped. Therefore, even if the opening of the door body is detected by the door opening detection means while the gaming machine is powered off, and the calculation means is started by the rising means for a predetermined period, the calculation means can be lowered during the second period. it can.

In a gaming machine including a main body, a door body that opens and closes the front surface of the main body, and a computing unit that executes a computation process related to game control, a door opening detection unit that detects opening of the door body with respect to the main body, Storage means capable of holding the opening detection of the door body by the door opening detection means even when the power of the gaming machine is turned off, and opening of the door body is detected by the door opening detection means while the power of the gaming machine is turned off. In this case, the storage means and the arithmetic means are provided with a startup means for starting up within a predetermined period, and an off-state operating means for supplying electric power to the startup means. A gaming machine B1 characterized by comprising a storage execution process for holding the opening detection of the door body in the storage means when the arithmetic means is activated by the upper means within a predetermined period.

According to the gaming machine B1, even when the power of the gaming machine is turned off and the computing means is finished, when the opening of the door is detected by the door opening detecting means, the electric power supplied by the off-operation means is used. The start-up means starts up the storage means and the calculation means within a predetermined period. Then, the arithmetic means that has been started up within the predetermined period executes the storage execution processing, and causes the storage means to hold the door body open detection. Therefore, for example, even if the door body is opened by someone's fraudulent activity after the game is closed with all the gaming machines powered off, the door execution detection is stored by the storage execution process executed by the computing means. It can be held by the means. Therefore, the opening of the door can be grasped even when the power of the gaming machine is turned off.

In the gaming machine B1, the arithmetic processing executed by the arithmetic means includes termination processing for terminating the activated arithmetic means, and the termination processing and the storage execution processing are activated by the arithmetic means by the activation means. A gaming machine B2, characterized in that the processing is completed within a predetermined period.

According to the gaming machine B2, even if the opening of the door body is detected by the door opening detecting means while the gaming machine is powered off, and the calculating means is started by the rising means, the calculating means executes the storage execution process and the end. The processing can be completed within a predetermined period. Therefore, even if the door body is opened while the power of the gaming machine is turned off, the opening detection of the door body can be held in the storage means by the storage execution processing, and the arithmetic means started within a predetermined period can be stored. It can be terminated by termination processing.

In the gaming machine B1 or B2, a detection signal receiving means for receiving a detection signal indicating the detection of opening the door body by the door opening detection means is provided, and the rising means opens the door body by the door opening detection means. When detection is made, detection signal output means for outputting a detection signal to the detection signal receiving means is provided, and when opening of the door body is detected by the door opening detection means during power off of the gaming machine. Means to activate the storage means, the computing means, the detection signal output means, and the detection signal receiving means within a predetermined period, and the computing means receives the detection signal by the detection signal receiving means. In this case, the game machine B3 executes the storage execution process.

According to the gaming machine B3, when the opening of the door is detected by the door opening detecting means while the power of the gaming machine is off, the rising means includes the storage means, the calculating means, and the detection signal output means for outputting the detection signal. The detection signal receiving means for receiving the detection signal is activated within a predetermined period. Then, when the detection signal output from the detection signal output unit is received by the detection signal receiving unit, the calculation unit executes the storage execution process to hold the door opening detection in the storage unit. In other words, the calculation means executes the storage execution processing only when the detection signal receiving means receives the detection signal after being started by the rising means within a predetermined period. Therefore, when the door is surely opened while the power of the gaming machine is turned off, the storage execution process by the calculation means can be executed for the first time.

In the gaming machine B1 or B2, the gaming means is provided with timing means for timing the operation period of the computing means, and the rising means detects the opening of the door body by the door opening detection means while the power of the gaming machine is off. In this case, the storage means, the computing means, and the clocking means are started up within a predetermined period, and the computing means has an operation period clocked by the clocking means within a predetermined second period. Nevertheless, when the end process is executed, the memory execution process is executed assuming that the door is opened while the power of the game machine is off. ..

According to the gaming machine B4, when the opening of the door body is detected by the door opening detecting means while the gaming machine is powered off, the rising means measures the storage means, the calculating means, and the operating means. Is started within a predetermined period. When the operation means executes the ending process despite the operation period timed by the timekeeping means being within the predetermined second period, the door body is opened while the power of the gaming machine is off. The storage execution process is executed as. In other words, the calculation means executes the storage execution processing for the first time when it is started by the startup means within the predetermined period and then the end processing is executed within the second period. Therefore, when it is determined that the opening of the door body is surely performed during the power-off of the gaming machine due to the operation period of the timing means, the storage execution processing by the computing means can be executed for the first time.

The gaming machine B3 or B4 is provided with a backup means capable of retaining data even after the power of the gaming machine is turned off, and the arithmetic processing executed by the arithmetic means determines whether or not the data retained in the backup means is valid. Judgment processing, return processing for returning to the state before power-off by using the data held in the backup means when judged to be valid by the judgment processing, and non-valid judged by the judgment processing In this case, an initialization process for initializing the data held in the backup means is provided, and the start of reception of the detection signal by the detection signal receiving means or the start of timing of the operation period by the timing means is the restoration processing or the initial stage. The gaming machine B5, which is performed immediately after the execution of any one of the activation processing.

According to the gaming machine B5, after the door opening detection means detects the opening of the door body during the power-off of the gaming machine, and the start-up means activates the computing means within a predetermined period, after the return processing or in the initial stage. Immediately after the conversion processing, that is, immediately after the various settings of the computing means are completed, the detection signal receiving means starts the reception of the detection signal or the time counting means starts the time counting of the operation period. Therefore, when the door is opened while the power of the gaming machine is off, the opening of the door can be immediately detected.

In the gaming machine B5, an informing means for informing when the door opening detection is held in the storage means by the storage execution processing is provided, and the informing means is provided when the power of the gaming machine is turned on. On the other hand, while the startup is performed, even if the opening of the door body is detected by the door opening detection means during the power-off of the gaming machine, the startup by the startup means is not executed. A gaming machine B6 characterized by being a thing.

According to the gaming machine B6, the notifying means performs the startup when the power of the gaming machine is turned on, and gives the notification when the storage means holds the door body open detection. On the other hand, the notification means does not execute the start-up by the start-up means even if the door-opening detection means detects the opening of the door body while the power of the gaming machine is off (the start-up means also starts up). Never be). In other words, the notification means is started up when the power of the gaming machine is turned on, but during the power off of the gaming machine, the door opening detection means detects the opening of the door body, and the rising means calculates Even if the means is started within the predetermined period, the start-up means does not start it. Therefore, for example, even if the door body is opened by a fraudulent person after the power is turned off for all the gaming machines and the door body open detection is held in the storage means by the storage execution processing, the notification means Will not be notified. Therefore, the fact that the door is opened while the power of the gaming machine is off can be held in the storage means without being noticed by a fraudulent person. Further, if the power of the gaming machine is turned on and the detection of the opening of the door body is held in the storage means, the notification means notifies the player. Therefore, the gaming machine in which the door body is opened while the power is off Can be specified.

In the gaming machine B6, an erasing means for setting the opening detection of the door body held in the storage means to the erasable state by the storage execution processing is provided, and the opening detection of the door body held in the storage means is performed. The release detection is set to an erasable state by the erasing means, and the erasing is executed when the power of the gaming machine is turned on and the arithmetic means is started up. A gaming machine B7.

According to the gaming machine B7, the opening detection of the door body held in the storage means is set to the state in which the opening detection of the door body can be erased by the erasing means, and the power of the gaming machine is turned on and the computing means is operated. When it is started up, it is erased. That is, firstly, when the opening detection of the door is set to the erasable state by the erasing means, and secondly, when the arithmetic means is started by turning on the power of the gaming machine, it is held in the memory means for the first time. The detected opening of the opened door is deleted. Therefore, once the door body open detection is held in the storage means, the door body open detection cannot be erased from the storage means unless the above procedure is performed. Therefore, when the door opening detection is held in the storage unit, it is possible to make it difficult for a fraudulent person to erase the door opening detection.

In any of the gaming machines B1 to B7, an output means for outputting a predetermined signal to a specific device based on the arithmetic processing of the arithmetic means is provided, and the rising means is capable of opening the door body by the door opening detection means. When detected while the power of the gaming machine is off, the output means is started up within a predetermined period, and the arithmetic processing executed by the arithmetic means is a detection of opening of the door body by the storage execution processing. When held in the storage means, an output process for outputting the door opening detection as a predetermined signal to the output means is provided, and the output processing is within a predetermined period in which the calculation means is started by the rising means. A gaming machine B8, characterized in that the processing is completed by.

According to the gaming machine B8, when the opening of the door body is detected by the door opening detecting means while the gaming machine is powered off, the rising means starts up the output means in addition to the storage means and the calculating means within a predetermined period. .. Then, the arithmetic means started up within a predetermined period executes an output process, and causes the output means to output the door open detection as a predetermined signal. Here, this predetermined signal is output to the specific device. Therefore, for example, even if the door body is opened by someone's cheating after closing all the power off gaming machines, it is possible to determine the gaming machine with the door opened by the specific device. ..

It should be noted that one specific device may receive a predetermined signal output from the output means provided for each of a plurality of gaming machines, or a specific device may be provided for each gaming machine, and the specific device may be provided for each gaming machine. You may arrange. When arranging the identifying device in each gaming machine, the box base and the box cover that covers the opening of the box base are connected to each other, and are identified in the space formed by the box cover and the box base. Store the device. Then, the box cover and the box base are connected in an unopenable manner by the sealing unit. Further, a seal sticker is attached to the connecting portion between the box cover and the box base, extending over the box cover and the box base. Then, the specific device may be provided on the back surface or the back surface side of the door body.

In a gaming machine including a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing relating to game control, a door opening detection means that detects opening of the door body with respect to the main body, and A gaming machine C1 characterized by further comprising a computing start-up means for starting the computing means for a predetermined period when the opening of the door body is detected by the door opening detecting means while the power of the gaming machine is off. ..

According to the gaming machine C1, even when the power of the gaming machine is turned off and the computing means is stopped, when the door opening detecting means detects the opening of the door body, the computing starting means causes the computing means to operate. For a predetermined period. Therefore, it is possible to use the arithmetic means that has been started up for a predetermined period of time, for example, to store the door opening detection, or to output the door opening detection to a specific device (specific device). it can.

In a gaming machine including a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing relating to game control, a door opening detection means that detects opening of the door body with respect to the main body, and When the opening of the door is detected by the door opening detecting means while the power of the gaming machine is off, the calculation starting means for starting the calculation means for a predetermined period and the calculation started by the calculation starting means An amusement machine D1 provided with an output means for outputting detection of opening of the door body to a specific device based on arithmetic processing of the means.

According to the gaming machine D1, even if the power of the gaming machine is turned off and the computing means is stopped, when the door opening detecting means detects the opening of the door body, the computing starting means causes the computing means to operate. It is launched for a predetermined period. Then, based on the arithmetic processing of the activated arithmetic means, the output means outputs the door opening detection to the specific device. Therefore, for example, even if the door body is opened by someone's fraudulent activity after closing all the gaming machines with the power turned off, the door body open detection can be output to the specific device. Therefore, the opening of the door can be grasped even when the power of the gaming machine is turned off.

Based on the main body, the door body that opens and closes the front surface of the main body, the main calculation means that executes the calculation processing related to the game control, and the calculation processing related to the control of the electric device based on the signal output from the main calculation means. In a gaming machine provided with a sub-calculation means for performing, a main calculation means, a sub-calculation means and a power supply means for supplying drive power to an electric device, a door opening detection means for detecting opening of the door body with respect to the main body, A holding means capable of holding the opening detection of the door body by the door opening detection means even when drive power from the power supply means is not supplied; and a case where drive power from the power supply means is not supplied. When the door opening detection means detects the opening of the door body, the holding means and the main calculation means are started for a predetermined period of time to hold the door body open detection in the holding means; When the driving power from the power supply means is not supplied and the opening of the door is detected by the door opening detection means, the off-state operating means for supplying the driving power to the rising means and the power supply means Output means for outputting a predetermined signal according to the holding state of the holding means for holding the opening detection of the door body when drive power is supplied to the main calculation means, the sub-calculation means and the electric device. A gaming machine E1 characterized in that.

According to the gaming machine E1, even when the driving power is not supplied from the power supply means to the main calculation means, the sub calculation means and the electric device, when the door opening detection means detects the opening of the door body, the rising means. Causes the holding means and the main calculation means to be started for a predetermined time by the driving power supplied by the off-state operating means, and causes the holding means to hold the detection of opening of the door body. Then, when the driving power is supplied from the power supply means to the main calculation means, the sub calculation means and the electric device, the output means outputs a predetermined signal according to the holding state of the holding means. Therefore, for example, even if the door body is opened by a fraudulent act by somebody after the store is closed when the driving power is not supplied by the power source means in all gaming machines, the opening of the door body is held and the power source means is used. A predetermined signal can be output when drive power is supplied. Therefore, when the driving power from the power supply means is not supplied, that is, when the power of the gaming machine is turned off, it is possible to grasp the opening of the door body.

In the gaming machine E1, the main calculation means is normally executed once when the drive power is supplied from the power supply means and after the start-up processing, and repeatedly executes a plurality of calculation processing. The output control process includes a process and an output control process for causing the output unit to output a second predetermined signal to the sub-calculation unit according to a holding state of a holding unit that holds the opening detection of the door body. The gaming machine E2, which is executed within the start-up process and then shifts to the normal process.

According to the gaming machine E2, drive power is supplied by the power supply means in the output control processing for causing the output means to output the second predetermined signal to the sub-calculation means in accordance with the holding state of the holding means for holding the door opening detection. If it is done, it is executed within the start-up process of the main calculation means that is executed once. In this way, when the driving power is supplied from the power supply means, the output control processing is immediately executed and the second predetermined signal is output to the sub-calculation means, so that it is performed when the power of the gaming machine is off. The opening of the opened door can be immediately grasped by the sub-calculation means. When the second predetermined signal is output to the sub-calculation unit, the sub-calculation unit controls, for example, the electric device to give a notification. Further, since the output control processing is executed within the startup processing of the main processing means, it is possible to make the output control processing non-executed in the normal processing in which a plurality of arithmetic processings are repeatedly executed.

In the gaming machine E1 or E2, the main computing means is provided separately from the main computing means and is electrically connected to a specific device for detecting an operating status of the gaming machine, and the startup means is When the door opening detection means detects the opening of the door body when the drive power from the power supply means is not supplied, a third predetermined signal is sent to the specific device according to the holding state of the holding means. A gaming machine E3, characterized in that the third output means for outputting is started for a predetermined period.

According to the gaming machine E3, when the door opening detection means detects the opening of the door body while the driving power from the power supply means is not supplied, the rising means starts the third output means for a predetermined time. Then, the third output means outputs the third predetermined signal to the specific device in accordance with the holding state of the holding means that holds the detection of opening the door. Therefore, when the drive power from the power supply means is not supplied, that is, when the opening of the door body is detected by the door opening detection means when the power supply of the gaming machine is turned off, at that time, The specific device can grasp the opening of the door body performed while the power of the game machine is turned off.

In the gaming machine E3, the main calculation means causes the third output means to output a third predetermined signal to the specific device according to the holding state of the holding means that holds the opening detection of the door body. A gaming machine E4 comprising a process, wherein the third output control process is executed in the start-up process, and then the process shifts to the normal process.

According to the gaming machine E4, the third output control processing for outputting the third predetermined signal to the specific device by the third output means is driven by the power supply means in accordance with the holding state of the holding means for holding the opening detection of the door body. This is executed within the startup process of the main calculation means that is executed once when electric power is supplied. In this way, when the driving power is supplied from the power supply means, the third output control process is immediately executed and the third predetermined signal is output to the specific device. Therefore, when the power of the gaming machine is off. The opening of the door body performed can be immediately grasped by the specific device. Further, since the third output control processing is executed in the startup processing of the main processing means, it is possible to make the third output control processing non-executable in the normal processing in which a plurality of arithmetic processings are repeatedly executed. ..

It goes without saying that it is naturally possible to realize a gaming machine in which the above gaming machines A1 to A7, gaming machines B1 to B8, gaming machine C1, gaming machine D1, and gaming machines E1 to E4 are appropriately combined. ..

10 Pachinko machines (gaming machines)
11 Outer frame (main body)
12 Inner frame (part of door)
14 Front frame (part of door)
110 Main controller (a part of main calculation means)
113 Voice lamp control device (part of sub-calculation means)
115 power supply device (a part of power supply means)
201 MPU (part of output means, part of third output means)
203 RAM (a part of holding means, backup means)
203a Off inside frame open flag (a part of holding means)
205 I/O port (part of output means)
226 Audio output device (part of electrical device)
227 Lamp display (part of electrical equipment)
260 frame open detection circuit (start-up means)
262 Hall computer (specific device)
CD1 capacitor (operation means during OFF)
S101 to S117, S227 to S229 Startup processing S201 to S203, S207 to S224 Main processing (normal processing)
S228 Startup processing (part of output control processing)
S229 Startup processing (part of third output control processing)
SW1 switch (part of door open detection means)
SW2 switch (part of door open detection means)

The present invention relates to a gaming machine.

In the pachinko machine, when a ball hit in the game area enters the symbol working opening, a lottery is performed at the timing of the entrance. In a spinning machine using a slot machine or a game ball, when the start lever is operated, a lottery is performed at the timing of the operation. A result of the lottery, for example, comes to the person have enough, and is ready payout of prize balls and coins. The control for determining the lottery and those or are performed by the main controller, the main controller is liable to be subject to fraud.

Specific fraud, for example, the main control unit, or replaced by illegal that those have enough occurs frequently, or connect the invalid substrate (e.g., "hanging board") to the main controller, an equivalent or there is illegal to those to be generated. Further, in the case of a pachinko machine, for example, there is also an illegal act or the like in which a nail that is driven on the surface of a game board is illegally bent to make it easy for a ball to enter the winning opening or the symbol operating opening.
In the case of a pachinko machine, for example, the inner frame can be opened and closed with respect to the outer frame . A glass frame is provided on the front surface of the inner frame, and the glass frame can be opened and closed with respect to the inner frame. Therefore, if a cheating person commits a cheating on the game board surface or the main control device, the inner frame or the glass frame must be opened, but if the inner frame or the glass frame is opened, the opening is detected by the sensor grasp, for example, or is notified to the hall computer which manages the game hall, by broadcast knowledge by the fact that the inner frame or glass frame is opened like a lamp lighting and audio output, the fraud can do.

JP 2001-198332 A

However, for example, midnight, etc. after closing of the game arcade, fraudster may enter, if the intruder was fraud by opening the inner frame or glass frame or the like, the power of the pachinko machine is sectional in the time and, since pachinko machine is stopped, it is impossible to detect the opening of such inner frame or glass frame, it has been a problem that it is very difficult to grasp the opening.

The present invention has been made to solve the above-described problems and the like, and makes it possible to grasp the opening of a door when the door is opened while the power of the gaming machine is off. It is intended to provide a game machine capable of playing.

In order to achieve this object, the gaming machine according to claim 1, a main body, a door body that can be opened and closed with respect to the main body , a main arithmetic means for executing arithmetic processing relating to game control, and a main arithmetic means thereof. are those in which a power supply means for supplying driving power, the driving power of the door opening detection means for detecting the opening of the pre Kitobiratai, the opening detection of the door body according to the door opening detection means from said power supply means When the opening of the door body is detected by the door opening detection means when the driving power from the power supply means is not supplied, the holding means and supplies power for a predetermined period of the main operating unit falling up, the open detection of the door body and a rise-up means for retaining said holding means, said main operation unit, the main processing unit and another member Which is electrically connected to a specific device provided in the above, a repeating process of repeatedly executing a plurality of arithmetic processes at a predetermined execution interval, and, when started by the rising means , the holding means of the door body. Output means for outputting a pulse having a length shorter than the execution interval of the repeating processing to the specific device based on the fact that the open detection is held .

According to the gaming machine of the first aspect, there is an effect that it is possible to grasp the opening of the door body performed when the power of the gaming machine is turned off.

It is a front view of a pachinko machine. It is a front view of the game board of the pachinko machine. It is a rear view of a pachinko machine. It is a perspective view of a pachinko machine in a state where an inner frame, a front frame, and a lower plate unit are opened. It is the figure which showed the structure of the switch. It is a block diagram which shows the electric constitution of a pachinko machine. It is a circuit diagram showing an electrical configuration of a frame open detection circuit. Inner frame state, front frame state, timer TRG terminal voltage, timer OUT terminal voltage, capacitor CD4 voltage, frame open detection circuit power supply output terminal voltage, frame open detection circuit reset signal output terminal 7 is a timing chart showing the relationship between the voltage and the voltage of the power failure signal output terminal of the frame open detection circuit. (A) is the figure which showed typically the area division setting and effective line setting of a display screen, (b) is the figure which illustrated the actual display screen. It is a figure which shows the outline of various counters. 7 is a flowchart showing a startup process executed by MPU 201 in main controller 110. It is a flow chart which shows the main processing performed by MPU in a main control unit. It is a flowchart which shows the fluctuation process performed in a main process. It is the flowchart which showed the fluctuation start processing which is executed in fluctuation processing. It is a flowchart which shows a timer interruption process. It is a flow chart which shows a starting winning a prize process performed in a timer interruption process. It is a flow chart which shows NMI interruption processing. It is the flowchart which showed the starting processing performed by MPU in a voice lamp control device. It is the flowchart which showed the main processing performed by MPU of a voice lamp control device. It is the flowchart which showed the door opening notification process performed by MPU of a voice lamp control device. It is the flowchart which showed the starting processing performed by MPU in the main controller of the pachinko machine of 2nd Embodiment. It is a flowchart which shows the timer interruption process performed by MPU in the main control device of the pachinko machine of 2nd Embodiment. It is a flow chart which shows the main processing performed by MPU in the main control device of the pachinko machine of a 2nd embodiment. It is the flowchart which showed the starting processing performed by MPU in the main controller of the pachinko machine of 3rd Embodiment. It is the flowchart which showed the main processing performed by MPU in the main control device of the pachinko machine of 3rd Embodiment. It is the flowchart which showed the starting processing performed by MPU in the main control device of the pachinko machine of 4th Embodiment. It is the flowchart which showed the main processing performed by MPU in the main control device of the pachinko machine of 4th Embodiment.

An embodiment of a pachinko gaming machine (hereinafter, simply referred to as "pachinko machine") will be described below with reference to the drawings. 1 is a front view of the pachinko machine 10, FIG. 2 is a front view of the game board 13 of the pachinko machine 10, and FIG. 3 is a rear view of the pachinko machine 10.

As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 in which an outer shell is formed by a wooden frame combined in a substantially rectangular shape, and an outer shape substantially the same as the outer frame 11 with respect to the outer frame 11. And an inner frame 12 that is openably and closably supported. To support the inner frame 12, metal hinges 18 are attached to the outer frame 11 at two upper and lower positions on the left side in front view (see FIG. 1), and the side on which the hinge 18 is provided serves as an opening/closing shaft. The frame 12 is supported openably and closably on the front side.

On the inner frame 12, a game board 13 (see FIG. 2) having a large number of nails, winning holes 63, 64, etc. is detachably mounted from the back side. A ball game is performed by the ball flowing down on the front surface of the game board 13. In addition, in the inner frame 12, a ball launching unit 112a (see FIG. 5) that launches a ball to the front area of the game board 13 and a launch that guides the ball launched from the ball launching unit 112a to the front area of the game board 13. Rails (not shown) and the like are attached.

On the front side of the inner frame 12, a front frame 14 that covers the upper side of the front and a lower plate unit 15 that covers the lower side thereof are provided. In order to support the front frame 14 and the lower plate unit 15, metal hinges 19 are attached at two upper and lower positions on the left side in a front view (see FIG. 1), and the side provided with the hinges 19 is used as an opening/closing shaft. The lower plate unit 14 and the lower plate unit 15 are supported openably and closably on the front side. The locking of the inner frame 12 and the locking of the front frame 14 are released by inserting a dedicated key into the keyhole 21 of the cylinder lock 20 and performing a predetermined operation.

The front frame 14 is assembled with a decorative resin component, an electrical component, and the like, and a window portion 14c having a substantially elliptical opening is provided at a substantially central portion thereof. A glass unit 16 having two glass plates is arranged on the back side of the front frame 14, and the front side of the game board 13 can be visually recognized on the front side of the pachinko machine 10 via the glass unit 16. An upper plate 17 for storing balls is formed in the front frame 14 in a substantially box-like shape having an open upper surface and protruding toward the front, and prize balls, rental balls, and the like are discharged to the upper plate 17. The bottom surface of the upper plate 17 is formed to be inclined downward to the right when viewed from the front (see FIG. 1), and the ball introduced into the upper plate 17 is guided to the ball firing unit 112a by the inclination. A frame button 22 is provided on the upper surface of the upper plate 17. The frame button 22 is operated by the player, for example, when changing the effect pattern of the variable display displayed on the third symbol display device 81 or when changing the effect contents during the reach effect.

In addition, the front frame 14 is provided with light emitting means such as various lamps around the front frame 14 (for example, a corner portion). These light emitting means change the light emitting mode by lighting or blinking according to the change of the game state at the time of a big hit or a predetermined reach, and play a role of enhancing the effect effect during the game. On the periphery of the window portion 14c, there are provided electric decoration portions 29 to 33 which incorporate a light emitting means such as an LED. In the pachinko machine 10, these illumination parts 29 to 33 function as a production lamp such as a jackpot lamp, and when a jackpot or a reach production is performed, each illumination portion 29 to 33 is turned on by turning on or blinking the built-in LED. Alternatively, it blinks to notify that the jackpot is in the midst of hitting, or that the reach is one step ahead of the jackpot.

Further, in the upper left portion of the front frame 14 when viewed from the front (see FIG. 1), a light emitting means such as an LED is provided, and a display lamp 34 capable of displaying during payout of a prize ball and when an error occurs is provided. In addition, a small window 35 is formed on the lower side of the right decorative portion 32 so that the back side of the front frame 14 can be visually recognized, and a small window 35 is formed. The certificate or the like attached to (see 2) is visible from the front of the pachinko machine 10. Further, in the pachinko machine 10, a plating member 36 made of ABS resin, which is plated with chrome, is attached to a region around the electric decorations 29 to 33 in order to bring out more brilliance.

A ball rental operation unit 40 is arranged below the window 14c. The ball lending operation unit 40 is provided with a frequency display unit 41, a ball lending button 42, and a return button 43. When the ball rental operation unit 40 is operated in a state where banknotes, cards, etc. are inserted into a card unit (ball lending unit) (not shown) arranged on the side of the pachinko machine 10, the ball is operated according to the operation. Lending is done. Specifically, the frequency display unit 41 is an area in which the balance information of a card or the like is displayed, and the built-in LED lights up to display the balance as a number as the balance information. The ball lending button 42 is operated to obtain a loan ball based on information recorded on a card or the like (recording medium), and the loan ball is supplied to the upper plate 17 as long as there is a balance on the card or the like. To be done. The return button 43 is operated when requesting return of a card or the like inserted in the card unit. It should be noted that the ball rental operation unit 40 is not necessary in a pachinko machine, which is a cash machine in which balls are lent directly to the upper plate 17 from a ball lending device or the like without using a card unit, but in this case, the ball rental operation unit 40 is used. It is also possible to add a decorative seal or the like to the installation portion of to make the parts configuration common. A pachinko machine using a card unit and a cash machine can be shared.

In the lower plate unit 15 located below the upper plate 17, a lower plate 50 for storing balls that cannot be stored in the upper plate 17 is formed in a central portion of the lower plate unit 15 in a substantially box shape with an open upper surface. There is. On the right side of the lower plate 50, an operation handle 51 operated by the player to drive the ball into the front surface of the game board 13 is provided, and inside the operation handle 51, the driving of the ball firing unit 112a is permitted. Sensor 51a for pressing, a push button type stop switch 51b for stopping the firing of the ball during the pressing operation, and a variable resistor for detecting the rotation operation amount of the operation handle 51 by the change of the electric resistance. (Not shown) and are built in. When the operation handle 51 is rotated clockwise by the player, the touch sensor is turned on and the resistance value of the variable resistor changes in accordance with the operation amount, and in accordance with the rotation operation amount of the operation handle 51. A ball is fired with a strength corresponding to the variable resistance value of the variable resistor, and thereby the ball is driven into the front surface of the game board 13 with a jump amount corresponding to the operation of the player. Further, when the operation handle 51 is not operated by the player, the touch sensor 51a and the stop switch 51b are off.

At the lower part of the front surface of the lower plate 50, a ball removing lever 52 for operating when the balls stored in the lower plate 50 are discharged downward is provided. This ball-pulling lever 52 is always biased to the right, and by sliding it to the left against the bias, the bottom opening formed on the bottom of the lower plate 50 opens, The sphere falls from the bottom opening and is discharged. The operation of the ball removing lever 52 is usually performed in a state in which a box (generally referred to as “thousand box”) for receiving the balls discharged from the lower plate 50 is placed below the lower plate 50. As described above, the operation handle 51 is arranged on the right side of the lower tray 50, and the ashtray 53 is attached on the left side of the lower tray 50.

As shown in FIG. 2, the game board 13 includes a wooden base plate 60 cut into a substantially square shape in a front view, a large number of nails for guiding balls, windmills and rails 61 and 62, a general winning opening 63, and a first winning opening 63. It is configured by assembling a ball entrance 64, a variable winning device 65, a variable display device unit 80, etc., and a peripheral portion thereof is attached to a back surface side of the inner frame 12. The general winning opening 63, the first winning opening 64, the variable winning device 65, and the variable display device unit 80 are arranged in through holes formed in the base plate 60 by router processing, and wood screws are applied from the front side of the game board 13. It is fixed by etc. Further, the central portion of the front surface of the game board 13 can be viewed from the front surface side of the inner frame 13 through the window portion 14c (see FIG. 1) of the front frame 14. The configuration of the game board 13 will be described below.

On the front surface of the game board 13, an outer rail 62 formed by bending a band-shaped metal plate into a substantially arc shape is planted. At the inner position of the outer rail 62, a band-shaped metal plate is formed like the outer rail 62. The arc-shaped inner rail 61 formed in step 1 is planted. The inner rail 61 and the outer rail 62 surround the outer periphery of the front surface of the game board 13, and the front and rear are surrounded by the game board 13 and the glass unit 16 (see FIG. 1), so that the front surface of the game board 13 has a ball. A game area in which a game is played is formed by the behavior of. The game area is a substantially circular area formed by partitioning the two rails 61 and 62 and the arc member 70 on the front surface of the game board 13 (where a winning opening or the like is provided, and a shot ball is It is the area that flows down.

The two rails 61 and 62 are provided to guide the ball fired from the ball firing unit 112a to the upper part of the game board 13. A return ball prevention member 68 is attached to the tip portion of the inner rail 61 (upper left portion in FIG. 2) to prevent the situation where the ball once guided to the upper part of the game board 13 returns to the ball guide passage again. To be done. At the tip of the outer rail 62 (upper right part in FIG. 2), a return rubber 69 is attached at a position corresponding to the maximum flight portion of the ball, and the ball launched with a momentum higher than a predetermined value hits the return rubber 69 to generate momentum. Is attenuated and bounces back toward the center. In addition, between the lower right end of the inner rail 61 and the upper right end of the outer rail 62, a resin arc member 70 formed by providing an arc connecting the rails on the inner surface side is a base. It is fixed by being driven into the plate 60.

A first symbol display device 37 provided with a plurality of LEDs 37a, which are light emitting means, and a 7-segment display 37b is disposed on the upper right side in the front view of the game area (upper right side in FIG. 2). The first symbol display device 37 is a display according to each control performed by the main control device 110, and mainly displays the gaming state of the pachinko machine 10. The plurality of LEDs 37a indicate whether the pachinko machine 10 is in a probability change, shortening time, or normal by a lighting state, indicate whether it is changing or not by a lighting state, and a stop symbol corresponding to a probability variation jackpot. Or, it is indicated by a lighting state whether it is a symbol corresponding to a normal jackpot or a deviating symbol, and the number of reserved balls is indicated by a lighting state. The 7-segment display device 37b is for displaying the number of rounds in a big hit and an error. The LEDs 37a are configured so that the light emission colors (for example, red, green, and blue) of the respective LEDs are different, and the combination of the light emission colors can suggest various game states of the pachinko machine 10 with a small number of LEDs. ..

In addition, the above-mentioned probability that the pachinko machine 10 is changing is a gaming state in which the jackpot probability increases and a special gaming state is likely to occur. Furthermore, during the probability change in the present embodiment, the probability of hitting the second symbol is increased, and the ball is easy to enter the first entrance 64. In addition, the pachinko machine 10 is in a game state in which it is easy for the ball to enter the first ball entrance 64 because the jackpot probability remains the same and only the second symbol hit probability increases. In addition, the pachinko machine 10 is in a normal state, which is a state of a game that is neither probable change nor time saving (a state in which neither the jackpot probability nor the winning probability of the second symbol is improved). It should be noted that, depending on the gaming state of the pachinko machine 10, the time for which the electric accessory (not shown) attached to the first ball inlet 64 is opened and the number of times the electric accessory is opened per one time are changed. Good as a thing.

Further, in the game area, a plurality of general winning openings 63 are provided in which 5 to 15 balls are paid out as prize balls when the balls are won. Further, a variable display device unit 80 is arranged in the center of the game area. In the variable display device unit 80, a third symbol display device 81 composed of a liquid crystal display (hereinafter simply referred to as “display device”) that variably displays the third symbol triggered by winning in the first ball entrance 64. And, a second symbol display device 82 including a light emitting diode (hereinafter, abbreviated as “LED”) that variably displays the second symbol with the passage of the sphere of the second ball entrance 67 as a trigger is provided. ..

The display content of the third symbol display device 81 is controlled by the display control device 114 described later, and, for example, three symbol columns of left, middle and right are displayed. Each symbol row is composed of a plurality of symbols, and these symbols are vertically scrolled for each symbol row so that the third symbol is variably displayed on the display screen of the third symbol display device 81. In addition, in the present embodiment, the third symbol display device 81 is composed of a large 8-inch liquid crystal display, and the variable display device unit 80 surrounds the outer periphery of the third symbol display device 81, and the center frame. 86 is provided. Third symbol display device 81 of the present embodiment, the display of the game state accompanied by the control of the main controller 110 is performed in the first symbol display device 37, the display of the first symbol display device 37 The decorative display is performed according to. Instead of the display device, for example, a reel or the like may be used to configure the third symbol display device 81.

In addition, when the ball enters the first ball entrance 64 until the stop symbol (one of the probability variation jackpot symbol, the ordinary jackpot symbol, and the deviation symbol) is displayed on the first symbol display device 37 The number of times the ball is entered is held up to a maximum of four times, and the number of times the ball is held is indicated by the first symbol display device 37 and the number of lights of the hold lamp 85. Four reserve lamps 85 are provided for the maximum reserve number, and are arranged symmetrically above the third symbol display device 81. In addition, in the present embodiment, the winning in the first entrance 64 is configured to be held up to 4 times, but the maximum number of holdings is not limited to 4 times, and 3 times or less. Alternatively, the number may be set to 5 times or more (for example, 8 times). In addition, the hold lamp 85 is deleted, and the number of times of variable display based on winning in the first entrance 64 is numerically displayed as a part of the third symbol display device 81, or an area divided into four is reserved. The display may be performed in a mode (for example, a color or a lighting pattern) different for the number of times. Further, since the number of times of holding is indicated by the first symbol display device 37, the holding lamp 85 may not perform the lighting display.

The second symbol display device 82 has a display unit 83 for the second symbol and a holding lamp 84, and each time the ball passes through the second entrance 67, as a display symbol (second symbol) on the display unit 83. The "○" symbol and the "X" symbol are alternately lit to perform a variable display, and when the variable display is stopped by a predetermined symbol ("○" symbol in the present embodiment), The 1 ball entrance 64 is configured to be activated (open) for a predetermined time. The number of times the ball has passed through the second entrance 67 is held up to a maximum of four times, and the number of times of holding is displayed by the first symbol display device 37 and the holding lamp 84 is also lit up. The variable display of the second symbol is performed by switching the lighting and non-lighting of a plurality of lamps on the display unit 83, as in the present embodiment, as well as the first symbol display device 37 and the third symbol display device. You may make it perform using a part of 81. Similarly, the holding lamp 84 may be turned on by a part of the third symbol display device 81. In addition, the maximum number of times of passing through the second entrance 67 is not limited to 4 as in the case of the first entrance 64, and is not more than 3 times or not less than 5 times (for example, (8 times). Further, since the number of times of holding is shown by the first symbol display device 37, the holding lamp 84 may not perform the lighting display.

Below the variable display device unit 80, a first ball entrance 64 into which a ball can enter is arranged. When a ball enters the first entrance 64, a first entrance switch (not shown) provided on the back side of the game board 13 is turned on, which is caused by turning on the first entrance switch. A lottery for the jackpot is made in the main controller 110, and a display corresponding to the lottery result is shown by the LED 37a of the first symbol display device 37. Further, the first ball entrance 64 is also one of the prize holes through which five balls are paid out as prize balls when the balls enter.

A variable winning device 65 is disposed below the first ball entrance 64, and a horizontally elongated rectangular specific winning opening (large opening) 65a is provided at a substantially central portion thereof. In the pachinko machine 10, when the lottery in the main controller 110 is a big hit, the LED 37a of the first symbol display device 37 is turned on so that a big hit stop pattern is lit after a predetermined time (variable time) has passed, and The stop symbol corresponding to the big hit is displayed on the third symbol display device 81, and the occurrence of the big hit is shown. After that, the game state transitions to a special game state (big hit) where the ball is easy to win. In this special game state, the specific winning opening 65a which is normally closed is opened for a predetermined time (for example, until 30 seconds elapse or 10 balls are won).

The specific winning opening 65a is closed after a predetermined time has passed, and after the closing, the specific winning opening 65a is opened again for a predetermined time. The opening/closing operation of the specific winning opening 65a can be repeated, for example, 16 times (16 rounds) at the maximum. The state in which this opening/closing operation is performed is one form of a special game state that is advantageous to the player, and the player is given a larger amount of prize balls than usual in order to give a game value (game value). Is done.

The variable winning device 65 is, specifically, a horizontally-long rectangular opening/closing plate that covers the specific winning opening 65a, and a large opening solenoid (not shown) for opening/closing the front side with the lower side of the opening/closing plate as an axis. It has and. The specific winning opening 65a is normally in a closed state in which the ball cannot be won or is difficult to win. At the time of a big hit, the large opening solenoid is driven to tilt the opening/closing plate to the lower side of the front surface to temporarily form an open state in which the ball easily wins the specific winning opening 65a, and the open state and the normal closing The state and the state operate alternately.

The special game state is not limited to the above-mentioned form. A large opening that is opened and closed separately from the specific winning opening 65a is provided in the game area, and when the LED 37a corresponding to the big hit on the first symbol display device 37 is turned on, the specific winning opening 65a is opened for a predetermined time, and the specific winning is achieved. A special game state is a game state in which a large opening provided separately from the specific winning opening 65a is opened for a predetermined time and a predetermined number of times when the ball wins into the specific winning opening 65a while opening the opening 65a. It may be formed.

Adhesive spaces K1 and K2 for adhering a certificate stamp, an identification label, etc. are provided in the left and right corners on the lower side of the game board 13, and the certificate stamp etc. affixed to the adhesive space K1 is the front frame 14 It can be seen through the small window 35 (see FIG. 1).

Further, the game board 13 is provided with an outlet 66. Balls that have not entered any of the winning openings 63, 64, 65a are guided to a ball discharge path (not shown) through the outlet 66. In the game board 13, a large number of nails are planted in order to appropriately disperse and adjust the falling direction of the balls, and various members (features) such as a wind turbine are arranged.

As shown in FIG. 3, control board units 90 and 91 and a back pack unit 94 are mainly provided on the back side of the pachinko machine 10. The control board unit 90 is a unit in which a main board (main control device 110), a voice lamp control board (voice lamp control device 113), and a display control board (display control device 114) are mounted. The control board unit 91 is unitized by mounting a payout control board (payout control device 111), a firing control board (firing control device 112), a power supply board (power supply device 115), and a card unit connection board 116.

The back pack unit 94 includes a back pack 92 forming a protective cover and a payout unit 93. In addition, each control board is used as an MPU as a one-chip microcomputer that controls each control, a port for communicating with various devices, a random number generator used in various lottery, time counting and synchronization. A clock pulse generating circuit and the like are installed as needed.

The main control device 110, the voice lamp control device 113 and the display control device 114, the payout control device 111 and the firing control device 112, the power supply device 115, and the card unit connection board 116 are housed in the board boxes 100 to 104, respectively. .. The board boxes 100 to 104 each include a box base and a box cover that covers an opening of the box base. The box base and the box cover are connected to each other to house each control device and each board.

Further, in the board box 100 (main controller 110) and the board box 102 (payout controller 111 and launch controller 112), a box base and a box cover are connected in an unopenable manner by a sealing unit (not shown) (caulking structure). (Consolidated by). In addition, a sealing seal (not shown) is attached to the connecting portion between the box base and the box cover, extending over the box base and the box cover. The seal sticker is made of a brittle material, and if the seal sticker is peeled off to open the board boxes 100 and 102, or if the board boxes 100 and 102 are forcibly opened, the box base side and the box cover are closed. To be cut into sides. Therefore, by checking the sealing unit or the sealing sticker, it is possible to know whether the substrate boxes 100 and 102 have been opened.

The payout unit 93 is located at the uppermost part of the back pack unit 94 and opens upward, a tank rail 131 connected below the tank 130 and gently inclined toward the downstream side, and a downstream side of the tank rail 131. A case rail 132 that is vertically connected to the side, and a payout device 133 that is provided at the most downstream portion of the case rail 132 and that pays out balls by a predetermined electrical configuration of the payout motor 216 (see FIG. 5). ing. The tank 130 is sequentially replenished with balls supplied from the island facility of the game hall, and the required number of balls are paid out by the payout device 133 as appropriate. A vibrator 134 for applying vibration to the tank rail 131 is attached to the tank rail 131.

The payout control device 111 is provided with a state return switch 120, the firing control device 112 is provided with a variable resistor operation knob 121, and the power supply device 115 is provided with a RAM erase switch 122. The state return switch 120 is operated to eliminate the ball clogging (return to the normal state) when a dispensing error occurs, such as a ball clogging of the dispensing motor 216 (see FIG. 4). The operation knob 121 is operated to adjust the firing force of the firing solenoid. The RAM erase switch 122 is operated when the power is turned on when it is desired to return the pachinko machine 10 to the initial state.

Next, an internal configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 4 is a perspective view of the pachinko machine 10 in a state where the inner frame 12, the front frame 14, and the lower plate unit 15 are opened.

The pachinko machine 10 is provided with an outer frame 11 forming an outer shell thereof, and an inner frame 12 is supported to the outer frame 11 so as to be openable and closable. In the game arcade, the outer peripheral surface of the outer frame 11 is fixed to an installation place called an island in the game arcade. The inner frame 12, the front frame 14, and the lower plate unit 15 are configured to be openable to the front side with respect to the outer frame 11, so that the inner side 12, the front side frame 14, and the lower dish unit 15 are not exposed from the front side of the pachinko machine 10. Inspection and adjustment are performed with the inner frame 12 and the like open to the front side with respect to the outer frame 11.

To support the inner frame 12, an upper hinge (not shown) and a lower hinge (not shown) made of metal are attached to the outer frame 11 at upper and lower portions on the left side in front view. The inner frame 12 is supported so as to be openable and closable with the side provided with the upper hinge and the lower hinge as an opening and closing shaft.

The inner frame 12 is mainly composed of an inner frame base 55 made of ABS resin and formed in a rectangular shape, and a substantially circular central window 55a is formed at the center of the inner frame base 55. A mounting portion for the game board 13 is provided on the back side of the inner frame base 55, and the game board 13 is detachably mounted.

The lower side of the central window 55a of the inner frame base 55 is formed in a concave shape with the front side open, and a flat mounting surface 52b is formed on the back side thereof. On the mounting surface 52b, a firing unit 140 for firing a ball to the front surface of the game board 13, a passage forming member 54 that forms a passage for discharging the ball to the upper plate 17 and the lower plate 50, and the like are attached.

A switch SW1 for detecting opening and closing of the inner frame 12 is provided between the outer frame 11 and the inner frame 12, and between the inner frame 12 and the front frame 14 the front frame 14 is opened and closed. A switch SW2 for detecting closing is provided.

Here, the structures of the switches SW1 and SW2 will be described with reference to FIG. Since the switches SW1 and SW2 have the same structure, the structure of the switch SW1 will be described, and the description of the switch SW2 will be omitted.

FIG. 5 is a sectional view of the switch SW1. FIG. 5A is a cross-sectional view showing a state (a cutoff state) of the switch SW1 when the inner frame 12 is closed. Further, FIG. 5B is a cross-sectional view showing a state (conduction state) of the switch SW1 in a state where the inner frame 12 is opened.

As shown in FIG. 5A, the switch SW1 disposed on the surface of the outer frame 11 facing the inner frame 12 includes a movable shaft SW1a that abuts the inner frame 12 in the closed state, and the movable shaft SW1a. A conductor plate SW1-1a made of a metal that is a conductive member arranged in SW1a, and a pair of terminal plates SW1-1b made of a metal arranged at a position facing the conductor plate SW1-1a. , The pair of terminal plates SW1-1b are respectively arranged on the support plate SW1-1c arranged on the housing SW1b and on the surface of the conductor plate SW1-1a opposite to the surface facing the pair of terminal plates SW1-1b. A pair of springs SW1c that are provided to generate a biasing force toward the pair of terminal plates SW1-1b with respect to the conductor plate SW1-1a are provided.

As shown in FIG. 5A, when the inner frame 12 is closed, the movable shaft SW1a comes into contact with the inner frame 12 and the movable shaft SW1a is pushed into the housing SW1b. Therefore, the contact between the conductor plate SW1-1a and the pair of terminal plates SW1-1b is prevented. Therefore, in the state where the inner frame 12 is closed, the switch SW1 is in a state in which conduction is cut off.

On the other hand, as shown in FIG. 5B, when the inner frame 12 is opened, the contact between the movable shaft SW1a and the inner frame 12 is released, so that the conductors are urged by the pair of springs SW1c. The board SW1-1a contacts the pair of terminal boards SW1-1b. Therefore, when the inner frame 12 is open, the switch SW1 is in a conductive state.

In this way, the switch SW1 is in the cutoff state when the inner frame 12 is closed, and is in the conductive state when the inner frame 12 is open. The structure of the switch SW1 is not limited to the shape shown in FIG. 5, and when the inner frame 12 is closed, the switch SW1 is in the cutoff state, while when the inner frame 12 is open, It is sufficient that the switch SW1 has a conductive state. The same applies to the structure of the switch SW2.

Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. FIG. 6 is a block diagram showing an electrical configuration of the pachinko machine 10.

The power supply unit 115 is provided with a power supply unit 251 for supplying power to each unit of the pachinko machine 10, a power failure monitoring circuit 252 for monitoring power interruption due to power failure, etc., and a RAM erase switch 122 (see FIG. 3). The erase switch circuit 253 and the reset circuit 254 that outputs the reset signal SG3a that makes the arithmetic processing of the MPU 201 executable are included. The power supply unit 251 is a device that supplies a necessary operating voltage to each of the control devices 110 to 114 and the like through a power supply path (not shown). As an outline thereof, the power supply unit 251 takes in a voltage of 24 V AC supplied from the outside, and 12 V voltage for driving various switches such as various switches 208, solenoids such as the solenoid 209, and motors, A 5 volt voltage for logic, a backup voltage for RAM backup, and the like are generated, and the 12 volt voltage, the 5 volt voltage, and the backup voltage are supplied to the respective control devices 110 to 114 as necessary. The power supply unit 251 also outputs the drive voltage Va of 5 V to the input terminal I13 of the multiplexer MP1.

When a power failure occurs due to a power failure or the like while the pachinko machine 10 is powered on, the power failure monitoring circuit 252, at the time of the power interruption, to the input terminal I11 of the multiplexer MP1 and the NMI terminal of the MPU211 of the payout control device 111, It is a circuit for outputting the power failure signal SG1a which is a positive pulse signal. The power failure monitoring circuit 252 monitors the voltage of DC stable 24V which is the maximum voltage output from the power supply unit 251, and determines that a power failure (power cut, power cut) occurs when this voltage becomes less than 22V. Then, the power failure signal SG1a is output to the multiplexer MP1 and the payout control device 111. The main controller 110 and the payout controller 111 recognize the occurrence of the power failure by the output of the power failure signal SG1a, and execute the NMI interrupt processing. Note that the power supply unit 251 outputs the voltage of 5 V which is the drive voltage of the control system for a time sufficient to execute the NMI interrupt processing even after the voltage of DC stable 24 V becomes less than 22 V. Is maintained at a normal value. Therefore, the main controller 110 and the payout controller 111 can normally execute and complete the NMI interrupt process (see FIG. 17).

The RAM erase switch circuit 253 is a circuit for outputting a RAM erase signal SG2 for clearing the backup data to the main controller 110 when the RAM erase switch 122 is pressed. The main control device 110 and the payout control device 111 clear the respective backup data when the RAM erase signal SG2 is input when the pachinko machine 10 is powered on, and at the same time, the payout control device 111 clears the backup data. The payout initialization command is transmitted to the payout control device 111.

The reset circuit 254 is a circuit that outputs a reset signal SG3a that puts the MPU 201 in a state in which it is possible to execute arithmetic processing. The reset circuit 254 outputs the voltage of 5 volts output from the power supply unit 251 as the reset signal SG3a. When the reset signal SG3a is input to the MPU 201 via the multiplexer MP2, the MPU 201 enters a state in which arithmetic processing can be executed. On the other hand, when the output of the reset signal SG3a is stopped, the MPU 201 is in a state in which the arithmetic processing cannot be executed. Although not shown, the reset signal SG3a output from the reset circuit 254 is also input to the MPU 211 of the payout control device 111, the MPU 221 of the voice lamp control device 113, and the MPU 231 of the display control device 114.

In the pachinko machine 10, the power failure monitoring circuit 252, the RAM erase switch circuit 253, and the reset circuit 254 are provided in the power supply device 115, but the invention is not limited to this, and the power failure monitoring circuit 252, the RAM erase switch circuit 253, or Any of the reset circuits 254 may be provided in the main controller 110. Further, a combination of any two circuits of the power failure monitoring circuit 252, the RAM erase switch circuit 253, and the reset circuit 254 may be provided in the main controller 110. Further, three circuits, that is, the power failure monitoring circuit 252, the RAM erase switch circuit 253, and the reset circuit 254 may be provided in the main controller 110. When the RAM erase switch circuit 253 is provided in the main controller 110, the RAM erase switch 112 is also provided in the main controller 110.

The main controller 110 is equipped with an MPU 201 as a one-chip microcomputer which is an arithmetic unit. The MPU 201 includes a ROM 202 that stores various control programs executed by the MPU 201 and fixed value data, and a memory for temporarily storing various data when the control program stored in the ROM 202 is executed. In addition to a certain RAM 203, various circuits such as an interrupt circuit, a timer circuit, and a data transmission/reception circuit are built in. Note that various commands are transmitted from the main control device 110 to the sub control device by the data transmission/reception circuit in order to instruct the sub control devices such as the payout control device 111 and the voice lamp control device 113 to operate. Such a command is transmitted from the main control device 110 to the sub control device in only one direction.

The MPU 201 has a power supply terminal to which a drive voltage Va or a drive voltage Vb that enables the MPU 201 is input, and either a reset signal SG3a or a reset signal SG3b that enables the arithmetic processing of the MPU 201. Is provided, and an NMI terminal (non-maskable interrupt terminal) to which either the power failure signal SG1a or the power failure signal SG1b is input is provided.

The lower limit value of the voltage at which the MPU 201 can operate is about 4.0 volts. Therefore, when the drive voltage Va or the drive voltage Vb supplied to the power supply terminal of the MPU 201 exceeds about 4.0 V, the MPU 201 is in a startable state (operable state) while the MPU 201 power supply terminal is in a ready state. When the drive voltage Va or the drive voltage Vb supplied to the device is about 4.0 V or less, the MPU 201 becomes inoperable. In addition, the lower limit value of the voltage at which the MPU 201 is in a state in which it is possible to perform calculation is approximately 4.3 volts. Therefore, if the voltage (reset signal SG3a or reset signal SG3b) supplied to the reset terminal of the MPU 201 exceeds approximately 4.3 volts, the MPU 201 is in a state in which it can execute the arithmetic processing, while the MPU 201 receives the reset terminal. When the supplied voltage (reset signal SG3a or reset signal SG3b) is about 4.3 V or less, the MPU 201 is in a state in which the arithmetic processing cannot be executed. Further, the NMI terminal of the MPU 201 is configured to receive the power failure signal SG1a output from the power failure monitoring circuit 252 or the power failure signal SG1b output from the frame opening detection circuit 260, and the power failure signal SG1a or the power failure signal SG1a. When any of the SG1b is input to the MPU 201, the NMI interrupt processing (see FIG. 17) as the power failure processing is immediately executed.

An input/output port 205 is connected to the MPU 201 of the main controller 110 via a bus line 204 composed of an address bus and a data bus. In the input/output port 205, the payout control device 111, the voice lamp control device 113, the first symbol display device 37, the second symbol display device 82, various switches 208 including a switch group and a sensor group not shown, and a specific prize. A solenoid 209 including a large opening solenoid for driving to open and close forward with the lower side of the opening/closing plate of the opening 65a as an axis and a solenoid for driving an electric accessory is connected.

Further, the input/output port 205 is connected to a hall computer 262 which operates continuously for 24 hours. When the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on while the pachinko machine 10 is powered off, the frame opening detection circuit 260 described later temporarily starts up the MPU 201. The MPU 201 that has risen temporarily outputs a pulse signal having a pulse width of about 1 ms to the hall computer 262 via the input/output port 205. The pulse signal output via the input/output port 205 is stored in the hall computer 262. Therefore, by analyzing the pulse signal stored in the hall computer 262, it is possible to detect the opening of the inner frame 12 or the front frame 14 performed while the power of the pachinko machine 10 is turned off. Furthermore, the pachinko machine 10 with the inner frame 12 or the front frame 14 opened can be specified.

Main controller 110 is provided with a frame opening detection circuit 260 that detects opening of inner frame 12 when switch SW1 conducts and detects opening of front frame 14 when switch SW2 conducts. The frame opening detection circuit 260 is connected to a switch SW1 that detects the opening of the inner frame 12 and a switch SW2 that detects the opening of the front frame 14. Note that the switches SW1 and SW2 are connected to the frame opening detection circuit 260 via an input/output unit (not shown in the drawing, which is different from the input/output port 205 (latch circuit or the like)) that inputs and outputs signals. Is being done. Although details will be described with reference to FIG. 7, since the frame open detection circuit 260 is provided with the capacitor CD1 for supplying power, the inner frame 12 or the front surface is provided when the pachinko machine 10 is powered off. Even if the frame 14 is opened, the frame opening detection circuit 260 can detect the opening and temporarily start up the MPU 201. Further, when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered on, the frame open detection circuit 260 naturally operates. Here, when the power of the pachinko machine 10 is on, the MPU 201 has already started up, and it is not necessary to start up the MPU 201 by the frame opening detection circuit 260, so the inner frame 12 or the front frame 14 is opened at this time. In this case, the frame opening detection circuit 260 outputs only the reset signal SG3b to the input/output port 205 by the operation of the multiplexers MP1 to MP3, instead of raising the MPU 201.

Further, the frame open detection circuit 260 receives an input from the multiplexer MP1 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on when the pachinko machine 10 is powered off. The terminal I21 is provided with an interruption signal output terminal that outputs the power failure signal SG1b for about 4.4 seconds after the switch SW1 or the switch SW2 is turned on. The power failure signal output terminal of the frame open detection circuit 260 is connected to the input terminal I21 of the multiplexer MP1 whose output terminal O1 is connected to the NMI terminal of the MPU 201. The input terminal I11 of the multiplexer MP1 is connected to the power failure monitoring circuit 252, and the control terminal S1 of the multiplexer MP1 is connected to the power supply unit 251. Therefore, when the pachinko machine 10 is powered on, a voltage of 5 V for logic is input from the power supply unit 251 to the control terminal S1 of the multiplexer MP1. On the other hand, when the pachinko machine 10 is powered off, the power supply unit 251 does not operate, so no voltage is input to the control terminal S1 of the multiplexer MP1 (the voltage of the control terminal S1 of the multiplexer MP1 is zero volts). Become).

Here, regarding the relationship between the power failure signal SG1a output from the power failure monitoring circuit 252 and the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260, a case where the power of the pachinko machine 10 is turned on. The case where the power of the pachinko machine 10 is turned off will be separately described.

When the pachinko machine 10 is powered on, a voltage of 5 volts is input from the power supply unit 251 to the control terminal S1 of the multiplexer MP1. When a voltage of 5 volts is input to the control terminal S1, the multiplexer MP1 conducts conduction between the input terminal I11 of the multiplexer MP1 and the output terminal O1 of the multiplexer MP1 (the input terminal I21 of the multiplexer MP1 and the output terminal of the multiplexer MP1). When the power of the pachinko machine 10 is turned on, the power failure signal SG1a output from the power failure monitoring circuit 252 can be input to the NMI terminal of the MPU 201 (since it is not electrically connected to O1) (frame open detection). Even if the power failure signal SG1b is output from the power failure signal output terminal of the circuit 260, it is not input to the NMI terminal of the MPU 201). On the other hand, when the power of the pachinko machine 10 is off, a voltage of zero volt is input from the power supply unit 251 to the control terminal S1 of the multiplexer MP1. When a voltage of zero volt is input to the control terminal S1, the multiplexer MP1 conducts the input terminal I21 of the multiplexer MP1 and the output terminal O1 of the multiplexer MP1 (the input terminal I11 of the multiplexer MP1 and the output terminal O1 of the multiplexer MP1). When the power of the pachinko machine 10 is off, the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 can be input to the NMI terminal of the MPU 201. Becomes As described above, the multiplexer MP1 outputs the signal output to the NMI terminal of the MPU 201 to the power failure signal SG1a or the power failure according to the voltage input from the power supply unit 251 to the control terminal S1, that is, according to the on/off state of the power supply of the pachinko machine 10. Switch to any of the signals SG1b.

Further, the frame open detection circuit 260 receives an input from the multiplexer MP2 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on when the pachinko machine 10 is powered off. A reset signal output terminal for outputting the reset signal SG3b is provided to the terminal I22 and the input/output port 205 for about 9.4 seconds after the switch SW1 or the switch SW2 is turned on. The reset signal output terminal of the frame open detection circuit 260 is connected to the input terminal I22 of the multiplexer MP2 whose output terminal O2 is connected to the reset terminal of the MPU 201 and the input/output port 205. The input terminal I12 of the multiplexer MP2 is connected to the reset circuit 254, and the control terminal S2 of the multiplexer MP2 is connected to the power supply unit 251. Therefore, when the power of the pachinko machine 10 is on, a voltage of 5 V for logic is input from the power supply unit 251 to the control terminal S2 of the multiplexer MP2. On the other hand, when the power of the pachinko machine 10 is off, the power supply unit 251 does not operate, so no voltage is input to the control terminal S2 of the multiplexer MP2 (the voltage of the control terminal S2 of the multiplexer MP2 is zero volts). Become).

Here, regarding the relationship between the reset signal SG3a output from the reset circuit 254 and the reset signal SG3b output from the reset signal output terminal of the frame opening detection circuit 260, the case where the power of the pachinko machine 10 is turned on and the case of the pachinko machine are The case where the power of 10 is turned off will be described separately.

When the pachinko machine 10 is powered on, a voltage of 5 volts is input from the power supply unit 251 to the control terminal S2 of the multiplexer MP2. When a voltage of 5 volts is input to the control terminal S2, the multiplexer MP2 conducts the input terminal I12 of the multiplexer MP2 and the output terminal O2 of the multiplexer MP2 (the input terminal I22 of the multiplexer MP2 and the output terminal of the multiplexer MP2). When the pachinko machine 10 is powered on, the reset signal SG3a output from the reset circuit 254 can be input to the reset terminal of the MPU 201 (since it is not electrically connected to O2) (frame opening detection circuit). Even if the reset signal SG3b is output from the reset signal output terminal of 260, it is not input to the reset terminal of MPU 201). On the other hand, when the power of the pachinko machine 10 is off, a voltage of zero volt is input from the power supply unit 251 to the control terminal S2 of the multiplexer MP2. When a voltage of zero volts is input to the control terminal S2, the multiplexer MP2 conducts the input terminal I22 of the multiplexer MP2 and the output terminal O2 of the multiplexer MP1 (the input terminal I12 of the multiplexer MP2 and the output terminal O2 of the multiplexer MP1). Therefore, when the power of the pachinko machine 10 is off, the reset signal SG3b output from the reset signal output terminal of the frame opening detection circuit 260 can be input to the reset terminal of the MPU 201. Become. In this way, the multiplexer MP2 outputs the signal output to the reset terminal of the MPU 201 to the reset signal SG3a or the reset signal according to the voltage input from the power supply unit 251 to the control terminal S, that is, according to the on/off state of the power supply of the pachinko machine 10. Switch to any of the signals SG3b.

The reset signal output terminal of the frame opening detection circuit 260 is also connected to the input/output port 205 as described above. Therefore, when the inner frame 12 or the front frame 14 is opened, the reset signal SG3b is sent from the reset signal output terminal of the frame open detection circuit 260 to the input/output port 205 regardless of whether the power of the pachinko machine 10 is turned on. Is output. The MPU 201 can detect the opening of the inner frame 12 or the front frame 14 by the reset signal SG3b output to the input/output port 205.

The frame open detection circuit 260 includes an input terminal I13 of the multiplexer MP3 when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on when the pachinko machine 10 is powered off. Is provided with a power supply output terminal for supplying a drive voltage Vb having a maximum value of about 5 volts for about 9.9 seconds after the switch SW1 or the switch SW2 is turned on. The power output terminal of the frame open detection circuit 260 is connected to the input terminal I23 of the multiplexer MP3 whose output terminal O3 is connected to the power terminal of the MPU 201. The input terminal I13 of the multiplexer MP3 is connected to the power supply unit 251, and the control terminal S3 of the multiplexer MP3 is also connected to the power supply unit 251. Therefore, when the pachinko machine 10 is powered on, a voltage of 5 V for logic is input from the power supply unit 251 to the control terminal S3 of the multiplexer MP3. On the other hand, when the power of the pachinko machine 10 is off, the power supply unit 251 does not operate, so no voltage is input to the control terminal S3 of the multiplexer MP3 (the voltage of the control terminal S3 of the multiplexer MP3 is zero volts). Become).

Here, regarding the relationship between the drive voltage Va output from the power supply unit 251 and the drive voltage Vb output from the power supply output terminal of the frame open detection circuit 260, which has a maximum value of about 5 volts, the power of the pachinko machine 10 is turned on. The case where the pachinko machine 10 is turned off and the case where the pachinko machine 10 is turned off will be described separately.

When the pachinko machine 10 is powered on, a voltage of 5 volts is input from the power supply unit 251 to the control terminal S3 of the multiplexer MP3. When a voltage of 5 volts is input to the control terminal S3, the multiplexer MP3 conducts the input terminal I13 of the multiplexer MP3 and the output terminal O3 of the multiplexer MP3 (the input terminal I23 of the multiplexer MP3 and the output terminal of the multiplexer MP3 are connected. When the pachinko machine 10 is powered on, the drive voltage Va output from the power supply unit 251 can be input to the power supply terminal of the MPU 201 (since it is not electrically connected to O3) (frame open detection circuit). Even if the drive voltage Vb is output from the power supply output terminal of 260, it is not input to the power supply terminal of MPU 201). On the other hand, when the power of the pachinko machine 10 is off, a voltage of zero volt is input from the power supply unit 251 to the control terminal S3 of the multiplexer MP3. When a voltage of zero volt is input to the control terminal S3, the multiplexer MP3 conducts the input terminal I23 of the multiplexer MP3 and the output terminal O3 of the multiplexer MP3 (the input terminal I13 of the multiplexer MP3 and the output terminal O3 of the multiplexer MP3). Therefore, when the power of the pachinko machine 10 is off, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 can be input to the power terminal of the MPU 201. .. In this way, the multiplexer MP3 outputs the voltage output from the power supply unit 251 to the power supply terminal of the MPU 201 according to the voltage input from the power supply unit 251 to the control terminal S, that is, according to the on/off state of the power supply of the pachinko machine 10. Either the output drive voltage Va or the drive voltage Vb output from the power supply output terminal of the frame open detection circuit 260 is switched.

Although not shown, the output terminal O3 of the multiplexer MP3 is also connected to the input/output port 205. Therefore, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is conducted while the power of the pachinko machine 10 is turned off, the power is output from the power output terminal of the frame open detection circuit 260. The drive voltage Vb that supplies the input/output port 205 is also supplied.

As described above, when the power of the pachinko machine 10 is turned on, various signals (power failure signal SG1a and reset signal SG3a) are output from each circuit (power supply unit 251, power failure monitoring circuit 252 and reset circuit 254) of the power supply device 115. And the drive voltage Va are output to each terminal (NMI terminal, reset terminal, and power supply terminal) of the MPU 201 via the multiplexers MP1 to MP3. Then, when the power of the pachinko machine 10 is turned on, the inner frame 12 or the front frame 14 is opened, and when the switch SW1 or the switch SW2 becomes conductive, only the reset signal SG3b is input from the frame opening detection circuit 260. It is output to the output port 205. On the other hand, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the switch SW1 or the switch SW2 is turned on, various signals (blackout signal SG1b) are output from the frame open detection circuit 260. The reset signal SG3b) and the drive voltage Vb are output to each terminal (NMI terminal, reset terminal, and power supply terminal) of the MPU 201 via the multiplexers MP1 to MP3 for a certain period. Therefore, even when the power of the pachinko machine 10 is turned off, the frame open detection circuit 260 causes the MPU 201 to temporarily (when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 becomes conductive (the present embodiment). Then, it can be started up for about 9.9 seconds.

As described above, the output terminal O3 of the multiplexer MP3 is also connected to the input/output port 205, though not shown. Therefore, when the power of the pachinko machine 10 is turned off and the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the power output terminal of the frame open detection circuit 260 to the input/output port 205. Also outputs the drive voltage Vb. Therefore, even when the power of the pachinko machine 10 is turned off, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 becomes conductive, the frame open detection circuit 260 also causes the input/output port 205 to be opened. It can be started up temporarily (about 9.9 seconds in this embodiment).

The RAM 203 is a stack area in which the contents of internal registers of the MPU 201 and the return address of the control program executed by the MPU 201 are stored, and a work area in which various flags, counters, I/O, and other values are stored. Area) and. Further, the RAM 203 has an OFF inside frame opening flag 203a and an ON inside frame opening flag 203b. Note that the RAM 203 is configured to be able to retain (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is cut off, and all the data stored in the RAM 203 is backed up. ..

When the power is cut off due to the occurrence of a power failure or the like, the RAM 203 stores the stack pointer when the power is cut off (including the occurrence of a power failure; the same applies hereinafter) and the value of each register. On the other hand, at the time of power-on (including power-on by elimination of power failure. The same applies hereinafter), the state of the pachinko machine 10 is restored to the state before the power-off, based on the information stored in the RAM 203. Writing to the RAM 203 is executed when the power is shut off by the main processing (see FIG. 12), and restoration of each value written to the RAM 203 is executed in the startup processing when the power is turned on (see FIG. 11).

When the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and the frame opening detection circuit 260 causes the frame opening detection circuit 260 to turn off the MPU 201. It is a flag that is turned on when it is temporarily started up (the process of S112 of the startup process of the main control device 110 described later). By turning on the off-frame open flag 203a, the MPU 201 can detect that the inner frame 12 or the front frame 14 has been opened while the pachinko machine 10 is powered off. When the pachinko machine 10 is turned on while the off-inside frame open detection flag 203a is turned on, the MPU 201 uses the audio output device 226 and the lamp display device 227 to make a notification. As a result, the pachinko machine 10 can notify an unspecified number of persons (a clerk, a player, etc.) that the inner frame 12 or the front frame 14 was opened while the power of the pachinko machine 10 was turned off. On the other hand, the off-in-frame opening flag 203a is turned off when the RAM erase switch 122 is operated and the used RAM area is cleared in the processing of S116 of the startup processing of the main controller 110 (see FIG. 11). .. Therefore, once the off-inside frame open flag 203a is turned on, the off-inside frame open flag 203a cannot be turned off unless the RAM erase switch 122 is operated to clear the used RAM area in the processing of S116. Therefore, when the power of the pachinko machine 10 is turned on, the pachinko machine 10 certainly does not confirm that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. It is possible to notify a specified number of people.

The on-frame opening flag 203b is a reset signal for the frame opening detection circuit 260 when the pachinko machine 10 is powered on, the inner frame 12 or the front frame 14 is opened, and the switch SW1 or the switch SW2 is turned on. This is a flag that is turned on when the reset signal SG3b is output from the output terminal to the input/output port 205 (the process of S219 of the main process). This on-frame opening flag 203b is turned off in the process of S220 of the main process when the opened inner frame 12 or the opened front frame 14 is closed. By turning on the on-frame opening flag 203b, the MPU 201 can detect that the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered on. When the pachinko machine 10 is powered on and the on-frame opening detection flag 203b is turned on, the MPU 201 uses the audio output device 226 and the lamp display device 227 to make a notification. As a result, the pachinko machine 10 can notify an unspecified number of persons that the inner frame 12 or the front frame 14 has been opened while the pachinko machine 10 is powered on.

The payout control device 111 drives the payout motor 216 to perform payout control of prize balls and rental balls. The MPU 211, which is an arithmetic unit, has a ROM 212 that stores a control program executed by the MPU 211, fixed value data, and the like, and a RAM 213 that is used as a work memory and the like.

The RAM 213 of the payout control device 111, like the RAM 203 of the main control device 110, has a stack area in which the contents of the internal registers of the MPU 211 and the return address of the control program executed by the MPU 211 are stored, and various flags and counters. , I/O, and the like are stored in a work area (work area). The RAM 213 is configured to be able to retain (backup) data by being supplied with a backup voltage from the power supply device 115 even after the power of the pachinko machine 10 is cut off, and all the data stored in the RAM 213 is backed up. The NMI terminal of the MPU 211 is configured to receive the power failure signal SG1a from the power failure monitoring circuit 252 when the power is shut off due to the occurrence of a power failure or the like. When the power failure signal SG1a is input to the MPU 211, the power failure occurs. The NMI interrupt process (see FIG. 17) as a process is immediately executed.

An input/output port 215 is connected to the MPU 211 of the payout control device 111 via a bus line 214 composed of an address bus and a data bus. The main controller 110, the payout motor 216, the firing controller 112, etc. are connected to the input/output port 215, respectively. Further, although not shown, the payout control device 111 is connected to a prize ball detection switch for detecting the paid prize balls. The prize ball detection switch is connected to the payout control device 111, but is not connected to the main control device 110.

The firing control device 112 controls the ball firing unit 112a so that when the main control device 110 gives an instruction to fire a sphere, the sphere launching unit 112a has a launching strength corresponding to the rotational operation amount of the operation handle 51. The ball firing unit 112a includes a firing solenoid and an electromagnet, which are not shown, and the firing solenoid and the electromagnet are permitted to be driven when a predetermined condition is satisfied. Specifically, the touch sensor 51a detects that the player is touching the operation handle 51, and the stop switch 51b for stopping the firing of the ball is turned off (not operated) on condition that the operation handle is not operated. The firing solenoid is excited according to the amount of rotation of 51, and the ball is fired with a strength corresponding to the amount of operation of the operation handle 51.

The voice lamp control device 113 outputs the voice output from the voice output device (such as a speaker not shown) 226, the light output from the lamp display device (such as the illumination parts 29 to 33 and the display lamp 34), and the display control device 114. It is for controlling setting of the display mode of the third symbol display device 81 that is performed. The MPU 221 as an arithmetic unit has a ROM 222 that stores a control program executed by the MPU 221 and fixed value data, and a RAM 223 used as a work memory.

An input/output port 225 is connected to the MPU 221 of the audio lamp control device 113 via a bus line 224 composed of an address bus and a data bus. The main control device 110, the display control device 114, the audio output device 226, the lamp display device 227, etc. are connected to the input/output port 225, respectively.

The display control device 114 controls the variable display of the third symbol on the third symbol display device (LCD) 81. The display control device 114 includes an MPU 231, a ROM (program ROM) 232, a work RAM 233, a video RAM 234, a character ROM 235, an image controller 236, an input port 237, an output port 238, bus lines 239 and 240. have. The input side of the input port 237 is connected to the output side of the audio lamp controller 113, and the output side of the input port 237 is connected to the MPU 231, the ROM 232, the work RAM 233, and the image controller 236. A video RAM 234 and a character ROM 235 are connected to the image controller 236, and an output port 238 is connected via a bus line 240. The third symbol display device 81 is connected to the output side of the output port 238. It should be noted that the pachinko machine 10 is a model having a completely same design as the symbol configuration displayed on the third symbol display device 81, even if it is a different model having a different winning probability for the jackpot or the number of prize balls paid out in one jackpot. Therefore, the display control device 114 is made into a common component to reduce the cost.

The MPU 231 of the display control device 114 controls the display content of the third symbol display device 81 based on the symbol display command input from the voice lamp control device 113. The ROM 232 is a memory for storing various control programs executed by the MPU 231 and fixed value data. The work RAM 233 is a memory for temporarily storing work data and flags used when the MPU 231 executes various programs. The character ROM 235 is a memory that stores data for effects such as symbols (background symbols and third symbols) displayed on the third symbol display device 81. The video RAM 234 is a memory for storing effect data displayed on the third symbol display device 81, and by rewriting the contents of the video RAM 234, the display content of the third symbol display device 81 is changed.

The image controller 236 adjusts the timing of each of the MPU 231, the video RAM 234, and the output port 238 to intervene in reading and writing of data, and reads the display data stored in the video RAM 234 at a predetermined timing to read the third symbol display device 81. To be displayed on.

Next, the frame open detection circuit 260 will be described with reference to FIG. FIG. 7 is a circuit diagram showing an electrical configuration of the frame open detection circuit 260. A frame opening detection circuit 260 for detecting opening of the inner frame 12 or opening of the front frame 14 includes a DC power supply DC1 that supplies a DC voltage of 12 V, diodes D1 to D5, capacitors CD1 to CD4, and resistors R1 to R5. And a timer IC1 (LMC555 manufactured by National Semiconductor) which is a C-MOS timer, a transistor TR1, FET1 to FET3, a reset IC2 (BD4843 manufactured by ROHM Co., Ltd.), and a NOTIC3 which is a logic negation circuit. doing.

In order to detect the opening of the inner frame 12 by the conduction of the switch SW1 and the opening of the front frame 14 by the conduction of the switch SW2, the frame opening detection circuit 260 has the above-mentioned components shown in FIG. Connected according to the circuit diagram. Since the switch SW1 and the switch SW2 are connected in parallel and then connected to the frame opening detection circuit 260, if either one of the switches is turned on, the frame opening detection circuit 260 causes the inner frame 12 or the front frame. The opening of 14 can be detected.

The DC power supply DC1 is a power supply that supplies a DC voltage of 12 V to the frame open detection circuit 260. Electric power (power supply) to the DC power supply DC1 is supplied from a power supply unit 251 provided in the power supply device 115 through a power supply path (not shown). The DC power supply DC1 is connected to the anode terminal of the diode D1. One end of a 1F (farad) capacitor CD1 is connected to the cathode terminal of the diode D1. The other end of the capacitor CD1 is grounded. Further, one end of the capacitor CD1 is connected to one end of the switch SW1, one end of the switch SW2, the VDD terminal of the timer IC1 and the RES terminal of the timer IC1.

The capacitor CD1 functions as a rechargeable battery that supplies a DC voltage to the frame open detection circuit 260 when the power supply to the pachinko machine 10 is cut off and the DC voltage of 12 V is not supplied from the DC power supply DC1. It is a part.

This is because the capacitor CD1 is applied to the capacitance 1F (farad) of the capacitor CD1 and the capacitor CD1 when the pachinko machine 10 is supplied with power and the DC voltage of 12 V is supplied from the DC power supply DC1. And a DC voltage (about 11.3 V obtained by subtracting about 0.7 V of the voltage drop in the diode D1 from 12 V supplied from the DC power supply DC1) are stored.

On the other hand, the capacitor CD1 is stored in the capacitor CD1 when the DC power of DC 12 DC is not supplied from the DC power supply DC1, for example, when power supply to the pachinko machine 10 is cut off after the business hours of the game arcade are over. Electric power based on the generated charges is supplied to the frame open detection circuit 260.

Therefore, the frame open detection circuit 260 naturally operates when the pachinko machine 10 is supplied with power and a DC voltage of 12 V is supplied from the DC power supply DC1, and further, for example, a game hall business. Even when the power supply to the pachinko machine 10 is cut off after the end of time and the DC voltage of 12 V is not supplied from the DC power supply DC1, the power is supplied by the capacitor CD1 to operate the inner frame. The opening of 12 and the opening of the front frame 14 can be detected. In the present embodiment, the capacitor CD1 is used as a component that supplies power to the frame open detection circuit 260 when a DC voltage of 12 V is not supplied from the DC power supply DC1. However, the present invention is not limited to this, and the capacitor CD1 may be a secondary battery (rechargeable battery) having a larger amount of stored electricity or a primary battery that does not need to be charged.

In addition, when the cathode terminal of the diode D1 is connected to one end of the capacitor CD1 and this diode D1 fulfills the function of preventing backflow of current, when the power is supplied from the capacitor CD1 to the frame open detection circuit 260. However, the voltage generated by the power is not applied to the DC power supply DC1, and the DC power supply DC1 is not damaged.

The timer IC1 is a C-MOS timer, and the inner frame 12 or the front frame 14 is opened by connecting the resistor R1 of 200 kΩ, the resistor R2 of 100 kΩ, the capacitor CD2 of 22 μF, and the capacitor CD3 of 0.1 μF. To function as a circuit for making the transistor TR1 conductive for about 4.4 seconds. When the transistor TR1 is turned on, a drive voltage Vb having a maximum value of about 5 volts is output from the power supply output terminal, a reset signal SG3b is output from the reset signal output terminal, and a power failure is output from the power interruption signal output terminal. The output of the signal SG1b is started.

The timer IC1 is supplied with electric power by the capacitor CD1, for example, when the power supply to the pachinko machine 10 is cut off after the business hours of the amusement hall are finished and the DC voltage of 12 V is not supplied from the DC power supply DC1. The case where the power is supplied to the pachinko machine 10 and the case where the DC voltage of 12 V is supplied from the DC power supply DC1 is shared. Therefore, naturally, the timer IC 1 can operate with a DC voltage of 12 V or less supplied to the frame open detection circuit 260 when power is being supplied to the pachinko machine 10. Further, since the timer IC1 is a timer composed of a C-MOS semiconductor, it is possible to suppress power consumption during operation and operate for a long time.

The VDD terminal of the timer IC1 is a terminal for inputting the DC voltage supplied to the timer IC1, and is connected to one end of the switch SW1, one end of the switch SW2, one end of the capacitor CD1 and the RES terminal of the timer IC1. The RES terminal of the timer IC1 is a terminal for activating a reset function that forcibly brings the voltage output from the OUT terminal into an output stopped state (zero volt) when a pulse signal is input to the RES terminal. However, since the frame open detection circuit 260 does not use this reset function, the RES terminal of the timer IC1 is connected to the VDD terminal of the timer IC1 so that the reset function does not operate. Since the VDD terminal of the timer IC1 and the RES terminal of the timer IC1 are connected to one end of the capacitor CD1 as described above, a DC voltage of about 11.3 volts is applied to the VDD terminal and the RES terminal of the timer IC1. Is applied.

When the switch SW1 and the switch SW2 are cut off (when the inner frame 12 and the front frame 14 are closed), the TRG terminal of the timer IC1 outputs about the voltage output from the OUT terminal of the timer IC1. While setting to 10.6 volts, when either the switch SW1 or the switch SW2 or both the switch SW1 and the switch SW2 become conductive (either the inner frame 12 or the front frame 14, or When both the inner frame 12 and the front frame 14 are open), the voltage output from the OUT terminal of the timer IC 1 is set to about 10.6 volts to zero volts about 4.4 seconds after the conduction. It is a terminal for doing. The TRG terminal of the timer IC1 is connected to the other end of the resistor R2.

The resistor R2 connected to the TRG terminal of the timer IC1 has a timer when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is in a conductive state (see FIG. 5B). This is a resistor for applying a DC voltage (about 11.3 V) to the TRG terminal of IC1. Since the input impedance of the TRG terminal of the timer IC1 is sufficiently larger than the resistance value of the resistor R2 (100 kΩ), the voltage drop due to the resistor R2 hardly occurs. Therefore, when the switch SW1 or the switch SW2 becomes conductive, a voltage of about 11.3 volts supplied from one end of the capacitor CD1 is applied to the TRG terminal of the timer IC1.

With the above connection, when the switch SW1 and the switch SW2 are in the cutoff state (when the inner frame 12 and the front frame 14 are in the closed state), no voltage is supplied to the resistor R2, so that the voltage is applied to the TRG terminal of the timer IC1. The voltage will be zero volts. At this time, the voltage output from the OUT terminal of the timer IC1 is about 10.6 volts.

On the other hand, when either the switch SW1 or the switch SW2, or both the switch SW1 and the switch SW2 are in the conductive state (either the inner frame 12 or the front frame 14, or both the inner frame 12 and the front frame 14 are Since the voltage is supplied to the resistor R2 (in the open state), the voltage applied to the TRG terminal of the timer IC1 is about 11.3 volts which is the same as the voltage applied to one end of the capacitor CD1. At this time, the voltage output from the OUT terminal of the timer IC1 is about 10.6 for about 4.4 seconds after either the switch SW1 or the switch SW2 or both the switch SW1 and the switch SW2 become conductive. Volts, then zero volts.

As described above, the voltage applied to the TRG terminal of the timer IC1 can set the voltage output from the OUT terminal of the timer IC1 to either about 10.6 volts or zero volts. When the switch SW1 or the switch SW2 is turned on (the inner frame 12 or the front frame 14 is opened) and the voltage applied to the TRG terminal of the timer IC 1 changes from zero volt to about 11.3 volt, as described above, After a delay of about 4.4 seconds from the rise of the voltage, the voltage of about 10.6 volts output from the OUT terminal of the timer IC1 falls to zero volts. Then, as will be described in detail later, the transistor is caused by the time difference (about 4.4 seconds) between the rise of the voltage applied to the TRG terminal of the timer IC1 and the fall of the voltage output from the OUT terminal of the timer IC1. TR1 conducts for about 4.4 seconds.

When the switch SW1 and the switch SW2 are cut off (the inner frame 12 and the front frame 14 are closed) and the voltage applied to the TRG terminal of the timer IC1 becomes zero volts, the OUT terminal of the timer IC1 has a voltage of about 10.6 volts. When the switch SW1 or the switch SW2 is turned on (the inner frame 12 or the front frame 14 is opened) and the voltage applied to the TRG terminal of the timer IC1 rises to about 11.3 volts, It is a terminal that sets the output voltage of about 10.6 volts to zero volts with a delay of 4.4 seconds. The OUT terminal is connected to the gate terminal G of FET1 and the gate terminal G of FET2.

The FET1 is an N-MOS switching element that switches between conduction and interruption by the voltage output from the OUT terminal of the timer IC1, and the drain terminal D of the FET1 is connected to the other end of the resistor R3 of 100 kΩ and the base terminal b of the transistor TR1. Connected. The emitter terminal e of the transistor TR1 is connected to one end of the resistor R3, one end of the resistor R2 and the input terminal of the NOTIC3. The collector terminal c of the transistor TR1 is connected to one end of the capacitor CD4, one end of the resistor R4, the anode terminal of the diode D3, and the anode terminal of the diode D4. Further, the source terminal S of the FET1 is connected to the cathode terminal of the Zener diode D2. The anode terminal of this Zener diode D2 is grounded.

When the voltage output from the OUT terminal of the timer IC1 is about 10.6 volts, the FET1 (when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds after the opening, When the inner frame 12 and the front frame 14 are closed), the drain terminal D and the source terminal S of the FET 1 are brought into conduction. On the other hand, when the voltage output from the OUT terminal of the timer IC1 is zero volt (when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed after the opening), the FET1 is FET1. The drain terminal D and the source terminal S of the above are cut off.

Here, three scenes of the operation of the FET1 and the operation of the transistor TR1 will be described in time series. First, the operation of the FET1 and the operation of the transistor TR1 from the opening of the inner frame 12 or the front frame 14 to the elapse of about 4.4 seconds will be described. When the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is in a conductive state, and therefore, until about 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened (the switch Until about 4.4 seconds have passed since the switch SW1 or the switch SW2 was turned on), the current supplied from the DC power source DC1 or the capacitor CD1 was passed through the resistor R3 to the drain terminal D and the source terminal S of the FET1. Between the zener diode D2 and the cathode terminal of the zener diode D2. Here, the limiting voltage of the Zener diode D2 is about 5.7 volts. When the drain terminal D and the source terminal S of the FET 1 are in a conductive state, the impedance between the drain terminal D and the source terminal S of the FET 1 is about several Ω. Therefore, the voltage of the base terminal b of the transistor TR1 becomes about 5.7 volts which is almost the same voltage as the limiting voltage of the Zener diode D2. When a voltage is generated in the resistor R3, a bias voltage is applied to the base terminal b of the transistor TR1 and the emitter terminal e of the transistor TR1. Therefore, the emitter terminal e and the collector terminal c of the transistor TR1 are also electrically connected, and the current supplied from the DC power supply DC1 or the capacitor CD1 flows from the emitter terminal e of the transistor TR1 to the collector terminal c. Here, when the base terminal b and the collector terminal c of the transistor TR1 are in a conductive state, the impedance between the base terminal b and the collector terminal c of the transistor TR1 is about several Ω. Therefore, the voltage of the collector terminal c of the transistor TR1 is approximately the same as the limiting voltage of the Zener diode D2, approximately 5.7, until approximately 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened. It becomes a bolt. By this operation, until about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened, a voltage of about 5.7 volts is applied to the capacitor CD4, the capacitor CD4 is charged, and the power source is turned on. A drive voltage Vb having a maximum value of about 5 V (a voltage obtained by subtracting 0.7 V of the voltage drop of the diode D3 from the voltage of about 5.7 V applied to the capacitor CD4) is started from the output terminal, and the reset signal output terminal outputs. The reset signal SG3b is started to be output, and the power failure signal SG1b is started to be output from the power failure signal output terminal.

Next, the operation of the FET1 and the operation of the transistor TR1 when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed from the opening will be described. When the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds have passed since the opening, the drain terminal D and the source terminal S of the FET 1 are cut off. Therefore, even if the switch SW1 or the switch SW2 is conductive, the current supplied from the DC power supply DC1 or the capacitor CD1 does not flow into the resistor R3, and the voltage generated in the resistor R3 becomes zero. Therefore, the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off. Therefore, when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have passed after the opening, the voltage of the collector terminal c of the transistor TR1 becomes zero volts. By this operation, the inner frame 12 or the front frame 14 is opened, and when about 4.4 seconds elapses from the opening, the voltage applied to the capacitor CD4 becomes zero volt, and the electric power stored in the capacitor CD4 is discharged. ..

Finally, the operation of the FET1 and the operation of the transistor TR1 when the inner frame 12 and the front frame 14 are closed will be described. When the inner frame 12 and the front frame 14 are closed, the voltage output from the OUT terminal of the timer IC1 becomes about 10.6 volts, and the drain terminal D and the source terminal S of the FET1 become conductive, but the switch SW1 and the switch SW1 SW2 is in the cutoff state. Therefore, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET1 become conductive, but no current is supplied from the DC power source DC1 or the capacitor CD1 and the transistor TR1 is The voltage between the base terminal b and the emitter terminal e is zero volt. As a result, the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off. Therefore, when the inner frame 12 and the front frame 14 are closed, no voltage is applied to the collector terminal c of the transistor TR1 and the voltage of the collector terminal c of the transistor TR1 becomes zero volts. By this operation, even when the inner frame 12 and the front frame 14 are closed, the voltage applied to the capacitor CD4 becomes zero volt, and the electric power stored in the capacitor CD4 is discharged.

Returning to the explanation of FIG. The capacitor CD4 charges the electric power supplied via the transistor TR1 and discharges the charged electric power to supply the electric power to the power supply output terminal and the reset IC 2 except the power interruption signal output terminal. Farad) capacitors. One end of the capacitor CD4 is connected to the collector terminal c of the transistor TR1, one end of the resistor R4, the anode terminal of the diode D3 and the anode terminal of the diode D4. On the other hand, the other end of the capacitor CD4 is grounded.

By this connection, in the capacitor CD4, the drain terminal D and the source terminal S of the FET1 become conductive and the emitter terminal of the transistor TR1 remains until about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened. The electric power supplied from the DC power supply DC1 or the capacitor CD1 is stored via the transistor TR1. Then, in the capacitor CD4, the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds after the opening (the drain terminal D and the source terminal S of the FET1 are cut off and the emitter terminal of the transistor TR1 is cut off). (Since e and the collector terminal c are cut off), the stored electric power is discharged and the electric power is supplied to the power output terminal and the reset IC 2. When the drain terminal D and the source terminal S of the FET1 are in the cutoff state, the conduction between the drain terminal D and the source terminal S of the FET2 is naturally cutoff, so that the current accompanying the power discharged by the capacitor CD4 is generated. It does not flow into the resistor R5. Therefore, the voltage associated with the electric power discharged from the capacitor CD4 is not output to the power failure signal output terminal. Therefore, the capacitor CD4 does not supply power to the power failure signal output terminal, but supplies power to the power supply output terminal and the reset IC 2.

The discharge time until the electric power stored in the capacitor CD4 becomes zero depends on the input impedance of the input terminal I23 of the multiplexer MP3 connected to the power output terminal and the power terminal of the MPU 201 connected to the output terminal O3 of the multiplexer MP3. , The input impedance of the input terminal IN of the reset IC2, the input impedance of the input terminal I22 of the multiplexer MP2 connected to the reset signal output terminal, and the input impedance of the reset terminal of the MPU201 connected to the output terminal O2 of the multiplexer MP2. Etc. In this embodiment, when the capacitor CD4 is fully charged, the discharge time until the fully charged electric power becomes zero is set to about 20 seconds. However, when the capacitor CD4 is fully charged, the discharge time until the fully charged power becomes zero is shorter than about 20 seconds or longer than about 20 seconds by adjusting the impedance described above. You may set it.

The electric power stored in the capacitor CD4 is discharged even when the inner frame 12 or the front frame 14 is opened, about 4.4 seconds elapses from the opening, and the inner frame 12 and the front frame 14 are closed. continue. In addition, when the inner frame 12 and the front frame 14 are closed, the voltage output from the OUT terminal of the timer IC1 becomes about 10.6 volts, and the drain terminal D and the source terminal S of the FET1 become conductive. , The switch SW1 and the switch SW2 are in a cutoff state. Therefore, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET1 are conducted, but no current is supplied from the DC power supply DC1 or the capacitor CD1 and the base of the transistor TR1 is not supplied. The voltage between terminal b and emitter terminal e is zero volts. Therefore, since the emitter terminal e and the collector terminal c of the transistor TR1 are cut off, the inner frame 12 or the front frame 14 is opened, and the capacitor CD4 is stored in the same manner as when about 4.4 seconds have passed since the opening. The discharged power is discharged to supply power to the power output terminal and the reset IC 2. Here, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET2 become conductive as in the FET1, and the power failure signal SG1b is output from the power failure signal output terminal. In this case, the power failure signal SG1b is not output from the power failure signal output terminal because the drain terminal D and the source terminal S of the FET3, which will be described later, become conductive. This description will be described later.

It should be noted that when the electric power stored in the capacitor CD4 becomes zero, the discharge naturally ends (stops). As a result, the power supplied from the capacitor CD4 to the power output terminal and the reset IC 2 is also stopped.

Like the FET1, the FET2 is an N-MOS switching element that switches between conduction and interruption by the voltage output from the OUT terminal of the timer IC1, and the drain terminal D of the FET2 is connected to the other end of the resistor R4 of 100 kΩ. It One end of the resistor R4 is connected to one end of the capacitor CD4, the collector terminal c of the transistor TR1, the anode terminal of the diode D3 and the anode terminal of the diode D4. Further, the source terminal S of the FET2 is connected to the anode terminal of the diode D5 for backflow prevention and one end of the resistor R5 of 100 MΩ. The other end of the resistor R5 is grounded. The cathode terminal of the diode D5 is connected to the power failure signal output terminal.

When the voltage output from the OUT terminal of the timer IC1 is about 10.6 volts, the FET2 (when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds after the opening) When the inner frame 12 and the front frame 14 are closed), the drain terminal D and the source terminal S of the FET 2 are brought into conduction. On the other hand, when the voltage output from the OUT terminal of the timer IC1 is zero volt (when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed after the opening), the FET2 is FET2. The drain terminal D and the source terminal S of the above are cut off.

NOTIC3 is a logical NOT circuit that applies a voltage to the gate terminal G of the FET3. The input terminal of the NOTIC3 is connected to the other end of the switch SW1, the other end of the switch SW2, one end of the resistor R1, one end of the resistor R2 and one end of the resistor R3. The power supply terminal of the NOTIC3 is connected to one end of the capacitor CD1 although not shown. Therefore, when the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is turned on, and a voltage of about 11.3 volts is applied to the input terminal of the NOTIC3, zero voltage is applied from the output terminal of the NOTIC3. Is output. On the other hand, when the inner frame 12 and the front frame 14 are closed, the switches SW1 and SW2 are cut off, and when zero volt is applied to the input terminal of the NOTIC3, a voltage of about 11.3 volts is output from the output terminal of the NOTIC3. Is output.

The FET 3 is an N-MOS switching element that controls the power failure signal SG1b output from the power interruption signal output terminal. The gate terminal G of the FET3 is connected to the output terminal of the NOTIC3. Further, the drain terminal D of the FET3 is connected to the anode terminal of the diode D5, and the source terminal S of the FET3 is grounded. Therefore, when zero volt is output from the output terminal of the NOTIC3, that is, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 becomes conductive, the drain terminal D and the source terminal S of the FET3 are The connection with is cut off. Therefore, when the inner frame 12 or the front frame 14 is opened, the power failure signal SG1b can be output from the power failure signal output terminal. On the other hand, when a voltage of about 11.3 V is output from the output terminal of NOTIC3, that is, when the inner frame 12 and the front frame 14 are closed and the switches SW1 and SW2 are cut off, the drain of the FET3 The terminals D and the source terminal S are electrically connected to each other. Therefore, when the inner frame 12 or the front frame 14 is closed, the power failure signal SG1b cannot be output from the power failure signal output terminal.

Here, as for the operation of the FET2 and the FET3, three scenes will be described in time series as in the case of the FET1. First, the operation of the FET 2 and the FET 3 from when the inner frame 12 or the front frame 14 is opened until a lapse of about 4.4 seconds will be described. When the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 is in a conductive state. Therefore, until about 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened (the switch Until about 4.4 seconds have passed since the switch SW2 or the switch SW2 was turned on), the current supplied from the DC power supply DC1 or the capacitor CD1 is supplied to the drain terminal D of the FET2 and the source of the FET2 via the resistor R4. It passes through between the terminals S and flows into the resistor R5. At this time, as described above, the voltage at the collector terminal c of the transistor TR1 is about 5.7 volts, so the voltage applied to one end of the resistor R4 is also about 5.7 volts. Here, when the drain terminal D and the source terminal S of the FET 2 are in a conductive state, the impedance between the drain terminal D and the source terminal S of the FET 2 is about several Ω. On the other hand, since the inner frame 12 or the front frame 14 is open, the conduction between the drain terminal D and the source terminal S of the FET 3 is cut off. Therefore, the voltage of about 5.7 volts applied to one end of the resistor R4 is divided by the resistors R4 and R5. The resistance ratio of the resistors R4 and R5 is 1:1000. Therefore, until about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened, the voltage applied to the resistor R5 is about 5.7 volts which is almost the same as the limit voltage of the Zener diode D2. Becomes By this operation, the power failure signal SG1b is output from the power failure signal output terminal until about 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened. At this time, the power failure signal SG1b output from the power interruption signal output terminal is about 5.0 V obtained by subtracting about 0.7 V of the voltage drop at the diode D5 from about 5.7 V applied to the resistor R5. Becomes

In addition, until about 4.4 seconds have passed since the inner frame 12 or the front frame 14 was opened (until about 4.4 seconds have passed since the switch SW1 or the switch SW2 became conductive), the DC power supply DC1 Alternatively, the voltage supplied from the capacitor CD1 is applied to the power supply signal output terminal via the diode D3 and is applied to the input terminal IN of the reset IC via the diode D4. Therefore, the drive voltage is output from the power supply signal output terminal, and the reset signal SG3b is also output from the reset signal output terminal.

Next, the operation of the FET 2 and the FET 3 when the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed from the opening will be described. When the inner frame 12 or the front frame 14 is opened and about 4.4 seconds have elapsed after the opening, the drain terminal D and the source terminal S of the FET 2 are cut off. At this time, as described above, since the conduction between the drain terminal D and the source terminal S of the FET1 is also cut off, even if the switch SW1 or the switch SW2 is in the conduction state, the emitter terminal e and the collector terminal of the transistor TR1 are c is cut off. As a result, the voltage supply from the DC voltage DC1 or the capacitor CD1 is stopped. By stopping this voltage supply, the discharge of the capacitor CD4 is started. Here, if the drain terminal D and the source terminal S of the FET 2 are in the cutoff state, even if the conduction between the drain terminal D and the source terminal S of the FET 3 is in the cutoff state, the voltage due to the discharge of the capacitor CD4 is not charged. No signal is applied to the signal output terminal. Therefore, the power failure signal SG1b output from the power failure signal output terminal is in a stopped state. On the other hand, the voltage accompanying the discharge of the capacitor CD4 is applied to the power supply output terminal via the diode D3, and is also applied to the input terminal IN of the reset IC via the diode D4. By this operation, the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds after the opening, the power failure signal SG1b output from the power interruption signal output terminal is in the stopped state, while it is output from the power supply output terminal. The drive voltage Vb and the reset signal SG3b output from the reset signal output terminal are continuously output. When the power stored in the capacitor CD4 becomes zero due to discharge, the drive voltage Vb and the reset signal SG3b output from the power supply output terminal are stopped.

Finally, the operation of the FET2 and FET3 when the inner frame 12 and the front frame 14 are closed will be described. When the inner frame 12 and the front frame 14 are closed, the voltage output from the OUT terminal of the timer IC1 becomes about 10.6 volts, and the drain terminal D and the source terminal S of the FET2 become conductive, but the switch SW1 and the switch SW1 SW2 is in the cutoff state. Therefore, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 2 are electrically connected, but no power is supplied from the DC power source DC1 or the capacitor CD1 and the capacitor CD4 The discharge is continued. Here, since the drain terminal D and the source terminal S of the FET2 are electrically connected, a path is generated in which a current accompanying the discharge of the capacitor CD4 flows into the resistor R5. However, in this case, since the inner frame 12 and the front frame 14 are closed, the terminals between the drain terminal D and the source terminal S of the FET 3 are also in a conductive state. When the drain terminal D and the source terminal S of the FET 3 are brought into conduction, the impedance between the drain terminal D and the source terminal S of the FET 3 becomes about several Ω, which is more than the resistance value of the resistor R5 of 100 MΩ. It is a sufficiently small value. Therefore, when the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 2 are electrically connected to each other to generate a path in which a current accompanying the discharge of the capacitor CD4 flows into the resistor R5. The current accompanying the discharge of CD4 flows into the drain terminal D of the FET3, so that no current also flows into the resistor R5. As a result, the power failure signal SG1b is not output from the power failure signal output terminal. Therefore, when the inner frame 12 and the front frame 14 are closed, the power failure signal SG1b output from the power interruption signal output terminal is in a stopped state, while the drive voltage Vb and the reset signal output terminal output from the power supply output terminal are stopped. The reset signal SG3b output from is continuously output. As described above, when the electric power stored in the capacitor CD4 becomes zero due to discharging, the drive voltage Vb and the reset signal SG3b output from the power supply output terminal are stopped.

If the voltage input to the input terminal IN exceeds 4.3 V, the reset IC 2 outputs the voltage input to the input terminal IN as it is from the output terminal OUT, while the voltage input to the input terminal IN The reset semiconductor circuit stops the voltage output from the output terminal OUT (sets the output voltage of the output terminal OUT to zero volt) when the voltage becomes 4.3 V or less. The input terminal IN of the reset IC 2 is connected to the cathode terminal of the diode D4 for backflow prevention. The anode terminal of the diode D4 is connected to the anode terminal of the diode D3 for backflow prevention, and is also connected to one end of the resistor R4, one end of the capacitor CD4 and the collector terminal c of the transistor TR1. The cathode terminal of the diode D3 is connected to the power output terminal. The output terminal OUT of the reset IC 2 is connected to the reset signal output terminal.

Although the output terminal OUT of the reset IC 2 is directly connected to the reset signal output terminal, a backflow prevention diode may be connected to the output terminal OUT of the reset IC 2. In this case, the anode terminal of the backflow prevention diode may be connected to the output terminal OUT of the reset IC 2, and the cathode terminal of the backflow prevention diode may be connected to the reset signal output terminal.

Here, the operation of the reset IC 2 will be described. When the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds have passed after the opening, the capacitor CD4 discharges the stored power and starts supplying power to the power output terminal and the reset IC 2. Since the electric power supplied from the capacitor CD4 decreases with the discharging time, the voltage generated by the discharging of the capacitor CD4 also decreases with the discharging time. Since only the backflow preventing diode D3 is connected between the power supply output terminal and the capacitor CD4, the voltage (driving voltage Vb) output to the power supply output terminal is generated by discharging the capacitor CD4. The voltage drops from the voltage by the forward voltage of the diode D3 (about 0.7 V). On the other hand, a reset IC 2 is connected between the reset signal output terminal and the capacitor CD4 in addition to the diode D4 for backflow prevention. As a result, the voltage output to the reset signal output terminal (reset signal SG3b) is about 4. The voltage dropped by the forward voltage of the diode D4 (about 0.7 V) from the voltage generated by the discharge of the capacitor CD4 is about 4. If the voltage exceeds 3 volts, that is, if the voltage input to the input terminal IN of the reset IC 2 exceeds approximately 4.3 volts, the voltage itself is input. On the other hand, when the voltage dropped by the forward voltage of the diode D4 from the voltage generated by the discharge of the capacitor CD4 is about 4.3 V or less, that is, the voltage input to the input terminal IN of the reset IC2. Is about 4.3 volts or less, the voltage output to the reset signal output terminal is zero volts.

Thus, if the voltage input to the input terminal IN exceeds about 4.3 volts, the reset IC 2 outputs the voltage input to the input terminal IN as it is from the output terminal OUT to the reset signal output terminal. While the voltage is being output (while the reset signal SG3b is being output), when the voltage input to the input terminal IN is about 4.3 V or less, the voltage output from the output terminal OUT is stopped and the reset signal output terminal is output. The output voltage is set to zero volt (the reset signal SG3b is stopped). Since the voltage (driving voltage Vb) output to the power supply output terminal can be 4.3 volts or less, the voltage generated by discharging the capacitor CD4 even after the voltage output from the reset signal output terminal becomes zero volts. Is continuously output until the voltage reaches zero volt.

Here, in order to normally terminate the MPU 201, when the driving voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, first, the MPU 201 is reset during the period of 10 clocks of the operation clock of the MPU 201. The reset signal SG3b input to the terminal is stopped to make the operation processing inexecutable, and then the drive voltage supplied to the power supply terminal of the MPU 201 is set to about 4.0 V or less to make the operation inoperable. There is a need. For example, if the operation clock of the MPU 201 is 100 MHz, in order to normally terminate the MPU 201, when the drive voltage Vb of 5 V is supplied to the power supply terminal of the MPU 201, first, the MPU 201 is input to the reset terminal of the MPU 201. The reset signal SG3b is stopped for at least 100 n seconds to make the arithmetic processing inexecutable, and then the drive voltage Vb supplied to the power supply terminal of the MPU 201 is set to about 4.0 V or less to make it inoperable. There is a need to. In order to realize this, in the frame opening detection circuit 260, first, the voltage input to the input terminal IN of the reset IC 2 is set to about 4.3 V or less, and the reset signal SG3b output from the reset signal output terminal is stopped. As a result, the MPU 201 is set in a state in which the arithmetic processing cannot be executed, and then the drive voltage Vb output from the power supply output terminal is set to about 4.0 V or less to set the MPU 201 in an inoperable state. Here, in the frame open detection circuit 260, after the reset signal SG3b output from the reset signal output terminal is stopped, the drive voltage Vb output from the power supply output terminal is reduced to about 4.0 volts or less. The period of 0.5 seconds is secured. As a result, even when the MPU 201 is temporarily activated by the frame opening detection circuit 260 when the pachinko machine 10 is powered off, the frame opening detection circuit 260 normally terminates the MPU 201 that has started up. You can

Further, when the voltage input to the input terminal IN of the reset IC 2 exceeds 4.3 volts, when the voltage is input to the input terminal IN of the reset IC 2, a delay of about 40 μsec occurs from the input of the voltage. Then, a voltage is output from the output terminal OUT. Due to the delay characteristic of the reset IC 2, the reset signal SG3b output to the reset signal output terminal is output about 40 μsec later than the drive voltage Vb output to the power supply output terminal.

Here, in order to normally start up the MPU 201, first, a drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201 to make the MPU 201 operable, and thereafter, at least 10 operating clocks of the MPU 201 are used. It is necessary to input the reset signal SG3b to the reset terminal of the MPU 201 after a period of (2) to make the arithmetic processing executable. For example, in order to normally start up the MPU 201 in which the operation clock of the MPU 201 is 100 MHz, first, the drive voltage Vb of 5 V is supplied to the power supply terminal of the MPU 201 to make the MPU 201 operable, and then at least 100 nsec. It is necessary to input the reset signal SG3b to the reset terminal of the MPU 201 after a period of (2) to make the arithmetic processing executable. In order to realize this, the frame open detection circuit 260 first outputs the drive voltage Vb of about 5 V from the power supply output terminal, and outputs the reset signal SG3b from the reset signal output terminal about 40 μsec after the output. As a result, even when the MPU 201 is temporarily activated by the frame opening detection circuit 260 when the power of the pachinko machine 10 is off, the activation can be normally performed.

The TH terminal of the timer IC1 is a terminal for measuring the voltage applied to the TH terminal, and is connected to the other end of the resistor R1, one end of the capacitor CD2, and the DCH terminal of the timer IC1. The DCH terminal of the timer IC1 has a voltage (about 7.5 volts) that is 2/3 of the DC voltage (about 11.3 volts) applied to the VDD terminal of the timer IC1 when the voltage applied to the TH terminal of the timer IC1. In this case, the impedance of the DCH terminal is switched from the infinite state to the zero state. When the impedance of the DCH terminal becomes zero (ground state), the voltage cannot be applied to the capacitor CD2. On the other hand, when the impedance of the DCH terminal is infinite, a voltage can be applied to the capacitor CD2.

The resistor R1 and the capacitor CD2 connected to the TH terminal of the timer IC1 and the DCH terminal of the timer IC1 open the inner frame 12 or the front frame 14 based on the time constant which is the product of the resistance value of the resistor R1 and the capacitor CD2. In this case, it is a part for determining a period of about 4.4 seconds until the voltage of about 10.6 V output from the OUT terminal of the timer IC 1 is switched to zero V. One end of the resistor R1 is connected to the other end of the switch SW1, the other end of the switch SW2, one end of the resistor R2, the input terminal of the NOTIC3, one end of the resistor R3 and the emitter terminal e of the transistor TR1. The other end of the resistor R1 is connected to the TH terminal of the timer IC1, the DCH terminal of the timer IC1, and one end of the capacitor CD2. The other end of the capacitor CD2 is grounded.

Here, the resistor R1 and the capacitor CD2 will be described together with the TRG terminal of the timer IC1, the TH terminal of the timer IC1, the DCH terminal of the timer IC1 and the OUT terminal of the timer IC1.

Since the voltage is not supplied to the resistor R1 when the inner frame 12 and the front frame 14 are in the closed state (when the switch SW1 and the switch SW2 are in the cutoff state), the voltage applied to the TH terminal of the timer IC1 is zero volt (about 7.5 volt). Less than) and the impedance of the DCH terminal of the timer IC1 is set to infinity. Therefore, a voltage can be applied to the capacitor CD2, and the capacitor CD2 is in a chargeable state (a state in which electric charge can be stored). However, when the switches SW1 and SW2 are cut off, the connection between the one end of the capacitor CD1 and the resistor R1 is cut off, so that no voltage is applied to the capacitor CD2 and the voltage applied to the capacitor CD2 is zero volt. Becomes Thus, the capacitor CD2 is in a chargeable state but is not charged. At this time, the voltage of the OUT terminal of the timer IC1 is about 10.6 volts, and the voltage between the drain terminal D and the source terminal S of the FET1 and the voltage between the drain terminal D and the source terminal S of the FET2 is reduced. There is continuity. However, since the switches SW1 and SW2 are in the cutoff state, no voltage is generated in the resistor R3 (between the base terminal b and the emitter terminal e of the transistor TR1), and the emitter terminal e and the collector terminal c of the transistor TR1 are not generated. And are cut off. Since the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal D of the FET 3 are electrically connected. Therefore, the power from the capacitor CD4 can be supplied to the power supply output terminal and the reset IC 2 excluding the power failure signal output terminal (when the power stored in the capacitor CD4 becomes zero due to discharge, No supply).

Next, when the inner frame 12 or the front frame 14 is opened (see FIG. 5B) and the switch SW1 or the switch SW2 is turned on, the voltage applied to the TRG terminal of the timer IC1 starts from zero volt. Switch to about 11.3 volts. At this time, the voltage of the OUT terminal of the timer IC1 is about 10.6 volts, and the drain terminal D and the source terminal S of the FET1 and the drain terminal D and the source terminal S of the FET2 are electrically connected. doing. Then, a voltage is generated in the resistor R3 (between the base terminal b and the emitter terminal e of the transistor TR1), and the emitter terminal e and the collector terminal c of the transistor TR1 are electrically connected. As a result, a voltage of about 5.7 volts is generated at the collector terminal c of the transistor TR1, and the generated voltage becomes about 5.0 volts via the diode D3 and is output to the power output terminal. The voltage of about 5.7 volts generated at the collector terminal c of the transistor TR1 becomes about 5.0 volts via the diode D4 and the reset IC2 and is output to the reset signal output terminal. In addition, since the inner frame 12 or the front frame 14 is in an open state and the drain terminal D and the source terminal D of the FET 3 are in a cutoff state, the voltage of about 5.7 volts generated at the collector terminal c of the transistor TR1 is generated. The voltage becomes about 5.0 V through the diode D5 and is output to the power interruption signal output terminal. Further, the capacitor CD4 is started to be charged by the voltage of about 5.7 volts generated at the collector terminal c of the transistor TR1.

Further, at the same time that the voltage applied to the TRG terminal of the timer IC1 is switched from zero volt to about 11.3 volt, the voltage is applied to the capacitor CD2 and the charging of the capacitor CD2 is started. At this time, the voltage applied to the TH terminal of the timer IC1 starts rising.

Regarding the voltage of the OUT terminal of the timer IC1, the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD2) is 2/the voltage (approximately 11.3 volts) input to the VDD terminal of the timer IC1. Continue to hold about 10.6 volts until it equals a voltage of 3, ie about 7.5 volts. When the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD2) rises and becomes equal to about 7.5 volts, the impedance of the DCH terminal of the timer IC1 changes from an infinite state to a zero state (ground). State). Then, the voltage applied to the capacitor CD2 is in a zero volt state, and the electric charge stored in the capacitor CD2 is discharged. As a result, the voltage applied to the TH terminal of timer IC1 switches from about 7.5 volts to zero volts. Due to the switching of the voltage applied to the TH terminal of the timer IC1, the voltage of the OUT terminal of the timer IC1 switches from about 10.6 volt to zero volt. Then, conduction between the drain terminal D and the source terminal S of the FET1 and between the drain terminal D and the source terminal S of the FET2 is cut off, and the resistance R3 (the base terminal b and the emitter terminal e of the transistor TR1 is disconnected). The voltage generated between the terminals) becomes zero volts. As a result, the capacitor CD4 discharges the stored power and supplies the power to the power output terminal and the reset IC2.

In this way, when the inner frame 12 or the front frame 14 is in the open state and the switch SW1 or the switch SW2 is in the conductive state (see FIG. 5B), it is output from the OUT terminal of the timer IC1. A period until the voltage of about 10.6 V is switched to zero V, that is, a period until the voltage applied to the TH terminal of the timer IC1 (the voltage applied to the capacitor CD2) changes from zero V to about 7.5 V. , 4.4 seconds based on the time constant which is the product of the resistance value of the resistor R1 and the capacitance of the capacitor CD2. Then, the frame open detection circuit 260 outputs a voltage to the power supply output terminal, the reset signal output terminal, and the power failure signal output terminal for about 4.4 seconds when the inner frame 12 or the front frame 14 is opened. To do. Then, when about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened, the frame open detection circuit 260 detects the voltage of about 10.6 volts output from the OUT terminal of the timer IC 1. The voltage is switched to zero volt, the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off, the voltage output to the power interruption signal output terminal is stopped, and the discharge of the capacitor CD4 is started. As a result, the frame open detection circuit 260 causes the power supply output terminals other than the power failure signal output terminal due to the discharge of the capacitor CD4 when about 4.4 seconds have elapsed after the inner frame 12 or the front frame 14 was opened. And outputs a voltage to the reset signal output terminal. As described above, when the voltage input to the input terminal IN of the reset IC 2 becomes approximately 4.3 V or less due to the discharge of the capacitor CD4, the reset IC 2 outputs the voltage output from the output terminal OUT, that is, the reset signal output. Set the terminal voltage to zero volts. On the other hand, the voltage of the power output terminal is output until the discharge by the capacitor CD4 is stopped. Therefore, when about 4.4 seconds elapse after the inner frame 12 or the front frame 14 is opened, the frame open detection circuit 260 first outputs the voltage (power failure signal SG1b) output to the power interruption signal output terminal. Then, the voltage output to the reset signal output terminal (reset signal SG3b) is stopped, and finally the voltage output to the power supply output terminal (drive voltage Vb) is stopped. Therefore, the frame opening detection circuit 260 can normally end the started MPU 201 even if the MPU 201 is temporarily started while the pachinko machine 10 is powered off.

After about 4.4 seconds have passed since the inner frame 12 or the front frame 14 was opened, the inner frame 12 and the front frame 14 are changed from the open state to the closed state (switch SW1 and switch SW2 are disconnected from the conductive state). State), that is, when the voltage applied to the TRG terminal of the timer IC1 switches from about 11.3 volts to zero volts, the voltage of the OUT terminal of the timer IC1 switches from zero volts to about 10.6 volts. In this state, as described above, the terminals between the drain terminal D and the source terminal S of the FET1 and the terminals between the drain terminal D and the source terminal S of the FET2 are in conduction, but the switches SW1 and SW2 are cut off. Since it is in the state, no electric power is supplied from the DC power source CD1 or the capacitor CD1, and the discharging state of the capacitor CD4 continues. When the inner frame 12 or the front frame 14 is closed, the drain terminal D and the gate terminal S of the FET 3 are electrically connected, so that the voltage due to the discharge of the capacitor CD4 is the power output terminal and the power output terminal except the power interruption signal output terminal. It is applied to the input terminal IN of the reset IC 2.

Here, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and before the elapse of about 4.4 seconds from the opening, the inner frame 12 and the front frame 14 are closed, When the switch SW1 and the switch SW2 are cut off, the voltage of the OUT terminal of the timer IC1 does not switch to zero volt and remains about 10.6 volt. However, also in this case, the frame open detection circuit 260 can stop the power failure signal SG1b, then the reset signal SG3b, and finally the drive voltage Vb. This case will be described. First, when the inner frame 12 or the front frame 14 is in the open state and the switch SW1 or the switch SW2 is conductive, the frame open detection circuit 260 causes the power supply output terminal, the reset signal output terminal, and the power failure signal output as in the above description. The voltage is output to the terminal and the capacitor CD4 is charged. When the inner frame 12 and the front frame 14 are closed within about 4.4 seconds from the open state, the switch SW1 and the switch SW2 are switched from the conductive state to the cutoff state, so that the emitter terminal e and the collector terminal c of the transistor TR1 are closed. Then, the conduction with and is cut off, and the discharge of the capacitor CD4 is started. Here, since the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 3 are electrically connected. Therefore, when the inner frame 12 and the front frame 14 are closed, the voltage due to the discharge of the capacitor CD4 is not applied to the power interruption signal output terminal, and the power failure signal SG1b is stopped. On the other hand, the voltage generated by discharging the capacitor CD4 is applied to the power supply output terminal and the input terminal IN of the reset IC 2. After that, the voltage accompanying the discharge of the capacitor CD4 decreases with the passage of time, the reset signal SG3b output from the reset signal output terminal is stopped, and finally the drive voltage Vb output from the power supply output terminal is stopped. .. By this operation, even if the inner frame 12 and the front frame 14 are closed within about 4.4 seconds after the inner frame 12 or the front frame 14 is opened, the frame open detection circuit 260 first detects It is possible to stop the power failure signal SG1b, then the reset signal SG3b, and finally the drive voltage Vb. Therefore, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and about 4.4 seconds after the opening, the inner frame 12 and the front frame 14 are closed, and the switch is turned on. Even when the switch SW1 and the switch SW2 are cut off, the frame opening detection circuit 260 can normally end the started MPU 201 even if the MPU 201 is temporarily started.

Returning to the explanation of FIG. The CNT terminal of the timer IC1 is a terminal that adjusts the output period of the voltage output from the OUT terminal of the timer IC1 according to the signal input to the CNT terminal. The CNT terminal of the timer IC1 is connected to one end of the capacitor CD3. The other end of this capacitor CD3 is grounded. In the frame opening detection circuit 260, the output period of the voltage output from the OUT terminal of the timer IC1 is not adjusted (the output period of the voltage output from the OUT terminal of the timer IC1 is fixed to about 4.4 seconds). The CNT terminal of the timer IC1 is grounded in an alternating current by the capacitor CD3.

As described above, when the power of the pachinko machine 10 is off, the frame opening detection circuit 260 opens the inner frame 12 or the front frame 14 and turns on the switch SW1 or the switch SW2 (FIG. 5(b)), the power supply output terminal, the reset signal output terminal and the power failure signal output terminal. On the other hand, the frame open detection circuit 260 first stops the voltage (power failure signal SG1b) output to the power interruption signal output terminal when about 4.4 seconds have elapsed since the inner frame 12 or the front frame 14 was opened. At the same time, the capacitor CD4 is started to discharge, after that, the voltage (reset signal SG3b) output to the reset signal output terminal is stopped, and finally the drive voltage Vb output to the power supply output terminal is stopped. Therefore, even if the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started up when the power of the pachinko machine 10 is off, the frame open detection circuit 260 does not restart the MPU 201 that has started up. It can be terminated normally.

Although the details will be described later, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame opening detection circuit 260, so that the pachinko machine 10 is activated. 10 turns on the open-middle frame open flag 203a. By turning on the off-frame open flag 203a, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off. Further, as will be described later in detail, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame open detection circuit 260. In addition to turning on the in-off-frame flag 203a, the switch 10 outputs a pulse signal having a pulse width of 1 msec to the hall computer 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours.

Here, there is a case where the game hall has a crime prevention contract with a private security company, and in this case, when there is an intruder in the game hall, the guard of the security company immediately rushes to the game hall. However, since fraudulent acts are carried out in a short time, in most cases the intruder has already escaped from the playground when the guards rush. Therefore, even if a security contract is made with a private security company, it is impossible to determine which pachinko machine 10 has been fraudulent. The pachinko machine 10 that has been cheated must return to a normal state, but if you do not know which pachinko machine 10 has been cheated, the inner frame 12 and the front frame 14 of all the pachinko machines 10 must be removed. It had to be opened and inspected one by one, and performing this work at a game hall where a large number of pachinko machines 10 were installed was a considerable heavy labor.

However, according to the pachinko machine 10 of the present embodiment, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame open detection circuit 260. Then, in addition to turning on the off-inside frame open flag 203a, a pulse signal having a pulse width of 1 msec is output to the hall computer 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours. Therefore, the pachinko machine 10 in which the inner frame 12 or the front frame 14 has been opened can be specified also by the pulse signal stored in the hall computer 262. Furthermore, by storing the pulse signal output from the pachinko machine 10 to the hall computer 262 and storing the output time of the output pulse signal, the opening time of the inner frame 12 or the front frame of the specified pachinko machine 10 is stored. The opening time of 14 can be detected.

However, as described above, when the power of the pachinko machine 10 is off, when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily activated by the frame open detection circuit 260, the open middle frame is opened. Since the flag 203a is turned on, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off, without using the hall computer 262. is there. Therefore, according to the pachinko machine 10 of this embodiment, the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off, even in a game hall where the hall computer 262 is not operated for 24 hours. Then, the pachinko machine 10 can be specified.

Further, as described above, since the frame open detection circuit 260 is provided with the 1F capacitor CD1, the frame open detection circuit 260 supplies power to the pachinko machine 10, and the DC power supply DC1 supplies 12V. When the DC voltage is supplied, the operation is naturally performed, and further, for example, after the business hours of the amusement park are finished, the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12V is supplied from the DC power supply DC1. Even when the opening is not performed, the opening of the inner frame 12 and the opening of the front frame 14 can be detected and the MPU 201 can be started up for a certain period of time.

In addition, for example, when the power supply to the pachinko machine 10 is cut off after the business hours of the amusement hall are finished and the DC voltage is supplied from the capacitor CD1 to the frame open detection circuit 260, the inner frame 12 or the front frame 14 is When the total supply period of the current from the capacitor CD1 associated with opening is extended or the number of times the opening of the inner frame 12 or the front frame 14 is detected is increased, the capacity of the capacitor CD1 is increased (for example, the capacitor The capacity of CD1 is set to 10 F), and the capacitor CD1 may be changed to a secondary battery having a large amount of stored electricity.

However, the power consumption of the capacitor CD1 by the frame opening detection circuit 260 when the power of the pachinko machine 10 is off and the inner frame 12 and the front frame 14 are closed is the standby power of the timer IC1 and the power consumption of the NOTIC3. However, it does not cause a significant reduction in the amount of charge of the capacitor CD1. Moreover, since a voltage is only applied to each gate terminal G of the FET1 to FET3, the power consumed by the FET1 to FET3 is very small. Therefore, by setting the capacity of the capacitor CD1 to 1F which is widely used, the frame open detection circuit 260 can be manufactured at low cost.

Further, in the door opening detection circuit 260, a circuit for detecting the opening of the inner frame 12 or the opening of the front frame 14 and making the transistor TR1 conductive for about 4.4 seconds is realized by using the LMC555 for the timer IC1. It is not limited to. That is, by using another integrated circuit or the like for the timer IC 1, a circuit that generates one pulse signal for one opening of the inner frame 12 or one opening of the front frame 14 is realized. It is sufficient that the transistor TR1 is energized for a predetermined period based on the pulse signal.

Next, referring to FIG. 8, when one of the inner frame 12 or the front frame 14 is opened and both the inner frame 12 and the front frame 14 are opened while the pachinko machine 10 is powered off. The case will be described. FIG. 8 shows the voltage of the TRG terminal of the timer IC1 and the voltage of the OUT terminal of the timer IC1, which change depending on the state of the switch SW1 (state of the inner frame 12) and the state of the switch SW2 (state of the front frame 14). , The voltage of the capacitor CD4, the voltage of the power supply output terminal of the frame open detection circuit 260 (output voltage to the multiplexer MP3), and the voltage of the reset signal output terminal of the frame open detection circuit 260 (to the multiplexer MP2 and the input/output port 205). 7 is a timing chart showing the relationship between the output voltage) and the voltage of the power failure signal output terminal of the frame open detection circuit 260 (output voltage to the multiplexer MP1). 8A is an enlarged view of the voltage of the reset signal output terminal of the frame open detection circuit 260, which changes from t1 time to about 0.01 seconds later. In A of FIG. 8(f), the voltage of the reset signal output terminal from t1 time to about 0.01 seconds is illustrated, but from t3 time to about 0.01 seconds, from t5 time to about 0.01 seconds. The voltage of the reset signal output terminal from after t7 to about 0.01 seconds after t7 has the same waveform as the voltage of the reset signal output terminal from t1 after about 0.01 seconds, and therefore is not shown. doing.

First, as shown in FIG. 8A, when the switch SW1 is turned on (the inner frame 12 is opened) at t1, the TRG terminal voltage of the timer IC1 is t1 as shown in FIG. 8C. At times, it switches from zero volts to about 11.3 volts. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds elapse from t1. As a result, the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7) are brought into conduction, and charging of the capacitor CD4 (see FIG. 7) is started (at t1), as shown in FIG. 8(e). .. Note that this charging is completed in about 0.01 seconds after the switch SW1 becomes conductive as shown in FIG. 8(e). When the charging of the capacitor CD4 is completed, the voltage of the capacitor CD4 becomes about 5.7 volts as shown in FIG. 8(e). It takes about 0.01 seconds to charge the capacitor CD4, but it is physically impossible to open and close the inner frame 12 or the front frame 14 within about 0.01 seconds. Therefore, when the inner frame 12 or the front frame 14 is opened, the charging of the capacitor CD4 is always completed.

Further, the voltage at the power output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I23 of the multiplexer MP3) starts rising at t1 and is about 0 from t1 as shown in FIG. 8(f). It will be about 5.0 volts after 0.01 seconds. As a result, the drive voltage Vb of about 5.0 V is started to be output from the power supply output terminal of the frame open detection circuit 260. Further, the voltage of the reset signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I22 of the multiplexer MP2 and the input/output port 205) is as shown in A of FIGS. 8(g) and 8(f). , About 40 μsec after t1 and starts to rise, and reaches about 5.0 volts about 0.01 sec after t1. As a result, the reset signal SG3b is started to be output from the reset signal output terminal of the frame opening detection circuit 260. The voltage rise at the reset signal output terminal of the frame open detection circuit 260 is about 40 μs after t1 due to the delay characteristic of the reset IC 2 (see FIG. 7) described above. As shown in FIGS. 8F and 8G, the voltage rise at the power supply output terminal of the frame opening detection circuit 260 is about 40 μsec earlier than the voltage rise at the reset signal output terminal of the frame opening detection circuit 260. , The drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, and then the reset signal SG3b is input to the reset signal output terminal of the MPU 201. Therefore, when the pachinko machine 10 is powered off, the frame opening detection circuit 260 can normally start up the MPU 201 when it is temporarily started up.

Although the details will be described later, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame opening detection circuit 260, so that the pachinko machine 10 is activated. 10 turns on the open-middle frame open flag 203a. By turning on this off-inside frame opening flag 203a, the pachinko machine 10 in which the inner frame 12 or the front frame 14 has been opened can be specified. Further, as will be described later in detail, when the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame opening detection circuit 260, so that the pachinko machine 10 is activated. 10 outputs a pulse signal having a pulse width of 1 msec to the hall computer 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours.

Further, as shown in FIG. 8E, when the voltage of the capacitor CD4 becomes about 5.7 volts, the voltage of the power failure signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I21 of the multiplexer MP1). As shown in FIG. 8(h), the voltage starts rising at t1 and reaches about 5.0 volts approximately 0.01 seconds after t1. Here, since the switch SW1 is in the conducting state (the inner frame 12 is in the open state), the drain terminal D and the source terminal S of the FET3 are cut off from each other. As a result, the power failure signal SG1b is started to be output from the power failure signal output terminal of the frame opening detection circuit 260.

Then, when about 4.4 seconds elapse from the time t1, the timer IC1 switches the voltage of the OUT terminal from about 10.6 volts to zero volts, as shown in FIG. Then, the conduction between the drain terminal D and the source terminal S of the FET1 is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7) is cut off, so that the charging of the capacitor CD4 is completed. To do. Then, since the discharge of the capacitor CD4 is started, the voltage of the capacitor CD4 starts to drop (after elapse of about 4.4 seconds from t1) as shown in FIG. 8(e). Following this, as shown in FIG. 8(f), the voltage of the power output terminal of the frame open detection circuit 260 (driving voltage Vb with a maximum value of about 5.0 volts) starts to drop (from t1). After about 4.4 seconds). Further, as shown in FIG. 8G, the voltage (reset signal SG3b) at the reset signal output terminal of the frame opening detection circuit 260 starts to drop (after about 4.4 seconds have elapsed from t1).

Note that when about 4.4 seconds have elapsed from the time t1, the conduction between the drain terminal D and the source terminal S of the FET2 is cut off, so that no current is supplied to the power failure signal output terminal of the frame open detection circuit 260. Therefore, as shown in FIG. 8(h), the voltage at the power failure signal output terminal of the frame open detection circuit 260 (power failure signal SG1b) becomes zero volts when about 4.4 seconds have elapsed from t1. Therefore, when about 4.4 seconds elapse after the inner frame 12 is opened and the switch SW1 is turned on, the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 to the NMI terminal of the MPU 201 is first , Stopped.

Next, when about 9.4 seconds have passed since t1 (about 4.4 seconds after t1 and about 5.0 seconds have passed), the voltage of the capacitor CD4 is changed as shown in FIG. 8(e). Drops to about 5.0 volts. Then, as shown in FIG. 8(f), the voltage of the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.3 volts (from t1). After about 9.4 seconds). As shown in FIG. 8(g), the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 drops to about 4.3 volts, and then the reset IC 2 operates to zero volts. (Approx. 9.4 seconds after t1). Therefore, when about 9.4 seconds have passed since the inner frame 12 was opened and the switch SW1 was turned on, the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 to the reset terminal of the MPU 201 is the power failure signal. Next to SG1b, it is stopped. As a result, the MPU 201 is set in a state in which execution of arithmetic processing is impossible (after 9.4 seconds have elapsed from t1).

Further, when about 9.9 seconds have passed from t1 (about 9.4 seconds after t1 and about 0.5 seconds have passed), the voltage of the capacitor CD4 is changed as shown in FIG. 8(e). It drops to about 4.7 volts. Then, as shown in FIG. 8(f), the voltage at the power output terminal of the frame open detection circuit 260 (driving voltage Vb with a maximum value of about 5.0 volts) drops to about 4.0 volts (from t1 time). After about 9.9 seconds). Here, the lower limit of the operating voltage of the MPU 201 is about 4.0 volts. Therefore, when about 9.9 seconds have passed since the inner frame 12 was opened and the switch SW1 was turned on, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 to the power terminal of the MPU 201 was finally changed to The MPU 201 is stopped and becomes inoperable. That is, the MPU 201 is set to the inoperable state (after about 9.4 seconds from t1 o'clock) after being set to the state in which the arithmetic processing cannot be executed (about 9.9 seconds from t1 o'clock). After the passage). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

It should be noted that, when about 20 seconds have elapsed from t1, the voltage of the capacitor CD4 becomes zero volts as shown in FIG. 8(e). Following this, the voltage of the power supply output terminal of the frame open detection circuit 260 (also the drive voltage Vb) becomes zero volts (about 20 seconds before t1). Therefore, when about 20 seconds elapse from t1, the charge amount of the capacitor CD4 becomes zero.

Finally, as shown in FIG. 8A, at time t2, when the switch SW1 is turned off (the inner frame 12 is closed), as shown in FIG. 8C, the TRG terminal voltage of the timer IC1 becomes about At the same time as switching from 11.3 volts to zero volts, the OUT terminal voltage of the timer IC1 switches from zero volts to about 10.6 volts (at t2). When the switch SW1 is turned off (the inner frame 12 is closed) at t2, the drain terminal D and the source terminal S of the FET3 are brought into conduction. As a result, the frame open detection circuit 260 is again set to a state in which the inner frame 12 and the front frame 14 can be detected.

Next, as shown in FIG. 8B, at time t3, when the switch SW2 is turned on (the front frame 14 is opened), the TRG terminal voltage of the timer IC1 becomes as shown in FIG. 8C. At t3, the voltage switches from zero volt to about 11.3 volt. At this time, as shown in FIG. 8(d), the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds elapse from t3. This causes conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7), and charging of the capacitor CD4 (see FIG. 7) is started (see FIG. 8E). t3). Note that this charging is completed in about 0.01 seconds after the switch SW2 becomes conductive as shown in FIG. 8(e). When the charging of the capacitor CD4 is completed, the voltage of the capacitor CD4 becomes about 5.7 volts as shown in FIG. 8(e).

In addition, the voltage at the power output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I2 of the multiplexer MP3) starts rising at t3 and reaches about 0 from t3, as shown in FIG. 8(f). It will be about 5.0 volts after 0.01 seconds. As a result, the drive voltage Vb having a maximum value of about 5.0 volts starts to be output from the power supply output terminal of the frame open detection circuit 260. Further, the voltage at the reset signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I2 of the multiplexer MP2 and the input/output port 205) is about 40 μs after t3 as shown in FIG. 8(g). The voltage starts to rise (see A in FIG. 8F), and becomes about 5.0 volts about 0.01 seconds after t3. As a result, the reset signal SG3 is started to be output from the reset signal output terminal of the frame opening detection circuit 260. The voltage increase at the reset signal output terminal of the frame open detection circuit 260 is about 40 μs after t3 because of the delay characteristic of the reset IC 2 (see FIG. 7) as described above. As shown in FIGS. 8F and 8G, the voltage rise at the power supply output terminal of the frame opening detection circuit 260 is about 40 μsec earlier than the voltage rise at the reset signal output terminal of the frame opening detection circuit 260. , The drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, and then the reset signal SG3b is input to the reset signal output terminal of the MPU 201. Therefore, when the pachinko machine 10 is powered off and the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily booted, the boot can be normally performed.

Further, as shown in FIG. 8E, when the voltage of the capacitor CD4 becomes about 5.7 volts, the voltage of the power failure signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I2 of the multiplexer MP1). As shown in FIG. 8(h), the voltage starts rising at t3 and reaches about 5.0 volts about 0.01 seconds after t3. Here, since the switch SW2 is in the conducting state (the front frame 14 is in the open state), the drain terminal D and the source terminal S of the FET3 are cut off from each other. As a result, the power failure signal SG1b is started to be output from the power failure signal output terminal of the frame opening detection circuit 260.

Then, when about 4.4 seconds elapse from t3, the timer IC1 switches the voltage of the OUT terminal from about 10.6 volts to zero volts as shown in FIG. 8(d). Then, the conduction between the drain terminal D and the source terminal S of the FET1 is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7) is cut off. Charging to CD4 is completed. Then, the discharge of the capacitor CD4 is started, so that the voltage of the capacitor CD4 starts to drop (after about 4.4 seconds have elapsed from t3) as shown in FIG. 8(e). Following this, as shown in FIG. 8(f), the voltage of the power supply output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) starts to drop (from t3 o'clock). After about 4.4 seconds). Further, as shown in FIG. 8G, the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 starts to drop (after about 4.4 seconds have elapsed from t3).

Note that when about 4.4 seconds elapse from t3, the conduction between the drain terminal D and the source terminal S of the FET2 is cut off, so that a current is supplied to the power failure signal output terminal of the frame open detection circuit 260. Not done. Therefore, as shown in FIG. 8(h), the voltage at the power interruption signal output terminal of the frame opening detection circuit 260 (power failure signal SG1b) becomes zero volts when about 4.4 seconds have elapsed from t3. Therefore, when about 4.4 seconds elapse after the front frame 14 is opened and the switch SW2 is turned on, the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 to the NMI terminal of the MPU 201 is first , Stopped.

Next, when about 9.4 seconds elapses from t3 o'clock (about 4.4 seconds elapses from t3 o'clock and further about 5.0 seconds elapses), as shown in FIG. Drops to about 5.0 volts. Then, as shown in FIG. 8F, the voltage of the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.3 volts (from t3 o'clock). After about 9.4 seconds). As shown in FIG. 8(g), the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 drops to about 4.3 volts, and then the reset IC 2 operates to zero volts. (After about 9.4 seconds have passed since t3). Therefore, when about 9.4 seconds have passed since the front frame 14 was opened and the switch SW2 was turned on, the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 to the reset terminal of the MPU 201 is the power failure signal. Next to SG1b, it is stopped. As a result, the MPU 201 is set in a state in which the arithmetic processing cannot be executed (after about 9.4 seconds have elapsed from t3).

Further, when about 9.9 seconds have passed from t3 o'clock (after about 9.4 seconds have passed from t3 o'clock, another 0.5 seconds have passed), the voltage of the capacitor CD4 is changed as shown in FIG. 8(e). It drops to about 4.7 volts. Then, as shown in FIG. 8F, the voltage at the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.0 volts (from t3). After about 9.9 seconds). Here, as described above, the lower limit of the operating voltage of the MPU 201 is about 4.0 volts. Therefore, when about 9.9 seconds have passed since the front frame 14 was opened and the switch SW2 was turned on, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 to the power terminal of the MPU 201 was finally changed to The MPU 201 is stopped and becomes inoperable. In other words, the MPU 201 is set to the inoperable state (after about 9.4 seconds from t3 o'clock) after being set to the state in which the arithmetic processing cannot be executed (about 9.9 seconds from t3 o'clock). After the passage). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

It should be noted that when about 20 seconds have elapsed from the time t3, the voltage of the capacitor CD4 becomes zero volts as shown in FIG. 8(e). Following this, the voltage at the power output terminal of the frame open detection circuit 260 (also the drive voltage) becomes zero volts (about 20 seconds before t3). Therefore, when about 20 seconds have passed from t3, the charge amount of the capacitor CD4 becomes zero.

Finally, as shown in FIG. 8A, at time t4, when the switch SW2 is turned off (the front frame 14 is closed), the TRG terminal voltage of the timer IC1 becomes about as shown in FIG. At the same time as switching from 11.3 volts to zero volts, the OUT terminal voltage of the timer IC1 switches from zero volts to about 10.6 volts (at t4). When the switch SW2 is turned off (the front frame 14 is closed) at t4, the drain terminal D and the source terminal S of the FET 3 are electrically connected. As a result, the frame open detection circuit 260 is again set to a state in which the inner frame 12 and the front frame 14 can be detected.

As described above, the frame open detection circuit 260 resets after outputting the drive voltage Vb and the power failure signal SG1b when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off. The signal SG3b is output. Therefore, when the pachinko machine 10 is powered off, when the MPU 201 is temporarily started up, it can be normally started up. In addition, the frame opening detection circuit 260 opens the inner frame 12 or the front frame 14 and turns on the switch SW1 or the switch SW2 when the power of the pachinko machine 10 is turned off, and about 4.4 times after the turning on. When the second has elapsed, first, the power failure signal SG1b is stopped. Then, the frame opening detection circuit 260 stops the reset signal SG3b when about 9.4 seconds have elapsed after the switch SW1 or the switch SW2 was turned on. Further, the frame open detection circuit 260 reduces the drive voltage Vb output to the power supply terminal of the MPU 201 to about 4.0 volts when about 9.9 seconds have elapsed after the switch SW1 or the switch SW2 was turned on. Therefore, even when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off, and the MPU 201 is temporarily started by the frame opening detection circuit 260, the MPU 201 that has started is normally operated. Can be ended.

As described above, the operation of the frame opening detection circuit 260 is the same when the inner frame 12 is opened and when the front frame 14 is opened. Therefore, the operation of the frame opening detection circuit 260 from t5 to t6, which will be described next, will be described only when the inner frame 12 is opened.

As shown in FIG. 8A, when the switch SW1 is in the conducting state (the inner frame 12 is in the open state) at time t5, the TRG terminal voltage of the timer IC1 is at time t5 as shown in FIG. 8C. Switching from zero volts to about 11.3 volts. At this time, as shown in FIG. 8D, the timer IC 1 continues to output a voltage of about 10.6 volts from the OUT terminal. This causes conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7), and charging of the capacitor CD4 (see FIG. 7) is started (see FIG. 8E). t5). When the charging of the capacitor CD4 is completed, the voltage of the capacitor CD4 becomes about 5.7 volts as shown in FIG. 8(e) (about 0.01 seconds after t5).

In addition, the voltage at the power output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I23 of the multiplexer MP3) starts rising at t5 and is about 0 from t5 as shown in FIG. 8(f). It will be about 5.0 volts after 0.01 seconds. As a result, the drive voltage Vb of about 5.0 V is started to be output from the power supply output terminal of the frame open detection circuit 260. The voltage at the reset signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I22 of the multiplexer MP2 and the input/output port 205) is about 40 μs after t5 as shown in FIG. 8(g). The voltage starts to rise (see A in FIG. 8F), and becomes about 5.0 volts about 0.01 seconds after t5. As a result, the reset signal SG3b is started to be output from the reset signal output terminal of the frame opening detection circuit 260. The voltage increase at the reset signal output terminal of the frame open detection circuit 260 is about 40 μs after t5 due to the delay characteristic of the reset IC 2 (see FIG. 7) as described above. As shown in FIGS. 8F and 8G, the voltage rise at the power supply output terminal of the frame opening detection circuit 260 is about 40 μsec earlier than the voltage rise at the reset signal output terminal of the frame opening detection circuit 260. , The drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, and then the reset signal SG3b is input to the reset signal output terminal of the MPU 201. Therefore, when the pachinko machine 10 is powered off and the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily booted, the boot can be normally performed.

Further, as shown in FIG. 8E, when the voltage of the capacitor CD4 becomes about 5.7 volts, the voltage of the power failure signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I21 of the multiplexer MP1). As shown in FIG. 8(h), the voltage starts rising at t5 and reaches about 5.0 volts about 0.01 seconds after t5. Here, since the switch SW1 is in the conducting state (the inner frame 12 is in the open state), the drain terminal D and the source terminal S of the FET3 are cut off from each other. As a result, the power failure signal SG1b is started to be output from the power failure signal output terminal of the frame opening detection circuit 260.

When the inner frame 12 is closed before the elapse of about 4.4 seconds from t5 o'clock (when the inner frame 12 is closed at t6 when about 3.0 seconds elapses from t5 o'clock), FIG. As shown, the timer IC1 continues to output the voltage of about 10.6 volts without switching the voltage of the OUT terminal to about 10.6 volts. At this time, the drain terminal D and the source terminal S of the FET1 remain electrically connected, but the switch SW1 is cut off as the inner frame 12 is closed, so that the emitter of the transistor TR1 (see FIG. 7) is closed. The voltage is not applied to the terminal e and the base terminal b, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off. As a result, the charging of the capacitor CD4 is completed (at t6). Then, since the discharge of the capacitor CD4 is started, the voltage of the capacitor CD4 starts to drop (at t6) as shown in FIG. 8D. Following this, as shown in FIG. 8F, the voltage of the power supply output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) starts to drop (at t6). .. Further, as shown in FIG. 8G, the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 starts to drop (at t6).

Note that when the inner frame 12 is closed and the switch SW1 is cut off (at t6), the discharge of the capacitor CD4 is started, but the voltage generated by this discharge is not supplied to the power interruption signal output terminal of the frame open detection circuit 260. Not supplied. As described above, when the inner frame 12 is closed, the switch SW1 is turned off, so that the drain terminal D and the source terminal S of the FET3 are electrically connected to each other and the capacitor CD4 is discharged. This is because the current does not flow in the resistor R5 but flows in the drain terminal D of the FET3. Therefore, as shown in FIG. 8(h), the voltage (power failure signal SG1b) at the power interruption signal output terminal of the frame open detection circuit 260 becomes zero volts at t6. Therefore, when the inner frame 12 is opened, and the switch SW1 is shut off by closing the inner frame 12 before about 4.4 seconds have passed from the opening, when the switch SW1 is shut off, the frame open detection circuit is opened. The power failure signal SG1b output from the power failure signal output terminal of 260 to the NMI terminal of the MPU 201 is first stopped.

Next, when about 5.0 seconds elapse from t6, the voltage of the capacitor CD4 drops to about 5.0 volts as shown in FIG. 8(e). Then, as shown in FIG. 8(f), the voltage at the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.3 volts (from t6 o'clock). After about 5.0 seconds). Further, as shown in FIG. 8(g), the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 drops to about 4.3 volts, and thereafter, the voltage of the reset IC 2 is reduced to zero volts. (About 5.0 seconds after t6). Therefore, about 5.0 seconds after the inner frame 12 is closed and the switch SW1 is shut off, the reset signal SG3b output from the reset signal output terminal of the frame opening detection circuit 260 to the reset terminal of the MPU 201 is the power failure signal. Next to SG1b, it is stopped. As a result, the MPU 201 is set in a state in which the arithmetic processing cannot be executed (after a lapse of about 5.0 seconds from t6).

Further, when about 5.5 seconds have passed since t6 (about 5.0 seconds after t6, and then about 0.5 seconds have passed), the voltage of the capacitor CD4 changes as shown in FIG. 8(e). It drops to about 4.7 volts. Then, as shown in FIG. 8F, the voltage at the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.0 volts (from t6 o'clock). After about 5.5 seconds). Here, the minimum operating voltage of MPU 201 is about 4.0 volts. Therefore, when approximately 5.5 seconds have passed after the inner frame 12 was closed and the switch SW1 was cut off, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 to the power terminal of the MPU 201 was finally stopped. Then, the MPU 201 becomes inoperable. That is, the MPU 201 is set to the inoperable state (after about 5.0 seconds from t6 o'clock) after being set to the state in which the arithmetic processing cannot be executed (about 5.5 seconds from t6 o'clock). After the passage). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

Note that when about 20 seconds have passed from t5, the voltage of the capacitor CD4 becomes zero volts as shown in FIG. 8(e). Following this, the voltage of the power supply output terminal of the frame open detection circuit 260 (also the drive voltage Vb) becomes zero volts (about 20 seconds before the time t5). Therefore, when about 20 seconds have passed from t5, the charged amount of the capacitor CD4 becomes zero.

Here, in the operation of the frame opening detection circuit 260 from t5 to t6, the capacitor CD4 is discharged even after the inner frame 12 is closed at t6. Even in this case, when the inner frame 12 is closed at t6 and the switch SW1 is cut off, the frame open detection circuit 260 causes conduction between the drain terminal D and the source terminal S of the FET3. The current generated by the discharge of CD4 does not flow through the resistor R5 but flows through the drain terminal D of the FET3. Therefore, when the inner frame 12 is closed at t6, as shown in FIG. 8(h), the voltage (power failure signal SG1b) at the power interruption signal output terminal of the frame opening detection circuit 260 can be set to zero volt.

After the power failure signal SG1b output from the power interruption signal output terminal of the frame opening detection circuit 260 is stopped, the voltage accompanying the discharge of the capacitor CD4 decreases with the passage of time, and the reset signal output terminal outputs the reset signal. The signal SG3b is stopped, and finally the drive voltage Vb output from the power supply output terminal is stopped. By this operation, even if the inner frame 12 is closed before the elapse of about 4.4 seconds from the time t5 at which the inner frame 12 is opened (the inner frame 12 is closed at t6 at about 3.0 seconds after t5). It is possible to stop the power failure signal SG1b first, then the reset signal SG3b, and finally the drive voltage Vb even if it is closed. Therefore, when the power of the pachinko machine 10 is turned off, the inner frame 12 is opened, and within about 4.4 seconds until the voltage output from the OUT terminal of the timer IC 1 is switched, the inner frame 12 is released. Even if the frame 12 is closed, the MPU 201 can be temporarily activated by the frame opening detection circuit 260, and the activated MPU 201 can be normally terminated.

After the inner frame 12 is closed at t6, the voltage of the capacitor CD4 decreases to about 4.7 volts as shown in FIG. 8(e), and the power source becomes as shown in FIG. When the drive voltage Vb output from the output terminal to the end becomes about 4.0 V and the MPU 201 ends normally, the frame open detection circuit 260 sets the state in which the inner frame 12 or the front frame 14 can be detected again. To be done.

Finally, the case where the switch SW2 is in the conductive state (the front frame 14 is in the open state) while the switch SW1 is in the conductive state (the inner frame 12 is in the open state) will be described. As shown in FIG. 8A, at time t7, the switch SW1 is in the conductive state (the inner frame 12 is in the open state), and as shown in FIG. 8B, at time t8, the switch SW2 is in the conductive state (front surface). When the frame 14 is opened, the TRG terminal voltage of the timer IC 1 switches from zero volt to about 11.3 volt at t7 as shown in FIG. 8C. At this time, as shown in FIG. 8D, the timer IC1 continues to output a voltage of about 10.6 volts from the OUT terminal until about 4.4 seconds elapse from t7. This causes conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7), and charging of the capacitor CD4 (see FIG. 7) is started (see FIG. 8E). t7). Note that this charging is completed in about 0.01 seconds after the switch SW1 becomes conductive as shown in FIG. 8(e). When the charging of the capacitor CD4 is completed, the voltage of the capacitor CD4 becomes about 5.7 volts as shown in FIG. 8(e).

Further, the voltage at the power output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I23 of the multiplexer MP3) starts rising at t7 and is about 0 from t7, as shown in FIG. 8(f). It will be about 5.0 volts after 0.01 seconds. As a result, the drive voltage Vb of about 5.0 V is started to be output from the power supply output terminal of the frame open detection circuit 260. The voltage at the reset signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I22 of the multiplexer MP2 and the input/output port 205) is about 40 μs after t7 as shown in FIG. 8(g). It starts to rise and reaches about 5.0 volts about 0.01 seconds after t7. As a result, the reset signal SG3b is started to be output from the reset signal output terminal of the frame opening detection circuit 260. The voltage increase at the reset signal output terminal of the frame open detection circuit 260 is about 40 μs after t7 because of the delay characteristic of the reset IC 2 (see FIG. 7) as described above. As shown in FIGS. 8F and 8G, the voltage rise at the power supply output terminal of the frame opening detection circuit 260 is about 40 μsec earlier than the voltage rise at the reset signal output terminal of the frame opening detection circuit 260. , The drive voltage Vb of about 5 V is supplied to the power supply terminal of the MPU 201, and then the reset signal SG3b is input to the reset signal output terminal of the MPU 201. Therefore, when the pachinko machine 10 is powered off and the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily booted, the boot can be normally performed.

Further, as shown in FIG. 8E, when the voltage of the capacitor CD4 becomes about 5.7 volts, the voltage of the power failure signal output terminal of the frame open detection circuit 260 (the output voltage to the input terminal I21 of the multiplexer MP1). As shown in FIG. 8(h), the voltage starts rising at t7 and reaches about 5.0 volts about 0.01 seconds after t7. Here, since the switch SW1 is in the conducting state (the inner frame 12 is in the open state), the drain terminal D and the source terminal S of the FET3 are cut off from each other. As a result, the power failure signal SG1b is started to be output from the power failure signal output terminal of the frame opening detection circuit 260.

Then, when about 4.4 seconds elapse from t7, as shown in FIG. 8D, the timer IC 1 switches the voltage of the OUT terminal from about 10.6 volt to zero volt. Then, the conduction between the drain terminal D and the source terminal S of the FET1 is cut off, and the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 (see FIG. 7) is cut off. Charging to CD4 is completed. Then, since the discharge of the capacitor CD4 is started, the voltage of the capacitor CD4 starts to drop (after about 4.4 seconds have elapsed from t7), as shown in FIG. 8(e). Following this, as shown in FIG. 8(f), the voltage of the power supply output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) starts to drop (from t7). After about 4.4 seconds). Further, as shown in FIG. 8G, the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 starts to drop (after about 4.4 seconds have elapsed from t7).

When about 4.4 seconds elapse from t7, the conduction between the drain terminal D and the source terminal S of the FET2 is cut off, so that the current is supplied to the power failure signal output terminal of the frame open detection circuit 260. Not done. Therefore, as shown in FIG. 8(h), the voltage at the power interruption signal output terminal of the frame open detection circuit 260 (power failure signal SG1b) becomes zero volts when approximately 4.4 seconds have elapsed from t7. Therefore, when about 4.4 seconds elapse after the inner frame 12 is opened and the switch SW1 is turned on, the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 to the NMI terminal of the MPU 201 is first , Stopped.

Next, when about 9.4 seconds elapses from t7 o'clock (about 4.4 seconds elapses from t7 o'clock and further about 5.0 seconds elapses), as shown in FIG. Drops to about 5.0 volts. Then, as shown in FIG. 8(f), the voltage of the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.3 volts (from t7 o'clock). After about 9.4 seconds). As shown in FIG. 8(g), the voltage (reset signal SG3b) at the reset signal output terminal of the frame open detection circuit 260 drops to about 4.3 volts, and then the reset IC 2 operates to zero volts. (After about 9.4 seconds from t7). Therefore, when about 9.4 seconds have passed since the inner frame 12 was opened and the switch SW1 was turned on, the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 to the reset terminal of the MPU 201 is the power failure signal. Next to SG1b, it is stopped. As a result, the MPU 201 is set in a state in which the arithmetic processing cannot be executed (after about 9.4 seconds have elapsed from t7).

Further, when about 9.9 seconds have passed from t7 o'clock (after about 9.4 seconds have passed from t7 o'clock and about 0.5 seconds have passed), the voltage of the capacitor CD4 is changed as shown in FIG. 8(e). It drops to about 4.7 volts. Then, as shown in FIG. 8F, the voltage at the power output terminal of the frame open detection circuit 260 (the maximum drive voltage Vb of about 5.0 volts) drops to about 4.0 volts (from t7). After about 9.9 seconds). Here, as described above, the lower limit of the operating voltage of the MPU 201 is about 4.0 volts. Therefore, when about 9.9 seconds have passed since the inner frame 12 was opened and the switch SW1 was turned on, the drive voltage Vb output from the power output terminal of the frame open detection circuit 260 to the power terminal of the MPU 201 was finally stopped. Then, the MPU 201 becomes inoperable. That is, the MPU 201 is set to the inoperable state (after about 9.4 seconds from t7 o'clock) after being set to the state in which the arithmetic processing cannot be executed (about 9.9 seconds from t7 o'clock). After the passage). Therefore, even when the MPU 201 is temporarily activated by the frame opening detection circuit 260 while the pachinko machine 10 is powered off, the frame opening detection circuit 260 can normally terminate the MPU 201 that has been started. it can.

It should be noted that, when about 20 seconds have passed from t7, the voltage of the capacitor CD4 becomes zero volts as shown in FIG. 8(e). Following this, the voltage of the power output terminal of the frame open detection circuit 260 (also the drive voltage Vb) becomes zero volts (about 20 seconds before t7). Therefore, when about 20 seconds have passed from t7, the charged amount of the capacitor CD4 becomes zero.

Finally, as shown in FIG. 8A, at time t9, the switch SW1 is turned off (the inner frame 12 is closed), and as shown in FIG. 8B, at time t10, the switch SW2 is turned off. When the state (front frame 14 is closed) is reached, as shown in FIG. 8C, at time t10, the TRG terminal voltage of the timer IC1 is switched from about 11.3 volts to zero volts and the OUT terminal voltage of the timer IC1 is changed. Switches from zero volts to about 10.6 volts. When the switch SW2 is turned off (the front frame 14 is closed) at t10, the drain terminal D and the source terminal S of the FET 3 are brought into conduction. As a result, the frame open detection circuit 260 is again set to a state in which the inner frame 12 and the front frame 14 can be detected.

As described above, even when the switch SW2 is in the conductive state (the front frame 14 is in the open state) when the switch SW1 is in the conductive state (the inner frame 12 is in the open state), the timer IC1 does not operate in the conductive period of the switch SW1. Of the switch SW1 or the switch SW2, regardless of the length of the switch SW2 (the length of the open period of the inner frame 12) and the length of the conductive period of the switch SW2 (the length of the open period of the front frame 14). When about 4.4 seconds elapse from the time when either the inner frame 12 or the front frame 14 is opened, the voltage of the OUT terminal is switched from about 10.6 volt to zero volt. As a result, the frame opening detection circuit 260 stops the power failure signal SG1b and starts discharging the capacitor CD4 after about 4.4 seconds have elapsed from the time when either the switch SW1 or the switch SW2 becomes conductive. .. After that, the frame opening detection circuit 260 stops the reset signal SG3b after about 9.4 seconds have elapsed from the time when either the switch SW1 or the switch SW2 becomes conductive, and the frame open detection circuit 260 selects either the switch SW1 or the switch SW2. The drive voltage Vb is stopped after about 9.9 seconds have passed from the time when one of them becomes conductive. Therefore, when the power of the pachinko machine 10 is off, the switch SW1 is in the conductive state (the inner frame 12 is in the open state), and then the switch SW2 is in the conductive state (the front frame 14 is in the open state). Even if the frame open detection circuit 260 temporarily starts up the MPU 201, the frame open detection circuit 260 can normally end the started up MPU 201.

As described above, the frame opening detection circuit 260 drives when one of the inner frame 12 or the front frame 14 and both the inner frame 12 and the front frame 14 are opened when the power of the pachinko machine 10 is off. After outputting the voltage Vb and the power failure signal SG1b, the reset signal SG3b is output. Therefore, even if the pachinko machine 10 is powered off, the MPU 201 can be temporarily started up normally. Although details will be described later, when the power of the pachinko machine 10 is off, when the MPU 201 is temporarily activated by the frame opening detection circuit 260, the pachinko machine 10 turns on the off-frame opening flag 203a. To do. When the off-inside frame opening flag 203a is turned on, the pachinko machine 10 uses the voice output device 226 and the lamp display device 227 to display the inner frame 12 or the front frame when the power of the pachinko machine 10 is turned on next time. Notify that 14 has been opened. Therefore, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off.

Further, as will be described in detail later, when the pachinko machine 10 is powered off and the MPU 201 is temporarily activated by the frame opening detection circuit 260, the pachinko machine 10 turns on the off-frame opening flag 203a. In addition, a pulse signal having a pulse width of 1 msec is output to the hall computer 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours. Therefore, by analyzing the pulse signal stored in the hall computer 262, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. You can

Further, in the frame open detection circuit 260, when the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 becomes conductive, and about 4.4 seconds after the conduction, first, the power failure signal SG1b is stopped ( If the open inner frame 12 or the open front frame 14 is closed before the switch SW1 or the switch SW2 is turned on and about 4.4 seconds have passed after the turn-on, a stop signal is issued when the switch is closed. Stop SG1b). Next, the frame opening detection circuit 260 stops the reset signal SG3b when about 9.4 seconds have passed after the switch SW1 or the switch SW2 was turned on (about 4.4 seconds passed after the switch SW1 or the switch SW2 was turned on). When the opened inner frame 12 or the opened front frame 14 is closed before, the reset signal SG3b is stopped about 5.0 seconds after the closing). Then, the frame opening detection circuit 260 reduces the drive voltage Vb output to the power supply terminal of the MPU 201 to about 4.0 volts when about 9.9 seconds have elapsed after the switch SW1 or the switch SW2 was turned on (the switch SW1 or the switch SW1 or If the opened inner frame 12 or the opened front frame 14 is closed before about 4.4 seconds have passed after the switch SW2 is turned on, the drive is performed about 5.5 seconds after the closing. The voltage Vb is reduced to about 4.0 volts). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily activated by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

In addition, even if the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is conducted, the frame open detection circuit 260 detects that the inner frame 12 or the front frame is still in operation for about 4.4 seconds. Regardless of the open period of 14, the transistor TR1 stops the output of the driving voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4, which are performed by the electric power supplied from the capacitor CD1. After the stop by the transistor TR1, the frame open detection circuit 260 outputs the drive voltage Vb and the reset signal SG3b by discharging the capacitor CD4. Therefore, the frame opening detection circuit 260, for example, when the business hours of the game hall is finished and the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1 to the frame opening detection circuit 260. That is, that is, when the DC voltage of about 11.3 volts is supplied from the capacitor CD1 to the frame open detection circuit 260, the period during which the power is supplied from the capacitor CD1 is the open period of the inner frame 12 or the front frame 14. Regardless, it can be held for about 4.4 seconds. Therefore, the frame opening detection circuit 260 can suppress the consumption of the electric power charged in the capacitor CD1 and detect the opening of the inner frame 12 or the front frame 14 multiple times.

Even if the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the frame open detection circuit 260 is opened before about 4.4 seconds elapses from the time when the switch SW1 or the switch SW2 is turned on. When the frame 12 or the opened front frame 14 is closed, the switch SW1 or the switch SW2 is cut off, and the output of the drive voltage Vb, the output of the reset signal SG3b, and the power failure signal SG1b performed by the power supplied from the capacitor CD1. And the charging of the capacitor CD4 are stopped. After the inner frame 12 and the front frame 14 are closed, the drive voltage Vb and the reset signal SG3 are output by discharging the capacitor CD4.

In this way, when the charging of the capacitor CD4 is completed, after that, the driving voltage Vb and the reset signal SG3b can be output by discharging the capacitor CD4, so that the opening period of the inner frame 12 or the front frame 14 is about. If it is within 4.4 seconds, the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4, which are performed by the power supply from the capacitor CD1, are further shortened. Can be kept at. Therefore, the power consumption of the capacitor CD1 due to the opening of the inner frame 12 or the front frame 14 can be further suppressed.

Here, since the capacitance of the capacitor CD1 is 1F and the voltage applied to the capacitor CD1 is about 11.3 volts, the charge accumulated in the capacitor CD1 is the product of the capacitance of the capacitor CD1 and the applied voltage of the capacitor CD1. To about 11.3 C (coulomb). The electric charge of about 11.3C stored in the capacitor CD1 is about during each period of the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b and the charging of the capacitor CD4 which are performed by the power supply from the capacitor CD1. In the case of 4.4 seconds, the number of times power is supplied corresponds to about 11 times. Therefore, for example, when the power supply to the pachinko machine 10 is cut off after the business hours of the game arcade and the DC voltage of 12 V is not supplied from the DC power supply DC1, the inner frame 12 is opened (the switch SW1 is turned on). Even when the front frame 14 is opened (conduction) or the front frame 14 is opened (conduction of the switch SW2) for a plurality of times, the frame open detection circuit 260 opens the inner frame 12 or opens the front frame 14 (conduction of the switch SW1 or It is possible to reliably detect that the switch SW2 is turned on up to about 11 times each time, temporarily start the MPU 201 normally, and turn on the off-inside frame open flag 203a. At this time, when the inner frame 12 is opened or the front frame 14 is opened about 11 times, the electric power stored in the capacitor CD1 decreases, and the driving voltage Vb decreases, the reset signal SG3b decreases, and the power failure signal SG1b decreases. A decrease and a decrease in the charge amount of the capacitor CD4 occur. However, when the inner frame 12 or the front frame 14 is opened, the voltage of the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 exceeds about 4.3 V and the frame open detection circuit 260 is released. If the voltage of the drive voltage Vb output from the power output terminal of the power supply and the voltage of the power failure signal SG1b output from the power failure signal output terminal of the frame open detection circuit 260 exceeds about 4.0 volts, the power of the pachinko machine 10 is Even if it is turned off, the MPU 201 can be temporarily started up normally and the off-inside frame open flag 203a can be turned on. Furthermore, a pulse signal having a pulse width of 1 msec can be output to the hall computer 262.

In the frame open detection circuit 260, the capacities of the capacitors CD1 and CD4 are set to 1F, respectively. However, the capacitor CD1 is displayed when the power of the pachinko machine 10 is turned off and the inner frame 12 or the front frame 14 is opened. Since it is a capacitor that serves as a power source for operating the open circuit detection circuit 260, the capacitance value may be larger than that of the capacitor CD4. By making the capacitance value of the capacitor CD1 larger than 1F, opening of the inner frame 12 or the front frame 14 while the power of the pachinko machine 10 is turned off can be detected more than 11 times.

In the frame opening detection circuit 260, when the inner frame 12 and the front frame 14 are closed (when the switches SW1 and SW2 are cut off), the OUT terminal voltage of the timer IC1 is about 10.6 volts. Therefore, the drain opening D and the source terminal S of the FET1 and the drain terminal D and the source terminal S of the FET2 of the frame opening detection circuit 260 are in a conductive state. Since the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 3 are electrically connected. However, at this time, since the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off, the drain terminal D and the source terminal S of the FET1 and the drain terminal D and the source terminal of the FET2 are cut off. The current from the capacitor CD1 does not flow between the terminals S and S3 and between the drain terminal D and the source terminal S of the FET3. Therefore, when the inner frame 12 and the front frame 14 are closed, the electric power charged in the capacitor CD1 is generated between the drain terminal D and the source terminal S of the FET1 and between the drain terminal D and the source terminal S of the FET2. It does not flow between the terminals and between the drain terminal D and the source terminal S of the FET 3 and are not consumed.

Further, the power consumption of the capacitor CD1 by the frame opening detection circuit 260 when the pachinko machine 10 is powered off and the inner frame 12 and the front frame 14 are closed is determined by the standby power of the timer IC1 and the power consumption of the NOTIC3. It is a degree. Moreover, since a voltage is only applied to each gate terminal G of the FET1 to FET3, the power consumed by the FET1 to FET3 is very small. Therefore, the consumption of these powers does not cause a significant reduction in the amount of charge of the capacitor CD1.

Next, the display content of the third symbol display device 81 will be described with reference to FIG. FIG. 9 is a drawing for explaining the display screen of the third symbol display device 81, and FIG. 9A is a diagram schematically showing the area division setting and the effective line setting of the display screen, FIG. 9B is a diagram exemplifying an actual display screen.

The third symbol is composed of ten types of main symbols numbered from "0" to "9" and one type of petal-shaped sub-symbol formed smaller than the main symbol. Each main symbol is formed by attaching numbers from "0" to "9" on the rear symbol made of a wooden box, of which the main symbols with odd numbers (1, 3, 5, 7, 9) are , A large number is added to almost the front of the wooden box. On the other hand, the main designs with even numbers (0, 2, 4, 6, 8) are protected almost entirely on the front of the wooden box, and additional designs imitating characters such as furoshiki and helmet are added. An even number is small in green on the lower right side of the attached design, and is added so as to be displayed on the front side of the attached design.

Further, in the pachinko machine 10 of the present embodiment, when the lottery result by the main controller 110 is a big hit, a variable display in which the same main symbols are arranged is displayed, and a big hit occurs after the fluctuation display ends. Is configured to. When transitioning to a high probability state (probability change state) after the end of a big hit, a variable display in which main symbols (corresponding to “high probability symbols”) to which odd numbers are added are displayed. On the other hand, when transitioning to the low-probability state after the end of the big hit, a variable display in which main symbols (corresponding to “low-probability symbols”) to which even numbers are added are arranged is performed. Here, the high-probability state refers to a state in which the subsequent jackpot probability increases as an added value after the jackpot ends, that is, when the probability changes (probability change). The normal state (low-probability state) refers to a time when there is no probability change, and a state where the jackpot probability is normal, that is, a state where the jackpot probability is lower than during the probability change.

As shown in FIG. 9(a), the display screen of the third symbol display device 81 is roughly divided into upper and lower parts, and the lower 2/3 is the main display area Dm in which the third symbol is variably displayed, other than that. The upper third ⅓ is the sub display area Ds for displaying the notice effect and the character.

In the main display area Dm, three symbol columns Z1, Z2, Z3 of left, middle and right are displayed. In each of the symbol columns Z1 to Z3, the above-mentioned third symbol is displayed in a prescribed order. That is, in each of the symbol columns Z1 to Z3, main symbols are arranged in ascending or descending order of numbers, and one sub symbol is arranged between each main symbol. Therefore, a total of 20 third symbols of 10 main symbols and 10 sub symbols are set in each symbol column, and scrolls from top to bottom with periodicity for each symbol column Z1 to Z3. Variable display is performed. In particular, in the left symbol column Z1, the numbers of the main symbols are arranged in descending order, and in the middle symbol column Z2 and the right symbol column Z3, the numbers of the main symbols are arranged in ascending order.

Further, in the main display area Dm, the third symbols are displayed in the upper, middle, and lower three rows for each of the symbol columns Z1 to Z3. Therefore, the third symbol display device 81 displays a total of nine third symbols in three rows and three columns. Five effective lines, that is, an upper line L1, a middle line L2, a lower line L3, a rightward rising line L4, and a leftward rising line L5 are set in the main display area Dm. Then, in each game, the variable display is stopped in the order of the left symbol column Z1→the right symbol column Z3→the middle symbol column Z2, and at the time of stopping, a combination of the jackpot symbols on any of the activated lines (in the present embodiment, A combination of the same main symbols) will be displayed as a jackpot and a jackpot video will be displayed.

The sub display area Ds is provided horizontally longer than the main display area Dm, and is further divided into three notice areas Ds1 to Ds3 in the left-right direction. Here, the notice areas Ds1 and Ds3 on the left and right are normally covered with a double-opening opaque door that is electrically opened and closed by a solenoid (not shown), and sometimes the solenoid is excited to bring the door to the front side. It is a display area that can be viewed by the player when opened. The notice area Ds2 at the center is a display area which is always visible without being covered by the door.

As shown in FIG. 9B, in the actual display screen, a total of nine main symbols and sub symbols of the third symbol are displayed in the main display area Dm. In the sub display area Ds, the left and right doors are closed, and the left and right notice areas Ds1 and Ds3 are covered and the display screen is invisible. When one or both of the left and right doors are opened in the middle of the variable display, a moving image is displayed in the left and right notice areas Ds1 and Ds3, and it is easier for the player to make a transition to a big hit than usual. It is suggested. In the central notice area Ds2, usually, a predetermined character (in this embodiment, a boy with a hachimaki) performs a predetermined motion, sometimes performs a special motion different from the predetermined motion, or another character A notice production is performed by appearing. The display screen of the third symbol display device 81 is divided into upper and lower display areas Dm and Ds in principle, but the third symbol and characters are displayed in a larger size across the respective display areas Dm and Ds. Display effect can be performed.

Next, with reference to FIG. 10, a counter and the like provided in the RAM 203 of the main controller 110 will be described. These counters and the like are used in the MPU 201 of the main control device 110 in order to perform jackpot lottery, setting of display of the first symbol display device 37, lottery of display result of the second symbol display device 82, and the like.

To set the jackpot lottery and the display of the first symbol display device 37, the first random number counter C1 used for the jackpot lottery, the first hit type symbol counter C2 used for the jackpot symbol selection, and the stop pattern selection counter C3, a first initial value random number counter CINI1 used for setting an initial value of the first random number counter C1, and fluctuation type counters CS1, CS2, CS3 used for selecting a fluctuation pattern are used. The second random number counter C4 is used for the lottery of the second symbol display device 82, and the second initial value random number counter CINI2 is used for the initial value setting of the second random number counter C4. Each of these counters is a loop counter in which 1 is added to the previous value each time it is updated, and after reaching the maximum value, it returns to 0.

Each counter is updated at an interval of 4 ms which is an execution interval of the main process (see FIG. 12) or at an interval of 2 ms which is an execution interval of the timer interrupt process (see FIG. 15), and the updated value is a predetermined area of the RAM 203. It is appropriately stored in the counter buffer set to. The RAM 203 is provided with a holding ball storage area consisting of one execution area and four holding areas (holding first to fourth areas), and each of these areas is provided with a first ball entrance 64. Values of the first random number counter C1, the first hit type counter C2, and the stop pattern selection counter C3 are stored in accordance with the winning timing of the ball.

Each counter will be described in detail. The first random number counter C1 is configured to be sequentially incremented by 1 in the range of 0 to 738, for example, and after reaching the maximum value (that is, 738), returns to 0. In particular, when the first random number counter C1 makes one round, the value of the first initial value random number counter CINI1 at that time is read as the initial value of the first random number counter C1. Further, the first initial value random number counter CINI1 is configured as a loop counter that is updated within the same range as the first random number counter C1 (value=0 to 738), and each time the timer interrupt process (see FIG. 15) is executed. It is updated once and is repeatedly updated within the remaining time of the main process (see FIG. 12). The value of the first random number counter C1 is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the reserved ball is stored in the RAM 203 at the timing when the ball wins the first ball entrance 64. Stored in the area. There are two types of random number values for jackpots, one for low probability and one for high probability. The number of random number values for jackpot in low probability is 2, and the value is "373,727". The number of random numbers that are a big hit at high probability is 14, and the value is “59,109,163,211,263,317,367,421,479,523,631,683,733”.

The first hit type counter C2 determines the display mode of the first symbol display device 37 at the time of a big hit, and in the present embodiment, 1 is sequentially added within the range of 0 to 4, and the maximum value ( In other words, it is configured to return to 0 after reaching 4). The value of the first hit type counter C2 is updated, for example, regularly (in this embodiment, once for each timer interrupt process), and the reserved ball is stored in the RAM 203 at the timing when the ball wins the first ball entrance 64. Stored in the area. In addition, the value of the random number which becomes a high probability state after the big hit is "1, 2, 3", and the value of the random number which becomes a low probability state after the big hit is "0, 4", and two kinds of hit types are determined. It Therefore, the display mode corresponding to the stop symbol displayed on the first symbol display device 37 is a display mode corresponding to two types of jackpots of a high-probability state and a low-probability state, and one type of display mode corresponding to the deviation. Any one of the three display modes in total is selected.

The stop pattern selection counter C3 is configured to be incremented by 1 in the range of 0 to 238, for example, and return to 0 after reaching the maximum value (that is, 238). In the present embodiment, the stop pattern selection counter C3 selects the effect pattern displayed on the third symbol display device 81, and after the reach occurs, the final stop symbol is shifted by one before and after the reach symbol. A "rear out-of-front-reach" (for example, a range of 0 to 8) that stops, and a "reach other than out-of-front-rear" (for example, a range of 9 to 38) that stops after the last stop symbol occurs other than before and after the reach symbol. , Three stop (effect) patterns of "completely disengaged" (for example, a range of 39 to 238) in which reach is not generated are selected. The value of the stop pattern selection counter C3 is updated, for example, periodically (in this embodiment, once for each timer interrupt process), and the reserved ball storage area of the RAM 203 at the timing when the ball wins the first ball entrance 64. Stored in.

Further, the stop pattern selection counter C3 is provided with a plurality of tables having different ranges of random number values for which stop patterns are selected. This depends on whether the current state of the pachinko machine 10 is a high-probability state or a low-probability state, in which area of the reserved ball storage area each random number value is stored (that is, the number of reserved pieces), and the like. This is for changing the selection ratio of the stop pattern.

For example, in the high-probability state, a large table is selected with a range of random number values of 10 to 238 corresponding to the stop pattern of “complete deviation” so that the reach effect is not unnecessarily selected because a jackpot is likely to occur. It is easy to select "Completely missed". In this table, the "front-rear outreach" is narrowed to 0 to 5, and the "reach other than front-rear outreach" is also narrowed to 6 to 9, which makes it difficult to select "rear-rear outreach" or "reach other than front-rear-reach". Further, if each random number value is not stored in the reserved ball storage area in the low probability state, the disturbance corresponding to the "completely missed" stop pattern in order to secure the time for the ball to enter the first entrance 64. A table with a narrow range of numerical values of 51 to 238 is selected, and it becomes difficult to select “complete deviation”. In this table, the range of the random number value corresponding to the stop pattern of "reach other than out of front/back" is widened to 9 to 50, and "reach other than out of front/rear" is easily selected. Therefore, in the low probability state, it is possible to secure the time for the ball to enter the first ball entrance 64, so that the variable display by the third symbol display device 81 can be easily continued.

Of the two fluctuation type counters CS1 and CS2, one of the fluctuation type counters CS1 is sequentially incremented by 1 in the range of 0 to 198, for example, and reaches a maximum value (that is, 198) and then returns to 0. However, the other variation type counter CS2 is configured to be incremented by 1 in the range of, for example, 0 to 240, and returns to 0 after reaching the maximum value (that is, 240). In the following description, CS1 is also referred to as a "first variation type counter" and CS2 is also referred to as a "second variation type counter".

The first variation type counter CS1 determines a rough display mode such as so-called normal reach, super reach, and premium reach. Specifically, the determination of the display mode is determination of the variation time of the symbol variation. Further, the second variation type counter CS2 determines the variation time (in other words, the variation symbol number) until the final stop symbol (in the present embodiment, the medium symbol) is stopped after the reach is generated. Based on the variation time determined by the variation type counters CS1, CS2, the display control device 114 determines the reach type and the detailed symbol variation mode of the third symbol displayed on the third display device 81. Therefore, by combining these fluctuation type counters CS1 and CS2, it is possible to easily realize a variety of fluctuation patterns. Further, it is also possible to determine the symbol variation mode only by the first variation type counter CS1 or similarly determine the symbol variation aspect by the combination of the first variation type counter CS1 and the stopped symbol. The values of the fluctuation type counters CS1 and CS2 are updated once every time a main process (see FIG. 12) described later is executed, and are repeatedly updated even within the remaining time in the main process.

For example, the value of the fluctuation type counter CS3 is incremented by 1 in the range of 0 to 162, and returns to 0 after reaching the maximum value (that is, 162). In the following description, CS3 is also referred to as a “third fluctuation type counter”. The third symbol display device 81 of the present embodiment is for performing a decorative effect according to the display mode of the first symbol display device 37, and in addition to the variation of the symbol, sliding the varying symbol or A notice effect is given such as passing a notice character for notifying the occurrence of the reach effect. The effect pattern of the notice effect is selected by the variation type counter CS3. Specifically, a production pattern is selected in which the time required for the notice production is added to the variation time, on the contrary, the variation time is subtracted in order to reduce the variation display time, and the variation time is not added or subtracted. .. As with the stop pattern selection counter C3, the variation type counter CS3 is provided with a plurality of tables having different ranges of random number values for which the effect patterns are selected, and whether the current state of the pachinko machine 10 is the high probability state. The selection ratio of each effect pattern is configured to be different depending on the low probability state, which area of the reserved ball storage area each random value is stored, and the like.

As described above, the variation type counters CS1 and CS2 determine the variation time of the symbol variation, and the variation type counter CS3 determines the time to be added to and subtracted from the variation time. Therefore, the final change time until the final stop symbol stops is determined by the change type counters CS1, CS2, CS3.

The second random number counter C4 is configured as a loop counter that is incremented by 1 in the range of 0 to 250, for example, and returns to 0 after reaching the maximum value (that is, 250). In the present embodiment, the value of the second random number counter C4 is updated, for example, periodically for each timer interrupt process, and it is determined that the ball has passed the second entrance (through gate) 67 on either the left or the right. It is acquired when it is detected. The number of random number values to be won is 149, and the range is “5 to 153”. The second initial value random number counter CINI2 is configured as a loop counter that is updated in the same range as the second random number counter C4 (value=0 to 250), and is once for each timer interrupt process (see FIG. 15). It is updated and is repeatedly updated within the remaining time of the main process (see FIG. 12).

Next, each control process executed by the MPU 201 in the main controller 110 will be described with reference to the flowcharts of FIGS. 11 to 17. The process of the MPU 201 is roughly classified into a startup process that is started when the power is turned on, a main process that is executed after the startup process, and a regular process (in this embodiment, a cycle of 2 msec). There are a timer interrupt process and an NMI interrupt process activated by the input of the power failure signal SG1 to the NMI terminal. For convenience of explanation, first, the timer interrupt process and the NMI interrupt process will be described, and then the startup process. The main processing will be described.

FIG. 15 is a flowchart showing the timer interrupt process. The timer interrupt process is executed by the MPU 201 of the main control device 110, for example, every 2 msec. In the timer interrupt process, first, a process of reading various winning switches is executed (S501). That is, the states of various switches connected to the main controller 110 are read, the states of the switches are determined, and the detection information (winning detection information) is stored.

Next, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S502). Specifically, the first initial value random number counter CINI1 is incremented by 1, and is cleared to 0 when the counter value reaches the maximum value (738 in this embodiment). Then, the updated value of the first initial value random number counter CINI1 is stored in the corresponding buffer area of the RAM 203. Similarly, the second initial value random number counter CINI2 is incremented by 1, and when the counter value reaches the maximum value (250 in the present embodiment), it is cleared to 0 and the second initial value random number counter CINI2 is updated. The value is stored in the corresponding buffer area of the RAM 203.

Further, the first per random number counter C1, the first per type counter C2, the stop pattern selection counter C3, and the second per random number counter C4 are updated (S503). Specifically, each of the first per random number counter C1, the first per type counter C2, the stop pattern selection counter C3, and the second per random number counter C4 is incremented by 1, and the counter values thereof reach the maximum value (in the present embodiment). Then, when each reaches 738, 4, 238, 250), it is cleared to 0. Then, the updated values of the counters C1 to C4 are stored in the corresponding buffer areas of the RAM 203.

After that, the start winning process (see FIG. 16) associated with the winning in the first ball entrance 64 is executed (S504), the firing control process is executed (S505), and the timer interrupt process is ended. The firing control process detects that the player is touching the operation handle 51 with the touch sensor 51a, and turns on the firing of the ball on condition that the stop switch 51b for stopping the firing is not operated. This is a process for determining ON/OFF. The main controller 110 instructs the launch controller 112 to launch a sphere when the launch of the sphere is on.

Here, with reference to the flowchart of FIG. 16, the start winning process executed in the process of S504 will be described. FIG. 16 is a flowchart showing a start winning process (S504) executed in the timer interrupt process (see FIG. 15).

When this start winning process is executed, it is first determined whether or not the ball has won the first ball entrance 64 (starting prize) (S601). When it is determined that the ball has won the first ball entrance 64 (S601: Yes), whether or not the number N of operation-holding balls of the first symbol display device 37 is less than the upper limit value (4 in the present embodiment). It is determined (S602). If there is a winning in the first ball entrance 64 and the number N of operation-holding balls is <4 (S602: Yes), the number N of operation-holding balls is incremented by 1 (S603), and further updated in step S503. The respective values of the first hit random number counter C1, the first hit type counter C2, and the stop pattern selection counter C3 are stored in the first area of the empty hold areas of the hold ball storage area of the RAM 203 (S604). On the other hand, whether or not there is a prize in the first ball entrance 64 (S601: No), or even if there is a prize in the first ball entrance 64 but the number N of operation-holding balls is not N<4 (S602: No) , S603 and S604 are skipped, the start winning process is ended, and the process returns to the timer interrupt process.

FIG. 17 is a flowchart showing the NMI interrupt processing. In the NMI interrupt processing, the power of the pachinko machine 10 is turned on, and the power of the pachinko machine 10 is cut off due to the occurrence of a power failure while the power is on, and the power failure signal output from the power failure monitoring circuit 252. In addition to the case where SG1a falls from 5 V to zero V, the power of the pachinko machine 10 is turned off. While the power is off, the inner frame 12 or the front frame 14 is opened, and the frame open detection circuit 260 causes This is a process executed by the MPU 201 of the main controller 110 when the MPU 201 is started up and the power failure signal SG1b output from the frame opening detection circuit 260 falls from 5 volts to zero volts. When the MPU 201 detects the fall of the power failure signal SG1a or the fall of the power failure signal SG1b, it interrupts the control being executed and starts the NMI interrupt processing, and sets the power failure occurrence information as the power failure occurrence information. Is stored in the RAM 203 (S701), and the NMI interrupt processing ends.

It should be noted that the above NMI interrupt processing is similarly executed in the payout launch control device 111 when the power of the pachinko machine 10 is turned on, and the power failure occurrence information is stored in the RAM 213 by the NMI interrupt processing. It That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like while the power of the pachinko machine 10 is turned on, the power failure signal SG1a (falling) is output from the power failure monitoring circuit 252 in the payout emission control device 111. Is output to the NMI terminal of the MPU 211, and the MPU 211 interrupts the control being executed and starts the NMI interrupt processing.

Next, with reference to FIG. 11, a startup process when the main controller 110 is powered on will be described. FIG. 11 is a flowchart showing a startup process executed by the MPU 201 in the main controller 110. This start-up process is started by a reset when the power is turned on, and when the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened, and the frame open detection circuit 260 The drive voltage Vb and the reset signal SG3b are output, the drive voltage Vb enables the MPU 201 to operate, and then the reset signal SG3b activates the MPU 201 when it can execute the arithmetic processing. In the start-up process, first, an initial setting process accompanying power-on is executed (S101). Specifically, the stack pointer is set to a predetermined value, and the sub-side control devices (peripheral control devices such as the voice lamp control device 113 and the payout control device 111) are activated. In order to wait, a wait process (1 second in this embodiment) is executed. Then, access to the RAM 203 is permitted (S103). Due to this weight process, the main control unit 110 shifts to the main process after the payout control unit 111, the voice lamp control unit 113, and the display control unit 114 shift to the main process. Therefore, the payout control device 111, the voice lamp control device 113, and the display control device 114 can reliably receive the command transmitted from the main control device 110 (the payout control device 111, the voice lamp control device 113, and the display control. It is possible to prevent the device 114 from erroneously receiving a command from the main control device 110).

After that, it is determined whether or not the RAM erase switch 122 (see FIG. 3) provided in the power supply device 115 is turned on (S104), and if it is turned on (S104: Yes), the process proceeds to S115. On the other hand, if the RAM erase switch 122 is not turned on (S104: No), it is further determined whether or not the power-off occurrence information is stored in the RAM 203 (S105), and if it is not stored (S105: No). Since there is a possibility that the previous process at the time of power-off was not completed normally, the process proceeds to S115 in this case as well.

If the power failure occurrence information is stored in the RAM 203 (S105: Yes), the RAM determination value is calculated (S106), and the calculated RAM determination value is not normal (S107: No), that is, the calculated RAM. If the determination value does not match the RAM determination value saved when the power is shut off, the backed up data has been destroyed, and in such a case also the process proceeds to S115. Note that the RAM determination value is, for example, a checksum value at the work area address of the RAM 203, as will be described later in the process of S223 of FIG. Instead of this RAM judgment value, the validity of the backup may be judged by whether or not the keyword written in a predetermined area of the RAM 203 is correctly stored. The pachinko machine 10 is determined to be No in the process of S107 because the RAM determination value is always abnormal when the pachinko machine 10 is shipped from the production factory and the power is first turned on. Also in this case, the process proceeds to S115.

In the process of S115, a payout initialization command is transmitted to initialize the payout control device 111, which is a sub-side control device (peripheral control device) (S115). Upon receipt of this payout initialization command, the payout control device 111 clears areas (work areas) other than the stack area of the RAM 213, sets initial values, and enters a state in which game ball payout control can be started. After transmitting the payout initialization command, main controller 110 executes initialization processing (S116, S117) of RAM 203.

As described above, in the pachinko machine 10, when the RAM data is initialized when the power is turned on, for example, at the start of business at the game arcade, the power is turned on while pressing the RAM erase switch 122. Therefore, if the RAM erase switch 122 is pressed during the start-up process, the RAM initialization process (S116, S117) is executed. In addition, the initialization processing (S116, S117) of the RAM 203 is executed in the same manner when the power-off occurrence information is not set or when a backup abnormality is confirmed by the RAM determination value (checksum value or the like). .. In the RAM initialization processing (S116, S117), the used area of the RAM 203 is cleared to 0, the off-inside frame open flag 203a is turned off (S116), and then the initial value of the RAM 203 is set (S117). After the initialization processing of the RAM 203 is executed, the process proceeds to S110.

On the other hand, if the RAM erase switch 122 is not turned on (S104: No), the information on the occurrence of power failure is stored (S105: Yes), and if the RAM determination value (checksum value or the like) is normal ( (S107: Yes), the power-off occurrence information is cleared while the data backed up in the RAM 203 is held (S108), a payout return command is sent to the payout control device 111 (S109), and the process proceeds to S110. ..

In the process of S110, the voltage (reset signal SG3b) output from the frame open detection circuit 260 to the input/output port 205 is read (S110). Then, it is determined whether or not the output (reset signal SG3b) from the frame opening detection circuit 260 to the input/output port is high (S111). If the output from the frame open detection circuit 260 to the input/output port is high (S111: Yes), the off-in-frame open flag 203a is turned on (S112). On the other hand, if the output from the frame open detection circuit 260 to the input/output port is not high (S111: No), the process of S112 is skipped. Whether the output from the frame opening detection circuit 260 to the input/output port (reset signal SG3b) is high or not depends on whether the voltage output from the frame opening detection circuit 260 to the input/output port exceeds about 4.3 volts. It is determined by whether or not there is.

Here, when the output from the frame opening detection circuit 260 to the input/output port is determined to be high (S111: Yes), the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off. In addition to the case where the switch SW1 or the switch SW2 is turned on, the drive voltage Vb, the power failure signal SG1b and the reset signal SG3b are output from the frame opening detection circuit 260 and the MPU 201 is temporarily turned on, two other patterns are considered. To be The first pattern is when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off, and the power of the pachinko machine 10 is turned on within about 9.4 seconds from the opening, that is, the pachinko machine. When the power of 10 is off, the inner frame 12 or the front frame 14 is opened, and the frame open detection circuit 260 outputs the drive voltage Vb, the power failure signal SG1b, and the reset signal SG3b. This is the case when the power is turned on. The second pattern is a case where the power of the pachinko machine 10 is turned on, the inner frame 12 or the front frame 14 is opened, and the frame open detection circuit 260 outputs the reset signal SG3b before the processing of S110. Even when the pattern corresponds to the first pattern or the second pattern, there is no problem even if the off-inside frame open flag 203a is turned on (S112). In order to correspond to the first pattern or the second pattern, it is indispensable that the power of the pachinko machine 10 is turned on, and the first pattern and the second pattern are clerk before the business hours of the game hall This is because it is performed by. That is, when the first pattern or the second pattern is performed by the store clerk, at least the store clerk opens the inner frame 12 or the front frame 14 by himself when the pachinko machine 10 is powered off, It is recognized that the pachinko machine 10 has been turned on by itself within about 9.4 seconds after the opening (first pattern), or the pachinko machine 10 is turned on itself and immediately after that (the process of S110). This is because it recognizes that the inner frame 12 or the front frame 14 is opened by itself (second pattern). That is, even if the off-inside-frame opening flag 203a is turned on, the clerk opens the inner frame 12 or the front frame 14 after recognizing that the off-inside frame opening flag 203a is turned on. is there. Further, it is because the clerk can perform an operation to turn off the off-inside frame open flag 203a again. Therefore, even if the output from the frame open detection circuit 260 to the input/output port is determined to be high in the above two patterns (S111: Yes), there is no problem. That is, the above two patterns cannot occur in normal use of the pachinko machine 10, and therefore, there is no problem even if they are not considered.

As described above, while the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 becomes conductive, and the frame open detection circuit 260 outputs the drive voltage Vb, the power failure signal SG1b, and the reset. In addition to the case where the signal SG3b is output and the MPU 201 is temporarily started up, the output from the frame open detection circuit 260 to the input/output port is also determined to be high in the above two patterns (S111: Yes). ), the off-inside frame open flag 203a is turned on (S112).

When it is determined No in S111 or when the process of S112 is executed, a payout return command at power recovery for returning the sub-side control device (peripheral control device) to the game state when the drive power is cut off Is transmitted (S113), and the process proceeds to S114. When the payout control device 111 receives this payout return command, the payout control device 111 is ready to start the payout control of the game balls while holding the data stored in the RAM 213. In the process of S114, the interrupt is permitted, and the process proceeds to the main process described later.

As described above, the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is turned off, and the drive voltage Vb, the power failure signal SG1b and the reset signal SG3b are output from the frame open detection circuit 260. When the MPU 201 is temporarily started up, the output from the frame opening detection circuit 260 to the input/output port 205 becomes high (S111: Yes), and the off frame opening flag 203a is turned on (S112). ..

The processes of S110 to S112 are executed immediately after the process of S109 is completed or immediately after the process of S117 is completed. That is, the processes of S110 to S112 are executed immediately after the various settings of the MPU 201 are completed. Therefore, if the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off, the opening can be immediately detected by the processing of S110 to S112.

Next, with reference to FIG. 12, a main process executed after the above-described startup process will be described. FIG. 12 is a flowchart showing a main process executed by the MPU 201 in the main controller 110. In this main processing, the main processing of the game is executed. As an outline thereof, each process of S201 to S212 is executed as a regular process of 4 msec cycle, and each process of S215 to S220 is executed in the remaining time.

In the main process, first, output data such as a command updated in the previous process is transmitted to each sub-side control device (peripheral control device) (S201). Specifically, the presence/absence of winning detection information detected in the switch reading process of S501 is determined, and if there is winning detection information, a prize ball command corresponding to the number of acquired balls is transmitted to the payout control device 111. Further, by this external output processing, the variable pattern command, the stop symbol command, the stop command, the effect time addition command and the like necessary for the variable display of the third symbol by the third symbol display device 81 are transmitted to the voice lamp control device 113. Furthermore, when a ball is to be launched, a ball launch signal is transmitted to the launch control device 112.

Next, the respective values of the fluctuation type counters CS1, CS2, CS3 are updated (S202). Specifically, the fluctuation type counters CS1, CS2, CS3 are incremented by 1, and when the counter values reach the maximum values (198, 240, 162 in the present embodiment), they are cleared to 0 respectively. Then, the updated values of the fluctuation type counters CS1, CS2, CS3 are stored in the corresponding buffer area of the RAM 203.

When the variation type counters CS1, CS2, CS3 are updated, the prize ball count signal and the payout abnormality signal received from the payout control device 111 are read (S203). After that, it is determined whether the off-inside frame open flag 203a is on (S204). If the off-frame open flag 203a is on (S204: Yes), the inner frame 12 or the front frame 14 is open while the power of the pachinko machine 10 is off, or the two patterns described above are applicable. An off-inside frame open command is transmitted to the control device 113 (S205). When the voice lamp control device 113 receives the OFF-time frame open command, it controls the voice output device 226 and the lamp display device 227 to start notification that the inner frame 12 or the front frame 14 has been opened. Then, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 (S206). The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours. In addition, when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off and the MPU 201 is temporarily started up, power is not supplied to the audio lamp control device 113. Even if the OFF-in-frame opening command is transmitted to the audio lamp control device 113, the audio output device 226 and the lamp display device 227 do not give notification. Therefore, even if the inner frame 12 or the front frame 14 is opened by a fraudulent person while the power of the pachinko machine 10 is turned off, the pachinko machine 10 sets the off middle frame open flag 203a without being recognized by the fraudster. Can be used to store the opening of the inner frame 12 or the front frame 14 (without the notification by the audio output device 226 and the lamp display device 227, the off-in-frame open flag 203a is used to open the inner frame 12 or the front frame). Only open storage of frame 14 can be done).

On the other hand, if the OFF inside frame opening flag 203a is OFF (S204: No), it is determined whether the ON inside frame opening flag 203b is ON (S207). If the on-in-frame opening flag 203b is on (S207: Yes), the on-in-frame opening command is transmitted to the voice lamp control device 113 (S208). When the voice lamp control device 113 receives the on-frame opening command, it controls the voice output device 226 and the lamp display device 227 to start the notification that the inner frame 12 or the front frame 14 has been opened. On the other hand, if the on-inside frame opening flag 203b is off (S207: No), an on-inside frame closing command is transmitted to the voice lamp control device 113 (S209). When the voice lamp control device 113 receives the on-frame closing command, the voice lamp control device 113 ends the notification performed by the voice output device 226 and the lamp display device 227. When the on-frame opening flag 203b is on (S207: Yes), a pulse signal having a pulse width of about 1 msec may be output to the hall computer 262 after the process of S208. In this case, since the output pulse signal is stored in the hall computer 262 that continues to operate for 24 hours, the hall computer 262 also specifies the pachinko machine 10 in which the inner frame 12 or the front frame 14 has been opened. be able to.

After the processing of S206, S208 or S209 is completed, the processing for displaying by the first symbol display device 37 and the variation processing for setting the variation pattern of the third symbol by the third symbol display device 81 and the like are executed (S210). The details of the fluctuation process will be described later with reference to FIG.

After the end of the variation process, a large opening opening/closing process for opening or closing the specific winning opening (large opening) 65a of the variable winning device 65 in the case of a big hit state is executed (S211). That is, the specific winning opening 65a is opened for each round of the jackpot state, and it is determined whether the maximum opening time of the specific winning opening 65a has passed or whether a specified number of balls have been won in the specific winning opening 65a. Then, if any of these conditions is established, the specific winning opening 65a is closed. The opening and closing of the specific winning opening 65a is repeatedly executed for a predetermined number of rounds.

Next, the display control process of the second symbol (for example, a symbol of "○" or "x") by the second symbol display device 82 is executed (S212). Briefly described, on the condition that the sphere has passed through the second entrance (through gate) 67, the value of the second random number counter C4 is acquired at the timing of the passage, and the second symbol display device 82 is also acquired. The variable display of the second symbol is carried out on the display section 83 of. Then, the lottery for the second symbol is carried out by the value of the second hit random number counter C4, and when the second symbol is hit, the electric accessory attached to the first entrance 64 is opened for a predetermined time.

After that, it is determined whether or not the power-off occurrence information is stored in the RAM 203 (S213). If the power-off occurrence information is not stored in the RAM 203 (S213: No), the frame open detection circuit 260 causes the MPU 201 to operate. Has not been started up temporarily. Further, the trailing edge of the power failure signal SG1a output from the power failure monitoring circuit 252 is not detected, and the power of the pachinko machine 10 is not shut off. Therefore, in such a case, it is determined whether or not the execution timing of the next main processing has been reached, that is, whether or not a predetermined time (4 ms in the present embodiment) has elapsed since the start of the previous main processing (S214). ). If the predetermined time has already passed (S214: Yes), the process proceeds to S201, and the above-described respective processes after S201 are repeatedly executed.

On the other hand, if the power-off occurrence information is stored in the RAM 203 (S213: Yes), the power of the pachinko machine 10 is off, and the inner frame 12 or the front frame 14 is opened during the power-off, The MPU 201 is temporarily activated by the frame opening detection circuit 260 and the power failure signal SG1b output from the frame opening detection circuit 260 falls, and as a result, the NMI interrupt process of FIG. 17 has been executed, or the pachinko machine 10 When the power is turned on, the power is shut off due to the occurrence of a power failure or the power is turned off, and the power failure signal SG1a output from the power failure monitoring circuit 252 falls. As a result, the NMI interrupt processing of FIG. 17 is executed. Therefore, the processing at the time of power shutdown after S221 is executed. First, the generation of each interrupt process is prohibited (S221), and a power-off command indicating that the power is cut off is sent to other control devices (peripheral control devices such as the payout control device 111 and the voice lamp control device 113). And transmits (S222). Then, the RAM judgment value is calculated, the value is stored (S223), access to the RAM 203 is prohibited (S224), and the infinite loop is continued until the power is completely cut off and the processing cannot be executed. Here, the RAM determination value is, for example, a checksum value in the stack area and work area of the RAM 203 that are backed up.

In the process of S214, if the predetermined time has not yet passed from the start of the previous main process (S214: No), the predetermined time is reached, that is, the remaining time until the execution timing of the next main process is reached. In, the first initial value random number counter CINI1, the second initial value random number counter CINI2, and the variation type counters CS1, CS2, CS3 are repeatedly updated (S215, S216).

First, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are updated (S215). Specifically, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are incremented by 1, and when the counter value reaches the maximum value (738 and 250 in this embodiment), it is cleared to 0. To do. Then, the updated values of the first initial value random number counter CINI1 and the second initial value random number counter CINI2 are stored in the corresponding buffer areas of the RAM 203, respectively.

Next, the fluctuation type counters CS1, CS2, CS3 are updated (S216). Specifically, the fluctuation type counters CS1, CS2, CS3 are incremented by 1, and when the counter values reach the maximum values (198, 240, 162 in the present embodiment), they are cleared to 0 respectively. Then, the updated values of the fluctuation type counters CS1, CS2, CS3 are stored in the corresponding buffer areas of the RAM 203, respectively.

Here, since the execution time of each processing of S201 to S212 changes according to the state of the game, the remaining time until the execution timing of the next main processing is not constant but fluctuates. Therefore, by repeatedly updating the first initial value random number counter CINI1 and the second initial value random number counter CINI2 using the remaining time, the first initial value random number counter CINI1 and the second initial value random number counter CINI2 (that is, , The initial value of the first random number counter C1 and the initial value of the second random number counter C4) can be randomly updated, and similarly, the fluctuation type counters CS1, CS2, CS3 can also be randomly updated.

After the processing of S216, the voltage (reset signal SG3b) output from the frame opening detection circuit 260 to the input/output port 205 is read (S217). Then, it is determined whether the output from the frame opening detection circuit 260 to the input/output port (reset signal SG3b) is high (S218). If the output from the frame open detection circuit 260 to the input/output port is high (S218: Yes), the on-frame open flag 203b is turned on (S219). On the other hand, if the output from the frame open detection circuit 260 to the input/output port is not high (S218: No), the on-frame open flag 203b is turned off (S220). After the processing of S219 or the processing of S220, the processing shifts to the processing of S213, and the processing of S213 and thereafter is executed.

Note that the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened while the power is off, and the frame open detection circuit 260 causes the MPU 201 to be temporarily started up. When the reset signal SG3b is output from 260, the on-medium frame release flag 203b is also turned on in addition to the off-medium frame release flag 203a. It takes about 4.4 seconds after the power failure signal SG1b becomes 5 volts until the power failure signal SG1b output from the power failure signal output terminal of the frame opening detection circuit 260 falls from 5 volts to zero volts ( It takes about 4.4 seconds until it is determined to be “Yes” in the processing of S213), and during that time, the processing of S218 is executed in addition to the startup processing, and it is determined to be “Yes” in this processing. Is.

However, even if the on-inside frame opening flag 203b is turned on in addition to the off-inside frame opening flag 203a, if the power of the pachinko machine 10 is next turned on, it is determined as “Yes” in the process of S204. Then, the process does not shift to the process of S207 for determining the state of the on-frame opening flag 203b. Therefore, main controller 110 can transmit only the OFF-in-frame opening command to voice lamp controller 113. Therefore, when the MPU 201 is temporarily activated by the frame open detection circuit 260, the on-in-frame open flag 203b is turned on in addition to the off-in-frame open flag 203a, but this does not cause any problem. is there.

On the other hand, when the inner frame 12 and the front frame 14 are not opened while the power of the pachinko machine 10 is off (when the inner frame 12 and the front frame 14 are closed), naturally, The OFF middle frame release flag 203a is never turned ON. Therefore, when the pachinko machine 10 is powered on next time, it is determined as “No” in the process of S204 and the process of S207 for determining the state of the on-frame opening flag 203b is executed. Naturally, the process of S218 is also executed. Therefore, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned on, the opening is detected by the processing of S217 and the processing of S218, and the processing of S208 executed thereafter. Then, main controller 110 can send only the on-frame open command to voice lamp controller 113.

As described above, when the off-inside frame opening flag 203a is turned on (S204: Yes), the pachinko machine 10 transmits an off-inside frame opening command to the voice lamp control device 113 (S205) and also to the hall computer 262. A pulse signal having a pulse width of about 1 msec is output (S206).

Note that the power of the pachinko machine 10 is off, the inner frame 12 or the front frame 14 is opened while the power is off, and the drive voltage Vb, the power failure signal SG1b, and the reset signal SG3b are output from the frame open detection circuit 260. The process of S201 to S213: Yes to S224, which is the process executed when the MPU 201 is temporarily started up, is at least the reset signal of the frame open detection circuit 260 due to the discharge of the capacitor CD4 (see FIG. 7). A program is set up so that execution is completed while the reset signal SG3b output from the output terminal drops to about 4.3 volts, that is, about 5.0 seconds (see FIG. 8). ing. The period of about 5.0 seconds is irrespective of the opening time of the inner frame 12 or the front frame 14 (the inner frame 12 or the front frame 14 is opened, and the inner frame 12 or the front frame 14 is immediately opened). (Although is closed), it is a period which is always generated by discharging the capacitor CD4 (see FIG. 8). Therefore, even when the MPU 201 is temporarily started up, the pachinko machine 10 temporarily turns on the off-inside frame opening flag 203a regardless of the opening time of the inner frame 12 or the front frame 14 and then temporarily. The MPU 201 that has started up can be normally terminated.

Note that the processing of S213 is at the timing when the series of processing corresponding to the game state change performed at S201 to S212 ends, or the end of one cycle of the processing of S215 to S220 performed within the remaining time. It is running. Therefore, in the main processing of the main controller 110, since the power-off occurrence information is confirmed at the timing when each setting is completed, when returning from the power-off state, the processing is performed after the start-up processing is completed. The process can be started from S201. That is, the process can be started from the process of S201 as in the case where the process is initialized in the startup process. Therefore, even if the contents of the registers used by the MPU 201 are not saved in the stack area or the stack pointer value is not saved in the power-off process, the stack pointer is not saved in the initial setting process (S101). By setting to a predetermined value (initial value), the process of S201 can be started. Therefore, the control load on the main control device 110 can be reduced, and accurate control can be performed without causing the main control device 110 to malfunction or run away.

Next, the variation process (S204) will be described with reference to FIG. FIG. 13 is a flowchart showing the variation process (S204) executed in the main process (see FIG. 12). In this variation process, first, it is determined whether or not a big hit is currently being made (S301). The jackpot includes the jackpot game displayed on the third symbol display device 81 and the first symbol display device 37 during the jackpot and the predetermined time period after the jackpot game ends. If the result of the determination is that the jackpot is in progress (S301: Yes), this processing is ended.

If it is not a big hit (S301: No), it is determined whether the display mode of the first symbol display device 37 is changing (S302), and if the display mode of the first symbol display device 37 is not changing. (S302: No), it is determined whether or not the number N of operation-holding balls is larger than 0 (S303). If the number N of operation-holding balls is 0 (S303: No), this process is terminated. If the number N of operation-holding balls> 0 (S303: Yes), the number N of operation-holding balls is subtracted by 1 (S304), and the data stored in the holding ball storage area is shifted (S305). This data shift process is a process of sequentially shifting the data stored in the holding first to fourth areas of the holding sphere storage area to the execution area side, that is, the holding first area→the execution area, the holding second area→ The data in each area is shifted such as the first reserved area, the third reserved area→the second reserved area, the fourth reserved area→the third reserved area. After the data shift process, the variation start process of the first symbol display device 37 is executed (S306). The fluctuation start process will be described later with reference to FIG.

In the process of S302, when it is determined that the display mode of the first symbol display device 37 is changing (S302: Yes), it is determined whether the changing time has elapsed (S307). The display time during change of the first symbol display device 37 is determined according to the change pattern selected by the change type counters CS1 and CS2 and the addition time selected by the change type counter CS3, and this change time is If not elapsed (S307: No), the display of the first symbol display device 37 is updated (S308).

In the present embodiment, among the LEDs 37a of the first symbol display device 37, until the variation time elapses after the variation is started, for example, if the currently lit LED is red, the red LED is Turn off the green LED and turn on the green LED. If the green LED is turned on, turn off the green LED and turn on the blue LED. If the blue LED is turned on, turn on the blue LED. A display mode is set in which the LED is turned off and the red LED is turned on.

The variation process is executed every 4 ms, but if the LED lighting color is changed every time the variation process is executed, the player cannot confirm the change in the LED lighting color. Therefore, a counter (not shown) is counted by 1 each time the variation process is executed so that the player can confirm the change in the LED lighting color, and when the counter reaches 100, the LED Change the lighting color of. That is, the lighting color of the LED is changed every 0.4 seconds. The value of the counter is reset to 0 when the lighting color of the LED is changed.

On the other hand, if the variation time of the first symbol display device 37 has elapsed (S307: Yes), the display mode corresponding to the stopped symbol of the first symbol display device 37 is set (S309). The setting of the stop symbol is determined whether or not it is a big hit depending on the value of the first random number counter C1, and in the case of a big hit, a symbol which becomes a high probability state after the big hit by the value of the first hit type counter C2. It is determined whether or not the symbol becomes a low probability state. In the present embodiment, the red LED is turned on when the high probability state is reached after the jackpot, the green LED is turned on when the low probability state is reached, and the blue LED is turned on when the probability is off. .. It should be noted that the display of each LED is turned off when the next change display is started, but may be turned on only for a few seconds after the change is stopped.

When the display mode of the first symbol display device 37 corresponding to the stopped symbol is set in the process of S309, the stop of the fluctuation of the third symbol display device 81 is stopped in order to synchronize with the lighting of the LED in the first symbol display device 37. The command is set (S310). Upon receiving this stop command, the voice lamp control device 113 gives a stop instruction to the display control device 114. The third symbol display device 81 stops the variation when the variation time elapses, and by receiving the stop command, the variation effect of 1 in the third symbol display device 81 ends.

Next, the fluctuation start process will be described with reference to FIG. FIG. 14 is a flowchart showing the fluctuation start process (S306) executed in the fluctuation process (see FIG. 13). In the fluctuation start process (S306), first, it is determined whether or not it is a big hit based on the value of the first winning random number counter C1 stored in the execution area of the reserved ball storage area (S401). Whether or not it is a big hit is determined based on the relationship between the value of the first random number counter C1 and the mode at that time. As described above, "373,727" of the numerical values 0 to 738 of the first random number counter C1 is the winning value at the normal low probability, and "59,109,163,211,263,317,367," at the high probability. "421, 479, 523, 631, 683, 733" is the winning value.

When it is determined that it is a big hit (S401: Yes), the value of the first hit type counter C2 stored in the execution area of the reserved ball storage area is confirmed, and the display mode at the time of a big hit is set (S402). ). In the process of S402, whether to shift to the high-probability state or the low-probability state after the big hit is set based on the value of the first hit type counter C2. When the transition state after the big hit is set, the display mode of the first symbol display device 37 (the lighting state of the LED 37a) is set. Also, based on the transition state after the big hit, the big hit stop symbol that is stopped and displayed on the third symbol display device 81 is set by the voice lamp control device 113 and the display control device 114. That is, the stop symbol in the third symbol display device 81 is set by setting the transition state after the big hit by the process of S402. In addition, among the numerical values 0 to 4 of the first hit type counter C2, in the case of "0, 4", the state shifts to the low probability state thereafter, and in the case of "1, 2, 3", the state shifts to the high probability state. ..

Next, the variation pattern at the time of a big hit is determined (S403). When the variation pattern is set in the process of S403, the display time of the first symbol display device 37 is set, and the variation time of the third symbol until the big symbol symbol stops on the third symbol display device 81 is determined. R. At this time, the values of the fluctuation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and based on the value of the first fluctuation type counter CS1, normal reach, super reach, premium reach, and other rough symbol fluctuations While determining the variation time, the variation time (in other words, variation symbol number) until the final stop symbol (in the present embodiment, the medium symbol Z2) is stopped after the reach is generated based on the value of the second variation type counter CS2 decide.

Note that the relationship between the numerical value of the first fluctuation type counter CS1 and the fluctuation time and the relationship between the numerical value of the second fluctuation type counter CS2 and the fluctuation time are preliminarily defined by a table or the like. However, the fluctuation time can be set using only the value of the first fluctuation type counter CS1 without using the value of the second fluctuation type counter CS2, and is set only by the value of the first fluctuation type counter CS1. Whether to set or to set with both values of both fluctuation type counters CS1 and CS2 is appropriately determined according to the value of the first fluctuation type counter CS1 and the game condition at each time.

When it is determined in the processing of S401 that the jackpot is not the big hit (S401: No), the display mode at the time of the deviation is set (S404). In the process of S404, the display mode of the first symbol display device 37 is set to a display mode corresponding to the out-of-design, and based on the value of the stop pattern selection counter C3 stored in the execution area of the reserved ball storage area, The effect displayed on the third symbol display device 81 is set to be a front/rear outreach, a reach other than the front/rear outreach, or a complete outreach. In the present embodiment, as described above, the range of values corresponding to each stop pattern of the stop pattern selection counter C3 is determined according to the high-probability state, the low-probability state, and the number N of operation suspensions. The tables are set differently.

Next, the variation pattern at the time of detachment is determined (S405), the display time of the first symbol display device 37 is set, and the variation time of the third symbol until it stops at the detachment symbol on the third symbol display device 81. Is determined. At this time, similarly to the processing of S403, the values of the fluctuation type counters CS1 and CS2 stored in the counter buffer of the RAM 203 are confirmed, and the normal reach, super reach, and premium reach are determined based on the values of the first fluctuation type counter CS1. While determining the variation time of the rough symbol variation such as, the variation time until the final stop symbol (the middle symbol Z2 in the present embodiment) stops after the reach is generated based on the value of the second variation type counter CS2 (in other words, For example, determine the number of variable symbols).

When the process of S403 or the process of S405 ends, the effect time that is added to or subtracted from the fluctuation time determined by the first and second type counters CS1 and CS2 is determined (S406). At this time, addition/subtraction of the effect time is determined based on the value of the third type counter CS3 stored in the counter buffer of the RAM 203, the display time of the first symbol display device 37 is set, and the third symbol display is performed. The variation time of the device 81 is set. In the present embodiment, the addition/subtraction of the effect time is determined by changing the variable display time by 2 when the variable display time is not changed and when the variable display time is added by 1 second according to the value of the third fluctuation type counter CS3. When adding seconds, four types of addition values are determined, which are the case where the variable display time is subtracted by 1 second.

In addition, when the variable display time is added or subtracted, a notice effect that the expected value of the big hit in the third symbol display device 81 becomes high (for example, a sliding effect in which the variation time of the variable symbol is made longer than usual to cause slippage, The effect of displaying the advance notice character, the effect of making the fluctuation time of the fluctuation pattern 1 shorter than usual and immediately stopping) are performed. Further, when the value of the first random number counter C1 is a big hit, the probability that the additional value of 2 seconds is selected is set high, so the player should expect a big hit by confirming the notice effect. You can

Next, the variation pattern command is set according to the variation pattern (variation time) determined in the processing of S403 or S405 (S407), and the stop symbol command is set according to the stop symbol set in the processing of S402 or S404. Yes (S408). Then, an effect time addition command is set according to the added value of the effect time determined in the process of S406 (S409), and the process returns to the variation process.

Next, with reference to FIGS. 18 to 20, the processing performed by the audio lamp control device 113 will be described. FIG. 18 is a flowchart showing a startup process executed by the MPU 221 in the voice lamp control device 113. This startup process is started when the power is turned on.

When the start-up process is executed, first, an initial setting process accompanying power-on is executed (S1001). Specifically, the stack pointer is set to a predetermined value. After that, depending on whether or not the power-off processing in progress flag is turned on, the power-up processing of S1115 (see FIG. 19) occurs due to a momentary voltage drop (instantaneous power failure, so-called “instantaneous stop”) in the startup processing of this time. It is determined whether or not the process is started during the execution of () (S1002). As will be described later with reference to FIG. 19, when the voice lamp control device 113 receives a power-off command from the main control device 110 (see S1112 of FIG. 19), the power-off process of S1115 is executed. The power-off processing flag is turned on before the power-off processing is executed, and the power-off processing flag is turned off after the power-off processing is completed. Therefore, whether or not the power-off processing in S1115 is being executed can be determined by the state of the power-off processing in progress flag.

If the power-off processing in progress flag is off (S1002: No), the startup processing of this time is started after the power is completely cut off, or after a momentary power failure occurs and the power-off in S1115 is performed. It is started after the execution of the process is completed, or is started (without receiving the power-off command from the main control unit 110) only on the MPU 221 of the voice lamp control unit 113 due to noise or the like. is there. Therefore, in these cases, it is confirmed whether or not the data in the RAM 223 is destroyed (S1003).

The confirmation of the data destruction of the RAM 223 is performed as follows. That is, the data as the keyword “55AAh” is written in the specific area of the RAM 223 by the processing of S1006. Therefore, it is possible to check the data stored in the specific area, and if the data is "55AAh", there is no data destruction in the RAM 223, and conversely, if it is "55AAh", it is possible to confirm the data destruction in the RAM 223. If the data destruction of the RAM 223 is confirmed (S1003: Yes), the process proceeds to S1004 and the initialization of the RAM 223 is started. On the other hand, if the data destruction of the RAM 223 is not confirmed (S1003: No), the process proceeds to S1008.

If the power-on process is started after the power is completely cut off, the keyword "55AAh" is not stored in the specific area of the RAM 223 (the memory of the RAM 223 is lost due to the power-off). Therefore, it is determined that the data in the RAM 223 has been destroyed (S1003: Yes), and the process proceeds to S1004. On the other hand, the startup process of this time was started after the momentary power failure occurred and after the execution of the power-off process of S1115 was completed, or only the MPU 221 of the audio lamp control device 113 was reset due to noise or the like. If it is started due to the trouble, the keyword “55AAh” is stored in the specific area of the RAM 223, so that the data of the RAM 223 is determined to be normal (S1003: No), and the process proceeds to S1008.

If the power-off processing in progress flag is on (S1002: Yes), the start-up processing this time is after the momentary power failure has occurred and during the execution of the power-off processing of S1115, the voice lamp control device 113 is executed. The MPU 221 has been reset and started. In such a case, since the power-off process is being executed, the storage state of the RAM 223 is not always correct. Therefore, in such a case, control cannot be continued, so the process moves to S1004, and initialization of the RAM 223 is started.

In the process of S1004, the entire storage area of the RAM 223 is checked (S1004). As a check method, first, “0FFh” is written for each byte, and it is read for each byte to check whether it is “0FFh”. If “0FFh”, it is determined to be normal. Such writing and confirmation for each byte is performed in the order of “55h”, “0AAh”, and “00h” after “0FFh”. By this read/write check of the RAM 223, all storage areas of the RAM 223 are cleared to 0.

If the read/write check is determined to be normal for all the storage areas of the RAM 223 (S1005: Yes), the keyword “55AAh” is written in the specific area of the RAM 223 to set the RAM destruction check data (S1006). By checking the keyword "55AAh" written in this specific area, it is checked whether or not there is data destruction in the RAM 223. On the other hand, if a read/write check abnormality is detected in any of the storage areas of the RAM 223 (S1005: No), the abnormality of the RAM 223 is notified (S1007), and an infinite loop is performed until the power is cut off. The abnormality of the RAM 223 is notified by the display lamp 34. The voice output device 226 may output voice to notify the abnormality of the RAM 223.

In the processing of S1008, it is determined whether or not the power-off flag is turned on (S1008). Since the power-off flag is turned on when the power-off process of S1115 is executed (see S1114 of FIG. 19), the power-off flag is turned on by the process of S1114, as described later with reference to FIG. That is, since the power-off flag is turned on before the power-off process of S1115 is executed, the process of S1008 with the power-off flag turned on is that the startup process of this time is instantaneous. This is the case after the power failure has occurred and the power-off process of S1115 is started without being completed. Therefore, in such a case (S1008: Yes), the work area of the RAM is cleared to initialize each process of the voice lamp control device 113 (S1009), the initial value of the RAM 223 is set (S1010), and then the interruption is performed. The permission is set (S1011), and the process proceeds to the main process. The work area of the RAM 223 is an area other than the area for storing commands and the like received from the main controller 110.

On the other hand, the reason why the process of S1008 is reached with the power-off flag turned off is that the present startup process is started after the power has been completely cut off, for example, and the process of S1004 to S1006 is followed to the process of S1008. This is the case when the processing has been started, or only the MPU 221 of the audio lamp control device 113 has been reset due to noise or the like (without receiving the power-off command from the main control device 110) and started. Therefore, in such a case (S1008: No), S1009 which is a work area clearing process of the RAM 223 is skipped, the process proceeds to S1010, the initial value of the RAM 223 is set (S1010), and then the interrupt permission is set. Then (S1011), the process proceeds to the main process.

It should be noted that the clear processing of S1009 is skipped because all the storage areas of the RAM 223 have already been cleared by the processing of S1004 when the processing of S1004 is passed through the processing of S1004 to the processing of S1008. When only the MPU 221 of the voice lamp control unit 113 is reset due to noise or the like and the start-up process is started, the data in the work area of the RAM 223 is saved without being cleared. This is because the control of can be continued.

Next, with reference to FIG. 19, a main process executed after the startup process of the voice lamp control device 113 will be described. FIG. 19 is a flowchart showing the main processing executed by the MPU 221 of the voice lamp control device 113. When the main process is executed, first, it is determined whether or not 1 msec or more has elapsed from the start of the main process (S1101), and if 1 msec or more has not elapsed (S1101: No), S1102 to S1109. The process shifts to S1110 without performing the process. In the process of S1101, determining whether 1 msec has elapsed is a process related to display (effect) in S1102 to S1109, and it is not necessary to edit in a short cycle (within 1 msec). This is because it is preferable to execute the updating process of each counter and the command receiving process of S1111 in a short cycle. As a result, it is possible to prevent omission of reception of commands transmitted from main controller 110.

If 1 ms or more has elapsed in the process of S1101 (S1101: Yes), the output of each lamp is set so that the lighting mode of the display lamp 34 is set or the lighting mode of the lamp edited in the process of S1107 described later is set. (S1102), and then the power-on notification process is executed (S1103). The power-on notification processing is to notify that the power is turned on for a predetermined time (for example, 30 seconds) when the power is turned on, and the notification is performed by the voice output device 226 or the lamp display device 227. Be seen. Further, a command may be transmitted to the display control device 114 so as to notify that the power is supplied on the screen of the third symbol display device 81. If it is not when the power is turned on, the process proceeds to the process of S1104 without performing the notification by the power-on notification process.

In the process of S1104, the customer waiting effect is executed, and then the retained quantity display update process is executed (S1105). In the customer waiting production, when the pachinko machine 10 is not played by the player for a predetermined time, the setting of switching the display of the third symbol display device 81 to the title screen is performed, and the setting is a command as a display control device. Sent to 114. In the retained quantity display updating process, a process of turning on the retaining lamp 85 according to the operation retaining ball N is performed.

Thereafter, frame button input monitoring/effect processing is executed (S1106). In this frame button input monitoring/production process, the input of whether or not the frame button 22 operated by the player in order to enhance the production effect is pressed is monitored, and it corresponds to the case where the input of the frame button 22 is confirmed. It is a process of setting to produce an effect. For example, when the notice character appears at the start of the variable display, pressing the frame button 22 displays the expected value of the jackpot due to this change, or by pressing the frame button 22 during the reach production, the expectation for the jackpot is displayed. It may be changed to a production that can be held or may be an enter button for selecting one of the reach productions. If the frame button 22 is not provided, the process of S1106 is omitted.

When the frame button input monitoring/effect process is finished, the ramp edit process is executed (S1107), and then the sound edit/output process is executed (S1108). In the lamp editing process, the lighting patterns of the illumination portions 29 to 33 are set so as to correspond to the display performed on the third symbol display device 81. In the sound editing/output process, the output pattern of the voice output device 226 is set so as to correspond to the display performed on the third symbol display device 81, and the sound is output from the voice output device 226 according to the setting.

Thereafter, the liquid crystal effect execution management process is executed (S1109), and the process proceeds to S1110. In the liquid crystal effect execution management process, time synchronized with the time required for the variable display performed on the third symbol display device 81 is set based on the variable pattern command and the effect time addition command transmitted from the main control device 110. Based on the time set in the liquid crystal effect execution monitoring process, the effect time of the lamp edit process of S1107 and the sound edit/output process of S1108 is set.

In the process of S1110, the variable display process of the third symbol display device 81 is executed. In this variable display processing, a plurality of counters (a counter for setting a stop symbol at the time of jackpot, a counter for selecting a stop symbol at the time of disengagement, etc.) mounted on the voice lamp control device 113 are updated, and the value of the counter and the main value are updated. Based on the variation pattern command and the stop symbol command transmitted from the control device 110, the symbol which is stopped and displayed on the third symbol display device 81 is set, and the pattern of the variable display (front/rear outreach, reach other than front/rear out, complete detachment) Etc. are set. The stop symbol and the variation pattern are transmitted to the display control device 114 as a command.

In the process of S1110, for example, when the command of the variation pattern transmitted from the main control device 110 is "completely missed", the completely missed A pattern is selected from among a plurality of patterns corresponding to the perfect miss, and the third symbol display is performed. A command is transmitted to the display control device 110 so that the device 81 produces the effect of the completely separated A pattern. Therefore, for one variation pattern determined by the main control device 110, the detailed variation pattern displayed on the third symbol display device 81 is determined by the voice lamp control device 113, so that the control of the main control device 110 is performed. The burden can be reduced. Furthermore, since the patterns of each effect determined in main controller 110 can be reduced, the storage capacity of ROM 202 can be reduced, and the cost can be reduced.

Then, the command from the main controller 110 is received (S1111). When the command from the main controller 110 is received, if the command is used by the voice lamp controller 113 according to the command, the process corresponding to the command is performed, the processing result is stored in the work RAM 233, and the display controller 114. If it is a command to be used, the command is transmitted to the display control device 114.

After the processing of S1111 is completed, it is determined whether or not the power-off occurrence information is stored in the work RAM 233 (S1112). The power-off occurrence information is stored when a power-off command is received from main controller 110. If the power-off occurrence information is stored in the process of S1112 (S1112: Yes), both the power-off flag and the power-off process in progress flag are turned on (S1114), and the power-off process is executed (S1115). After the power-off process is executed, the power-off process in progress flag is turned off (S1116), and then the process is infinitely looped. In the power-off process, the generation of the interrupt process is prohibited, each output port is turned off, and the outputs from the audio output device 226 and the lamp display device 227 are turned off. Also, the storage of the information on the occurrence of power failure is erased.

On the other hand, if the power-off occurrence information is not stored in the process of S1112 (S1112: No), either the inner frame 12 or the front frame 14 is opened, or both the inner frame 12 and the front frame 14 are opened. If there is, a door opening notification process (S1113) for performing notification using the voice output device 226 and the lamp display device 227 is executed.

Here, the door opening notification process (S1113) will be described with reference to FIG. FIG. 20 is a flowchart showing a door opening notification process executed by the MPU 221 of the voice lamp control device 113. This door opening notification processing determines whether or not the voice lamp control device 113 has received any one of an off-inside frame opening command, an on-inside frame opening command, and a frame closing command, and makes a notification according to the determination. This is a process that starts or ends execution.

In the door open notification process, first, in the process of S1111 (see FIG. 19 ), an OFF middle frame open command indicating that the inner frame 12 or the front frame 14 is open while the power of the pachinko machine 10 is turned off is received. It is determined whether or not (S1201). When the off-frame opening command is received (S1201: Yes), the audio output device 226 and the lamp display device indicate that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off. Notification is started using 227 (S1202). Specifically, in this notification, for example, the lamp display device 227 is used to indicate that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. Blinking is started once per second, and the voice output device 226 is used to start an electronic sound "Please check". As a result, it is possible to notify an unspecified number of people that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off.

After the processing of S1202, the frame opening notification processing ends. When the notification in the process of S1202 has already been executed, if the off-inside frame open command is received again in the process of S1111 (S1201: Yes), the process of S1202 is not performed again. The processing of S1202 that has already been executed is continuously executed.

On the other hand, in the process of S1111 (see FIG. 19), when the off-inside frame open command is not received (S1201: No), the power of the pachinko machine 10 is turned on in the process of S1111 (see FIG. 19). It is determined whether or not an on-frame opening command indicating that the inner frame 12 or the front frame 14 has been opened is received during the period (S1203). When an on-frame opening command is received (S1203: Yes), the audio output device 226 and the lamp display device indicate that the inner frame 12 or the front frame 14 has been opened while the pachinko machine 10 is powered on. Notification is started using 227 (S1204). Specifically, in this notification, for example, the lamp display device 227 is used to indicate that the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered on. Blinking is started once per second, or the voice output device 226 is used to start notification by electronic sound that the door is open. Thereby, it is possible to notify an unspecified number of people that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned on.

Furthermore, in the process of S1111 (see FIG. 19), if the on-frame open command is not received (S1203: No), the power of the pachinko machine 10 is turned on in the process of S1111 (see FIG. 19). It is determined whether or not an ON-inside frame closing command indicating that the inner frame 12 and the front frame 14 are closed while being received is received (S1205). When the on-frame closing command is received (S1205: Yes), the notification started in the process of S1204 ends (S1206). After that, the frame opening notification process ends. In the process of S1111 (see FIG. 19), if the on-frame closing command has not been received (S1205: No), the frame opening notification process ends.

As described above, when the voice lamp control device 113 receives the OFF-inside frame opening command in the process of S1111 (see FIG. 19), the inner frame 12 or the front frame is turned on while the pachinko machine 10 is powered off. Notification of the opening of 14 is started using the voice output device 226 and the lamp display device 227 (S1202). This notification is performed by operating the RAM erasing switch 122, turning on the power of the pachinko machine 10, and by the process of S116 of the startup process of the main control device 110 until the off middle frame open flag 203a is turned off. It will continue.

As described above, in order to turn off the off-inside frame opening flag 203a that has been turned on, unless the RAM erase switch 122 is operated and the pachinko machine 10 is powered on and the used RAM area is cleared in the processing of S116. , OFF The open frame flag 203a cannot be turned off. Therefore, when the power of the pachinko machine 10 is turned on, the pachinko machine 10 certainly does not confirm that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. It is possible to notify a specified number of people.

Further, as described above, when the voice lamp control device 113 receives the ON-in-frame opening command in the processing of S1111 (see FIG. 19), the inner frame 12 or while the pachinko machine 10 is powered on. Notification that the front frame 14 has been opened is started using the voice output device 226 and the lamp display device 227 (S1204). Since this notification is continuously performed until the inner frame 12 and the front frame 14 are closed and the ON-in-frame close command is received, the inner frame 12 or the front frame 12 is turned on while the pachinko machine 10 is powered on. It is possible to notify an unspecified number of people that the frame 14 is open.

Returning to the explanation of FIG. After the door opening notification process (S1113) is executed, it is determined whether or not the RAM 223 is destroyed based on the keyword stored in the RAM 223 (S1117). If the RAM 223 is not destroyed (S1117: No), S1101 is executed. Returning to the processing, the main processing is repeatedly executed. On the other hand, if the RAM 223 is destroyed (S1117: Yes), the process is infinitely looped to stop the execution of the subsequent processes. Here, if it is determined that the RAM is destroyed and the loop is infinite, the main process is not executed, and thereafter the display by the third symbol display device 81 does not change. Therefore, since the player can know that the abnormality has occurred, he can call a clerk in the hall or the like to request the pachinko machine 10 to be repaired. Further, when it is confirmed that the RAM 223 is destroyed, the voice output device 226 or the lamp display device 227 may be used to notify the RAM destruction.

As described above, according to the pachinko machine 10, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is off, the frame open detection circuit 260 causes the frame open detection circuit 260 to detect the drive voltage Vb and After outputting the power failure signal SG1b, the reset signal SG3b is output. Therefore, even if the pachinko machine 10 is powered off, the MPU 201 can be temporarily started up normally. It should be noted that when the pachinko machine 10 is powered off and the MPU 201 is temporarily activated by the frame opening detection circuit 260, the pachinko machine 10 turns on the in-off frame opening flag 203a. When the off-inside frame opening flag 203a is turned on, the pachinko machine 10 uses the voice output device 226 and the lamp display device 227 to display the inner frame 12 or the front frame when the power of the pachinko machine 10 is turned on next time. Notify that 14 has been opened. Therefore, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. Therefore, even in a game hall where the hall computer 262 is not operated for 24 hours, it is possible to detect that the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off.

Further, the off-in-frame opening flag 203a is turned off when the RAM erasing switch 122 is operated to clear the used RAM area in the process of S116 of the startup process of the main controller 110. Therefore, once the off-inside frame open flag 203a is turned on, the off-inside frame open flag 203a cannot be turned off unless the RAM erase switch 122 is operated to clear the used RAM area in the processing of S116. Therefore, when the inner frame 12 or the front frame 14 is opened and the off-inside frame open flag 203a is turned on when the power of the pachinko machine is turned off, after that, the cheating person turns off the off-inside frame. It may be impossible to turn off the open flag 203a. Further, since the off-in-frame opening flag 203a cannot be turned off unless the RAM erasing switch 122 is operated to clear the used RAM area in S116, when the pachinko machine 10 is powered on, The pachinko machine 10 can reliably notify the unspecified number of people that the inner frame 12 or the front frame 14 has been opened while the power of the pachinko machine 10 is off.

Further, when the pachinko machine 10 is powered off and the MPU 201 is temporarily activated by the frame open detection circuit 260, the pachinko machine 10 turns on the off-time frame open flag 203a, and also in addition to the hall computer. A pulse signal having a pulse width of 1 msec is output to 262. The output pulse signal is stored in the hall computer 262 which operates continuously for 24 hours. Therefore, by analyzing the pulse signal stored in the hall computer 262, it is possible to identify the pachinko machine 10 in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine 10 is turned off. You can Furthermore, by storing the pulse signal output from the pachinko machine 10 to the hall computer 262 and storing the output time of the output pulse signal, the opening time of the inner frame 12 or the front frame of the specified pachinko machine 10 is stored. The opening time of 14 can be detected.

Further, in the frame open detection circuit 260, when the inner frame 12 or the front frame 14 is opened, the switch SW1 or the switch SW2 becomes conductive, and about 4.4 seconds after the conduction, first, the power failure signal SG1b is stopped ( If the open inner frame 12 or the open front frame 14 is closed before the switch SW1 or the switch SW2 is turned on and about 4.4 seconds have passed after the turn-on, a stop signal is issued when the switch is closed. Stop SG1b). Next, the frame opening detection circuit 260 stops the reset signal SG3b when about 9.4 seconds have passed after the switch SW1 or the switch SW2 was turned on (about 4.4 seconds passed after the switch SW1 or the switch SW2 was turned on). When the opened inner frame 12 or the opened front frame 14 is closed before, the reset signal SG3b is stopped about 5.0 seconds after the closing). Then, the frame opening detection circuit 260 reduces the drive voltage Vb output to the power supply terminal of the MPU 201 to about 4.0 volts when about 9.9 seconds have elapsed after the switch SW1 or the switch SW2 was turned on (the switch SW1 or the switch SW1 or If the opened inner frame 12 or the opened front frame 14 is closed before about 4.4 seconds have passed after the switch SW2 is turned on, the drive is performed about 5.5 seconds after the closing. The voltage Vb is reduced to about 4.0 volts). Therefore, even when the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily activated by the frame opening detection circuit 260 when the power of the pachinko machine 10 is turned off, the frame opening detection circuit 260 still operates. The MPU 201 that has started up can be normally terminated.

In addition, even if the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is conducted, the frame open detection circuit 260 detects that the inner frame 12 or the front frame is still in operation for about 4.4 seconds. Regardless of the open period of 14, the transistor TR1 stops the output of the driving voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4, which are performed by the electric power supplied from the capacitor CD1. After the stop by the transistor TR1, the frame open detection circuit 260 outputs the drive voltage Vb and the reset signal SG3b by discharging the capacitor CD4. Therefore, the frame opening detection circuit 260, for example, when the business hours of the game hall is finished and the power supply to the pachinko machine 10 is cut off, and the DC voltage of 12 volts is not supplied from the DC power supply DC1 to the frame opening detection circuit 260. That is, that is, when the DC voltage of about 11.3 volts is supplied from the capacitor CD1 to the frame open detection circuit 260, the period during which the power is supplied from the capacitor CD1 is the open period of the inner frame 12 or the front frame 14. Regardless, it can be held for about 4.4 seconds. Therefore, the frame opening detection circuit 260 can suppress the consumption of the electric power charged in the capacitor CD1 and detect the opening of the inner frame 12 or the front frame 14 multiple times.

Even if the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is turned on, the frame open detection circuit 260 is opened before about 4.4 seconds elapses from the time when the switch SW1 or the switch SW2 is turned on. When the frame 12 or the opened front frame 14 is closed, the switch SW1 or the switch SW2 is cut off, and the output of the drive voltage Vb, the output of the reset signal SG3b, and the power failure signal SG1b performed by the power supplied from the capacitor CD1. And the charging of the capacitor CD4 are stopped. After the inner frame 12 and the front frame 14 are closed, the drive voltage Vb and the reset signal SG3b are output by discharging the capacitor CD4.

In this way, when the charging of the capacitor CD4 is completed, after that, the driving voltage Vb and the reset signal SG3b can be output by discharging the capacitor CD4, so that the opening period of the inner frame 12 or the front frame 14 is about. If it is within 4.4 seconds, the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4, which are performed by the power supply from the capacitor CD1, are further shortened. Can be kept at. Therefore, the power consumption of the capacitor CD1 due to the opening of the inner frame 12 or the front frame 14 can be further suppressed.

Here, since the capacitance of the capacitor CD1 is 1F and the voltage applied to the capacitor CD1 is about 11.3 volts, the charge accumulated in the capacitor CD1 is the product of the capacitance of the capacitor CD1 and the applied voltage of the capacitor CD1. To about 11.3 C (coulomb). The electric charge of about 11.3C stored in the capacitor CD1 is about during each period of the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b and the charging of the capacitor CD4 which are performed by the power supply from the capacitor CD1. In the case of 4.4 seconds, the number of times power is supplied corresponds to about 11 times. Therefore, for example, when the power supply to the pachinko machine 10 is cut off after the business hours of the game arcade and the DC voltage of 12 V is not supplied from the DC power supply DC1, the inner frame 12 is opened (the switch SW1 is turned on). Even when the front frame 14 is opened (conduction) or the front frame 14 is opened (conduction of the switch SW2) for a plurality of times, the frame open detection circuit 260 opens the inner frame 12 or opens the front frame 14 (conduction of the switch SW1 or It is possible to reliably detect that the switch SW2 is turned on up to about 11 times each time, temporarily start the MPU 201 normally, and turn on the off-inside frame open flag 203a. At this time, when the inner frame 12 is opened or the front frame 14 is opened about 11 times, the electric power stored in the capacitor CD1 decreases, and the driving voltage Vb decreases, the reset signal SG3 decreases, and the power failure signal SG1 decreases. A decrease and a decrease in the charge amount of the capacitor CD4 occur. However, when the inner frame 12 or the front frame 14 is opened, the voltage of the reset signal SG3b output from the reset signal output terminal of the frame open detection circuit 260 exceeds about 4.3 V and the frame open detection circuit 260 is released. If the voltage of the drive voltage Vb output from the power output terminal of the power supply and the voltage of the power failure signal SG1b output from the power failure signal output terminal of the frame open detection circuit 260 exceeds about 4.0 volts, the power of the pachinko machine 10 is Even if it is turned off, the MPU 201 can be temporarily started up normally and the off-inside frame open flag 203a can be turned on. Furthermore, a pulse signal having a pulse width of 1 msec can be output to the hall computer 262.

In the frame opening detection circuit 260, when the inner frame 12 and the front frame 14 are closed (when the switches SW1 and SW2 are cut off), the OUT terminal voltage of the timer IC1 is about 10.6 volts. Therefore, the drain opening D and the source terminal S of the FET1 and the drain terminal D and the source terminal S of the FET2 of the frame opening detection circuit 260 are in a conductive state. Since the inner frame 12 and the front frame 14 are closed, the drain terminal D and the source terminal S of the FET 3 are electrically connected. However, at this time, since the conduction between the emitter terminal e and the collector terminal c of the transistor TR1 is cut off, the drain terminal D and the source terminal S of the FET1 and the drain terminal D and the source terminal of the FET2 are cut off. The current from the capacitor CD1 does not flow between the terminals S and S3 and between the drain terminal D and the source terminal S of the FET3. Therefore, when the inner frame 12 and the front frame 14 are closed, the electric power charged in the capacitor CD1 is generated between the drain terminal D and the source terminal S of the FET1 and between the drain terminal D and the source terminal S of the FET2. It does not flow between the terminals and between the drain terminal D and the source terminal S of the FET 3 and are not consumed.

Further, the power consumption of the capacitor CD1 by the frame opening detection circuit 260 when the pachinko machine 10 is powered off and the inner frame 12 and the front frame 14 are closed is determined by the standby power of the timer IC1 and the power consumption of the NOTIC3. It is a degree. Moreover, since a voltage is only applied to each gate terminal G of the FET1 to FET3, the power consumed by the FET1 to FET3 is very small. Therefore, the consumption of these powers does not cause a significant reduction in the amount of charge of the capacitor CD1.

In the pachinko machine 10 of the present embodiment, the notification that the inner frame 12 or the front frame 14 has been opened is performed using the audio output device 226 and the lamp display device 227 controlled by the audio lamp control device 113. However, it is not limited to this. Instead of using the voice output device 226 and the lamp display device 227 controlled by the voice lamp control device 113 to notify that the inner frame 12 or the front frame 14 has been opened, it becomes possible to operate when the MPU 201 starts up. It is of course possible to use an audio output device or a lamp display device controlled by the MPU 201. However, in this case, when the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened by a cheating person, and the frame open detection circuit 260 temporarily starts up the MPU 201. Then, the voice output device and the lamp display device controlled by the MPU 201 also start up, and when the off-inside frame open flag 203a is turned on, the fraudulent person is notified. Here, it is executed when the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened while the power is off, and the frame open detection circuit 260 temporarily starts up the MPU 201. The processing of S201 to S213: Yes to S224 (see FIG. 12), which is the processing performed, is such that at least the reset signal SG3b output from the reset signal output terminal of the frame opening detection circuit 260 by the discharge of the capacitor CD4 is about 4. The program is designed so that the execution is completed in the period until the voltage drops to 3 volts, that is, in the period of about 5.0 seconds (see FIG. 8). When making use of this identification to notify by the audio output device or the lamp display device that the MPU 201 controls, the time after the power of the pachinko machine 10 is turned on is measured by a counter, and for example, the power of the pachinko machine 10 is The notification may be started 30 seconds after being turned on (after the counter measures 30 seconds). Then, when the MPU 201 is temporarily activated by the frame opening detection circuit 260, 30 seconds after the power of the pachinko machine 10 is turned on, that is, before the counter counts 30 seconds. , Since the MPU 201 has been shut down (because it has ended), the notification is not executed, but when the power of the pachinko machine 10 is turned on normally and the MPU 201 is started, the notification is performed. It is possible to perform notification when the power of the pachinko machine 10 is normally turned on while preventing notification to the actor.

In the pachinko machine 10 of the present embodiment, when the power of the pachinko machine 10 is turned off, the inner frame 12 or the front frame 14 is opened, and the switch SW1 or the switch SW2 is electrically connected. The output of the voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4 are started, but the present invention is not limited to this. That is, when the connection of each component mounted in the frame opening detection circuit 260 of the pachinko machine 10 is changed, the inner frame 12 or the front frame 14 is opened, and the opened inner frame 12 or the front frame 14 is closed. In addition, the output of the drive voltage Vb, the output of the reset signal SG3b, the output of the power failure signal SG1b, and the charging of the capacitor CD4 may be started from the time of closing.

However, in the frame opening detection circuit 260 of the pachinko machine 10 of the present embodiment, when the inner frame 12 or the front frame 14 is opened and the switch SW1 or the switch SW2 is conducted, the output of the reset signal SG3b is started. With this configuration, the opening of the inner frame 12 or the front frame 14 can be quickly detected. Therefore, particularly during business hours when the power of the pachinko machine 10 is turned on, before the inner frame 12 or the front frame 14 is opened and a fraudulent act is performed on the main controller 110 or the game board 13, the inner frame 12 is opened. Alternatively, the opening of the front frame 14 can be detected. Therefore, it is possible to prevent abnormal operation due to fraudulent behavior that occurs when power is supplied to the pachinko machine 10.

It should be noted that the main frame opening detection circuit 260 is used to separately store which of the inner frame 12 and the front frame 14 is opened by using a flag, and to notify the opening of the inner frame 12 or the front frame 14 separately. When it is desired to separately store which of the inner frame 12 and the front frame 14 is opened in the hall computer 262, the following configuration may be adopted. First, one frame opening detection circuit 260 used in the present embodiment is newly added, the switch SW2 connected in parallel to the switch SW1 is cut off, and the cut switch SW2 is added to the newly added frame opening detection circuit 260. Connecting. Specifically, one end of the disconnected switch SW2 is connected to one end of the capacitor CD1 of the newly added frame opening detection circuit 260, the VDD terminal of the timer IC1 and the RES terminal of the timer IC1, and the other of the disconnected switch SW2 is connected. The end may be connected to one end of the resistor R1 of the newly provided frame opening detection circuit 260, one end of the resistor R2, the input terminal of the NOTIC3, one end of the resistor R3, and the emitter terminal e of the transistor TR1.

The power output terminal, the reset signal output terminal, and the power failure signal output terminal of the added frame opening detection circuit 260 are replaced by the power supply output terminal, the reset signal output terminal, and the power failure signal output of the existing frame opening detection circuit 260. Connect in parallel to the terminals. Further, the reset signal output terminal of the added frame opening detection circuit 260 is connected to an input port different from the input port to which the reset signal output terminal of the existing frame opening detection circuit 260 is connected to the input/output port 205. As a result, the MPU 201 can be temporarily activated separately when the switch SW1 is conducted (the inner frame 12 is opened) and when the switch SW2 is conducted (the front frame 14 is opened). Further, when there is conduction of the switch SW1 (opening of the inner frame 12), there is conduction of the reset signal SG3b output from the existing frame opening detection circuit 260 and conduction of the switch SW2 (opening of the front frame 14). In addition, the reset signal SG3b output from the newly added frame opening detection circuit 260 can be separately output to the input/output port 205.

In addition, the RAM 203 is provided with four flags: an inside-off-frame opening flag, an off-front-side frame opening flag, an on-inside frame opening flag, and an on-front frame opening flag. Then, in the process of S110 of the start-up process (see FIG. 11), the voltage (reset signal SG3b) output from the existing frame open detection circuit 260 to the input/output port 205 is read and the newly added frame open detection is performed. The voltage (reset signal SG3b) output from the circuit 260 to the input/output port 205 may be read. In accordance with the read result, in the process of S112, the OFF inner frame opening flag or the OFF front frame opening flag is individually turned ON.

Then, in the process of S205 of the main process (see FIG. 12), when the OFF inner frame opening flag is turned ON, the MPU 201 transmits an “OFF inner frame opening command” to the voice lamp control device 113 to turn OFF. When the middle front frame opening flag is turned on, the MPU 201 transmits an “off middle front frame opening command” to the voice lamp control device 113. Then, when the voice lamp control device 113 receives each command transmitted from the MPU 201 when the power of the pachinko machine 10 is turned on, the voice lamp control device 113 receives the off-time inner frame opening command and the off-time. Notification is made in a different mode from when the front frame opening command is received. For example, different warning sounds are output from the audio output device 226, and the lighting mode of the lamp display device 227 is changed.

In addition, the pulse width of the pulse signal transmitted from the pachinko machine 10 to the hall computer 262 may be changed in the processing of S206 in accordance with the ON state of each flag of the OFF inner frame opening flag or the OFF front frame opening flag. For example, when the inner frame open flag during off is on, a pulse signal having a pulse width of about 1 msec is transmitted to the hall computer 262, and when the front frame open flag during off is on, the pulse width is about 2 msec. The pulse signal may be transmitted to the hall computer 262. Accordingly, when the power of the pachinko machine 10 is turned off, the pachinko machine 10 can separately notify whether the inner frame 12 has been opened or the front frame 14 has been opened, and the hall It can be stored separately in the computer 262.

Further, in the processing of S217 of the main processing (see FIG. 12), the voltage (reset signal SG3b) output from the existing frame opening detection circuit 260 to the input/output port 205 is read, and the newly added frame opening detection circuit is added. The voltage (reset signal SG3b) output from 260 to the input/output port 205 may be read. In accordance with the read result, in the processing of S219 or S220, the on-inside inner frame opening flag or the on-inside front frame opening flag is individually turned on.

Then, in the process of S208 of the main process (see FIG. 12), when the on-inside inner frame opening flag is turned on, the MPU 201 transmits an “on-inside inner frame opening command” to the voice lamp control device 113 to turn on. When the middle front frame opening flag is turned on, the MPU 201 transmits an "on middle front frame opening command" to the voice lamp control device 113. Then, when the voice lamp control device 113 receives each command transmitted from the MPU 201, the voice lamp control device 113 differs depending on whether an on-inside inner frame opening command is received or an on-inside front frame opening command. A form is notified. For example, different warning sounds are output from the audio output device 226, and the lighting mode of the lamp display device 227 is changed. Accordingly, when the pachinko machine 10 is powered on, the pachinko machine 10 can separately notify whether the inner frame 12 has been opened or the front frame 14 has been opened.

In the present embodiment, the pulse signal output from the pachinko machine 10 is output to the hall computer 262, which is installed at a location different from that of the pachinko machine 10, but the present invention is not limited to this. A dedicated storage device having the function of the hall computer 262 may be provided for each pachinko machine 10, and the dedicated storage device may be provided on the back side of each pachinko machine 10 in which the main controller 110 and the like are provided. In this case, better, the main controller 110, the payout controller 111, and the launch controller 112 store a dedicated storage device in the board box, and the box base and the box cover provided in the board box. And are connected by a sealing unit (not shown) so that they cannot be opened (connection by a caulking structure). Then, a seal sticker (not shown) is attached to the connecting portion between the box base and the box cover across the box cover and the box base.

Next, a pachinko machine according to the second embodiment will be described with reference to FIGS. 21 to 23. The pachinko machine of the second embodiment is a modification of the pachinko machine 10 startup process, timer interrupt process, and main process of the first embodiment. Specifically, the pachinko machine according to the second embodiment is provided with a power-on counter 203c (not shown) in the RAM 203, which starts clocking when the MPU 201 is started up, and the power-on counter 203c can measure the time period. If there is power-off occurrence information within the predetermined period (5.0 seconds or less in the present embodiment), the inner frame 12 or the front frame is displayed when the pachinko machine is powered off. 14 is opened, and the frame open detection circuit 260 determines that the MPU 201 has been temporarily started up, and the off-in-frame open flag 203a is turned on.

According to the pachinko machine of the second embodiment, whether the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off is determined according to the time period of the power-on counter 203c. To do. Therefore, when the inner frame 12 or the front frame 14 is opened while the pachinko machine is powered off, power is supplied from the frame opening detection circuit 260 to the input/output port 205 to open the frame opening detection circuit 260. It is not necessary for the MPU 201 to detect whether the output from the input to the input/output port 205 is high. Therefore, according to the pachinko machine of the second embodiment, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is off, the power is supplied from the frame open detection circuit 260 to the input/output port 205. Compared to the pachinko machine 10 of the first embodiment (power is supplied from the frame opening detection circuit 260 to the input/output port 205 to output from the frame opening detection circuit 260 to the input/output port 205. It is possible to suppress the power consumption stored in the capacitor CD1 by comparing with the pachinko machine 10 of the first embodiment in which the MPU 201 detects whether or not is high.

The power-on counter 203c (not shown) is powered on for the pachinko machine 10 to execute the start-up process (FIG. 21), and a predetermined period (see FIG. 21) from the process (see FIG. 21) of the start-up process described later. In this embodiment, it is a counter that counts whether or not 5.0 seconds has elapsed. The power-on counter 203c is set to "0 (zero)" in the start-up process, starts counting up, and every time the timer interrupt process (see FIG. 22) is executed (every 2 ms). ) The count is incremented by one. When the count-up exceeds "2500 (5.0 seconds)" and becomes "2501", the count-up ends. Therefore, the power-on counter 203c can measure whether or not 5.0 seconds have elapsed since S119 of the startup processing.

Next, with reference to FIG. 21, a startup process executed by the MPU 201 of the pachinko machine according to the second embodiment will be described. FIG. 21 is a flowchart showing a startup process executed by the MPU 201 of the pachinko machine according to the second embodiment. The same parts as those in the startup process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the pachinko machine startup process of the second embodiment, the processes of S110 to S112 of the pachinko machine startup process of the first embodiment are deleted and the processes of S118 and S119 are added. In the pachinko machine startup process of the second embodiment, after the process of S109 or S117, the power-on counter 203c is set to "0 (zero)" (S118). Then, the power-on counter 203c starts counting up (S119). Then, the process proceeds to S113.

The processes of S118 to S119 are executed immediately after the process of S109 is completed or immediately after the process of S117 is completed. That is, the processing of S118 to S119 is executed immediately after the various settings of the MPU 201 are completed. Therefore, when the inner frame 12 or the front frame 14 is opened while the pachinko machine 10 is powered off, the opening can be immediately detected by the processes of S118 to S119.

Next, with reference to FIG. 22, a timer interrupt process executed by the MPU 201 of the pachinko machine according to the second embodiment will be described. FIG. 22 is a flowchart showing the timer interrupt processing executed by the MPU 201 of the pachinko machine of the second embodiment. The timer interrupt process of the pachinko machine of the second embodiment is executed by the MPU 201 of the main control device 110, for example, every 2 msec, like the timer interrupt process of the pachinko machine 10 of the first embodiment. The same parts as those in the timer interrupt process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 15 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the pachinko machine timer interrupt process of the second embodiment, the processes of S506 and S507 are added to the pachinko machine 10 timer interrupt process of the first embodiment. In the timer interrupt process of the pachinko machine of the second embodiment, after the process of S503, it is determined whether the count value of the power-on counter 203c is larger than "2500" (S506). Since the timer interrupt process is executed every 2 msec, if the count value of the power-on counter 203c is “2500”, 2500 (count value)×2 msec is 5.0 sec, which is the process of S119. It indicates that 5.0 seconds have elapsed since the power-on counter 203c started counting up.

If the count value of the power-on counter 203c is equal to or less than "2500" (S506: No), 5.0 seconds have elapsed since the count-up of the power-on counter 203c was started (after the processing of S119 was started). Therefore, the count value of the power-on counter 203c is incremented by "1" (S507). On the other hand, if the count value of the power-on counter 203c is larger than "2500", that is, if the count value of the power-on counter 203c is "2501" (S506: Yes), the count-up of the power-on counter 203c is started. Since 5.0 seconds have elapsed (since the processing of S119 is started), the processing of S507 is skipped and the count-up of the power-on counter 203c is stopped.

It should be noted that if it is determined “Yes” in the process of S506 and if the process of S507 is completed, the process proceeds to the process of S504.

Next, with reference to FIG. 23, a main process executed by the MPU 201 of the pachinko machine according to the second embodiment will be described. FIG. 23 is a flowchart showing main processing executed by the MPU 201 of the pachinko machine of the second embodiment. The same parts as those of the main process of the pachinko machine 10 of the first embodiment described above with reference to FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the main process of the pachinko machine of the second embodiment, the processes of S225 and S226 are added to the main process of the pachinko machine 10 of the first embodiment. In the main processing of the pachinko machine of the second embodiment, after the processing of S222, whether or not the count value of the power-on counter 203c is "2500" or less (S225), that is, the power-on counter 203c is incremented by the processing of S119. It is determined whether or not 5.0 seconds have passed since the start. If the count value of the power-on counter 203c is "2500" or less (S225: Yes), the off-inside frame open flag 203a is turned on (S226), and the process proceeds to S223. Note that when the count value of the power-on counter 203c is "2500" or less, the following two patterns are conceivable, and the off-inside frame open flag 203a is turned on regardless of which pattern occurs.

The first pattern is a case where the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily activated by the frame opening detection circuit 260 while the power of the pachinko machine is turned off. In this case, since the falling edge of the power failure signal SG1b is input to the MPU 201 together with the drive voltage Vb and the reset signal SG3b from the frame open detection circuit 260, the NMI interrupt process (see FIG. 17) is executed, and thus the MPU 201 rises. After the raising process (FIG. 21), it is determined in the process of S213 that there is power-off occurrence information (S213: Yes), and the processes of S221 to S225 are executed. Here, when the MPU 201 is temporarily activated by the frame opening detection circuit 260, the power failure signal SG1b output from the frame opening detection circuit 260 is (the MPU 201 is started when the power failure signal SG1b starts to be output. Then, it will fall in about 4.4 seconds. Therefore, if the count value of the power-on counter 203c is set to "2500" (5.0 seconds), the process is performed before the count value of the power-on counter 203c becomes "2500". The process can be shifted to S225. Therefore, when the power of the pachinko machine is turned off, the inner frame 12 or the front frame 14 is opened, and the MPU 201 is temporarily activated by the frame opening detection circuit 260, the count value of the power-on counter 203c. Is "2500" or less (S225: Yes), it is determined that the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is off, and the off middle frame open flag 203a is turned on. This is done (S226).

The second pattern is that the power of the pachinko machine is turned on, and the power of the pachinko machine is turned off within about 4.4 seconds after the power is turned on. In this case, after the power of the pachinko machine is turned off (before the determination of S213), the power failure signal SG1a output from the power failure monitoring circuit 252 falls and the NMI interrupt processing (see FIG. 17) is executed, In the process of S213, it is determined that there is power-off occurrence information (S213: Yes), and the processes of S221 to S225 are executed. Here, since the count value of the power-on counter 203c is set to "2500" (since it is set to 5.0 seconds), the power of the pachinko machine is turned on, and about 4.4 after the power is turned on. Even when the power of the pachinko machine is turned off within a second, the count value of the power-on counter 203c is determined to be "2500" or less (S225: Yes), and the off-inside frame open flag 203a is turned on (S226).

In this second pattern, since it is necessary to turn on/off the power of the pachinko machine, it cannot be executed by a fraudulent person, and it is limited to the case where it is executed by a store clerk. Therefore, in the case of this second pattern, the clerk can recognize that the OFF inside frame opening flag 203a is turned on by his/her own action, and thus the turned off inside frame opening flag 203a is set to OFF again. can do. Therefore, even in the case of the second pattern, there is no problem even if the off-inside frame open flag 203a is turned on in the process of S226.

In the process of S225, if the count value of the power-on counter 203c is not "2500" or less (S225: No), at least 5.0 seconds have passed since the count-up of the power-on counter 203c was started in the process of S119. Since it does not correspond to any of the above two patterns, the process of S226 is skipped and the process proceeds to S223. Since the frequency with which the above-mentioned two patterns occur is low, 5.0 seconds have elapsed since the count-up of the power-on counter 203c was started in the processing of S119, that is, the count value of the power-on counter 203c is "2500". It is normal to determine that it is not less than or equal to (S225: No).

As described above, according to the pachinko machine of the second embodiment, whether the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off is determined by the power-on counter 203c. In response (determination is made according to whether 5.0 seconds have elapsed since the power-on counter 203c started counting up in S119). Therefore, when the power of the pachinko machine is turned off and the inner frame 12 or the front frame 14 is opened, power is supplied from the frame opening detection circuit 260 to the input/output port 205, and the frame opening detection circuit 260 is input/output port. The MPU 201 does not need to detect whether the output to 205 is high. Therefore, according to the pachinko machine of the second embodiment, when the power of the pachinko machine is turned off and the inner frame 12 or the front frame 14 is opened, power is supplied from the frame opening detection circuit 260 to the input/output port 205. It is not necessary to compare with the pachinko machine 10 of the first embodiment (power is supplied from the frame opening detection circuit 260 to the input/output port 205 so that the output from the frame opening detection circuit 260 to the input/output port 205 is high. (Compared with the pachinko machine 10 of the first embodiment in which the MPU 201 detects whether or not), it is possible to suppress the power consumption stored in the capacitor CD1.

Next, a pachinko machine according to the third embodiment will be described with reference to FIGS. 24 and 25. The pachinko machine of the third embodiment is a modification of the startup process and main process of the pachinko machine 10 of the first embodiment. Specifically, the pachinko machine of the third embodiment outputs a pulse signal having a pulse width of about 1 msec to the hall computer 262 every time the startup process is executed.

According to the pachinko machine of the third embodiment, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 every time the startup process is executed, so that the pachinko machine is powered off. At this time, the fact that the inner frame 12 or the front frame 14 is opened and the MPU 201 is temporarily started up by the frame opening detection circuit 260 can be stored in the hall computer 262 that continues to operate for 24 hours. Thus, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off, a pulse signal of about 1 msec is output to the hall computer 262 to open the hall. Since it is stored in the computer 262, the off-inside frame opening flag 203a that stores that the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off can be eliminated. Therefore, the memory capacity of the RAM 203 can be reduced. Furthermore, the determination regarding the off-inside frame open flag 203a (each process of S110 to S112 in FIG. 11 and S204 to S206 in FIG. 12) can be eliminated, and thus the determination regarding the off-inside frame open flag 203a is performed. The program capacity of can be reduced.

First, the startup process executed by the MPU 201 of the pachinko machine according to the third embodiment will be described with reference to FIG. FIG. 24 is a flowchart showing a startup process executed by the MPU 201 of the pachinko machine according to the third embodiment. The same parts as those in the startup process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the pachinko machine startup process of the third embodiment, the processes of S110 to S112 of the pachinko machine startup process of the first embodiment are deleted and the process of S120 is added. Further, in the pachinko machine startup processing of the third embodiment, the processing content of S116 of the pachinko machine startup processing of the first embodiment is changed to the processing of S121.

In the pachinko machine startup processing of the third embodiment, after the processing of S101, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 (S120). Then, the process proceeds to S102. In the process of S120, since a pulse signal having a pulse width of about 1 msec is output, if it is left as it is, at least about 1 msec is required to complete the process of S120. When shortening the time (about 1 msec) until the process of S120 is completed, the output of the pulse signal to the hall computer 262 is started in the process of S120, and then the process proceeds to S102 and the wait of S102 is performed. It is sufficient to stop the pulse signal being output about 1 msec after the processing of S120 is started within the time. Since the wait process of S102 waits for about 1.0 second, there is no problem even if the process of stopping the pulse signal that started the output in the wait process is executed.

Further, in the pachinko machine startup process of the third embodiment, after the process of S115, the used area of the RAM 203 is cleared to 0 (S121), and then the process proceeds to S117. Since the pachinko machine of the third embodiment does not require the off-inside frame open flag 203a, the process of turning off the off-inside frame open flag 203a performed in the startup process of the pachinko machine 10 of the first embodiment (S116: (Execution within processing) is unnecessary. Therefore, in the processing of S121, only the processing of clearing the used area of the RAM 203 to 0 is executed.

Next, the main processing executed by the MPU 201 of the pachinko machine according to the third embodiment will be described with reference to FIG. FIG. 25 is a flowchart showing main processing executed by the MPU 201 of the pachinko machine according to the third embodiment. The same parts as those of the main process of the pachinko machine 10 of the first embodiment described above with reference to FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the main processing of the pachinko machine of the third embodiment, the processing of S204 to S206 of the main processing of the pachinko machine 10 of the first embodiment is deleted. That is, in the main processing of the pachinko machine of the third embodiment, after the processing of S203, it is determined whether or not the on-frame opening flag 203b is on (S207). If the on-frame open flag 203b is on (S207: Yes), the inner frame 12 or the front frame 14 is open while the power of the pachinko machine is on, so the on-frame open to the voice lamp control device 113. The command is transmitted (S208), and the process proceeds to S210. On the other hand, when the on-frame opening flag 203b is off (S207: No), the inner frame 12 or the front frame 14 is not opened (because the inner frame 12 and the front frame 14 are closed), the voice lamp An on-frame closing command is transmitted to the control device 113 (S209), and the process proceeds to S210.

Here, there is no determination (processing in S204 to S206) for the off-inside frame open flag 203a provided in the pachinko machines of the first and second embodiments for the following reason. That is, in the pachinko machine of the third embodiment, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is off, the pulse width of the pulse to the hall computer 262 is about 1 msec. By outputting the signal, the fact that the inner frame 12 or the front frame 14 has been opened can be stored in the hall computer 262 which continues to operate for 24 hours. As a result, the pachinko machine of the third embodiment does not require the off-in-frame opening flag 203a for storing that the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is off. Become. For this reason, in the pachinko machine according to the third embodiment, there is no determination regarding the off-in-frame opening flag 203a.

As described above, according to the pachinko machine of the third embodiment, since the off-inside frame open flag 203a is unnecessary, the memory capacity of the RAM 203 can be reduced. Further, according to the pachinko machine of the third embodiment, the determination regarding the off-inside frame open flag 203a (the processes of S110 to S112 in FIG. 11 and S204 to S206 in FIG. 12) is not necessary, so the off-inside frame open is performed. It is possible to reduce the program capacity of the process of making the determination regarding the flag 203a.

Further, according to the pachinko machine of the third embodiment, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 every time the startup process is executed, so that the pachinko machine is powered off. The fact that the inner frame 12 or the front frame 14 is released while the frame is open and the MPU 201 is temporarily activated by the frame open detection circuit 260 can be stored in the hall computer 262 that continues to operate for 24 hours. Therefore, the pulse signal stored in the hall computer 262 can identify the pachinko machine in which the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is off. Furthermore, by storing the pulse signal output from the pachinko machine to the hall computer 262 and storing the output time of the output pulse signal, the opening time of the inner frame 12 or the front frame 14 of the specified pachinko machine is stored. The opening time can be detected.

Next, a pachinko machine according to the fourth embodiment will be described with reference to FIGS. 26 and 27. The pachinko machine of the fourth embodiment is a modification of the startup process and main process of the pachinko machine 10 of the first embodiment. Specifically, the pachinko machine of the fourth embodiment determines whether or not the off-inside frame opening flag 203a is on during the startup process, and if the off-inside frame opening flag 203a is on, the audio lamp control device. The off-frame opening command is transmitted to 113, and then a pulse signal having a pulse width of about 1 msec is output to the hall computer 262.

According to the pachinko machine of the fourth embodiment, if the off-inside frame open flag 203a is on, the off-inside frame open command is transmitted to the voice lamp control device 113 in the startup process, and then the hall computer. Since a pulse signal having a pulse width of about 1 msec is output to 262, the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off, and the MPU 201 is temporarily operated by the frame open detection circuit 260. The fact that the pachinko machine is powered on can be immediately recognized when it is turned on next time.

First, with reference to FIG. 26, a startup process executed by the MPU 201 of the pachinko machine according to the fourth embodiment will be described. FIG. 26 is a flowchart showing a startup process executed by the MPU 201 of the pachinko machine according to the fourth embodiment. The same parts as those in the startup process of the pachinko machine 10 according to the first embodiment described above with reference to FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the pachinko machine startup process of the fourth embodiment, the processes of S204 to S206 that were executed in the main process of the pachinko machine 10 of the first embodiment are the processes of S227 to S229, and are added before the process of S113. doing.

In the pachinko machine startup process of the fourth embodiment, it is determined whether or not the off-inside frame open flag 203a is on after it is determined as "No" in the process of S111 or after the process of S112 (S227). .. If the off-inside frame opening flag 203a is on (S227: Yes), an off-inside frame opening command is transmitted to the voice lamp control device 113 (S228). When the voice lamp control device 113 receives the OFF-time frame open command, it controls the voice output device 226 and the lamp display device 227 to start notification that the inner frame 12 or the front frame 14 has been opened. Then, a pulse signal having a pulse width of about 1 msec is output to the hall computer 262 (S229). In addition, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off and the MPU 201 is temporarily started up, power is not supplied to the voice lamp control device 113. Even if the off-frame opening command is transmitted to the voice lamp control device 113, the notification by the voice output device 226 and the lamp display device 227 is not performed. Therefore, even if the fraudulent person opens the inner frame 12 or the front frame 14 while the power of the pachinko machine is turned off, the pachinko machine uses the off-medium frame open flag 203a without being recognized by the fraudster. It is possible to store the opening of the inner frame 12 or the front frame 14 (without the notification by the voice output device 226 and the lamp display device 227, the off-inside frame open flag 203a is used to set the inner frame 12 or the front frame 14). Only open storage can be done).

On the other hand, if the OFF medium frame opening flag 203a is OFF (S227: No), the processes of S228 and S229 are skipped, and the process proceeds to S113.

Next, with reference to FIG. 27, a main process executed by the MPU 201 of the pachinko machine according to the fourth embodiment will be described. FIG. 27 is a flowchart showing main processing executed by the MPU 201 of the pachinko machine of the fourth embodiment. The same parts as those of the main process of the pachinko machine 10 of the first embodiment described above with reference to FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In the main processing of the pachinko machine of the fourth embodiment, the processing of S204 to S206 of the main processing of the pachinko machine 10 of the first embodiment is deleted. That is, in the main processing of the pachinko machine of the fourth embodiment, after the processing of S203, it is determined whether or not the on-frame opening flag 203b is on (S207). If the on-frame open flag 203b is on (S207: Yes), the inner frame 12 or the front frame 14 is open while the power of the pachinko machine is on, so the on-frame open to the voice lamp control device 113. The command is transmitted (S208), and the process proceeds to S210. On the other hand, when the on-frame opening flag 203b is off (S207: No), the inner frame 12 or the front frame 14 is not opened (because the inner frame 12 and the front frame 14 are closed), the voice lamp An on-frame closing command is transmitted to the control device 113 (S209), and the process proceeds to S210.

As described above, according to the pachinko machine of the fourth embodiment, if the off-inside frame opening flag 203a is on, the off-inside frame opening command is transmitted to the voice lamp control device 113 within the startup process, and then Since a pulse signal having a pulse width of about 1 msec is output to the hall computer 262, the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off, and the MPU 201 is opened by the frame open detection circuit 260. The fact that the pachinko machine is powered up temporarily can be immediately recognized when the power of the pachinko machine is turned on next time.

Further, the processing of S228 for transmitting the OFF-in-frame opening command to the voice lamp control device 113 and the processing of S229 for outputting a pulse signal having a pulse width of 1 msec to the hall computer 262 are executed within the pachinko machine startup processing. Therefore, the processes of S228 and S229 can be unexecuted in the main process in which the updating of the fluctuation type counters CS1, CS2, CS3, etc. is repeatedly executed. Therefore, it is possible to prevent the off-frame opening command and the pulse signal from being repeatedly output.

It should be noted that the modification of deleting the processing of S204 to S206 in the main processing performed by the pachinko machine of the fourth embodiment and adding the deleted processing of S204 to S206 before S113 in the startup processing is as follows. You may apply to the pachinko machine of 2 embodiment. Specifically, in the pachinko machine of the second embodiment, the processing of S204 to S206 is deleted from the main processing (see FIG. 23) of the pachinko machine of the second embodiment. Then, the deleted processing of S204 to S206 may be added between S119 and S113 of the pachinko machine startup processing (see FIG. 21) of the second embodiment.

The present invention has been described above based on the embodiment, but the present invention is not limited to the above-mentioned embodiment, and various modifications and improvements are easily possible without departing from the spirit of the present invention. Can be inferred.

It goes without saying that the respective pachinko machines described in the first to fourth embodiments can be combined to realize a pachinko machine having the function of each embodiment.

In the first to fourth embodiments, when the off-inside frame open flag 203a is on, an off-inside frame open command is transmitted to the voice lamp control device 113, and a pulse having a pulse width of 1 msec is sent to the hall computer 262. The signal is output, but is not limited to this. When the OFF middle frame release flag 203a is ON, the main control device 110 does not send a command to the voice lamp control device 113, unlike the pachinko machine according to the first to fourth embodiments, and the hall is opened. While the pulse signal is not output to the computer 262 as well, when the off-inside frame open flag 203a is off, the main control device 110 transmits a command to the voice lamp control device 113 and outputs the pulse signal to the hall computer 262. It may be configured to output. When the main controller 110 is configured in this way, the voice lamp controller 113 supplies the power to the pachinko machine when the command from the main controller 110 is not received within a predetermined time after the power to the pachinko machine is turned on. It may be configured to determine that the inner frame 12 or the front frame 14 is opened during the off state. Similarly, when the hall computer 262 does not receive the pulse signal from the main controller 110 within a predetermined time after the power of the pachinko machine is turned on, it is determined that the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off. It may be configured to make a determination. With the above configuration, it is possible to realize a pachinko machine that does not transmit a command to the voice lamp control device 113 and does not output a pulse signal to the hall computer 262 when the off-inside frame open flag 203a is on.

In the first to fourth embodiments, the pachinko machine outputs a pulse signal having a pulse width of about 1 msec to the hall computer 262 to cause the hall computer 262 to store the opening of the inner frame 12 or the front frame 14. , But not limited to this. For example, a pachinko machine is provided with an EEPROM (Electronically Erasable and Programmable Read Only Memory) and a backup RAM. Then, the EEPROM or backup RAM and the input/output port 205 are connected via a bus line. With this configuration, the opening of the inner frame 12 or the front frame 14 can be stored in the EEPROM or the backup RAM. Then, when the power of the pachinko machine is turned on, the storage of the EEPROM or the backup RAM is confirmed by the MPU 201. Thereby, the opening of the inner frame 12 or the front frame 14 can be detected by using a pachinko machine without using the hall computer 262. That is, the role of the hall computer 262 can be assigned to the EEPROM or the backup RAM (the role of the "specific device" described in the claims can be assigned to the EEPROM or the backup RAM). The RAM 203 may be used as the backup RAM.

Further, in the first to fourth embodiments, the drive voltage, the reset signal SG3, and the power failure signal SG1 are output from the frame opening detection circuit 260 and the target to be temporarily started is the MPU 201, but the present invention is not limited to this. is not. For example, if a CPU (MPU) different from the MPU 201 and a RAM are provided in the main controller 110 and the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off, The CPU (MPU) and the RAM may be temporarily activated by the frame open detection circuit 260. Specifically, first, the off-inside-frame opening flag 203a is provided in the separately provided RAM. Then, the power supply output terminal, the reset signal output terminal, and the power failure signal output terminal of the frame opening detection circuit 260 are connected to a CPU (MPU) separately provided, and the RAM provided separately at the power supply output terminal of the frame opening detection circuit 260. Connect. Further, a separately provided CPU (MPU) and a separately provided RAM are connected. As a result, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned off, the CPU (MPU) and RAM separately provided by the frame open detection circuit 260 temporarily rise. The off-inside frame open flag 203a provided in another RAM is turned on. Therefore, when the inner frame 12 or the front frame 14 is opened when the power of the pachinko machine is turned off, the opening can be stored by the RAM provided separately. The frame open detection circuit 260, a CPU (MPU) provided separately, and a RAM provided separately may be integrated into a one-chip integrated circuit. In this case, the signals (driving voltage Vb, power failure signal SG1b, and reset signal SG3b) output from the frame opening detection circuit 260 are directly input to the CPU (MPU), so that the first to third embodiments can be used. The multiplexers MP1 to MP3 used in the pachinko machine are unnecessary. Further, the separately provided CPU (MPU) and the separately provided RAM may be provided inside the main control device 110, for example, inside the power supply device 115 outside the main control device 110.

Further, in the first to fourth embodiments, the voltage output from the OUT terminal of the timer IC1 provided in the frame open detection circuit 260 is the inner frame 12 or the front frame depending on the time constant of the resistor R1 and the capacitor CD2. It was set to zero volts about 14 seconds after 14 was opened, but it is not limited to this. For example, if the resistance value of the resistor R1 is set to 200 kΩ, the capacitance value of the capacitor CD2 is set to 10 μF, and the time constant is set to about 2 seconds, the voltage output from the OUT terminal of the timer IC1 is set to the inner frame 12 or the front surface. About 2 seconds after the frame 14 is opened, the voltage can be set to zero volt. Therefore, the startup process (see FIG. 11) which is a process executed when the MPU 201 is temporarily booted by the frame open detection circuit 260 and the processes of S201 to S213: Yes to S224 of the main process (see FIG. 12). ) Can be executed in a relatively short time (specifically, the above process is performed for about 2 seconds when the inner frame 12 or the front frame 14 is opened and a voltage is output from the OUT terminal of the timer IC 1). In the case where the reset signal SG3 output from the reset signal output terminal of the frame opening detection circuit 260 can be executed within a total of 7 seconds, which is about 5 seconds until the reset signal SG3 is reduced to about 4.3 volts), As described above, by setting the time constant to about 2 seconds, the output period of the voltage output from the OUT terminal of the timer IC 1 after the inner frame 12 or the front frame 14 is opened can be suppressed to about 2 seconds. .. Therefore, when the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is off, it is possible to suppress the power consumption stored in the capacitor CD1.

Further, in the first to fourth embodiments, when the inner frame 12 or the front frame 14 is opened, the notification is executed using the voice lamp control device 113, but the present invention is not limited to this. .. When the inner frame 12 or the front frame 14 is opened, the notification may be performed using the display control device 114 in addition to the notification using the voice lamp control device 113. In this case, when the audio lamp control device 113 receives the OFF inside frame opening command or the ON inside frame opening command, the audio lamp control device 113 receives the OFF inside frame opening command or the ON inside frame opening command received by the display control device 114. To send. Then, when the display control device 114 receives the off-inside frame opening command or the on-inside frame opening command, it starts displaying "Check" or "The door is open" on the third symbol display device 81. Just configure it. With this configuration, not only the notification of the voice lamp control device 113 but also the notification of the display control device 113 is performed. Therefore, it is possible to notify the unspecified number of people that the inner frame 12 or the front frame 14 has been opened more easily. it can.

Further, in the first to fourth embodiments, the signals (driving voltage Va, power failure signal SG1a and reset signal SG3a) output from the power supply device 115 and the signals (driving voltage Vb, The switching between the power failure signal SG1b and the reset signal SG3b) is performed using the multiplexers MP1 to MP3, but the invention is not limited to this. Switching between the signals (driving voltage Va, power failure signal SG1a and reset signal SG3a) output from the power supply device 115 and the signals (driving voltage Vb, power failure signal SG1b and reset signal SG3b) output from the frame opening detection circuit 260, Instead of the multiplexers MP1 to MP3, three OR circuits which are OR circuits may be used.

Further, in the first to fourth embodiments, in the processing of S218 for determining whether the inner frame 12 or the front frame 14 is opened while the power of the pachinko machine is turned on, and the processing of S218. Depending on the determination, the process of S219 for turning on the on-frame opening flag 203b and the process of S220 for turning off the on-frame opening flag 203b were executed in the remaining time of the main process, but this is not the only case. Not a thing. The processing of S218 to S220 may be executed within the regular processing of the 4 msec cycle of the main processing. Further, the processes of S218 to S220 may be executed within the timer interrupt process executed every 2 ms.

Further, in the first embodiment, the second embodiment, and the fourth embodiment, when the off-inside-frame opening flag 203a is on, the sound output device 226 and the lamp display device 227 are used to notify and the hall is displayed. A pulse signal of 1 msec was output to the computer 262, but the invention is not limited to this. That is, when the off-inside frame open flag 203a is on, a 1 msec pulse signal is not output to the hall computer 262, and only the notification is performed using the audio output device 226 and the lamp display device 227. May be. On the contrary, when the off-inside frame open flag 203a is on, the sound output device 226 and the lamp display device 227 are not used for notification, and only the pulse signal is output to the hall computer 262. It may be configured.

Further, for example, in each of the above-described embodiments, each command is transmitted from the main control device 110 to the voice lamp control device 113, and the display instruction is issued from the voice lamp control device 113 to the display control device 114. However, the command may be directly transmitted from the main controller 110 to the display controller 114. It is also possible to connect an audio lamp control device to the display control device, and to transmit a command for outputting each voice and lighting the lamp from the display control device to the audio lamp control device. Further, the voice lamp control device and the display control device may be configured as one control device.

Further, in the above-described embodiment, the winning of the first entrance 64 and the passage of the second entrance 67 are configured to be held up to four times at maximum, but the maximum number of holdings is four times. The number of times is not limited, and may be set to 3 times or less, or 5 times or more (for example, 8 times). In addition, the number of times the variable display is held based on the winning in the first entrance 64 is also changed by a number or the number of times the four divided areas are held even in a part of the third symbol display device 81. A mode (for example, a color or a lighting pattern) may be displayed, and a light emitting member such as a lamp is provided separately from the first symbol display device 37, and the number of holdings is notified by the light emitting member. You may do it.

Further, as shown in the above-mentioned embodiment, the variable display, which is a kind of dynamic display, is not limited to scrolling the symbol as the identification information in the vertical direction on the display screen of the third symbol display device 81, The symbols may be moved and displayed along a predetermined path such as a lateral direction or an L-shape. Further, the dynamic display of the identification information is not limited to the variable display of the symbols, and for example, one or a plurality of characters may be displayed together with the symbols, or may be displayed in various motions or changed in addition to the symbols. It also includes a display effect that is displayed. In this case, one or more characters are used as the third symbol.

The present invention may be applied to a pachinko machine or the like of a type different from the above embodiment. For example, it may be implemented in a so-called second-class pachinko gaming machine having a winning device having a special area such as a V zone. Further, in addition to a pachinko machine, it may be implemented as another game machine such as an arepachi or a sparrow ball.

The present invention may be applied to a pachinko machine or the like of a type different from the above embodiment. For example, once a big hit occurs, a pachinko machine (commonly called a 2nd right property, a 3rd right property, etc.) that can increase the jackpot expected value until a big hit state occurs multiple times (for example, 2 or 3 times) including that. It is also possible to carry out. Further, it may be implemented as a pachinko machine for generating a special game that gives a predetermined game value to a player on condition that a ball is won in a predetermined area after the jackpot pattern is displayed. Further, it may be implemented in a pachinko machine which is in a special game state, having a winning device having a special area such as a V zone and winning a ball in the special area as a necessary condition. Further, in addition to the pachinko machine, it may be implemented as various game machines such as arepaches, sparrow balls, slot machines, and game machines in which so-called pachinko machines and slot machines are integrated.

In the slot machine, for example, a symbol is changed by operating the operation lever in a state where a coin is inserted and the symbol effective line is determined, and by operating the stop button, the symbol is stopped and confirmed. It is a thing. Therefore, the basic concept of the slot machine is that "a display device for confirming and displaying the identification information after variably displaying the identification information sequence including a plurality of identification information is provided, which is caused by the operation of the starting operation means (for example, the operation lever). The variable display of the identification information is started by the operation of the stop operation means (for example, the stop button) or when a predetermined time elapses, the variable display of the identification information is stopped and confirmed, and then stopped. It becomes a slot machine that generates a special game that gives a predetermined game value to the player, provided that the combination of identification information at the time is specific".In this case, the game medium is typically a coin, medal, etc. As an example.

Further, as a specific example of a gaming machine in which a pachinko machine and a slot machine are fused, a display device for confirming and displaying the symbols after variably displaying a symbol row consisting of a plurality of symbols is provided, and a handle for ball launching is provided. Some are not. In this case, after throwing in a predetermined amount of balls based on a predetermined operation (button operation), the fluctuation of the symbol is started, for example, due to the operation of the operation lever, or due to, for example, the operation of the stop button, or By the passage of time, the fluctuation of the symbol is stopped, and a special game that gives a predetermined game value to the player is generated as a necessary condition that the definite symbol at the time of stop is a so-called jackpot symbol, and the player is caused to do so. Is a large amount of balls dispensed to the lower tray.

In the following, in addition to the gaming machine of the present invention, the concept of various inventions included in the above-described various embodiments will be shown. In a gaming machine including a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing relating to game control, a door opening detection means that detects opening of the door body with respect to the main body, and Storage means for storing detection of the opening of the door body by the door opening detection means; and when the opening of the door body is detected by the door opening detection means, the opening detection is stored based on the calculation processing of the calculation means. When the opening of the door body is detected by the door opening detecting means to be stored in the means during the power-off of the gaming machine, the storing means, the memory executing means, and the calculating means are activated for a predetermined period. And a start-up means for enabling storage of the release detection by the storage execution means, the gaming machine A1.

According to the gaming machine A1, even when the power of the gaming machine is turned off and the computing means is stopped, when the opening of the door is detected by the door opening detection means, the startup means is the storage means, The storage executing means and the calculating means are activated for a predetermined period of time so that the storage executing means can store the door open detection. Therefore, for example, even if the door body is opened by a person's fraudulent activity after the game is closed with all the game machines powered off, the storage execution means stores the door body open detection in the storage means. You can Therefore, the opening of the door can be grasped even when the power of the gaming machine is turned off.

The computing means is generally provided in the space formed by the door body and the main body. Further, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side (including the back surface side of the main body) of the door body that cannot be touched when the door body is closed.

The gaming machine A1 is provided with off-time operating means that is charged while the power of the gaming machine is on and that enables the memory means, the memory executing means, the computing means, and the rising means to operate with the charged electric power. A game machine A2 characterized by.

According to the gaming machine A2, the gaming machine A2 is provided with the off-time operating means to be charged while the power of the game machine is on, and the storage means, the memory executing means, the computing means and the startup means are charged to the off-time operating means. Operates on electricity. Therefore, the storage means, the storage execution means, the calculation means, and the startup means can be operated even after the power of the game machine is turned off.

In the gaming machine A1 or A2, the rising means is one of the storage means, the storage executing means, and the computing means when the opening of the door is detected by the door opening detecting means while the power of the gaming machine is off. An operation period determining unit that determines an operation period as a first operation period, and an operation period of the storage unit, the storage executing unit, and the calculating unit when the first operation period determined by the operation period determining unit ends And a second operation period extended by the extension unit and a first operation period determined by the operation period determination unit, the sum of the second operation period and the first operation period being the predetermined period. The extension means is configured to operate the storage means, the storage execution means, and the calculation means with less power than the power consumed by the operation period determination means.

According to the gaming machine A3, when the first operation period determined by the operation period determining means has ended, that is, when the first operation period has elapsed, the extending means causes the storage means, the storage executing means, and the calculation. The operating period of the means is extended to the second operating period. Here, the sum of the first operating period determined by the operating period determining unit and the second operating period extended by the extending unit is set as a predetermined period during which the rising unit starts up the storage unit, the storage execution unit and the calculation unit. There is. Therefore, of the predetermined period, the period in which the power filled in the off-time operating unit is consumed by the operating period determining unit is limited to the first operating period, and thereafter the extending unit that consumes less power than the operating period determining unit does. The storage means, the storage execution means, and the calculation means can be operated. Therefore, it is possible to suppress the consumption of the electric power charged in the off-time operating means, increase the operable number of times of the storage means, the storage executing means, the arithmetic means, and the rising means, and increase the detectable number of times the door body is opened.

In the gaming machine A3, the operation period determination means, when the door opening detection means detects the opening of the door body in a period shorter than the first operation period, the storage means, the storage execution means and the calculation means. The first operation period, which is the operation period, is set to the short operation period, and the extension means, after the end of the short operation period determined by the operation period determination means, the storage means, the storage execution means, and the calculation means. Is extended to a second operation period, and the second operation period extended by the extension means is set to a period in which the storage of the release detection by the storage execution means can be executed. A game machine A4.

According to the gaming machine A4, when the door opening detection means detects the opening of the door body in a period shorter than the first operation period, the operation period determination means operates the storage means, the storage execution means, and the operation means. Let the period be its short operating period. Then, after the short operation period determined by the operation period determination means ends, the extension means extends the operation period of the storage means, the storage execution means, and the calculation means to the second operation period. The second operation period is set to a period in which the storage executing means can store the door open detection. Therefore, even if the door is opened within a short period, the detection of opening the door can be surely stored in the storage means by the storage execution means. In addition, when the door is opened within a short period, the period during which the electric power charged in the off-time operating unit is consumed by the operating period determining unit can be limited to a short period. Therefore, it is possible to suppress the consumption of the electric power charged in the operating means during OFF, increase the number of operations of the storage means, the storage execution means, the calculation means, and the rising means, and increase the number of times the door can be opened. ..

In the gaming machine A3 or A4, the extension means operates in the off state when the operation period of the storage means, the storage execution means and the arithmetic means is within the first operation period determined by the operation period determination means. While being filled with the electric power supplied by the means, when the first operation period determined by the operation period determining means ends, the charged electric power is used to perform the storage means, the storage executing means, and the calculation. A gaming machine A5, characterized in that it supplies power to the means and extends its operation period to a second operation period.

According to the gaming machine A5, when the operation period of the storage unit, the storage execution unit and the calculation unit is within the first operation period determined by the operation period determination unit, the extension unit is supplied by the off-state operation unit. Filled with electric power. On the other hand, when the first operation period determined by the operation period determination means has ended, the extension means supplies electric power to the storage means, the storage execution means, and the calculation means by using the charged electric power. The power supply of the extension means extends the operation period of the storage means, the storage execution means, and the calculation means to the second operation period. As described above, by reliably executing the filling from the off-time operating means to the extending means, the extending means can reliably extend the operation period of the storage means, the storage executing means, and the calculating means to the second operation period. it can.

In any of the gaming machines A3 to A5, the arithmetic means inputs a drive voltage input means for inputting a drive voltage for enabling the arithmetic means and an operation signal for making the arithmetic processing executable. And an operation signal inputting means, wherein the rising means drives the driving voltage inputting means to the driving voltage inputting means when the opening of the door is detected by the door opening detecting means while the gaming machine is powered off. An operation signal for outputting the operation signal to the operation signal input means when the opening of the door body is detected by the door opening detection means for supplying a voltage while the power of the gaming machine is off. Output means for stopping the operation signal output by the operation signal output means during the second operation period extended by the extension means, and thereafter, the drive voltage supplied by the drive voltage supply means. A gaming machine A6, which stops the game.

According to the gaming machine A6, when the opening of the door is detected by the door opening detection means while the gaming machine is powered off, the operation signal is output from the operation signal output means of the rising means to the operation signal input means of the arithmetic means. At the same time, the drive voltage is supplied from the drive voltage supply means of the rising means to the drive voltage input means of the arithmetic means. Then, the rising means first stops the operation signal output by the operation signal output means during the second operation period extended by the extension means, and thereafter, the drive voltage supplied by the drive voltage supply means. To stop. Therefore, the calculation means is first set to a state in which the calculation processing cannot be executed, and then is stopped. Therefore, even if the opening of the door body is detected by the door opening detection means while the gaming machine is powered off and the calculation means is started by the startup means for a predetermined period, the calculation means is stopped during the second operation period. You can

In the gaming machine A6, the arithmetic means is configured to be able to start up when the drive voltage input to the drive voltage input means is a first value or more, and the operation signal output means is the extension means. When connected and the voltage supplied by the extension means is a second value or more that exceeds the first value, the supplied voltage is output to the operation signal input means as the operation signal, When the voltage supplied by the extension means becomes less than the second value that exceeds the first value, the operation signal output to the operation signal input means is stopped, and the drive voltage supply means, A gaming machine A7, which is connected to the extension means and outputs the supplied voltage as the drive voltage to the drive voltage input means regardless of the voltage supplied by the extension means. ..

According to the gaming machine A7, both the operation signal output means and the drive voltage supply means are connected to the extension means. When the voltage supplied by the extension means is a second value or more that exceeds the first value, the operation signal output means of the rising means uses the supplied voltage as an operation signal and the operation signal output means of the arithmetic means. Output to. On the other hand, the operation signal output means of the rising means stops the operation signal output to the operation signal output means of the arithmetic means when the voltage supplied by the extension means is less than the second value. Unlike the operation of the operation signal output means, the drive voltage supply means outputs the supplied voltage as a drive voltage to the drive voltage input means of the arithmetic means regardless of the voltage supplied by the extension means. That is, even when the voltage supplied by the extension means becomes less than the second value, the drive voltage supply means continues to output the supplied voltage as the drive voltage to the drive voltage input means of the arithmetic means. Here, the arithmetic means is configured to be able to start up (operable) when the drive voltage input to the drive voltage input means is equal to or higher than the first value. Therefore, even if the drive voltage supplied from the drive voltage supply means of the rising means to the drive voltage input means of the arithmetic means is less than the second value and is equal to or higher than the first value, the arithmetic means is kept activated. You can (can continue to operate). As a result, the calculation means is first set to a state in which the calculation processing cannot be executed, and then is stopped. Therefore, even if the opening of the door body is detected by the door opening detection means while the gaming machine is powered off, and the calculation means is started by the rising means for a predetermined period, the calculation means can be lowered during the second period. it can.

In a gaming machine including a main body, a door body that opens and closes the front surface of the main body, and a computing unit that executes a computation process related to game control, a door opening detection unit that detects opening of the door body with respect to the main body, Storage means capable of holding the opening detection of the door body by the door opening detection means even when the power of the gaming machine is turned off, and opening of the door body is detected by the door opening detection means while the power of the gaming machine is turned off. In this case, the storage means and the arithmetic means are provided with a startup means for starting up within a predetermined period, and an off-state operating means for supplying electric power to the startup means. A gaming machine B1 characterized by comprising a storage execution process for holding the opening detection of the door body in the storage means when the arithmetic means is activated by the upper means within a predetermined period.

According to the gaming machine B1, even when the power of the gaming machine is turned off and the computing means is finished, when the opening of the door is detected by the door opening detecting means, the electric power supplied by the off-operation means is used. The start-up means starts up the storage means and the calculation means within a predetermined period. Then, the arithmetic means that has been started up within the predetermined period executes the storage execution processing, and causes the storage means to hold the door body open detection. Therefore, for example, even if the door body is opened by someone's fraudulent activity after the game is closed with all the gaming machines powered off, the door execution detection is stored by the storage execution process executed by the computing means. It can be held by the means. Therefore, the opening of the door can be grasped even when the power of the gaming machine is turned off.

In the gaming machine B1, the arithmetic processing executed by the arithmetic means includes termination processing for terminating the activated arithmetic means, and the termination processing and the storage execution processing are activated by the arithmetic means by the activation means. A gaming machine B2, characterized in that the processing is completed within a predetermined period.

According to the gaming machine B2, even if the opening of the door body is detected by the door opening detecting means while the gaming machine is powered off, and the calculating means is started by the rising means, the calculating means executes the storage execution process and the end. The processing can be completed within a predetermined period. Therefore, even if the door body is opened while the power of the gaming machine is turned off, the opening detection of the door body can be held in the storage means by the storage execution processing, and the arithmetic means started within a predetermined period can be stored. It can be terminated by termination processing.

In the gaming machine B1 or B2, a detection signal receiving means for receiving a detection signal indicating the detection of opening the door body by the door opening detection means is provided, and the rising means opens the door body by the door opening detection means. When detection is made, detection signal output means for outputting a detection signal to the detection signal receiving means is provided, and when opening of the door body is detected by the door opening detection means during power off of the gaming machine. Means to activate the storage means, the computing means, the detection signal output means, and the detection signal receiving means within a predetermined period, and the computing means receives the detection signal by the detection signal receiving means. In this case, the game machine B3 executes the storage execution process.

According to the gaming machine B3, when the opening of the door is detected by the door opening detecting means while the power of the gaming machine is off, the rising means includes the storage means, the calculating means, and the detection signal output means for outputting the detection signal. The detection signal receiving means for receiving the detection signal is activated within a predetermined period. Then, when the detection signal output from the detection signal output unit is received by the detection signal receiving unit, the calculation unit executes the storage execution process to hold the door opening detection in the storage unit. In other words, the calculation means executes the storage execution processing only when the detection signal receiving means receives the detection signal after being started by the rising means within a predetermined period. Therefore, when the door is surely opened while the power of the gaming machine is turned off, the storage execution process by the calculation means can be executed for the first time.

In the gaming machine B1 or B2, the gaming means is provided with timing means for timing the operation period of the computing means, and the rising means detects the opening of the door body by the door opening detection means while the power of the gaming machine is off. In this case, the storage means, the computing means, and the clocking means are started up within a predetermined period, and the computing means has an operation period clocked by the clocking means within a predetermined second period. Nevertheless, when the end process is executed, the memory execution process is executed assuming that the door is opened while the power of the game machine is off. ..

According to the gaming machine B4, when the opening of the door body is detected by the door opening detecting means while the gaming machine is powered off, the rising means measures the storage means, the calculating means, and the operating means. Is started within a predetermined period. When the operation means executes the ending process despite the operation period timed by the timekeeping means being within the predetermined second period, the door body is opened while the power of the gaming machine is off. The storage execution process is executed as. In other words, the calculation means executes the storage execution processing for the first time when it is started by the startup means within the predetermined period and then the end processing is executed within the second period. Therefore, when it is determined that the opening of the door body is surely performed during the power-off of the gaming machine due to the operation period of the timing means, the storage execution processing by the computing means can be executed for the first time.

The gaming machine B3 or B4 is provided with a backup means capable of retaining data even after the power of the gaming machine is turned off, and the arithmetic processing executed by the arithmetic means determines whether or not the data retained in the backup means is valid. Judgment processing, return processing for returning to the state before power-off by using the data held in the backup means when judged to be valid by the judgment processing, and non-valid judged by the judgment processing In this case, an initialization process for initializing the data held in the backup means is provided, and the start of reception of the detection signal by the detection signal receiving means or the start of timing of the operation period by the timing means is the restoration processing or the initial stage. The gaming machine B5, which is performed immediately after the execution of any one of the activation processing.

According to the gaming machine B5, after the door opening detection means detects the opening of the door body during the power-off of the gaming machine, and the start-up means activates the computing means within a predetermined period, after the return processing or in the initial stage. Immediately after the conversion processing, that is, immediately after the various settings of the computing means are completed, the detection signal receiving means starts the reception of the detection signal or the time counting means starts the time counting of the operation period. Therefore, when the door is opened while the power of the gaming machine is off, the opening of the door can be immediately detected.

In the gaming machine B5, an informing means for informing when the door opening detection is held in the storage means by the storage execution processing is provided, and the informing means is provided when the power of the gaming machine is turned on. On the other hand, while the startup is performed, even if the opening of the door body is detected by the door opening detection means during the power-off of the gaming machine, the startup by the startup means is not executed. A gaming machine B6 characterized by being a thing.

According to the gaming machine B6, the notifying means performs the startup when the power of the gaming machine is turned on, and gives the notification when the storage means holds the door body open detection. On the other hand, the notification means does not execute the start-up by the start-up means even if the door-opening detection means detects the opening of the door body while the power of the gaming machine is off (the start-up means also starts up). Never be). In other words, the notification means is started up when the power of the gaming machine is turned on, but during the power off of the gaming machine, the door opening detection means detects the opening of the door body, and the rising means calculates Even if the means is started within the predetermined period, the start-up means does not start it. Therefore, for example, even if the door body is opened by a fraudulent person after the power is turned off for all the gaming machines and the door body open detection is held in the storage means by the storage execution processing, the notification means Will not be notified. Therefore, the fact that the door is opened while the power of the gaming machine is off can be held in the storage means without being noticed by a fraudulent person. Further, if the power of the gaming machine is turned on and the detection of the opening of the door body is held in the storage means, the notification means notifies the player. Therefore, the gaming machine in which the door body is opened while the power is off Can be specified.

In the gaming machine B6, an erasing means for setting the opening detection of the door body held in the storage means to the erasable state by the storage execution processing is provided, and the opening detection of the door body held in the storage means is performed. The release detection is set to an erasable state by the erasing means, and the erasing is executed when the power of the gaming machine is turned on and the arithmetic means is started up. A gaming machine B7.

According to the gaming machine B7, the opening detection of the door body held in the storage means is set to the state in which the opening detection of the door body can be erased by the erasing means, and the power of the gaming machine is turned on and the computing means is operated. When it is started up, it is erased. That is, firstly, when the opening detection of the door is set to the erasable state by the erasing means, and secondly, when the arithmetic means is started by turning on the power of the gaming machine, it is held in the memory means for the first time. The detected opening of the opened door is deleted. Therefore, once the door body open detection is held in the storage means, the door body open detection cannot be erased from the storage means unless the above procedure is performed. Therefore, when the door opening detection is held in the storage unit, it is possible to make it difficult for a fraudulent person to erase the door opening detection.

In any of the gaming machines B1 to B7, an output means for outputting a predetermined signal to a specific device based on the arithmetic processing of the arithmetic means is provided, and the rising means is capable of opening the door body by the door opening detection means. When detected while the power of the gaming machine is off, the output means is started up within a predetermined period, and the arithmetic processing executed by the arithmetic means is a detection of opening of the door body by the storage execution processing. When held in the storage means, an output process for outputting the door opening detection as a predetermined signal to the output means is provided, and the output processing is within a predetermined period in which the calculation means is started by the rising means. A gaming machine B8, characterized in that the processing is completed by.

According to the gaming machine B8, when the opening of the door body is detected by the door opening detecting means while the gaming machine is powered off, the rising means starts up the output means in addition to the storage means and the calculating means within a predetermined period. .. Then, the arithmetic means started up within a predetermined period executes an output process, and causes the output means to output the door open detection as a predetermined signal. Here, this predetermined signal is output to the specific device. Therefore, for example, even if the door body is opened by someone's cheating after closing all the power off gaming machines, it is possible to determine the gaming machine with the door opened by the specific device. ..

It should be noted that one specific device may receive a predetermined signal output from the output means provided for each of a plurality of gaming machines, or a specific device may be provided for each gaming machine, and the specific device may be provided for each gaming machine. You may arrange. When arranging the identifying device in each gaming machine, the box base and the box cover that covers the opening of the box base are connected to each other, and are identified in the space formed by the box cover and the box base. Store the device. Then, the box cover and the box base are connected in an unopenable manner by the sealing unit. Further, a seal sticker is attached to the connecting portion between the box cover and the box base, extending over the box cover and the box base. Then, the specific device may be provided on the back surface or the back surface side of the door body.

In a gaming machine including a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing relating to game control, a door opening detection means that detects opening of the door body with respect to the main body, and A gaming machine C1 characterized by further comprising a computing start-up means for starting the computing means for a predetermined period when the opening of the door body is detected by the door opening detecting means while the power of the gaming machine is off. ..

According to the gaming machine C1, even when the power of the gaming machine is turned off and the computing means is stopped, when the door opening detecting means detects the opening of the door body, the computing starting means causes the computing means to operate. For a predetermined period. Therefore, it is possible to use the arithmetic means that has been started up for a predetermined period of time, for example, to store the door opening detection, or to output the door opening detection to a specific device (specific device). it can.

In a gaming machine including a main body, a door body that opens and closes the front surface of the main body, and an arithmetic means that performs arithmetic processing relating to game control, a door opening detection means that detects opening of the door body with respect to the main body, and When the opening of the door is detected by the door opening detecting means while the power of the gaming machine is off, the calculation starting means for starting the calculation means for a predetermined period and the calculation started by the calculation starting means An amusement machine D1 provided with an output means for outputting detection of opening of the door body to a specific device based on arithmetic processing of the means.

According to the gaming machine D1, even if the power of the gaming machine is turned off and the computing means is stopped, when the door opening detecting means detects the opening of the door body, the computing starting means causes the computing means to operate. It is launched for a predetermined period. Then, based on the arithmetic processing of the activated arithmetic means, the output means outputs the door opening detection to the specific device. Therefore, for example, even if the door body is opened by someone's fraudulent activity after closing all the gaming machines with the power turned off, the door body open detection can be output to the specific device. Therefore, the opening of the door can be grasped even when the power of the gaming machine is turned off.

Based on the main body, the door body that opens and closes the front surface of the main body, the main calculation means that executes the calculation processing related to the game control, and the calculation processing related to the control of the electric device based on the signal output from the main calculation means. In a gaming machine provided with a sub-calculation means for performing, a main calculation means, a sub-calculation means and a power supply means for supplying drive power to an electric device, a door opening detection means for detecting opening of the door body with respect to the main body, A holding means capable of holding the opening detection of the door body by the door opening detection means even when drive power from the power supply means is not supplied; and a case where drive power from the power supply means is not supplied. When the door opening detection means detects the opening of the door body, the holding means and the main calculation means are started for a predetermined period of time to hold the door body open detection in the holding means; When the driving power from the power supply means is not supplied and the opening of the door is detected by the door opening detection means, the off-state operating means for supplying the driving power to the rising means and the power supply means Output means for outputting a predetermined signal according to the holding state of the holding means for holding the opening detection of the door body when drive power is supplied to the main calculation means, the sub-calculation means and the electric device. A gaming machine E1 characterized in that.

According to the gaming machine E1, even when the driving power is not supplied from the power supply means to the main calculation means, the sub calculation means and the electric device, when the door opening detection means detects the opening of the door body, the rising means. Causes the holding means and the main calculation means to be started for a predetermined time by the driving power supplied by the off-state operating means, and causes the holding means to hold the detection of opening of the door body. Then, when the driving power is supplied from the power supply means to the main calculation means, the sub calculation means and the electric device, the output means outputs a predetermined signal according to the holding state of the holding means. Therefore, for example, even if the door body is opened by a fraudulent act by somebody after the store is closed when the driving power is not supplied by the power source means in all gaming machines, the opening of the door body is held and the power source means is used. A predetermined signal can be output when drive power is supplied. Therefore, when the driving power from the power supply means is not supplied, that is, when the power of the gaming machine is turned off, it is possible to grasp the opening of the door body.

In the gaming machine E1, the main calculation means is normally executed once when the drive power is supplied from the power supply means and after the start-up processing, and repeatedly executes a plurality of calculation processing. The output control process includes a process and an output control process for causing the output unit to output a second predetermined signal to the sub-calculation unit according to a holding state of a holding unit that holds the opening detection of the door body. The gaming machine E2, which is executed within the start-up process and then shifts to the normal process.

According to the gaming machine E2, drive power is supplied by the power supply means in the output control processing for causing the output means to output the second predetermined signal to the sub-calculation means in accordance with the holding state of the holding means for holding the door opening detection. If it is done, it is executed within the start-up process of the main calculation means that is executed once. In this way, when the driving power is supplied from the power supply means, the output control processing is immediately executed and the second predetermined signal is output to the sub-calculation means, so that it is performed when the power of the gaming machine is off. The opening of the opened door can be immediately grasped by the sub-calculation means. When the second predetermined signal is output to the sub-calculation unit, the sub-calculation unit controls, for example, the electric device to give a notification. Further, since the output control processing is executed within the startup processing of the main processing means, it is possible to make the output control processing non-executed in the normal processing in which a plurality of arithmetic processings are repeatedly executed.

In the gaming machine E1 or E2, the main computing means is provided separately from the main computing means and is electrically connected to a specific device for detecting an operating status of the gaming machine, and the startup means is When the door opening detection means detects the opening of the door body when the drive power from the power supply means is not supplied, a third predetermined signal is sent to the specific device according to the holding state of the holding means. A gaming machine E3, characterized in that the third output means for outputting is started for a predetermined period.

According to the gaming machine E3, when the door opening detection means detects the opening of the door body while the driving power from the power supply means is not supplied, the rising means starts the third output means for a predetermined time. Then, the third output means outputs the third predetermined signal to the specific device in accordance with the holding state of the holding means that holds the detection of opening the door. Therefore, when the drive power from the power supply means is not supplied, that is, when the opening of the door body is detected by the door opening detection means when the power supply of the gaming machine is turned off, at that time, The specific device can grasp the opening of the door body performed while the power of the game machine is turned off.

In the gaming machine E3, the main calculation means causes the third output means to output a third predetermined signal to the specific device according to the holding state of the holding means that holds the opening detection of the door body. A gaming machine E4 comprising a process, wherein the third output control process is executed in the start-up process, and then the process shifts to the normal process.

According to the gaming machine E4, the third output control processing for outputting the third predetermined signal to the specific device by the third output means is driven by the power supply means in accordance with the holding state of the holding means for holding the opening detection of the door body. This is executed within the startup process of the main calculation means that is executed once when electric power is supplied. In this way, when the driving power is supplied from the power supply means, the third output control process is immediately executed and the third predetermined signal is output to the specific device. Therefore, when the power of the gaming machine is off. The opening of the door body performed can be immediately grasped by the specific device. Further, since the third output control processing is executed in the startup processing of the main processing means, it is possible to make the third output control processing non-executable in the normal processing in which a plurality of arithmetic processings are repeatedly executed. ..

It goes without saying that it is naturally possible to realize a gaming machine in which the above gaming machines A1 to A7, gaming machines B1 to B8, gaming machine C1, gaming machine D1, and gaming machines E1 to E4 are appropriately combined. ..
<Other>
In a pachinko machine, when a ball driven into the game area enters the symbol operation port, lottery is performed at the timing of the entering ball (for example, Patent Document 1: JP 2001-198332 A). In a spinning machine using a slot machine or a game ball, when the start lever is operated, a lottery is performed at the timing of the operation. As a result of the lottery, for example, when a big hit is reached, a large amount of prize balls and coins can be paid out. Since the control for determining the lottery and the big hit is performed by the main control device, the main control device is likely to be the target of fraudulent activity.
Specific fraudulent acts include, for example, replacing the main control device with a fraudulent one that frequently causes jackpots, or connecting a fraudulent board (eg, "hanging board") to the main control device Are illegally generated. Further, in the case of a pachinko machine, there is also an illegal act in which a nail that is driven on the surface of the game board is illegally bent to make it easier for the ball to enter the winning opening or the symbol operating opening.
In the case of a pachinko machine, the main controller is mounted on the back surface of the game board. A frame body is provided on the back surface of the game board, and an inner frame on which the game board is mounted is provided on the front surface of the frame body. The inner frame can be opened and closed with respect to the frame body. A glass frame is provided on the front surface of the inner frame, and the glass frame can be opened and closed with respect to the inner frame. Therefore, if a cheating person commits a cheating on the game board surface or the main control device, the inner frame or the glass frame must be opened, but if the inner frame or the glass frame is opened, the Opening is detected by the sensor, and it is notified to the hall computer that manages the amusement hall.Also, by notifying the outside that the inner frame or the glass frame is opened by lighting the lamp or outputting audio, which pachinko machine It is possible to easily grasp whether or not a fraudulent act has been performed.
However, when a fraudster invades, for example, at midnight after the amusement park is closed, and the intruder opens the inner frame or the glass frame and conducts a fraudulent act, the power of the pachinko machine is cut off at that time. Since the pachinko machine is stopped, the opening of the inner frame or the glass frame cannot be detected, and it is very difficult to grasp the opening.
This technical idea has been made in order to solve the above-mentioned problems and the like, and when the door is opened while the power of the gaming machine is off, it is possible to grasp the opening. It is an object of the present invention to provide a gaming machine that can
<Means>
In order to achieve this object, the gaming machine of the technical idea 1 is a main body, a door body that opens and closes the front surface of the main body, a main arithmetic means for executing arithmetic processing related to game control, and an output from the main arithmetic means. A sub-computing means for performing a computation process relating to the control of the electric device based on the signal, and the main computing means, the sub-computing means and a power supply means for supplying driving power to the electric device, Door opening detection means for detecting opening of the door body with respect to the main body, and holding means capable of holding detection of opening of the door body by the door opening detection means even when drive power from the power supply means is not supplied. And when the opening of the door body is detected by the door opening detection means when the drive power from the power supply means is not supplied, the holding means and the main calculation means are activated for a predetermined period, and the door body is opened. Means for holding the opening detection in the holding means, and the rising means when drive power from the power supply means is not supplied and opening of the door body is detected by the door opening detection means. An off-state operating means for supplying drive power to the holding means and a holding means for holding detection of opening of the door body when drive power is supplied to the main computing means, the sub computing means and the electric device by the power supply means. An output unit that outputs a predetermined signal according to the holding state is provided. The main calculation means is generally provided in the space formed by the door body and the main body. Further, the inside of the space formed by the door body and the main body indicates the back surface or the back surface side (including the back surface side of the main body) of the door body that cannot be touched when the door body is closed.
The gaming machine according to the technical idea 2 is the gaming machine according to the technical idea 1, in which the main calculation means is executed once when the driving power is supplied from the power supply means, and the startup processing. The second predetermined signal is output to the sub-calculation unit by the output unit according to the normal process that is executed after the process and repeatedly executes a plurality of calculation processes and the holding state of the holding unit that holds the opening detection of the door body. The output control process is performed, the output control process is executed in the start-up process, and then the normal process is performed.
The gaming machine of the technical idea 3 is the gaming machine described in the technical idea 1 or 2, wherein the main computing means is provided separately from the main computing means, and is a specific device for detecting the operating status of the gaming machine. If the opening of the door body is detected by the door opening detection means when the drive power from the power supply means is not supplied, the holding means is electrically connected. The third output means for outputting the third predetermined signal to the specific device according to the holding state of (3) is started for a predetermined period. The electrical connection between the main processing means and the specific device means that the main processing means and the specific device are connected by a signal line, or an input/output port composed of a latch circuit or the like. It also includes the case of connecting via wireless communication and the case of connecting via wireless communication.
A gaming machine according to technical idea 4 is the gaming machine according to technical idea 3, wherein the main computing means is configured to operate by the third output means according to a holding state of a holding means that holds detection of opening of the door body. A third output control process for outputting the third predetermined signal to the specific device is provided, the third output control process is executed in the startup process, and then the normal process is performed.
<Effect>
According to the gaming machine described in the technical idea 1, even when the driving power is not supplied from the power supply means to the main calculation means, the sub calculation means and the electric device, the door opening detection means detects the opening of the door body. Then, the rising means starts up the holding means and the main calculation means for a predetermined time by the drive power supplied by the off-time operating means, and causes the holding means to hold the opening detection of the door body. Then, when the driving power is supplied from the power supply means to the main calculation means, the sub calculation means and the electric device, the output means outputs a predetermined signal according to the holding state of the holding means. Therefore, for example, even if the door body is opened by a fraudulent act by somebody after the store is closed when the driving power is not supplied by the power source means in all gaming machines, the opening of the door body is held and the power source means is used. A predetermined signal can be output when drive power is supplied. Therefore, there is an effect that it is possible to grasp the opening of the door body performed when the driving power by the power supply means is not supplied, that is, when the power of the gaming machine is turned off.
According to the gaming machine described in the technical idea 2, in addition to the effect of the gaming machine described in the technical idea 1, the output means transfers the auxiliary operation means to the sub-calculation means in accordance with the holding state of the holding means for holding the detection of opening of the door body. The output control processing for outputting the second predetermined signal is executed within the startup processing of the main calculation means that is executed once when the driving power is supplied from the power supply means. In this way, when the driving power is supplied from the power supply means, the output control processing is immediately executed and the second predetermined signal is output to the sub-calculation means, so that it is performed when the power of the gaming machine is off. There is an effect that the opening of the opened door can be immediately grasped by the sub calculation means. When the second predetermined signal is output to the sub-calculation unit, the sub-calculation unit controls, for example, the electric device to give a notification. Further, since the output control processing is executed within the startup processing of the main processing means, it is possible to make the output control processing non-executable in the normal processing in which a plurality of arithmetic processings are repeatedly executed. ..
According to the gaming machine described in the technical idea 3, in addition to the effect exhibited by the gaming machine described in the technical idea 1 or 2, when the driving power from the power supply means is not supplied, the door opening detection means opens the door body. When is detected, the rising means starts the third output means for a predetermined time. Then, the third output means outputs the third predetermined signal to the specific device in accordance with the holding state of the holding means that holds the detection of opening the door. Therefore, when the drive power from the power supply means is not supplied, that is, when the opening of the door body is detected by the door opening detection means when the power supply of the gaming machine is turned off, at that time, The specific device has an effect of being able to grasp the opening of the door body performed while the power of the game machine is turned off.
According to the gaming machine described in the technical idea 4, in addition to the effect of the gaming machine described in the technical idea 3, the third output means determines the specific device according to the holding state of the holding means that holds the opening detection of the door body. The third output control processing for outputting the third predetermined signal to is executed within the startup processing of the main calculation means that is executed once when the driving power is supplied from the power supply means. In this way, when the driving power is supplied by the power supply means, the third output control process is immediately executed and the third predetermined signal is output to the specific device. Therefore, when the power of the gaming machine is off. There is an effect that the opening of the door body that has been performed can be immediately grasped by the specific device. Further, since the third output control processing is executed in the startup processing of the main processing means, it is possible to make the third output control processing non-executed in the normal processing in which a plurality of arithmetic processings are repeatedly executed. There is an effect.

10 Pachinko machines (gaming machines)
11 Outer frame (main body)
12 Inner frame (part of door)
14 Front frame (part of door)
110 Main controller (a part of main calculation means)
113 voice lamp control equipment 115 power supply (part of the power supply means)
201 MPU (part of the main processing unit, part of the output means)
203 RAM (part of the holding means)
203a Off inside frame open flag (a part of holding means)
205 I/O port (part of output means)
226 audio output equipment 227 lamp display equipment 260 frame opening detection circuit (rising section)
262 Hall computer (specific device)
CD1 capacitor (start-up means)
S101 to S117, S227 to S229 Startup processing S201 to S203, S207 to S224 Main processing (normal processing)
S201 to S212 Main processing (repeated processing)
S228 Startup processing (part of output control processing)
S229 Startup processing (part of third output control processing)
SW1 switch (part of door open detection means)
SW2 switch (part of door open detection means)

Claims (4)

Based on the main body, the door that opens and closes the front surface of the main body, the main arithmetic means for executing arithmetic processing relating to the control of the game, and the arithmetic processing relating to the control of the electric device based on the signal output from the main arithmetic means. In a gaming machine provided with a sub-calculation means for performing, a power supply means for supplying drive power to the main calculation means, the sub-calculation means, and an electric device
Door opening detection means for detecting opening of the door body with respect to the main body,
Holding means capable of holding the door open detection by the door open detection means even when drive power from the power supply means is not supplied,
When the opening of the door body is detected by the door opening detection means when the drive power from the power supply means is not supplied, the holding means and the main calculation means are activated for a predetermined period to open the door body. Rising means for holding the detection in the holding means,
When the drive power from the power supply means is not supplied and the opening of the door body is detected by the door opening detection means, an off-state operating means that supplies drive power to the rising means,
An output that outputs a predetermined signal in accordance with the holding state of the holding unit that holds the opening detection of the door body when drive power is supplied from the power supply unit to the main computing unit, the sub-computing unit, and an electric device. A gaming machine comprising: means. The main calculation means is
A start-up process executed once when drive power is supplied from the power supply means;
A normal process that is executed after the startup process and that repeatedly executes multiple arithmetic processes,
An output control process for causing the output unit to output a second predetermined signal to the sub-calculation unit in accordance with a holding state of a holding unit that holds the opening detection of the door body;
2. The gaming machine according to claim 1, wherein the output control process is executed in the startup process, and then the normal process is performed. The main arithmetic means is provided separately from the main arithmetic means and is electrically connected to a specific device for detecting an operating condition of the gaming machine,
When the opening of the door is detected by the door opening detection means when the drive power from the power supply means is not supplied, the startup means determines the identification according to the holding state of the holding means. The gaming machine according to claim 1 or 2, wherein a third output means for outputting a third predetermined signal to the device is started up for a predetermined period. The main calculation means is
A third output control process that causes the third output unit to output a third predetermined signal to the specific device according to a holding state of a holding unit that holds the detection of opening of the door body;
The gaming machine according to claim 3, wherein the third output control process is executed in the startup process, and then the normal process is performed.

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