JP2009152487A - Thin-film transistor, semiconductor device and electrooptical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor that prevents deterioration in characteristics thereof by generation of heat, without dividing a channel region into a plurality of regions, and to provide a semiconductor device and an electrooptical device. <P>SOLUTION: A metal layer 3 is formed on a substrate 1, and a semiconductor layer 5 is formed on the metal layer 3 through an insulating layer 4. Unevenness is formed, by a convex part 3a, in at least one part of region which is opposed to the semiconductor layer 4 of the metal layer 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thin film transistor, a semiconductor device, and an electro-optical device.

2. Description of the Related Art Conventionally, a thin film transistor (hereinafter referred to as TFT) whose characteristics are hardly deteriorated is known. This TFT prevents heat generation by dividing the TFT channel region into a plurality of parts in order to prevent the hydrogen that had terminated the dangling bonds of the channel from escaping due to heat generation during operation and degrading the characteristics. Yes (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 11-97701

  However, the conventional TFT has a problem that the channel region must be divided into a plurality of parts in order to prevent heat generation. Therefore, there are problems that the installation area of the TFT is increased and the manufacturing process is complicated.

  Accordingly, the present invention provides a thin film transistor, a semiconductor device, and an electro-optical device that can prevent deterioration of characteristics due to heat generation without dividing a channel region into a plurality of regions.

  In order to solve the above problems, in the thin film transistor of the present invention, a metal layer is formed on a substrate, a semiconductor layer is formed on the metal layer via an insulating layer, and the semiconductor layer of the metal layer is opposed to the semiconductor layer. Unevenness is formed in at least a part of the region.

  By comprising in this way, the surface area of the surface which opposes the semiconductor layer of a metal layer increases. Therefore, compared with the case where unevenness | corrugation is not formed in the metal layer, it becomes easy to radiate the heat | fever generate | occur | produced in the semiconductor layer to the metal layer, and the heat dissipation of a semiconductor layer improves. Thereby, the temperature rise of the semiconductor layer can be suppressed and deterioration of the characteristics of the thin film transistor can be prevented.

  In the thin film transistor of the present invention, the unevenness is formed in a region facing the channel region of the semiconductor layer.

  With this configuration, the heat generated in the channel region can be easily radiated to the metal layer, and the temperature increase in the channel region can be more effectively prevented.

  Further, the thin film transistor of the present invention is characterized in that the convex portions forming the concave and convex portions are formed so as to extend along the direction of current flowing through the channel region.

  By configuring in this manner, even if the unevenness of the metal layer causes unevenness in the insulating layer, and the semiconductor layer is partially discontinuous at the corners of the unevenness of the insulating layer, the semiconductor layer Can be prevented from becoming electrically discontinuous, and a current can flow through the semiconductor layer.

  The thin film transistor of the present invention is characterized in that the metal layer is a lower electrode electrically connected to a source electrode of the thin film transistor.

  With this configuration, the potential of the lower electrode becomes the same as that of the source electrode, so that the parasitic bipolar effect can be suppressed and the characteristics of the thin film transistor can be improved.

  In the thin film transistor of the present invention, the metal layer is a light shielding layer that shields the semiconductor layer.

  With this configuration, the surface area of the light shielding layer facing the semiconductor layer can be increased, heat generated in the semiconductor layer can be easily radiated to the light shielding layer, and the temperature rise of the semiconductor layer can be suppressed.

  In the thin film transistor of the present invention, the metal film is a gate electrode of the thin film transistor.

  With this configuration, the surface area of the gate electrode facing the semiconductor layer can be increased, heat generated in the semiconductor layer can be easily radiated to the gate electrode, and the temperature rise of the semiconductor layer can be suppressed.

A semiconductor device of the present invention includes any of the above thin film transistors.
As described above, since the thin film transistor with improved characteristics is provided, the performance of the semiconductor device can be improved.

The electro-optical device of the present invention includes any one of the above thin film transistors.
As described above, since the thin film transistor having improved characteristics is provided, the switching performance of the electro-optical device is improved, and the display performance of the electro-optical device can be improved.

<First embodiment>
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the scale is appropriately changed for each layer and each member so that each layer and each member can be recognized on the drawing.

(Thin film transistor)
FIG. 1 is a cross-sectional view showing a schematic configuration of the TFT 10 of this embodiment. As shown in FIG. 1, an insulating layer 2 is formed on a substrate 1, and a lower electrode (metal layer) 3 is formed on the insulating layer 2 in an island shape. Here, the substrate 1 is made of a transparent material such as quartz or glass, and the insulating layer 2 is made of SiO ₂ or the like. The lower electrode 3 is made of a metal material such as Al, for example.

An insulating layer 4 is formed on the lower electrode 3 so as to cover the lower electrode 3 and the insulating layer 2. The insulating layer 4 is made of, for example, SiO ₂ or the like. In the insulating layer 4, a contact hole 4 a that penetrates the insulating layer 4 and reaches the lower electrode 3 is formed.

  A semiconductor layer 5 is formed on the insulating layer 4 so as to face the lower electrode 3. The semiconductor layer 5 is formed along the surface of the insulating layer 4 including the inner surface of the contact hole 4a, and is in contact with and electrically connected to the lower electrode 3. The semiconductor layer 5 is formed of, for example, polycrystalline silicon or the like, and one end portion in the extending direction is a source region 5s and the other end portion is a drain region 5d. Impurities are implanted at a high concentration in the source region 5s and the drain region 5d. A region between the source region 5s and the drain region 5d of the semiconductor layer 5 is a channel region 5c.

A gate insulating film 6 is formed on the semiconductor layer 5 so as to cover the semiconductor layer 5 and the insulating layer 4. The gate insulating film 6 is made of, for example, SiO ₂ or the like.
On the gate insulating film 6, a gate electrode 7 is formed in a region facing the channel region 5 c of the semiconductor layer 5. The gate electrode 7 is made of, for example, a metal material such as Al.

  An insulating layer 8 is formed on the gate electrode 7 so as to cover the gate electrode 7 and the gate insulating film 6. The insulating layer 8 penetrates the insulating layer 8 and the gate insulating film 6, communicates with the contact hole 4 a and reaches the source region 5 s of the semiconductor layer 5, and penetrates the insulating layer 8 and the gate insulating film 6. A contact hole 8b reaching the drain region 5d of the semiconductor layer 5 is formed. On the insulating layer 8, a source electrode 11 and a drain electrode 12 are formed of a metal material such as Al, for example. The source electrode 11 and the drain electrode 12 are connected to the source region 5s and the drain region 5d of the semiconductor layer 5 through contact holes 8a and 8b, respectively.

  Here, in this embodiment, a plurality of convex portions 3 a are formed in a region of the lower electrode 3 facing the semiconductor layer 5. Further, the convex portion 3 a is also formed in a region facing the channel region 5 c, thereby forming irregularities on the surface of the lower electrode 3. The shape and arrangement of the convex portions 3a shown in FIG. 1 are for easy understanding of the arrangement of the convex portions 3a, and the convex portions 3a can have any shape and arrangement as will be described later. Further, the convex portion 3a is not formed in the portion corresponding to the contact hole 4a of the lower electrode 3, and has a flat shape.

  FIGS. 2A to 2D are plan views showing examples of the arrangement of the protrusions 3a when the lower electrode 3 is viewed from the semiconductor layer 5 side. In each figure, the source electrode 11 is connected to the left end side of the lower electrode 3, and the drain electrode 12 is disposed so as to overlap the right end side in a plane. Accordingly, the current flowing through the channel region 5c shown in FIG. 1 flows in the direction from the left to the right in FIGS. 2 (a) to 2 (d).

In the shape and arrangement shown in FIG. 2A, the convex portion 3a is formed in a substantially rectangular shape in cross section and is formed so as to extend along the direction of the current i flowing through the channel region 5c. Here, it is desirable that the side surface 3b in the surface direction of the substrate 1 of the convex portion 3a shown in FIG.
In the shape and arrangement shown in FIG. 2B, the convex portion 3a is formed in the same cross-sectional shape as the convex portion 3a shown in FIG. 2A, and intersects the direction of the current i flowing through the channel region 5c. Are arranged as follows.
Further, in the shape and arrangement shown in FIG. 2C, the convex portions 3a have the same cross-sectional shape and arrangement as the convex portions 3a shown in FIG. 2B, and are bent zigzag in the extending direction in plan view. Is formed.
In the shape and arrangement shown in FIG. 2D, the convex portions 3 a are formed in a substantially hemispherical shape, and a plurality of convex portions 3 a are scattered on the lower electrode 3.

Next, the operation of this embodiment will be described.
When a current is supplied to the source electrode 11 shown in FIG. 1 and a current flows through the channel region 5c of the semiconductor layer 5, the temperature of the channel region 5c rises. A part of the heat generated in the channel region 5 c is radiated to the lower electrode 3.

  Here, as described above, irregularities are formed on the surface of the lower electrode 3 on the semiconductor layer 5 side by the convex portions 3a. Therefore, the surface area of the surface facing the semiconductor layer 5 of the lower electrode 3 is increased as compared with the case where the unevenness is not formed. Therefore, the heat generated in the semiconductor layer 5 can be easily dissipated to the lower electrode 3, and the heat dissipation performance of the semiconductor layer 5 to the lower electrode 3 is improved. Thereby, the temperature rise of the semiconductor layer 5 can be suppressed and deterioration of the characteristics of the TFT 10 can be prevented.

  Further, in this embodiment, since the convex portion 3a is also formed in the region facing the channel region 5c of the semiconductor layer 5 to form irregularities, the heat generated in the channel region 5c is further radiated to the lower electrode 3. Therefore, the temperature rise of the channel region 5c can be more effectively suppressed.

In addition, when the protrusion 3a has the shape and arrangement shown in FIG. 2A, unevenness is formed in the insulating layer 4 by the unevenness of the lower electrode 3, and the semiconductor layer 5 is partially at the unevenness corner of the insulating layer. Even when a so-called step discontinuity occurs, the semiconductor layer 5 can be prevented from being electrically discontinuous, and the current i can be stably supplied to the semiconductor layer 5. Therefore, the reliability of the TFT 10 can be improved.
Further, as described above, by forming the side surface 3b of the convex portion 3a so as to be tapered, the semiconductor layer 5 can be prevented from being disconnected.

  Further, when the convex portion 3a has the shape and arrangement shown in FIG. 2B, more irregularities are formed as compared with the shape and arrangement shown in FIG. 2A, and the semiconductor layer 5 of the lower electrode 3 is formed. The side surface area can be enlarged. Moreover, when the convex part 3a is made into the shape and arrangement | positioning shown in FIG.2 (c), the surface area by the side of the semiconductor layer 5 of the lower electrode 3 can be expanded compared with the shape and arrangement | positioning shown in FIG.2 (b). . Therefore, the heat dissipation of the semiconductor layer 5 and the channel region 5c can be further improved.

  When the convex portion 3a has the shape and arrangement shown in FIG. 2D, not only can the surface area of the lower electrode 3 on the semiconductor layer 5 side be increased, but the convex portion 3a has a hemispherical shape. Therefore, the step of the semiconductor layer 5 due to the corners of the unevenness can be prevented, and the reliability of the TFT 10 can be improved.

Further, since the lower electrode 3 is connected to the source electrode 11 and the potential becomes the same as that of the source electrode 11, the parasitic bipolar effect can be suppressed and the characteristics of the TFT 10 can be improved.
Further, the convex portion 3a is not formed in a portion corresponding to the formation position of the contact hole 4a of the lower electrode 3, and has a flat shape. Thereby, formation of the contact hole 4a can be facilitated. Further, the reliability of the connection portion between the source electrode 11 and the semiconductor layer 5 can be improved, and the reliability of the TFT 10 can be improved.

  As described above, according to the TFT 10 of this embodiment, it is possible to prevent deterioration of the characteristics of the TFT 10 due to heat generation without dividing the channel region 5c into a plurality of parts, and the TFT 10 having good characteristics and high reliability. Can be provided.

<Second embodiment>
Next, a second embodiment of the present invention will be described with reference to FIG. 3 with reference to FIGS. 2 (a) to 2 (d). This embodiment is different from the TFT 10 described in the above embodiment in that a light shielding layer (metal layer) 13 is formed on the substrate 1 and a TFT 20 is formed on the light shielding layer 13. Since the other points are the same as those of the above-described embodiment, the same parts are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 3, an insulating layer 2 is formed on the substrate 1 so as to cover the substrate 1, and an island-shaped light shielding layer 13 is formed on the insulating layer 2. The light shielding layer 13 is made of a metal material such as aluminum, for example. An insulating layer 4 is formed on the light shielding layer 13 so as to cover the light shielding layer 13 and the insulating layer 2. On the insulating layer 4, the semiconductor layer 5 is formed in an island shape. A gate insulating film 6 is formed on the semiconductor layer 5 so as to cover the semiconductor layer 5 and the insulating layer 4. On the gate insulating film 6, a gate electrode 7 is formed in a region facing the channel region 5 c of the semiconductor layer 5.

  An insulating layer 8 is formed on the gate electrode 7 so as to cover the gate electrode 7 and the gate insulating film 6. A source electrode 11 and a drain electrode 12 are formed in an island shape on the insulating layer 8. In the insulating layer 8, contact holes 8 a that penetrate the insulating layer 8 and reach the source region 5 s and the drain region 5 d of the semiconductor layer 5 are formed. The source electrode 11 and the drain electrode 12 are connected to the source region 5s and the drain region 5d through contact holes 8a and 8b, respectively.

Here, in this embodiment, a convex portion 13a similar to the convex portion 3a of the lower electrode 3 described in the above-described embodiment is formed on the surface of the light shielding layer 13 on the semiconductor layer 5 side. An uneven shape is formed. Therefore, according to this embodiment, the surface area of the light shielding layer 13 facing the semiconductor layer 5 is increased, and the heat generated in the semiconductor layer 5 is easily dissipated to the light shielding layer 13, so that the same as in the above embodiment. Moreover, the temperature rise of the semiconductor layer 5 can be suppressed.
Therefore, according to the TFT of this embodiment, it is possible to prevent deterioration of the characteristics of the TFT 20 due to heat generation without dividing the channel region 5c into a plurality of parts, and to provide a TFT 20 with good characteristics and high reliability. Can do.

<Third embodiment>
Next, a third embodiment of the present invention will be described with reference to FIG. 4 with reference to FIGS. 2 (a) to 2 (d). In this embodiment, a gate electrode (metal layer) 7 is formed on the TFTs 10 and 20 described in the above embodiment and the substrate 1, and a semiconductor layer 5 is formed on the gate electrode 7 via a gate insulating film 6. Is different in that it is. Since the other points are the same as those of the above-described embodiment, the same parts are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 4, an insulating layer 2 is formed on the substrate 1 so as to cover the substrate 1, and an island-shaped gate electrode 7 is formed on the insulating layer 2. A gate insulating film 6 is formed on the gate electrode 7 so as to cover the gate electrode 7 and the insulating layer 2. On the gate insulating film 6, the semiconductor layer 5 is formed in an island shape. An insulating layer 8 is formed on the semiconductor layer 5 so as to cover the semiconductor layer 5 and the gate insulating film 6.

  A source electrode 11 and a drain electrode 12 are formed in an island shape on the insulating layer 8. In the insulating layer 8, contact holes 8 a and 8 b that penetrate the insulating layer 8 and reach the source region 5 s and the drain region 5 d of the semiconductor layer 5 are formed. The source electrode 11 and the drain electrode 12 are connected to the source region 5s and the drain region 5d through contact holes 8a and 8b, respectively.

Here, in this embodiment, a convex portion 7a similar to the convex portions 3a and 13a described in the above-described embodiment is formed on the surface of the gate electrode 7 on the semiconductor layer 5 side, and the convex portion 7a forms an irregular shape. Is formed. Therefore, according to this embodiment, the surface area of the gate electrode 7 facing the semiconductor layer 5 is increased, and the heat generated in the semiconductor layer 5 can be easily dissipated to the gate electrode 7. In addition, the temperature rise of the semiconductor layer 5 and the channel region 5c can be suppressed.
Therefore, according to the TFT 30 of this embodiment, it is possible to prevent deterioration of the characteristics of the TFT 30 due to heat generation without dividing the channel region 5c into a plurality of parts, and to provide a TFT 30 with good characteristics and high reliability. Can do.

(Semiconductor devices, electro-optical devices)
Next, among the TFTs 10, 20, and 30 described in the above embodiments, for example, a semiconductor device and an electro-optical device including the TFT 30 will be described.
FIG. 5 is a circuit configuration diagram of a pixel 200 (semiconductor device) constituting the liquid crystal device (electro-optical device) 100 of this embodiment. As shown in FIG. 5, a large number of pixels 200 are arranged in a matrix, and each pixel 200 is formed with a pixel electrode 9 and a TFT 30. The TFT 30 is a switching element that performs switching control of the pixel 200. A data line 60 extending from a data line driving circuit (not shown) is electrically connected to the source of the TFT 30, and the pixel electrode 9 is electrically connected to the drain of the TFT 30. The data line driving circuit supplies image signals S 1, S 2,..., Sn to each pixel 200 via the data line 60.
In the case of an electro-optical device for full color display, the minimum unit of full color display is composed of a plurality of single color display units, for example, red, blue, and green. In this case, the pixel corresponding to the single color display unit is referred to as a sub-pixel. That is, in the case of a full-color display liquid crystal device, the pixel 200 is referred to as a sub-pixel.

  A scanning line 50 extending from a scanning line driving circuit (not shown) is electrically connected to the gate of the TFT 30. The scanning signals G1, G2,..., Gm supplied from the scanning line driving circuit to the scanning line 50 at a predetermined timing are applied to the gates of the TFTs 30 in this order in a line-sequential manner. When the scanning signals G1 to Gm are applied to the gate of the TFT 30, the gate and source of the TFT 30 are turned on for a certain period, and the image signals S1 to Sn supplied from the data line 60 are applied to the pixel electrode 9 at a predetermined timing. It is to be written.

  The pixel electrode 9 faces a common electrode (not shown), and a liquid crystal capacitor is formed between the pixel electrode 9 and the common electrode. Further, the pixel 200 is provided with a storage capacitor 70 connected to the capacitor line 40 provided in parallel with the scanning line 50 and connected between the drain of the TFT 30 and the pixel electrode 9. The liquid crystal capacitor and the storage capacitor 70 are connected in parallel, and image signals S1 to Sn of a predetermined level written in the pixel electrode 9 are held in the liquid crystal capacitor and the storage capacitor 70 for a certain period. By providing the storage capacitor 70, the image signal held in the liquid crystal capacitor is prevented from leaking.

  As described above, the pixel 200 and the liquid crystal device 100 include the TFT 30 with improved characteristics and improved reliability as described above. Therefore, the switching performance in the pixel 200 is improved, and the display performance of the liquid crystal device 100 can be improved.

The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the shape and arrangement of the protrusions are not limited to the shape and arrangement described in the above embodiment. For example, the convex portions may be formed in a spiral shape, arranged in a lattice shape, or a plurality of patterns may be combined.
Further, in the first embodiment described above, the case where the concave and convex portions are formed on the lower electrode has been described. However, the back gate is used instead of the lower electrode, the convex portion is formed on the back gate, and the surface on the semiconductor layer side of the back gate. Unevenness may be formed on the surface. Thereby, the heat generated in the semiconductor layer and the channel portion can be easily radiated to the back gate, and the same effect as in the first embodiment can be obtained.
Further, the convex portion may be formed only in a region facing the channel region of the metal layer, and the concave and convex portions may be formed only in that region. Thereby, the metal layer in the region other than the region facing the channel region can be flattened while ensuring the heat dissipation of the channel region.
In addition, the convex portion may be formed in the region facing the gate electrode, and the convex portion may be formed only in the other region to form the unevenness. As a result, the gate electrode can be flattened to improve the switching characteristics.
In addition, as long as the unevenness can be formed on the surface of the metal layer on the semiconductor layer side, the metal layer may be formed with a concave portion instead of the convex portion.
Moreover, the material of each member is not limited to the material demonstrated in the above-mentioned embodiment.

It is sectional drawing which shows the structure of TFT which concerns on 1st embodiment of this invention. (A)-(c) is a top view which shows the convex part which concerns on 1st embodiment of this invention. It is sectional drawing which shows the structure of TFT which concerns on 2nd embodiment of this invention. It is sectional drawing which shows the structure of TFT which concerns on 3rd embodiment of this invention. 1 is an equivalent circuit diagram of a liquid crystal device according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate, 3 Lower electrode (metal layer), 3a Convex portion (concave / convex), 4 Insulating layer, 5 Semiconductor layer, 5c Channel region, 6 Gate insulating film (insulating layer), 7 Gate electrode (metal layer), 7a Convex portion (Unevenness), 10 TFT (thin film transistor), 11 source electrode, 13 light shielding layer (metal layer), 13a protrusion (unevenness), 20 TFT (thin film transistor), 30 TFT (thin film transistor), 100 liquid crystal device (electro-optical device), 200 pixels (semiconductor device), i current

Claims (8)

A metal layer is formed on the substrate, a semiconductor layer is formed on the metal layer via an insulating layer,
A thin film transistor, wherein unevenness is formed in at least a part of a region of the metal layer facing the semiconductor layer.   2. The thin film transistor according to claim 1, wherein the unevenness is formed in a region facing the channel region of the semiconductor layer.   3. The thin film transistor according to claim 1, wherein the projections forming the projections and depressions are formed so as to extend along a direction of a current flowing through the channel region.   The thin film transistor according to claim 1, wherein the metal layer is a lower electrode electrically connected to a source electrode of the thin film transistor.   4. The thin film transistor according to claim 1, wherein the metal layer is a light shielding layer that shields light from the channel region. 5.   The thin film transistor according to any one of claims 1 to 3, wherein the metal layer is a gate electrode of the thin film transistor.   A semiconductor device comprising the thin film transistor according to claim 1.   An electro-optical device comprising the thin film transistor according to claim 1.

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