JP2009150868A - Burn-in device and burn-in method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a burn-in device and burn-in method of a semiconductor device. <P>SOLUTION: The burn-in device mainly includes a main burn-in chamber, and at least one slot substrate can be mounted in the main burn-in chamber. A plurality of slots are disposed on the slot substrate, and a burn-in board can be inserted into each slot. A plurality of test sockets are disposed on the burn-in board. Each test socket can store a semiconductor device. The burn-in device includes at least one buffer burn-in chamber, and a gate is disposed on the side of the buffer burn-in chamber connected to the main burn-in chamber and can communicate with the main burn-in chamber. The burn-in device further includes a controller, and can control each of the temperatures of the main burn-in chamber and the buffer burn-in chamber and the voltage of each slot in the main burn-in chamber. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a burn-in apparatus and burn-in method for semiconductor elements, and more particularly to a burn-in apparatus having a multi-chamber and a burn-in method therefor.

  In recent years, semiconductor devices have become an important economic source in Japan. As technology advances, the demands on the reliability of semiconductor devices are becoming increasingly severe. Currently, an index often used in the industry for evaluating the reliability of semiconductor device products is the failure rate. The reliability of a semiconductor element product is the remaining rate after operating the semiconductor product for a certain time (relative to the failure rate). The higher the remaining rate (that is, the lower the failure rate), the more reliable the semiconductor element product is. Will be better.

  In general, semiconductor device products have a relatively high failure rate in the initial stage of use, but the failure rate decreases with the passage of time. This stage is also called the initial failure period. For this reason, the initial failure period of a semiconductor element product is an equally important index for evaluating whether or not a product conforms to a quality standard requirement at the time of acceptance or failure, and is a basis for removing defective products.

  In general, failure mechanisms that are often seen in the early failure stage are failures caused by design or process defects, etc., and are usually early using the burn-in method during the test process of semiconductor devices. The failure period can be eliminated. Burn-in means that semiconductor elements are inserted on a special high-temperature-resistant burn-in board, and semiconductor device operating conditions such as voltage and current are applied and then placed in a high-temperature environment for accelerated aging. Is.

  Currently, burn-in technology is: 1. Raise the temperature and wait for the temperature to stabilize. 2. Burn in. It can be divided into three steps: waiting for the temperature to drop and ending burn-in. The disadvantage of such a method is that in the process of performing burn-in in one burn-in chamber, the temperature raising and lowering processes are very time consuming. In addition, since all of the current burn-in methods in one burn-in chamber burn in the semiconductor elements of the entire lot, when some of the semiconductor elements have already reached the burn-in completion condition, the burn-in of all the semiconductor elements is completed. If you don't wait for it, you can't remove it and cool it down. In the burn-in process of a semiconductor element, even if there is another slot in which no burn-in board is inserted in the burn-in chamber, the burn-in test cannot be performed by adding another semiconductor element.

  As described above, in one burn-in chamber, only one lot of semiconductor elements can be burned in at a time, the processing capacity of one burn-in chamber is lowered, and the cost is increased, and the waiting time is large in production capacity. affect.

Patent Document 1 of the prior art discloses a dual burn-in chamber type burn-in apparatus. This dual burn-in chamber type burn-in apparatus heats air via a heater and circulates hot air between two burn-in chambers via a transmission tube to raise the temperature of the two burn-in chambers. It is impossible to effectively solve the problem that it takes time to raise and lower the temperature and the problem that the processing capacity of the burn-in chamber is not good and affects the production capacity. Therefore, how to solve the above problem is a serious issue in the industry.
US Pat. No. 7,111,211

  In order to solve the above problems, the present invention provides a semiconductor device burn-in apparatus having a multi-chamber structure including a main burn-in chamber and at least one buffer burn-in chamber. The volume of the buffer burn-in chamber is smaller than the volume of the main burn-in chamber, and at least one slot substrate is provided in the main burn-in chamber. A plurality of slots are provided on the slot substrate, and a burn-in board can be inserted into each slot. A plurality of test sockets are provided on the burn-in board, and a semiconductor element can be accommodated in each test socket. In addition, it includes a control device that can control the temperatures of the main burn-in chamber and the buffer burn-in chamber, and can control the output voltage of the slots in the main burn-in chamber. In addition, it may further include a load device capable of moving the burn-in board from the buffer burn-in chamber to the main burn-in chamber or moving the burn-in board from the main burn-in chamber to the buffer burn-in chamber.

  SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor element burn-in apparatus having a multi-chamber structure capable of effectively solving the problem that burn-in cannot be performed by adding other semiconductor elements in the semiconductor element burn-in process. is there.

  Another object of the present invention is to lower the temperature in a semiconductor element burn-in process when some of the semiconductor elements have already reached the burn-in condition, and after waiting for the burn-in of all the semiconductor elements to be completed, the temperature is lowered. An object of the present invention is to provide a semiconductor device burn-in apparatus having a multi-chamber structure that can effectively solve the problem that cannot be achieved.

  Still another object of the present invention is to provide a semiconductor element burn-in apparatus having a multi-chamber structure capable of effectively solving the problem that it takes time to increase and decrease the temperature in a semiconductor element burn-in process.

  Still another object of the present invention is to provide a semiconductor element burn-in method having a multi-chamber structure that can effectively solve the problem that burn-in cannot be performed by adding other semiconductor elements in the semiconductor element burn-in process. It is.

  Still another object of the present invention is to reduce the temperature in the semiconductor element burn-in process after waiting for the burn-in of all the semiconductor elements to be completed when some of the semiconductor elements have already reached the burn-in condition. It is an object of the present invention to provide a multi-chamber semiconductor device burn-in method capable of effectively solving the problem that cannot be taken out.

  Still another object of the present invention is to provide a semiconductor element burn-in method having a multi-chamber structure capable of effectively solving the problem of time required for temperature increase and decrease in a semiconductor element burn-in process.

  The present invention discloses a burn-in apparatus and burn-in method for a semiconductor device, and the structure and basic principle used can be understood by those having ordinary knowledge in the related technical field. In the description, a complete description is not given. Further, the drawings referred to in the following text are for showing an outline of the structure related to the features of the present invention, and do not need to be drawn completely based on actual dimensions.

  FIG. 1 is a schematic diagram of a semiconductor device burn-in apparatus having a multi-chamber structure of the present invention. As shown in FIG. 1, the semiconductor device burn-in apparatus of the present invention includes a main burn-in chamber 102, a buffer burn-in chamber 104, a control device 106, and at least one load device.

  The volume of the buffer burn-in chamber 104 is smaller than the volume of the main burn-in chamber 102. Since the volume of the buffer burn-in chamber is relatively small, the waiting time in the heating and cooling process can be saved.

  Further, a slot substrate (not shown) is provided in the main burn-in chamber 102, for example, as a backplane in US7112111. For example, a plurality of slots (not shown) are provided on a slot substrate like a socket in US7112111, and the burn-in board 20 can be inserted into each slot.

  In the present embodiment, not only the gate 110 is disposed between the main burn-in chamber 102 and the buffer burn-in chamber 104, but also another gate 120 is disposed on the side of the buffer burn-in chamber 104. Yes. In the process of performing burn-in, the controller 106 can control the temperature of the main burn-in chamber 102 and the buffer burn-in chamber 104, and can control the current or voltage of each slot in the main burn-in chamber 102.

  Further, the control device 106 can control the opening and closing of the gate 110 and the gate 120 based on the test status of each burn-in board 20. For example, the burn-in board 20 that has been tested is moved from the main burn-in chamber 102 to the buffer burn-in chamber 104 via a load device (not shown) such as an arm robot, and after passing through the temperature lowering process, the buffer burn-in board is finally transferred from the gate 120. Transfer to chamber 104.

  Naturally, after transferring the burn-in board 20 to the buffer burn-in chamber 104, the control device 106 causes the load device to transfer another pre-test burn-in board 20 into the buffer burn-in chamber 104 first, and preheats it to a predetermined temperature. After that, the burn-in board 20 can be electrically connected to the slot on the slot substrate by entering the main burn-in chamber 102 via the gate 110.

  It should be emphasized that the load device can be located outside the burn-in chamber 104 or inside the burn-in chamber 104, and the present invention does not limit this.

  FIG. 2 is a schematic diagram of the burn-in board 20. On the burn-in board 20, a plurality of test sockets 202 and a connection interface 204 such as a gold finger are provided. A semiconductor element 206 can be accommodated in each test socket 202.

  The connection interface 204 can be inserted into a slot on the slot substrate in the main burn-in chamber 102. Therefore, in the process of performing the burn-in test, the control device 106 can transmit a test signal through the connection interface 204 on the burn-in board 20 and receive a test signal for the semiconductor element 206. As a result, the failure rate of the semiconductor element 206 on each burn-in board 20 can be calculated to determine which burn-in board 20 has completed the burn-in test.

  Reference is now made to FIGS. 1 and 3 simultaneously. FIG. 3 is a schematic flow diagram of semiconductor device burn-in having a multi-chamber structure of the present invention.

  First, as shown in step 301 in FIG. 3, a main burn-in chamber and a buffer burn-in chamber are provided.

  Next, as shown in step 302, at least one burn-in board 20 is provided. A plurality of test sockets 202 are provided on the burn-in board 20, and the semiconductor element 206 can be accommodated in the test socket 202.

  Next, step 303 is performed to detect the temperature. The temperatures of the main burn-in chamber 102 and the buffer burn-in chamber 104 are detected via the control device 106.

  Next, step 304 is performed and a preheating step is performed. After the load apparatus places the pre-test burn-in board 20 in the buffer burn-in chamber 104, a preheating step is performed, and when the temperature in the buffer burn-in chamber 104 is heated to around the same temperature as the main burn-in chamber 102, the burn-in board 20 The temperature of each semiconductor element 206 above can reach the preheating temperature. Thereafter, step 305 is performed. The load device loads the burn-in board 20 into the main burn-in chamber 102 and electrically connects it onto the slot of the slot substrate.

  Next, step 306 is performed to conduct an electrical test. An electrical test signal is transmitted from the control device 106 to the burn-in board 20 via the slot substrate, and an electrical test is performed on each semiconductor element 206 via the burn-in board 20 and a plurality of test sockets 202 thereon.

  Step 307 is performed and the failure rate is calculated. When the control device 106 receives the test signal returned from each semiconductor element, the failure rate of these semiconductor elements can be calculated, and a failure rate growth curve (see FIG. 4) can be obtained.

Thereafter, it is determined whether or not to end the test (see step 308). Based on the failure rate empirical reference line (see FIG. 5, the ideal relationship between the failure rate of the semiconductor element and the time obtained from the characteristics of the semiconductor element) It is determined whether or not to end the burn-in test flow of the burn-in board 20 together with the following determination formula. First, the failure rate difference G _t within the unit time of the failure rate experience verification line is calculated.
G _t = F _x −F _x−1

Next, the difference GA _n of the failure rates FA _n within the unit time of each semiconductor element 206 is calculated.
GA _n = FA _n −FA _n−1

Further, it is determined whether or not to end the burn-in test. If the difference in failure rate within the unit time of the semiconductor element 206 that has continued for K times is smaller than the difference in failure rate within the unit time on the failure rate experience reference line, it is determined that the burn-in test flow of the burn-in board 20 is completed. . For example,
(GA _n <G _t ) and (GA _n-1 <G _t ) and ... and (GA _{n- (k-1)} <G _t )

  If the difference in failure rate within the unit time of the semiconductor element 206 that has continued for K times is not smaller than the difference in failure rate within the unit time of the failure rate experience reference line, step 307 is performed again after a certain time, 308 is performed again.

  FIG. 6 is a schematic flow diagram of a burn-in method according to another specific embodiment of the present invention. First, before performing the burn-in step, a plurality of burn-in boards 20 are placed in the slot substrate in the main burn-in chamber 102, and then the gate 110 is closed. The controller 106 controls the heating device to raise the temperature in the burn-in chamber 102 to a predetermined high temperature.

  Next, the control device 106 provides an electrical signal (for example, voltage, current) to the semiconductor elements 206 on each burn-in board 20, performs a test, and calculates the test status of the semiconductor elements 206 on each burn-in board 20.

  After it is determined that a burn-in test has been completed for a certain burn-in board 20, the controller 106 causes the load device to move the burn-in board 20 that has already completed the burn-in test from the main burn-in chamber into the buffer burn-in chamber (step 601). reference).

  Next, the controller 106 adjusts the temperature of the buffer burn-in chamber 104. For example, the temperature in the buffer burn-in chamber 104 is adjusted to room temperature, a temperature at which a human body can contact, or less than 50 ° C. (see step 602). After all the semiconductor elements 206 on the burn-in board 20 are cooled, the control device 106 causes the load device to move the burn-in board 20 out of the buffer burn-in chamber 104 (see step 603).

  Next, the control device causes the load device to take the pre-test burn-in board 20 and transport it into the buffer burn-in chamber 104 (see step 604).

  Next, the temperature in the buffer burn-in chamber 104 is adjusted so that the temperature in the buffer burn-in chamber 104 reaches the burn-in temperature (see step 605). Thereafter, the control device 106 causes the load device to move the pre-test burn-in board 20 into the main burn-in chamber 102 (see step 606).

  Further, as the electrical test is performed, the control device 106 is electrically connected to the slot substrate, and performs an electrical test on each semiconductor element 206 via each burn-in board 20 and a plurality of test sockets 202 thereon. (See step 607).

  Next, the control device 106 continues to calculate the failure rate of each semiconductor element 206 (see step 608). The controller 106 determines whether or not the burn-in board 20 has reached the end of the burn-in test (step 609).

  Thereafter, steps 601 to 608 are repeated. The process is the same as in the previous example. It will not be repeated here.

  Lastly, it should be emphasized that the main burn-in chamber 102 and the buffer burn-in chamber 104 of the present invention can be separated, and during that time, they are hermetically joined via a connection mechanism (not shown in the figure). Can do. Its purpose is to allow a plurality of burn-in boards 20 to be quickly placed in the slot substrate in the main burn-in chamber 102 before the first burn-in begins.

  Also, based on the above disclosure of the present invention, it is possible to choose to use multiple buffer burn-in chambers 104 and a single main burn-in chamber 102 for placement together. The plurality of burn-in boards 20 in the main burn-in chamber 102 are replaced with another one when another burn-in board 20 reaches the end of the burn-in test within a certain time, for example, in the process of raising or lowering the temperature of the buffer burn-in chamber 104. The burn-in board 20 can be loaded via the buffer burn-in chamber 104. In the embodiment, for example, the first buffer burn-in chamber 104 is set as a temperature rising chamber, and the other buffer burn-in chamber 104 is set as a temperature decreasing chamber.

  When the burn-in board 20 of the main burn-in chamber 102 reaches the end of the burn-in test, the controller 106 causes the load device to send the burn-in board 20 into the buffer burn-in chamber 104 for lowering the temperature, and lowers the temperature.

  At the same time, the control device 106 causes the load device to send the burn-in board 20 before the test into the buffer burn-in chamber 104 at the elevated temperature, and after the preheating is completed, sends the burn-in board 20 before the test to the main burn-in chamber 102. Perform a burn-in test. When the preheating test is the same type of semiconductor device 206 (for example, DRAM), the semiconductor device burn-in apparatus having the multi-chamber structure of the present invention can perform the test for 24 hours without stopping, and the throughput of the test (throughput) ) Can be effectively increased. In this embodiment, except for the addition of the buffer burn-in chamber 104, the other structures and the test process are the same as described above, and thus will not be described in detail.

The above description is only a comparatively excellent example of the present invention and does not limit the patent application right of the present invention. Further, since the above description can be understood and carried out by those skilled in the art, other equivalent changes or modifications completed without departing from the gist of the present disclosure are claimed. Included in the range.

1 is a schematic view of a semiconductor element burn-in apparatus having a multi-chamber structure of the present invention. It is a schematic diagram of a burn-in board. It is a burn-in flow schematic diagram of the semiconductor element which has the multi-chamber structure of this invention. It is a semiconductor element failure rate growth curve. It is a failure rate experience reference line. It is a burn-in flow schematic diagram of another specific Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Burn-in apparatus 102 Main burn-in chamber 104 Buffer burn-in chamber 106 Control apparatus 110 Gate 120 Gate 20 Burn-in board 202 Test socket 204 Connection interface 206 Semiconductor element

Claims (4)

At least one burn-in board is disposed, a plurality of test sockets are provided on the burn-in board, and each test socket has a main burn-in chamber capable of accommodating a semiconductor element;
A buffer burn-in chamber in which a first gate and a second gate are arranged and communicated with the main burn-in chamber via the first gate;
A load device that loads these burn-in boards and is movable between the first gate and the second gate;
A control device capable of controlling the main burn-in chamber and each buffer burn-in chamber, and the load device;
A semiconductor device burn-in apparatus having a multi-chamber structure. Providing a main burn-in chamber provided with at least one slot substrate provided with a plurality of slots, and a buffer burn-in chamber;
Providing at least one burn-in board provided with a plurality of test sockets containing semiconductor elements;
Loading the burn-in board into a buffered burn-in chamber;
Heating the buffer burn-in chamber and performing preheating so that the temperature of each semiconductor device on the burn-in board reaches the burn-in temperature;
Loading each burn-in board in the buffer burn-in chamber to the main burn-in chamber, loading the burn-in board;
Providing an electrical test signal from the control device to each semiconductor element to perform an electrical test;
Calculating a failure rate of these semiconductor elements by receiving a test signal returned from each semiconductor element by the control device; and
The controller determines whether the burn-in test is completed on these burn-in boards; and
A semiconductor device burn-in method having a multi-chamber structure including at least After determining that the burn-in test is completed on a burn-in board with a control device, the flow that the control device continues is:
Transferring the burn-in board from the main burn-in chamber into a buffered burn-in chamber, loading the burn-in board that has already completed the burn-in test;
Lowering the temperature in the buffer burn-in chamber and adjusting the temperature;
Removing the burn-in board that has already completed the burn-in test and transporting the burn-in board out of the buffer burn-in chamber;
Providing a pre-test burn-in board and placing it in a buffered burn-in chamber;
Adjusting the temperature in the buffer burn-in chamber so that the temperature in the buffer burn-in chamber reaches the temperature of the burn-in;
Loading the pre-test burn-in board into the main burn-in chamber;
Performing electrical tests, providing electrical test signals, and performing electrical tests on each semiconductor device;
Calculating a failure rate of these semiconductor elements by receiving a test signal returned from each semiconductor element by the control device; and
The controller determines whether the burn-in test is completed on these burn-in boards; and
A semiconductor device burn-in method having a multi-chamber structure. At least one burn-in board is disposed, a plurality of test sockets are provided on the burn-in board, and each test socket has a main burn-in chamber capable of accommodating a semiconductor element;
A temperature rising buffer burn-in chamber in which a first gate and a second gate are arranged and communicated with the main burn-in chamber via the first gate;
A temperature-decreasing buffer burn-in chamber, wherein the first gate and the third gate are arranged, and can be communicated with the main burn-in chamber through the first gate;
At least one load device that loads these burn-in boards and is movable between the first gate, the second gate, and the third gate;
A control device capable of controlling the main burn-in chamber and each buffer burn-in chamber, and the load device;
A semiconductor device burn-in apparatus having a multi-chamber structure.

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