JP2009147257A - Substrate laminating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate laminating method in which semiconductor wafers can be bonded together more suitably. <P>SOLUTION: The substrate laminating method includes: a measurement step (P11, P12) of measuring positions of a previously selected predetermined number of sample measurement points (SA) among measurement points set in each of regions (ES) to be measured of a first substrate (W1) and a second substrate (W2) under a first condition; a calculation step (P13) of performing statistical operations using the measured positions of the sample measurement points as operation parameters to calculate offsets of an array of the regions to be processed based upon a first reference mark and a second reference mark, etc.; a surface activating step (P15) of activating the surfaces of the first substrate and second substrate under a second condition different from the first condition; and a step (P18, P19) of putting the first substrate and second substrate one over the other based upon the calculation results of the calculation step while observing the first reference mark and second reference mark under the second condition. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a substrate bonding method for laminating substrates such as semiconductor wafers, and more particularly to a substrate bonding method for accurately bonding substrates on which a plurality of chips are formed.

  In recent years, as electronic devices such as mobile phones and IC cards have become highly functional, semiconductor chips (LSI, IC, etc.) mounted therein have been made thinner or smaller. In addition, in order to increase the storage capacity without reducing the line width, a three-dimensional mounting type semiconductor chip in which several layers of semiconductor wafers are stacked, such as an SD card or MEMS, is increasing.

Patent Document 1 discloses a method for bonding the bonding surfaces of semiconductor wafers by hydrophilization with plasma. The apparatus disclosed in Patent Document 1 bonds semiconductor wafers without exposing the semiconductor wafers to the atmosphere after performing a plasma treatment process using an energy wave that is an atomic beam, an ion beam, or plasma. In the second embodiment of Patent Document 1, plasma processing is first performed in a vacuum state, and a pair of semiconductor wafers are aligned and bonded.
JP-A-2005-294800

  However, if the alignment is performed after performing the plasma treatment process even in vacuum, the surfaces of the semiconductor wafers cleaned (activated) by plasma treatment are contaminated and the semiconductor wafers cannot be bonded to each other. A situation occurs. Further, it is difficult to move the stage with high accuracy in a vacuum, for example, about 300 mm. Further, in the first patent document 1, two points of alignment marks formed on the surface of the semiconductor wafer are observed. However, since hundreds of semiconductor chips are formed on the semiconductor wafer, it is only necessary to observe the two points. It is very difficult to join these hundreds of semiconductor chips without error.

In Patent Document 1, an alignment mark formed on the surface of a semiconductor wafer is observed from the back side of the wafer by infrared transmission, but infrared rays cannot be transmitted through a wafer doped with a high concentration of impurities. For this reason, there are cases where it cannot be applied to a MOS device wafer that is normally used.
Further, in Patent Document 1, a through hole is provided in the wafer holder for observation from the back side of the wafer. The electrostatic chuck or the vacuum chuck does not function in the region of the through hole, so that there is a problem that non-uniformity occurs in the wafer holding suction.

  The present invention has been made in order to solve the above-described problems, and the arrangement of the work areas under the first condition with respect to the work areas provided on the first substrate or the second substrate including the semiconductor wafer. The offset, rotation, and orthogonality are calculated, the surface activation process is performed under the second inspection, and the first substrate and the second substrate are overlapped with each other. It aims at providing the board | substrate bonding method which can perform joining.

The substrate bonding method according to this aspect is a substrate bonding method in which a first substrate having a measurement point set for each processing region is bonded to a second substrate. The substrate bonding method includes a holding step of holding a first substrate by a first substrate holding portion having a first reference mark, and holding a second substrate by a second substrate holding portion having a second reference mark, and a first condition Below, the measurement process of measuring the position of a predetermined number of sample measurement points selected in advance among the measurement points set for each processing region of the first substrate and the second substrate, and measurement of the sample measurement points A calculation step of performing statistical calculation using the position as a calculation parameter, and calculating at least one of the offset, rotation, and orthogonality of the arrangement of the respective work areas with reference to the first reference mark and the second reference mark; A surface activation process for activating the surfaces of the first substrate and the second substrate under a second condition different from the first condition; and a first reference mark and a second reference mark under the second condition. Guess While comprises a superposition step of first superimposing the substrate and the second substrate on the basis of the calculation result of the calculating step.
According to such a configuration, the arrangement of the work areas set on the first substrate and the second substrate is measured under the first condition, and the surface activation treatment is performed under the second condition to perform the first substrate and the second substrate. The work area with two substrates is joined. Measurement of the region to be processed can be accurately performed under the first condition, and the first substrate and the second substrate can be quickly bonded while maintaining the surface active state in the surface activation process.

  The substrate laminating method of the present invention can arrange individual processing regions formed on the substrate with high precision alignment, and can be quickly joined after the surface activation process, so that the processing regions are accurate and stable. Can be joined.

<Overall configuration of wafer bonding apparatus>
FIG. 1 is an overall perspective view of the wafer bonding apparatus 100.
The wafer bonding apparatus 100 includes a wafer loader WL and a wafer holder loader WHL. The wafer loader WL and the wafer holder loader WHL are articulated robots, and are movable in directions of six degrees of freedom (X, Y, Z, θX, θY, θZ). Further, the wafer loader WL can move a long distance in the Y direction along the rail RA, and the wafer holder loader WHL can move a long distance in the X direction along the rail RA.

  The wafer bonding apparatus 100 has a wafer stocker 10 for storing a plurality of semiconductor wafers W in the periphery thereof. The wafer bonding apparatus 100 has a wafer stocker 10-1 for storing the first semiconductor wafer W1 and a wafer stocker 10-2 for storing the second semiconductor wafer W2 in order to bond the first semiconductor wafer W1 and the second semiconductor wafer W2. And are prepared. Further, a wafer pre-alignment apparatus 20 for pre-aligning a semiconductor wafer W (hereinafter, referred to as a semiconductor wafer W when the first semiconductor wafer W1 and the second semiconductor wafer W2 are not distinguished) is provided near the wafer stocker 10. ing. The semiconductor wafer W taken out from the wafer stocker 10 by the wafer loader WL is sent to the wafer pre-alignment apparatus 20.

  The wafer bonding apparatus 100 includes a wafer holder stocker 30 that stores a plurality of wafer holders WH. Since the wafer holder WH can be used for both the first semiconductor wafer W1 and the second semiconductor wafer W2, the wafer holder stocker 30 is provided in one place. A wafer hod pre-alignment apparatus 40 that pre-aligns the wafer holder WH is provided in the vicinity of the wafer holder stocker 30. The wafer holder WH taken out from the wafer holder stocker 30 by the wafer holder loader WHL is sent to the wafer holder pre-alignment apparatus 40. In the wafer holder pre-alignment apparatus 40, the pre-aligned semiconductor wafer W is placed on the pre-aligned wafer holder WH by the wafer loader WL.

  The wafer bonding apparatus 100 has an aligner 50 for aligning a wafer holder WH on which a pair of semiconductor wafers W are placed. The aligner 50 determines which alignment mark AM is formed for each chip (one shot) formed on the semiconductor wafer W with respect to the reference mark FM (see FIG. 2 or FIG. 3) provided on the wafer holder WH at atmospheric pressure. Measure how they are arranged. Since several hundred chips are formed on the semiconductor wafer W, the alignment mark AM is measured at the main 8 to 30 sample measurement points, and the offset, rotation and orthogonality of the entire semiconductor wafer W are measured. Calculate degrees etc. Such an alignment method is hereinafter referred to as EGA (Enhanced Global Alignment).

  The wafer holder WH on which the semiconductor wafer W is placed is sent from the wafer holder pre-alignment apparatus 40 to the aligner 50 by the wafer holder loader WHL. The wafer holder WH that has finished the alignment measurement is sent to the plasma bonding apparatus 70 by the wafer holder loader WHL. The aligner 50 will be described in detail with reference to FIG.

  The plasma bonding apparatus 70 of the wafer bonding apparatus 100 performs plasma processing on a pair of semiconductor wafers W aligned by the aligner 50 via the wafer holder WH. Further, the plasma bonding apparatus 70 superposes the pair of semiconductor wafers W activated by the plasma processing while observing the reference mark FM. By doing so, metal bumps such as Cu, which are electrodes on the pair of semiconductor wafers W, are joined to each other. Further, the inside of the plasma bonding apparatus 70 is kept in a vacuum state. The plasma bonding apparatus 70 will be described in detail with reference to FIG.

  The wafer bonding apparatus 100 has a separation unit 80 next to the plasma bonding apparatus 70. The separation unit 80 removes the bonded semiconductor wafer W from the wafer holder WH. The semiconductor wafer W is taken out from the separation unit 80 by the wafer loader WL and sent to the bonded wafer stocker 85. The wafer holder WH is taken out from the separation unit 80 by the wafer holder loader WHL and returned to the wafer holder stocker 30 again. The bonded semiconductor wafer W is then diced and cut into individual chips.

  The wafer bonding apparatus 100 is provided with a main control unit 90 that controls the entire wafer bonding apparatus 100. The main control unit 90 performs overall control by exchanging signals with a control device that controls each device such as the wafer loader WL, the wafer holder loader WHL, the wafer pre-alignment device 20, and the wafer holder pre-alignment device 40.

<EGA with aligner 50>
FIG. 2 is a conceptual diagram showing the aligner 50 of the present embodiment. The semiconductor wafer W is placed on a wafer table 52 that is positioned two-dimensionally via a wafer holder WH. The wafer table 52 is supported on an air pressure bearing (not shown) on the stage 51 in an atmospheric pressure chamber. The stage 51 is provided with a linear motor 54, and the linear motor 54 drives the wafer table 52 in the XY directions. For example, when the diameter of the semiconductor wafer W is 300 mm, the moving range of the wafer table 52 is 300 mm or more.

  A moving mirror 53 is fixed to one end of the upper surface of the wafer table 52, and a laser interferometer 55 is disposed so as to face the moving mirror 53. Although the illustration is simplified in FIG. 2, the movable mirror 53 is composed of a plane mirror having a reflecting surface perpendicular to the X axis and a plane mirror having a reflecting surface perpendicular to the Y axis. The laser interferometer 55 includes two X-axis laser interferometers that irradiate the moving mirror 53 along the X axis and a Y axis that irradiates the moving mirror 53 along the Y axis. The X coordinate and Y coordinate of the wafer table 52 are measured by one laser interferometer 55 for the X axis and one laser interferometer 55 for the Y axis. The coordinate system (X, Y) composed of the X coordinate and the Y coordinate measured by the laser interferometer 55 is hereinafter referred to as a stage coordinate system.

  Further, the rotation angle of the wafer table 52 is measured by the difference between the measurement values of the two laser interferometers 55 for the X axis. Information on the X coordinate, the Y coordinate, and the rotation angle measured by the laser interferometer 55 is supplied to the coordinate measurement circuit 60 and the main control unit 90. The main control unit 90 monitors the supplied coordinates, and the linear motor 54 is monitored. Then, the positioning operation of the wafer table 52 is controlled.

  The aligner 50 has an alignment system CA. The alignment system CA includes a light source 62 that emits light having a wide-band wavelength, such as a halogen lamp, and the illumination light emitted from the light source 62 passes through a collimator lens 63, a beam splitter 64, and an objective lens 61. An alignment mark AM as a measurement point formed on W or a reference mark FM on the wafer holder is irradiated. Reflected light from the alignment mark AM or the reference mark FM on the wafer holder is guided onto the index plate 66 through the objective lens 61, the beam splitter 64, and the condenser lens 65, and an image of the alignment mark AM is formed on the index plate 66. Imaged.

  The light transmitted through the index plate 66 passes through the first relay lens 67 toward the beam splitter 68, and the light transmitted through the beam splitter 68 is formed by a two-dimensional CCD by the X-axis second relay lens 69X. Focused on the imaging surface of the CAX. The light reflected by the beam splitter 68 is focused on the imaging surface of the Y-axis imaging device CAY made of a two-dimensional CCD by the second Y-axis relay lens 69Y. On the imaging surfaces of the X-axis imaging device CAX and the Y-axis imaging device CAY, an image of the alignment mark AM or the reference mark FM and an image of the index mark on the index plate 66 are superimposed. The imaging signals of the imaging devices CAX and CAY are both supplied to the coordinate measuring circuit 60.

  FIG. 3A is a view for explaining an example of a plurality of alignment marks AM formed on the semiconductor wafer W. FIG. FIG. 3B shows a state in which the image of the alignment mark AM is formed on the index plate 66. The alignment mark AM shown in FIG. 3A is drawn only for sample measurement points, but may be formed for chips other than the sample measurement points.

  As shown in FIG. 3, chip regions ES1, ES2,..., ESM (M is an integer of 3 or more) are regularly formed on the semiconductor wafer W. A chip pattern is formed in each chip region ESi (i = 1 to M) by the steps up to that point. Further, each chip region ESi is divided by street lines (scribe lines) having a predetermined width extending in the x direction and the y direction, and an X axis and a Y axis are arranged at the center of the street line extending in the x direction in contact with each chip region ESi. An alignment mark AMi for measuring the two-dimensional direction of the shaft is formed.

  The x coordinate (design coordinate value) Dxi and the y coordinate (design coordinate value) Dyi of the alignment mark AMi on the semiconductor wafer W are known and stored in the storage unit in the main control unit 90 of FIG. ing. In this case, the x coordinate and the y coordinate of the alignment mark AMi are regarded as the x coordinate and the y coordinate of the chip region ESi, respectively.

  Of the plurality of chip areas ES1 to ESM set on the semiconductor wafer W, a predetermined number of chip areas are selected in advance as sample chips (sample measurement points). In the example shown in FIG. 3A, nine chip areas with hatching are selected as sample chips SA1 to SA9. Each of the sample chips SA1 to SA9 is provided with an alignment mark AMi along with the chip region ESi.

  In addition, a reference mark FM is formed on the wafer holder WH on which the semiconductor wafer W is placed at two locations on both sides of the semiconductor wafer W. The positional relationship between these two reference marks FM is known.

  The alignment mark AM and the reference mark FM used in the present embodiment have a cross shape including a linear pattern extending in the X direction and a linear pattern extending in the Y direction perpendicular to the X pattern. When the image of the alignment mark AM or the reference mark FM is formed on the index plate 66, an image shown in FIG. 3B is obtained. The image of the alignment mark AM includes an image AMx extending in the X direction and an image AMy extending in the Y direction, and the X-axis imaging device CAX and the Y-axis imaging device CAY detect the image AMx and the image AMy. Similarly, the image of the reference mark FM includes an image FMx extending in the X direction and an image FMy extending in the Y direction, and the X-axis imaging device CAX and the Y-axis imaging device CAY detect the image FMx and the image FMy.

  The scanning directions for reading photoelectric conversion signals from the pixels of the X-axis imaging device CAX and the Y-axis imaging device CAY are set in the X direction and the Y direction, respectively. By processing the image pickup signal of the image pickup apparatus CAY, the amount of X-direction misalignment between the X-axis alignment mark image AMy and the index mark 66a, and the Y-axis alignment mark AMx image and the index mark 66b Y The amount of displacement in the direction can be obtained. By using this alignment mark AM, position information in the X direction and position information in the Y direction can be obtained with a single measurement. The position information of the reference mark FM can be obtained similarly.

  Returning to FIG. 2 again, the coordinate measuring circuit 60 determines that the positional relationship between the image AMx of the alignment mark AM on the semiconductor wafer W and the index mark 66a on the index plate 66 and the measurement result of the laser interferometer 55 at that time. The X coordinate on the stage coordinate system (X, Y) of the alignment mark AM is obtained, and the X coordinate thus measured is supplied to the main control unit 90. Similarly, the Y coordinate on the stage coordinate system (X, Y) of the Y-axis alignment mark is also measured and supplied to the main controller 90.

  First, the main control unit 90 generates a measurement result using the alignment system CA of the chip area (sample chip) of the sample measurement point selected in advance from the chip area as the work area set on the semiconductor wafer W. Based on the EGA calculation, the arrangement of the chip areas on the semiconductor wafer W is calculated. Here, the EGA calculation performed in the main control unit 90 is outlined as follows.

  The main control unit 90 performs EGA calculation based on each measurement value and each design value of the sample chips SA1 to SA9. The EGA calculation performed here is a factor causing an alignment error, such as the residual rotation error Θ of the semiconductor wafer W, the orthogonality error Ω of the stage coordinate system (X, Y), and the linear expansion / contraction (scaling) of the semiconductor wafer W. Six operational parameters including Γx and Γy and offsets Ox and Oy of the semiconductor wafer W are taken into consideration. When these are used, they are expressed by the following equation (1). Further, the design x-coordinate and y-coordinate of the alignment mark AMn on the semiconductor wafer W are Dxn and Dyn, respectively.

An array coordinate value (Fxn, Fyn) for calculation of a position to be actually aligned is calculated from the above equation (1), and the semiconductor is based on the calculated coordinate value in the stage coordinate system (X, Y). The position of each chip area on the wafer W is determined.

  Further, the main controller 90 determines the coordinates of at least two reference marks FM on the wafer holder WH by the laser interferometer 55 in the stage coordinate system (X, Y). Next, the main control unit 90 converts the position of each chip region on the semiconductor wafer W in the wafer holder coordinate system with reference to the reference mark FM instead of the stage coordinate system (X, Y). This is because the wafer holder WH on which the semiconductor wafer W is placed is transferred to the plasma bonding apparatus 70 and bonded to the semiconductor wafer W.

  The main control unit 90 measures the two semiconductor wafers W (the first semiconductor wafer W1 and the second semiconductor wafer W2) to be combined with the alignment system CA, and uses the wafer holder coordinate system of each wafer holder WH as a reference to each semiconductor wafer. The state where the arrangement of the chip regions ESi of W overlaps most is calculated. That is, the main control unit 90 obtains an adjustment component that minimizes the error in the coordinate values of the chip regions ESn of the first semiconductor wafer W1 and the second semiconductor wafer W2 to be combined. The adjustment component is a shift amount (δx,) between the pair of reference marks FM1 of the first wafer holder WH1 on which the first semiconductor wafer W1 is placed and the pair of reference marks FM2 of the second wafer holder WH2 on which the second semiconductor wafer W2 is placed. δy). The shift amounts (δx, δy) are stored in a storage unit such as an internal memory of the main control unit 90.

  In the above embodiment, the case where nine sample chips SA1 to SA9 are set on the semiconductor wafer W has been described. However, the number of sample chips may be arbitrary.

<Plasma bonding apparatus 70>
FIG. 4 is a conceptual diagram showing the plasma bonding apparatus 70. The plasma bonding apparatus 70 can perform cleaning and pressure bonding of the semiconductor wafer W, and is performed in a vacuum chamber frame 71 as shown in FIG.

  The plasma bonding apparatus 70 holds the first semiconductor wafer W1 and the second semiconductor wafer W2 that have been EGA-measured by the aligner 50. The first semiconductor wafer W1 is supported by the first top plate TP1 in the −Z direction via the first wafer holder WH1. The first top plate TP1 is supported by the first base plate BP1, and the first base plate BP1 is provided in the chamber frame 71 of the plasma bonding apparatus 70.

On the other hand, the second semiconductor wafer W2 is supported by the second top plate TP2 in the + Z direction via the second wafer holder WH2. The second top plate TP2 is supported by a movable stage PZ provided with a piezo actuator. The movable stage PZ can move the second top plate TP2 in sub-micron units in the XY direction. The maximum stroke of the movable stage PZ is about 2 mm, and no air bearing or the like is required, so that the second top plate TP2 can be moved even at a vacuum degree of about 10 × 10 ² Pa.

  Further, the movable stage PZ is supported by a pressure elevator EV. The pressurized elevator EV can move the second semiconductor wafer W2 in the Z direction (vertical direction). Further, the pressurizing elevator EV can pressurize the semiconductor wafer W so that the semiconductor wafer W is evenly pressurized as necessary after the first semiconductor wafer W1 and the second semiconductor wafer W2 are brought into contact with each other. The pressurizing elevator EV is supported by the second base plate BP 2, and the second base plate BP 2 is provided in the chamber frame 71 of the plasma bonding apparatus 70.

The chamber frame 71 of the plasma bonding apparatus 70 has an exhaust pipe 74 in a part thereof, and a vacuum pump 73 is connected to the exhaust pipe 74. The degree of vacuum in the chamber frame 71 can be 10 × 10 ⁻² Pa or less, preferably 10 × 10 ⁻³ Pa or less. Further, the chamber frame 71 has a load lock gate 79, and the wafer holder WH on which the semiconductor wafer W is placed is carried into the plasma bonding apparatus 70 by the wafer holder loader WHL, and is carried out of the plasma bonding apparatus 70. can do. Although not shown, a load lock chamber for preliminary exhaust may be provided.

In the chamber frame 71, irradiation means 77 for irradiating energy waves or energy particles from the side is provided in a gap formed between the first semiconductor wafer W1 and the second semiconductor wafer W2 facing each other. Since the surface of the semiconductor wafer W is oxidized or a surface layer stabilized by adsorption of organic substances is formed, plasma, accelerated ion beam, fast atom beam (FAB) or radical beam in vacuum Such stable surface layer is removed by irradiating an energy wave such as a laser or the like, and an unstable and active surface is exposed to allow room temperature bonding. In this embodiment, the irradiation unit 77 is a unit that irradiates an ion beam. The ion beam is irradiated in a state where the degree of vacuum in the chamber frame 71 is 10 × 10 ⁻² Pa or less, preferably 10 × 10 ⁻³ Pa or less. In addition, you may provide further the mechanism which joins by heating at high temperature instead of normal temperature joining.

  The irradiation means 77 is inclined and arranged so as to prevent reflection in the irradiation direction of an ion beam as an irradiation energy wave or energetic particles. In this embodiment, the impurities are exhausted by the vacuum pump 73 via the exhaust pipe 74 in order to more reliably prevent the reflection and flying of the impurities generated by the etching by the ion beam irradiation.

  The cleaned first semiconductor wafer W1 and second semiconductor wafer W2 are aligned (positioned) by an infrared camera IRS provided in the plasma bonding apparatus 70. However, the infrared camera IRS does not observe the alignment mark AM formed on the semiconductor wafer W, but observes the reference mark FM provided on the wafer holder WH.

  In the alignment step, the second semiconductor wafer W2 is lifted together with the movable stage PZ by the pressure elevator EV and is brought close to the first semiconductor wafer W1 with a minute gap. In this state, the relative position between the first wafer holder WH1 and the second wafer holder WH2 is observed by the infrared camera IRS. In the present embodiment, the infrared camera IRS is disposed above, but may be disposed below.

Here, the reference mark FM provided on the wafer holder WH will be described with reference to FIG. FIG. 5A is a top view of the wafer holder WH, and FIG. 5B is a cross-sectional view taken along the line AA in FIG.
In the reference mark FM, a transmission shape pattern or a metal pattern is formed on the mark base material 41. Two or more fiducial marks FM are attached to the wafer holder WH. Although the outer shape of the mark base material 41 is not particularly defined, a circular shape as shown in FIG. As shown in FIG. 5B, the wafer holder WH having the reference mark FM has an electrostatic chuck electrode 45 of an electrostatic chuck for attracting the semiconductor wafer.

  The relationship between the material of the wafer holder WH and the material of the mark base material 41 is preferably the one having substantially the same coefficient of thermal expansion. For example, the wafer holder WH is made of silicon carbide or aluminum nitride, and the same material is used for the mark base material 41. preferable. The mark base material 41 may be formed by forming a mark pattern of copper or titanium on silicon (Si). As an example, the thickness of the mark base material 41 is preferably 200 μm to 700 μm, particularly 300 μm, from the viewpoint of strength, processing accuracy, and processability.

  The mark base material 41 is attached to a through hole 43 provided in the wafer holder WH. The through hole 43 is designed in consideration of the field of view of the microscope of the infrared camera IRS. For example, the inner diameter is 10 mm, and the diameter of the mark base material 41 (or one side of the square) is preferably about 16 mm. Note that the reference mark FM can be read not only by infrared rays but also by using, for example, X-rays or visible light.

<Operation from EGA measurement to bonding of semiconductor wafer W>
FIG. 6 is a flowchart from the EGA measurement of the alignment mark AM of the first semiconductor wafer W1 to the bonding of the first semiconductor wafer W1 and the second semiconductor wafer W2. Steps P11 to P14 described below are steps performed in the aligner 50 at atmospheric pressure, and steps P15 to P19 are steps performed in the plasma bonding apparatus 70 in vacuum.

In Step P11, the aligner 50 measures the sample chips SA1 to SA9 of the first semiconductor wafer W1, calculates the entire arrangement of the chip areas ES1 to ESn by EGA, and also measures the reference mark FM1 of the first wafer holder WH1.
Similarly, in step P12, the aligner 50 measures the sample chips SA1 to SA9 of the second semiconductor wafer W2, calculates the entire arrangement of the chip areas ES1 to ESn by EGA, and also measures the reference mark FM2 of the second wafer holder WH2. To do.

  In step P13, the main control unit 90 sets the reference mark FM1 and the reference mark FM1 so that the overlap error between the entire chip area ES of the first semiconductor wafer W1 and the entire chip area ES of the second semiconductor wafer W2 is minimized. A shift amount (σx, σy) from the reference mark FM2 is calculated. Thus, regardless of the alignment mark AM on the semiconductor wafer W, if the reference mark FM1 and the reference mark FM2 are shifted and overlapped by the shift amounts (σx, σy), the chip region ES of the first semiconductor wafer W1 and the first mark (2) The chip area ES of the semiconductor wafer W2 is bonded with a minimum error.

  In Step P14, the first wafer holder WH1 and the second wafer holder WH2 are transferred from the aligner 50 to the plasma bonding apparatus 70 by the wafer holder loader WHL. As a result, the first wafer holder WH1 and the second wafer holder WH2 are arranged from atmospheric pressure to vacuum.

  In Step P15, the plasma bonding apparatus 70 irradiates the first semiconductor wafer W1 and the second semiconductor wafer W2 with an ion beam by the irradiation means 77. As a result, the surfaces of the first semiconductor wafer W1 and the second semiconductor wafer W2 are cleaned, and the respective metal bumps are in a surface active state and are bonded to each other at room temperature. Note that the first semiconductor wafer W1 and the second semiconductor wafer W2 may be heated as necessary.

In Step P16, the pressure elevator EV of the plasma bonding apparatus 70 brings the second semiconductor wafer W2 close to the first semiconductor wafer W1.
In step P17, the infrared camera IRS simultaneously observes the reference mark FM1 of the first wafer holder WH1 and the reference mark FM2 of the second wafer holder WH2 in a state where the first semiconductor wafer W1 and the second semiconductor wafer W2 are close to each other. . The infrared camera IRS observes at least two fiducial marks FM1 and at least two fiducial marks FM2, and the errors in the XY directions and the rotation errors are observed, and the error signals are sent to the main controller 90. .

  In Step P18, the main control unit 90 drives the movable stage PZ so that the reference mark FM1 and the reference mark FM2 are in the relationship of the shift amount (δx, δy) from the observation result of the infrared camera IRS. That is, the aligner 50 has already determined an adjustment component that minimizes the error in the coordinate values of the chip regions ESn of the first semiconductor wafer W1 and the second semiconductor wafer W2 to be joined. The adjustment component is a shift amount (δx,) between the pair of reference marks FM1 of the first wafer holder WH1 on which the first semiconductor wafer W1 is placed and the pair of reference marks FM2 of the second wafer holder WH2 on which the second semiconductor wafer W2 is placed. δy). For this reason, the main control unit 90 drives the movable stage PZ so that the reference mark FM1 and the reference mark FM2 are in the relationship of the shift amount (δx, δy) from the observation result of the infrared camera IRS. By this driving, the error of the coordinate value of each chip area ESn of the first semiconductor wafer W1 and the second semiconductor wafer W2 is minimized.

  In step P19, the pressure elevator EV raises the second semiconductor wafer W2 and brings it into contact with the first semiconductor wafer W1. Even when a pressure operation is applied at the time of joining and there is a non-smooth portion on the joining surface, the joining surfaces are surely brought into close contact over the entire predetermined area by applying an appropriate pressure. The semiconductor wafer W1 and the second semiconductor wafer W2 are in a desired good bonded state. In addition, when heating is performed, heating can be used together by embedding a heater in the top plate TP or the like.

  When three or more semiconductor wafers W are sequentially stacked, the next semiconductor wafer W may be sequentially stacked and bonded to the stacked body of semiconductor wafers W previously bonded.

  The plasma bonding apparatus 70 described with reference to FIGS. 4 to 6 performs irradiation with an ion beam 77, alignment with an infrared camera IRS, and superposition with a pressurizing elevator EV, and heating and pressurizing as necessary. However, an apparatus for irradiating an ion beam, an apparatus for performing alignment and superposition, and a heating / pressurizing apparatus may be disposed separately. A plurality of time-consuming apparatuses, such as heating and pressing apparatuses, may be arranged.

1 is an overall perspective view of a wafer bonding apparatus 100. FIG. It is the conceptual diagram which showed the aligner 50. (A) is a figure for demonstrating an example of multiple alignment mark AM formed in the semiconductor wafer W. FIG. FIG. 6B is a diagram showing a state in which an image of the alignment mark AM is formed on the index plate 66. FIG. It is the conceptual diagram which showed the plasma bonding apparatus 70. (A) is a top view of the wafer holder WH. (B) is AA sectional drawing of (a). 4 is a flowchart from EGA measurement of an alignment mark AM of a semiconductor wafer W to bonding of the semiconductor wafer W.

Explanation of symbols

BP ... Base plate (BP1 ... First base plate, BP2 ... Second base plate)
CA ... Imaging device (CAX ... X-axis imaging device, CAY ... Y-axis imaging device)
EV ... Pressurized elevator IRS ... Infrared camera RA ... Rail SA ... Sample chip TP ... Top plate (TP1 ... First top plate, TP2 ... Second top plate)
W: Semiconductor wafer (W1: First semiconductor wafer, W2: Second semiconductor wafer)
WH: Wafer holder (WH1: First wafer holder, WH2: Second wafer holder)
WL ... Wafer loader WHL ... Wafer holder loader 10 ... Wafer stocker 20 ... Wafer pre-alignment device 30 ... Wafer holder stocker 40 ... Wafer holder pre-alignment device 50 ... Aligner 51 ... Stage 52 ... Wafer table 53 ... Moving mirror 54 ... Linear motor 61 ... Objective lens 64 ... Beam splitter 66 ... Indicator plate (66a, 66b ... Indicator mark)
DESCRIPTION OF SYMBOLS 70 ... Plasma bonding apparatus 71 ... Chamber frame 77 ... Irradiation means 80 ... Separation unit 85 ... Wafer stocker 90 ... Main control part 100 ... Wafer bonding apparatus

Claims (7)

In the substrate laminating method for laminating the first substrate and the second substrate having the measurement points set for each processing region,
A holding step of holding the first substrate by a first substrate holding part having a first reference mark and holding the second substrate by a second substrate holding part having a second reference mark;
A measurement step of measuring the positions of a predetermined number of sample measurement points selected in advance among measurement points set for each of the processing regions of the first substrate and the second substrate under a first condition;
Statistical calculation is performed using the measurement position of the sample measurement point as a calculation parameter, and at least one of the offset, rotation, and orthogonality of the array of the respective work areas based on the first reference mark and the second reference mark A calculation step of calculating
A surface activation step of activating surfaces of the first substrate and the second substrate under a second condition different from the first condition;
An overlaying step of superimposing the first substrate and the second substrate based on a calculation result of the calculation step while observing the first reference mark and the second reference mark under the second condition;
A method for laminating substrates, comprising: The substrate bonding method according to claim 1, further comprising a pressing step of pressing the first substrate and the second substrate after the overlaying step. 3. The substrate bonding method according to claim 2, wherein the pressurizing step includes a step of heating the first substrate and the second substrate. 4. The substrate bonding method according to claim 1, wherein the first condition is a state of normal temperature and atmospheric pressure, and the second condition is in a vacuum or an inert gas. 5. The substrate bonding method according to claim 1, wherein in the superimposing step, a positional relationship between the first reference mark and the second reference mark is observed by image processing. . 2. The superimposing step of superimposing the first substrate and the second substrate by moving an electromechanical displacement driving stage on which the first substrate holder is placed. The substrate bonding method according to claim 5. 6. The measurement step according to claim 1, wherein a laser interferometer is used to measure the position of a stage that moves with an air bearing on which the first substrate holding part or the second substrate holding part is placed. The board | substrate bonding method as described in any one of Claims.