JP2009147199A - Semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, capable of suppressing variations in the drive forces of MOS transistors even when a liner film for giving strain to a channel is formed. <P>SOLUTION: In order to cover gate structures 5 and 6, a lower layer insulating film 10 is formed on a semiconductor substrate 1. Thereafter, the liner film 11 consisting of silicon nitride is formed on the lower layer insulating film 10. Then, a stress change process for changing the stress of the liner film 11 is executed. Also, coverage that the lower layer insulating film 10 has when forming the film is higher (better) than coverage that the liner film 11 has when forming the film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a SiN liner film capable of generating strain in a channel region of a MOS transistor and a method for manufacturing the same.

  In recent semiconductor devices, a technique for applying a local strain to a channel region of a MOS (Metal Oxide Semiconductor) transistor is being adopted. By employing this technique, the mobility of carriers in the channel region can be improved. There are several methods for applying a local strain to the channel region. As one of the typical techniques, there is a technique using a liner film made of a silicon nitride film having a tensile stress or a compressive stress in the film itself (for example, Patent Document 1).

  For example, a liner film having a compressive stress that the film itself tends to shrink is applied to the NMOS transistor. On the other hand, a liner film having a tensile stress that the film itself tends to stretch is applied to the PMOS transistor. By applying these liner films, strain in the tensile direction or strain in the compression direction can be generated in the channel region of each MOS transistor, and carrier mobility can be improved. When the strain in the channel region applied by the liner film is large, the carrier mobility is further improved. Therefore, it is important to improve the driving capability of the MOS transistor by forming a thicker film having higher stress.

  In the case of forming a liner nitride film having compressive stress on the NMOS transistor, for example, the following process is adopted. First, a silicon nitride film (liner film) having a low film density and a low compressive stress is formed by plasma CVD so as to cover the gate electrode. The silicon nitride film generally has poor coverage (film coverage). Thereafter, for example, the silicon nitride film is subjected to UV irradiation while being subjected to heat treatment (including UV irradiation treatment or treatment including at least one of the heat treatment). Thereby, the film density of the silicon nitride film is increased, and the compressive stress of the silicon nitride film can be further increased. Therefore, a larger strain can be generated in the channel region of the NMOS transistor.

  In general, an NMOS transistor and a PMOS transistor have different directions of strain generated in a channel region for improving carrier mobility. Therefore, when a liner film having compressive stress is applied to a PMOS transistor, the carrier mobility in the PMOS transistor is reduced. Therefore, a technique called DSL (Dual Stress Liner) that can form liner films having different stresses in the NMOS transistor and the PMOS transistor is employed.

JP 2007-59473 A

  As described above, when the film quality of the liner nitride film is changed by UV irradiation, a greater stress is concentrated on the liner nitride film (silicon nitride film) near the boundary between the gate structure and the semiconductor substrate. Therefore, the stress concentration may cause slits in the liner nitride film near the boundary. The degree of formation / non-formation and formation of the slit differs for each MOS transistor. When variations occur in the formation of slits as described above, variations occur in the strain generated in the channel region. That is, the driving force varies for each MOS transistor.

  Accordingly, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device that can suppress variation in driving force of a MOS transistor even when a liner nitride film for applying strain to a channel is formed. With the goal.

  In one embodiment according to the present invention, a liner film made of a silicon nitride film is formed on a lower insulating film. Here, the coverage of the lower insulating film during film formation is higher (good) than the coverage of the liner film during film formation.

  According to the above embodiment, the formation of the lower insulating film improves the overhang shape of the liner film. Thereby, it can suppress that a slit generate | occur | produces in a liner film | membrane. Therefore, even if a liner film for applying strain to the channel is formed on the semiconductor substrate, variation in driving force of the NMOS transistor can be suppressed.

  First, an outline of a method for manufacturing a semiconductor device according to the present invention will be described.

  First, a lower insulating film is formed on a semiconductor substrate in a region where an NMOS transistor is formed. The coverage of the lower insulating film when forming the lower insulating film is better (that is, higher) than the coverage of the liner film when forming the liner film described later. In other words, the density of the lower insulating film when forming the lower insulating film is higher than the density of the liner film when forming the liner film described later (however, in the case of the same SiN-based film type) ).

  Next, a liner film made of silicon nitride (SiN) is formed on the lower insulating film. The liner film has a low density (lower density than the lower insulating film and the upper insulating film) and has a first stress (low compressive stress). The liner film can generate tensile strain in the channel region of the NMOS transistor.

  Next, a process for increasing the stress (for example, UV irradiation process or heat treatment, which can be grasped as a stress change process) is performed on the liner film. By the stress change treatment, the liner film becomes a film having a higher second stress (the second stress is a higher compressive stress than the low compressive stress).

  Thereafter, an upper insulating film is formed on the liner film. The coverage of the upper insulating film when forming the upper insulating film is better (higher) than the coverage of the liner film when forming the liner film. In other words, the density of the upper insulating film when forming the upper insulating film is higher than the density of the liner film when forming the liner film.

  Note that the step of performing the stress change process and the step of forming the upper insulating film may be interchanged. That is, after the liner film is formed, after the upper insulating film is formed on the liner film, a process for increasing the stress of the liner film may be performed.

  In general, the following relationship is established between the coverage of a film at the time of film formation and the density of the film at the time of film formation. That is, the higher the density of the film during film formation, the better the coverage of the film during film formation. Note that in a finished product, the relationship between the film density and the coverage may not be established depending on a series of steps performed on the semiconductor device.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to process cross-sectional views.

  Forming element isolation film 2, well regions 3 and 4, gate structures 5 and 6, sidewall films SW 1 and SW 2, and source / drain regions 7 and 8 on a semiconductor substrate 1 made of silicon by a normal CMOS process. (See FIG. 1).

  The semiconductor substrate 1 has a first region 100 in which an NMOS transistor is formed and a second region 200 in which a PMOS transistor is formed. The element isolation film 2 is formed in the upper surface of the semiconductor substrate 1. The element isolation can electrically isolate the NMOS transistor and the PMOS transistor.

  A p-type well region 3 is formed in the upper surface of the semiconductor substrate 1 in the first region 100. On the other hand, an n-type well region 4 is formed in the upper surface of the semiconductor substrate 1 in the second region 200. A gate structure (which can be grasped as a first gate structure) 5 constituting an NMOS transistor is formed on the semiconductor substrate 1 in the first region 100. On the other hand, on the semiconductor substrate 1 in the second region 200, a gate structure (which can be grasped as a second gate structure) 6 constituting a PMOS transistor is formed.

  Here, each of the gate structures 5 and 6 is a stacked body in which a gate insulating film and a gate electrode are stacked in this order. In each cross-sectional view including FIG. 1, the boundary between the gate insulating film and the gate electrode is not shown. An L-shaped first sidewall film SW1 is formed on both side surfaces of each gate structure 5 and 6. Furthermore, a second sidewall film SW2 is formed on the first sidewall film SW1.

  In the upper surface of the semiconductor substrate 1 on both sides of the gate structure 5, n + type source / drain regions 7 are formed. On the other hand, p + type source / drain regions 8 are formed in the upper surface of the semiconductor substrate 1 on both sides of the gate structure 6. Here, each of the source / drain regions 7 and 8 has a two-stage structure with different impurity concentrations.

  The formation method of the element isolation film 2, the well regions 3 and 4, the gate structures 5 and 6, and the source / drain regions 7 and 8 is a well-known technique. Therefore, description of these detailed forming methods is omitted here.

  Next, a known silicide process is performed on the upper surface of the predetermined semiconductor substrate 1 and the upper surfaces of the gate structures 5 and 6. Thereby, as shown in FIG. 1, silicide films 9 made of NiSi are formed on the upper surface of the predetermined semiconductor substrate 1 and the upper surfaces of the gate structures 5 and 6, respectively.

  Next, for example, a thermal CVD (Chemical Vapor Deposition) method is performed on the semiconductor substrate 1. Thereby, as shown in FIG. 1, a lower insulating film (which can be grasped as a first lower insulating film) 10 is formed on the semiconductor substrate 1 adjacent to the gate structures 5 and 6 so as to cover the gate structures 5 and 6. Form a film.

  The lower insulating film 10 can also be formed by a plasma CVD method under conditions that increase the film density. For example, the plasma CVD method is a condition for increasing the stage temperature or a condition under a low pressure.

As described above, when the lower insulating film 10 is formed by the thermal CVD method or the plasma CVD method under the above-described conditions, the lower insulating film 10 is a conformal (high coverage) film with a high density. It is formed. That is, the coverage of the lower insulating film 10 is higher than the coverage of the liner film 11 described later at least when the lower insulating film 10 is formed. As the lower insulating film 10, for example, a SiO ₂ film, a SiN film, a SiON film or the like can be employed.

  In the case of forming the lower insulating film 10 having the above film quality, the thermal CVD method is more suitable than the plasma CVD method.

  Next, a plasma CVD method is performed on the semiconductor substrate 1. The conditions for the plasma CVD method are, for example, a low stage temperature or high pressure. As a result, a liner film 11 made of silicon nitride (SiN) is formed on the lower insulating film 10 as shown in FIG.

  The liner film 11 formed by the plasma CVD method has a low film density and low coverage (bad) during film formation. The liner film 11 is a film that can generate tensile strain in the channel region of the NMOS transistor. At the stage of forming the liner film 11, the liner film 11 has a weak compressive stress (including a case where there is almost no stress). The liner film 11 also functions as an etching stopper for an insulating film formed in an upper layer.

  Thereafter, UV irradiation is performed on the liner film 11 formed in the first region 100 and the second region 200.

  The liner film 11 is a film that can increase the stress of the film by, for example, UV irradiation treatment or heat treatment. From this point of view, the UV irradiation treatment, heat treatment, and the like can be understood as “treatment for increasing the stress of the film (stress change treatment)”. Therefore, the compressive stress of the liner film 11 becomes stronger by the UV irradiation.

  When the liner film 11 having the above film quality is formed, the plasma CVD method is most suitable.

  Next, for example, a thermal CVD method is performed on the semiconductor substrate 1. Thereby, as shown in FIG. 3, an upper insulating film (which can be grasped as a first upper insulating film) 12 is formed on the liner film 11 so as to cover the gate structures 5 and 6.

  The upper insulating film 12 can also be formed by a plasma CVD method under conditions that increase the film density. For example, the plasma CVD method is a condition for increasing the stage temperature or a condition under a low pressure.

As described above, when the upper insulating film 12 is formed by the thermal CVD method or the plasma CVD method under the above conditions, the upper insulating film 12 is a conformal (high coverage) film. It is formed. That is, the coverage of the upper insulating film 12 is higher than the coverage at the time of forming the liner film 11 at least when the upper insulating film 12 is formed. As the upper insulating film 12, for example, a SiO ₂ film, a SiN film, a SiON film or the like can be employed.

  In the case of forming the upper insulating film 12 having the above film quality, the thermal CVD method is more suitable than the plasma CVD method.

  Thereafter, normal semiconductor device manufacturing processes such as interlayer insulating films, contact plugs, and wiring are performed.

  In the above description, the case where both the formation of the lower insulating film 10 and the formation of the upper insulating film 12 are performed is mentioned. However, the formation of the lower insulating film 10 or the formation of the upper insulating film 12 can be omitted. When the formation of the lower insulating film 10 is omitted, the liner film 11 is formed directly on the semiconductor substrate 1 so as to cover the gate structures 5 and 6. Here, when the formation is omitted, naturally, the lower insulating film 10 or the upper insulating film 12 is not formed in the finished product (a configuration in which the lower insulating film 10 or the upper insulating film 12 in FIG. 3 is omitted).

  By the way, without forming the lower insulating film 10, the liner film 11 is formed on the semiconductor substrate 1 so as to cover the gate structures 5 and 6, and then the stress change process is performed on the liner film 11. And In this case, stress concentrates on the liner film 11 near the boundary between the gate structures 5 and 6 (more specifically, the sidewall SW2) and the semiconductor substrate 1 due to the stress change process. That is, stress concentrates in the refracted region of the liner film 11. Therefore, as shown in FIG. 4, a slit (crack) S <b> 1 can occur in the refracted region of the liner film 11.

  On the other hand, in the method of manufacturing a semiconductor device according to the present embodiment, the liner film 11 is formed on the lower insulating film 10 after the lower insulating film 10 is formed. The coverage of the lower insulating film 10 is better (higher) than the coverage of the liner film 11 at the time of film formation, at least when the lower insulating film 10 is formed.

  Therefore, the formation of the lower insulating film 10 makes the uneven shape of the base on which the lower insulating film 10 is formed smoother. As a result, the overhang shape of the liner film 11 is improved. Therefore, even if stress concentrates on the liner film 11 near the boundary between the gate structures 5 and 6 (more specifically, the sidewall SW2) and the semiconductor substrate 1 due to the stress change process, the lower insulating film 10 is not formed. Compared with the case (FIG. 4), the stress is relieved. Therefore, the occurrence of the slit S1 in the liner film 11 near the boundary between the gate structures 5 and 6 (or the gate structures 5 and 6 in which the sidewall films SW1 and SW2 are formed) and the semiconductor substrate 1 is suppressed. be able to. In other words, it is possible to suppress variations in the driving power of the NMOS transistor, which are caused by the generation of the slit S1.

  The lower insulating film 10 is not affected by the stress change process. Therefore, no slit is generated in the lower insulating film 10.

  In the above manufacturing method, the upper insulating film 12 is formed on the liner film 11. The coverage of the upper insulating film 12 is better (higher) than the coverage of the liner film 11 at the time of film formation, at least when the upper insulating film 12 is formed.

  Therefore, for example, even if the formation of the lower insulating film 10 is omitted and the slit S1 is formed in the liner film 11 as shown in FIG. 4 by the stress change process, the slit S1 is connected by the upper insulating film 12. Therefore, the slit S1 enlargement and variation in the subsequent steps are improved. In other words, even if the slit S1 is generated in the liner film 11, the formation of the upper insulating film 12 can suppress variations in driving force of the NMOS transistor.

  As described above, the formation of either the lower insulating film 10 or the upper insulating film 12 may be omitted. However, by forming both insulating films 10 and 12, it is possible to achieve both suppression of the generation of the slit S1 in the liner film 11 and suppression of the influence of the driving force of the transistor due to the slit S1.

  Further, as described above, after the upper insulating film 12 is formed, the liner film 11 may be subjected to stress change processing. In this case, even if the stress change process is performed on the liner film 11, the occurrence of the slit S <b> 1 in the liner film 11 due to the presence of the upper insulating film 12 with good coverage can be suppressed.

  By the way, the insulating film containing at least oxygen generally has better coverage than the liner film 11 which is a SiN film at the time of film formation. Therefore, an insulating film containing at least oxygen can be employed as the lower insulating film 10 and the upper insulating film 12 which are films with good coverage. Here, the good / bad relationship (high / low relationship) of the coverage among the lower insulating film 10, the liner film 11 and the upper insulating film 12 can change depending on the semiconductor device process after the step of FIG. However, the composition of the lower insulating film 10, the liner film 11, and the upper insulating film 12 does not change even in the finished product.

  That is, when an insulating film containing at least oxygen is employed as the lower insulating film 10 and the upper insulating film 12, even in a finished semiconductor device, the lower insulating film 10 has a composition containing oxygen, and the upper insulating film 12 Also has a composition containing oxygen. The liner film 11 remains SiN even in the finished product. As described above, the formation of the lower insulating film 10 or the upper insulating film 12 can be omitted.

  In general, the thinner the film thickness, the better the coverage during film formation. For example, similarly to the liner film 11, it is assumed that the lower insulating film 10 and the upper insulating film 12 contain nitrogen. If the film thickness of the lower insulating film 10 and the film thickness of the upper insulating film 12 are smaller than the film thickness of the liner film 11, the coverage of both the insulating films 10 and 12 is better than the coverage of the liner film 11. (high).

  Further, when both the insulating films 10 and 12 contain oxygen as described above, the both insulating films 10 and 12 have better coverage (higher) than the liner film 11 made of SiN. Furthermore, as described above, if the thickness of both insulating films 10 and 12 containing oxygen is made thinner than the thickness of the liner film 11 made of SiN, the coverage of both insulating films 10 and 12 is further improved. (Becomes higher).

  Therefore, an insulating film containing at least oxygen or nitrogen can be employed as the lower insulating film 10 and the upper insulating film 12. Here, the good / bad relationship (high / low relationship) of the coverage among the lower insulating film 10, the liner film 11 and the upper insulating film 12 can change depending on the semiconductor device process after the step of FIG. However, the composition and film thickness of each film 10-12 do not change even in the finished product.

  Therefore, it is assumed that the lower insulating film 10 and the upper insulating film 12 are made of insulating films containing oxygen or nitrogen and having a thickness smaller than that of the liner film 11 made of SiN. In this case, even in the finished semiconductor device, the lower insulating film 10 and the upper insulating film 12 have a composition containing oxygen or nitrogen. The liner film 11 remains SiN even in the finished product. Further, the film thickness of the lower insulating film 10 and the film thickness of the upper insulating film 12 remain thinner than the film thickness of the liner film 11. As described above, the formation of the lower insulating film 10 or the upper insulating film 12 can be omitted.

  Here, examples of the insulating film containing at least oxygen or nitrogen include SiO, SiN, and SiON, and SiO, SiN, and SiON containing fluorine or carbon.

  Further, the space between the adjacent gate structures 5 (or adjacent gate structures 6) is about 140 nm, the thickness of the first sidewall film SW1 is 10 nm, and the thickness of the second sidewall film SW2 is 30 nm. Suppose that it is a degree. In this case, the film thickness of each film 10-12 can be set as follows, for example. The film thickness of the lower insulating film 10 is 5 to 15 nm, the film thickness of the liner film 11 is approximately 25 to 15 nm, and the film thickness of the upper insulating film 12 is approximately 5 to 15 nm.

  Further, both the lower insulating film 10 and the upper insulating film 12 have a high density and a high coverage when formed. Therefore, the film quality does not change even when the stress change process is performed. That is, both the stress of the lower insulating film 10 and the stress of the upper insulating film 12 hardly change even in the finished product. Note that since both the lower insulating film 10 and the upper insulating film 12 are not films that function as stress films in this embodiment, the stress in the film is small (including zero).

  On the other hand, the liner film 11 is a film for applying strain to the channel region of the NMOS transistor. The liner film 11 has a low density and a low coverage at the time of film formation. Therefore, the film quality changes greatly by applying the stress change process. That is, the compressive stress of the liner film 11 increases greatly.

  Here, the good / bad relationship (high / low relationship) of the coverage among the lower insulating film 10, the liner film 11 and the upper insulating film 12 can change depending on the semiconductor device process after the step of FIG. However, when the manufacturing method according to the present embodiment is employed, the magnitude relationship between the stresses of the respective films 10 to 12 can be specified as follows in the semiconductor device that is a finished product.

  That is, in the finished product, the stress that the lower insulating film 10 has is smaller than the stress that the liner film 11 has. Further, in the finished product, the stress that the upper insulating film 12 has is smaller than the stress that the liner film 11 has. As described above, the formation of the lower insulating film 10 or the upper insulating film 12 can be omitted.

  When the liner film 11 has a compressive stress (stress that tends to shrink itself), strain in the tensile direction can be generated in the channel region of the NMOS transistor. Therefore, the driving power of the NMOS transistor can be improved.

<Embodiment 2>
A feature of the semiconductor device according to the present embodiment is that the thickness of the lower insulating film 10 formed on the PMOS transistor side is larger than the thickness of the lower insulating film 10 formed on the NMOS transistor side. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to process cross-sectional views.

  First, the process of forming the configuration of FIG. 1 is executed as in the first embodiment. Here, it is assumed that the thickness of the lower insulating film (which can be grasped as the first lower insulating film) 10 to be formed is thicker in the present embodiment than in the first embodiment. Thereafter, as shown in FIG. 5, a resist R1 is formed on the second region 200 side. The resist R1 is formed so as to cover the gate electrode 6. As described in the first embodiment, the lower insulating film 10 is formed on the semiconductor substrate 1 in the first region 100 and the second region 200 so as to cover the gate structures 5 and 6.

  Next, in order to reduce the film thickness of the lower insulating film 10, an etch-back process is performed on the lower insulating film 10 formed on the first region 100 side using the resist R1 as a mask. FIG. 6 shows the state after the resist R1 is removed. As shown in FIG. 6, the lower insulating film 10 covering the gate electrode 5 is thinner than the lower insulating film 10 covering the gate electrode 6. That is, the thickness of the lower insulating film 10 formed in the first region 100 that is the NMOS transistor forming region is thinner than the lower insulating film 10 formed in the second region 200 that is the PMOS transistor forming region. For example, the thickness of the lower insulating film 10 covering the gate electrode 5 is reduced to about the thickness of the lower insulating film 10 mentioned in the first embodiment by the etch back process.

  Here, when the film thickness of the lower insulating film 10 as a result of the reduction is approximately the same as the film thickness of the lower insulating film 10 according to the first embodiment, the film thickness of the lower insulating film 10 on the second region 200 side. Needless to say, the thickness is larger than the thickness of the lower insulating film 10 according to the first embodiment.

  Note that an insulating film having the same film quality as that of the lower insulating film 10 may be additionally formed on the semiconductor substrate 1 shown in FIG. In this case, the lower insulating film is constituted by the lower insulating film 10 and the additionally formed insulating film.

  Next, as described in the first embodiment, the liner film 11 made of SiN having compressive stress is formed on the lower insulating film 10 on the first region 100 side and the second region 200 side (FIG. 7). ). Thereafter, the stress change process described in the first embodiment is performed on the liner film 11. Here, as described in the first embodiment, the stress change process may be performed after the formation of the upper insulating film 12 described later.

  Next, as described in the first embodiment, the upper insulating film 12 with good coverage is formed on the liner film 11 on the first region 100 side and the second region 200 side (FIG. 8). The film composition and film properties of the upper insulating film 12 are the same as those described in the first embodiment.

  Note that the space between adjacent gate structures 5 (or adjacent gate structures 6) is about 140 nm, the thickness of the first sidewall film SW1 is 10 nm, and the thickness of the second sidewall film SW2 is 30 nm. Suppose that it is a degree. In this case, in this Embodiment, the film thickness of each film | membrane 10-12 can be set as follows, for example. The film thickness of the lower insulating film 10 on the first region 100 side is 5 to 15 nm, the film thickness of the liner film 11 on the first region 100 side is about 25 to 15 nm, and the film thickness of the upper insulating film 12 is It is about 5 to 15 nm. Further, the total thickness of the lower insulating film 10 on the second region 200 side and the liner film 11 on the second region 200 side is 40 nm or more (for example, the lower insulating film 10 has a thickness of 20 nm, the liner The film thickness of the film 11 is 20 nm). Here, as described above, the lower insulating film 10 on the second region 200 side is thicker than the lower insulating film 10 on the first region 100 side. The magnitude relationship of the film thickness is the same in the finished product.

  Other configurations and processes are the same as those described in the first embodiment.

  As described above, in the present embodiment, the film thickness of the lower insulating film 10 formed on the PMOS transistor side is larger than the film thickness of the lower insulating film 10 formed on the NMOS transistor side. Therefore, the influence of the liner film 11 having compressive stress on the PMOS transistor can be reduced. Therefore, it is possible to suppress a decrease in driving force of the PMOS transistor due to the liner film 11 having compressive stress.

  Needless to say, this embodiment also has the same effect as that of the first embodiment.

<Embodiment 3>
The film thickness of the upper insulating film formed on the PMOS transistor side is larger than the film thickness of the upper insulating film formed on the NMOS transistor side, and that the upper insulating film has a tensile stress. This is a feature of the semiconductor device according to the embodiment. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to process cross-sectional views.

  First, the process described in Embodiment 1 with reference to FIGS. As described in the first embodiment, the stress change treatment may be performed before the formation of the upper insulating film (which can be grasped as the first upper insulating film) 12, and the stress may be changed after the formation of the upper insulating film 12. Change processing may be performed. In the present embodiment, the upper insulating film 12 has a tensile stress. That is, the upper insulating film 12 can generate compressive strain in the channel region of the PMOS transistor. Similarly to the first embodiment, the lower insulating film 10, the liner film 11, and the upper insulating film 12 cover the semiconductor substrate 1 in the first region 100 and the second region 200 so as to cover the gate structures 5 and 6. Formed on top.

  Thereafter, as shown in FIG. 9, a resist R2 is formed on the second region 200 side. The resist R2 is formed so as to cover the gate electrode 6. Next, in order to remove the upper insulating film 12, an etch-back process is performed on the upper insulating film 12 formed on the first region 100 side using the resist R2 as a mask. By the etch back process, as shown in FIG. 9, the upper insulating film 12 covering the gate electrode 5 is removed. Needless to say, the upper insulating film 12 covering the gate electrode 6 remains. In other words, the upper insulating film 12 is removed in the first region 100 which is an NMOS transistor formation region. On the other hand, the upper insulating film 10 remains in the second region 200 which is a PMOS transistor formation region.

  Next, the resist R2 is removed. Thereafter, by the same method as the formation of the upper insulating film 12, a second upper insulating film that additionally constitutes the upper insulating film is formed on both the first region 100 side and the second region 200 side. . Specifically, the second upper layer insulating film is formed on the liner film 11 on the first region 100 side, while the second upper layer insulating film is formed on the liner film 11 on the second region 200 side. 12 is formed.

  The additionally formed second upper insulating film is a film having the same composition and the same properties as the upper insulating film 12. The second upper insulating film is formed on the semiconductor substrate 1 in the first region 100 and the second region 200 so as to cover the gate structures 5 and 6.

  Therefore, the coverage of the second upper insulating film is better (higher) than that of the liner film 11 at the time of forming the second upper insulating film. Further, the density of the second upper insulating film is higher than the density of the liner film 11 at the time of forming the second upper insulating film. The second upper insulating film also has a tensile stress. That is, the second upper insulating film can generate compressive strain in the channel region of the PMOS transistor. Furthermore, the thickness of the additionally formed second upper insulating film is approximately the same as the thickness of the upper insulating film 12 according to the first embodiment.

  In the following description of the present embodiment, the upper insulating film 12 formed in the first region 100 is referred to as the upper insulating film 20. Further, the laminated structure of the upper insulating film 12 formed in the second region 200 and the second upper insulating film is also referred to as the upper insulating film 20.

  As a result, as shown in FIG. 10, the film thickness of the upper insulating film 20 formed on the PMOS transistor side becomes thicker than the film thickness of the upper insulating film 20 formed on the NMOS transistor side. As described above, the upper insulating film 20 has a single-layer structure on the first region 100 side. On the second region 200 side, the upper insulating film 20 includes the first upper insulating film 12 and the second upper insulating film. A two-layer structure consisting of a film. Therefore, when the thickness of the additionally formed second upper insulating film is substantially the same as the thickness of the upper insulating film 12 according to the first embodiment, the upper insulating film 20 on the second region 200 side The film thickness is larger than the film thickness of the upper insulating film 12 according to the first embodiment.

  Note that the space between adjacent gate structures 5 (or adjacent gate structures 6) is about 140 nm, the thickness of the first sidewall film SW1 is 10 nm, and the thickness of the second sidewall film SW2 is 30 nm. Suppose that it is a degree. In this case, in this Embodiment, the film thickness of each film | membrane 10-12 can be set as follows, for example. The film thickness of the lower insulating film 10 is 5 to 15 nm, the film thickness of the liner film 11 is approximately 25 to 15 nm, and the film thickness of the upper insulating film 20 on the first region 100 side is approximately 5 to 15 nm. The film thickness of the upper insulating film 20 on the second region 200 side is at least 15 nm. However, the film thickness of the upper insulating film 20 on the second region 200 side is larger than the film thickness of the upper insulating film 20 on the first region 100 side. The magnitude relationship of the film thickness is the same in the finished product.

  Other configurations and processes are the same as those described in the first embodiment.

  As described above, in the present embodiment, the film thickness of the upper insulating film 20 formed on the PMOS transistor side is larger than the film thickness of the upper insulating film 20 formed on the NMOS transistor side. Furthermore, the upper insulating film 20 has a tensile stress. That is, the upper insulating film 20 can generate compressive strain in the channel region of the PMOS transistor.

  Therefore, the formation of the upper insulating film 20 can relieve the tensile strain generated in the channel region of the PMOS transistor or the tensile strain generated by the liner film 11. Due to the occurrence of the compressive strain, the driving force of the PMOS transistor can be improved.

  Further, by the manufacturing method according to the present embodiment, tensile strain is generated in the channel region of the NMOS transistor, and compressive strain is generated in the channel region of the PMOS transistor. The method according to the present embodiment makes the manufacturing process easier than the case where the DSL method causes distortion in different directions in the channel region of each transistor. This is because in the case of the present embodiment, it is not necessary to remove the liner film 11 and it is not necessary to create a boundary between the upper insulating film having compressive stress and the upper insulating film having tensile stress. It is.

  Note that the second upper insulating film can also be formed by a thermal CVD method or a plasma CVD method under conditions that increase the film density. For example, the plasma CVD method is a condition for increasing the stage temperature or a condition under a low pressure.

As described above, when the second upper-layer insulating film is formed by the thermal CVD method or the plasma CVD method under the above-described conditions, it is a conformal (high coverage (good)) film and a high-density second film. An upper insulating film is formed. That is, the coverage of the second upper insulating film is higher than the coverage at the time of forming the liner film 11 at least when the second upper insulating film is formed. As the second upper insulating film, for example, a SiO ₂ film, a SiN film, a SiON film, or the like can be employed.

  When forming the second upper insulating film having the above film quality, the thermal CVD method is more suitable than the plasma CVD method.

  Needless to say, this embodiment also has the same effect as that of the first embodiment.

<Embodiment 4>
On the semiconductor substrate 1 side, the film thickness of the lower insulating film at the ends of the gate structures 5 and 6 (more specifically, the sidewall films SW1 and SW2) is thicker than the film thickness of the lower insulating film other than the end parts. The formation is a feature of the semiconductor device according to the present embodiment. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to process cross-sectional views.

  First, the process of forming the configuration of FIG. 1 is executed as in the first embodiment. Next, anisotropic etching is performed on the lower insulating film (which can be grasped as the first lower insulating film) 10. As a result, as shown in FIG. 11, the lower insulating film 10 remains at the ends of the gate structures 5 and 6 (more specifically, the sidewall films SW1 and SW2) on the semiconductor substrate 1 side. Note that, as shown in FIG. 11, the lower insulating film 10 formed except for the end portion is removed by the anisotropic etching process.

  As described in the first embodiment, the formation process of the silicide film 9 is performed before the lower insulating film 10 is formed. However, silicidation may be performed after the anisotropic etching of the lower insulating film 10 to form the silicide film 9 on the predetermined upper surface of the semiconductor substrate 1 and the upper surfaces of the gate structures 5 and 6.

  Next, a lower insulating film (second lower insulating film) 30 having the same composition and properties as the lower insulating film 10 is additionally formed by the same method as the lower insulating film 10. Here, as shown in FIG. 12, the lower insulating film 30 covers the gate structures 5 and 6 in which the sidewall films SW1 and SW2 are formed and the remaining lower insulating film 10 so as to cover the remaining lower insulating film 10. , 6 are formed on the semiconductor substrate 1 adjacent to each other. The film thickness of the lower insulating film 30 is approximately the same as the film thickness of the lower insulating film 10 described in the first embodiment, for example. As shown in FIG. 12, the lower insulating film 35 is constituted by the remaining lower insulating film 10 and the additionally formed lower insulating film 30.

  Accordingly, the film thickness of the lower insulating film 35 at the end portions of the gate structures 5 and 6 (more specifically, the sidewall films SW1 and SW2) on the semiconductor substrate 1 side is other than the end portions (for example, the gate structure). 5 and 6), which is thicker than the thickness of the lower insulating film 35. The magnitude relationship of the film thickness is the same in the finished product.

  Next, as described in the first embodiment, the liner film 11 made of SiN having compressive stress is formed on the lower insulating film 35 in the first region 100 and the second region 200 (FIG. 13). Thereafter, the stress change process described in the first embodiment is performed on the liner film 11. Here, as described in the first embodiment, the stress change process may be performed after the formation of the upper insulating film 12 described later.

  Next, as described in the first embodiment, the upper insulating film 12 with good (high) coverage is formed on the liner film 11 in the first region 100 and the second region 200 (FIG. 14). Here, the film composition and film properties of the upper insulating film 12 are the same as those described in the first embodiment.

  Other configurations and processes are the same as those described in the first embodiment.

  As described above, in the present embodiment, the film thickness of the lower insulating film 35 at the end portions of the gate structures 5 and 6 on the semiconductor substrate 1 side is larger than the film thickness of the lower insulating film 35 other than the end portions. thick. Therefore, the angle at the end of the gate structures 5 and 6 is relaxed. Therefore, refraction of the liner film 11 formed on the lower insulating film 35 is relaxed in the vicinity of the ends of the gate structures 5 and 6. Therefore, even if the stress change process is performed on the liner film 11, it is possible to further suppress the occurrence of slits in the liner film 11 near the ends of the gate structures 5 and 6.

  The lower insulating film 30 can also be formed by a thermal CVD method or a plasma CVD method under conditions that increase the film density. For example, the plasma CVD method is a condition for increasing the stage temperature or a condition under a low pressure.

As described above, when the lower insulating film 30 is formed by the thermal CVD method or the plasma CVD method under the above-described conditions, the lower insulating film 30 is a conformal (high coverage) film with a high density. It is formed. That is, the coverage of the lower insulating film 30 is higher than the coverage at the time of forming the liner film 11 at least when the lower insulating film 30 is formed. As the lower insulating film 30, for example, a SiO ₂ film, a SiN film, a SiON film or the like can be employed.

  When forming the lower insulating film 30 having the above film quality, the thermal CVD method is more suitable than the plasma CVD method.

  Needless to say, this embodiment also has the same effect as that of the first embodiment.

<Embodiment 5>
The semiconductor device and the method for manufacturing the semiconductor device according to the present embodiment are more effective when the device is further miniaturized and the pitch between the gate structures is narrowed. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to process cross-sectional views.

  First, as described in the first embodiment, the element isolation film 2, the well regions 3 and 4, the gate structures 5 and 6, and the laminated film are formed on the semiconductor substrate 1 made of silicon by a normal CMOS process. Sidewall films SW1 and SW2 and source / drain regions 7 and 8 are formed (see FIG. 15).

  Here, as in the first embodiment, each of the gate structures 5 and 6 is a stacked body in which a gate insulating film and a gate electrode are stacked in this order. In each cross-sectional view including FIG. 15, the boundary between the gate insulating film and the gate electrode is not shown. In addition, L-shaped first sidewall films SW1 are formed on both side surfaces of the gate structures 5 and 6 (FIG. 15). Further, a second sidewall film SW2 is formed on the first sidewall film SW1 (FIG. 15). The first sidewall film SW1 is made of, for example, a silicon oxide film, and the second sidewall film SW2 is made of, for example, a silicon nitride film.

  By forming the sidewall films SW1 and SW2, the source / drain regions 7 and 8 on the deep side of the step-shaped source / drain regions 7 and 8 can be formed. That is, after the formation of the sidewall films SW1 and SW2, the semiconductor substrates 1 on both sides of the gate structure 5 and the semiconductor substrates 1 on both sides of the gate structure 6 using the sidewall films SW1 and SW2 as a mask. In contrast, different impurity ion implantations are performed. As a result, the deep source / drain regions 7 and 8 are formed. The first sidewall film SW1 functions as an etching stopper for the second sidewall film SW2.

  After each of the above ion implantations, the second sidewall film SW2 is removed using hot phosphoric acid. Alternatively, the second sidewall film SW2 may be removed by a dry etching process. FIG. 16 shows a state after the second sidewall film SW2 is removed. As can be seen from FIG. 16, only the L-shaped first sidewall film SW1 remains on both side surfaces of the gate structures 5 and 6.

  Next, on the semiconductor substrate 1 adjacent to the gate structures 5 and 6 so as to cover the gate structures 5 and 6 having the first sidewall film SW1 formed on the side surfaces by the same method as in the first embodiment, A lower insulating film (which can be grasped as a first lower insulating film) 10 is formed. As described in the first embodiment, the lower insulating film 10 can be formed by a thermal CVD method or a plasma CVD method under a predetermined condition (the thermal CVD method is easier to form). A state after the lower insulating film 10 is formed is shown in FIG. The film configuration and properties of the lower insulating film 10 are the same as those described in the first embodiment.

  That is, the coverage of the lower insulating film 10 when forming the lower insulating film 10 is better (that is, higher) than the coverage of the liner film 11 when forming the liner film 11 described later. In other words, the density of the lower insulating film 10 when forming the lower insulating film 10 is higher than the density of the liner film when forming the liner film 11 described later.

  Next, as described in the fourth embodiment, the lower insulating film 10 is subjected to anisotropic etching. As a result, as shown in FIG. 18, the lower insulating film 10 remains at the ends of the gate structures 5 and 6 (more specifically, the corners of the sidewall film SW1) on the semiconductor substrate 1 side. As shown in FIG. 18, the lower insulating film 10 is removed except for the end portions by the anisotropic etching process.

  Thereafter, as described in the first embodiment, silicide treatment is performed on the upper surfaces of the gate structures 5 and 6 and the predetermined upper surface of the semiconductor substrate 1. Thus, as shown in FIG. 18, silicide films 9 made of NiSi are formed on the upper surfaces of the gate structures 5 and 6 and the predetermined upper surface of the semiconductor substrate 1, respectively.

  Here, in the present embodiment, the silicidation process is performed after the anisotropic etching of the lower insulating film 10. However, silicidation treatment may be performed before forming the lower insulating film 10 to form the silicide film 9 on the upper surfaces of the gate structures 5 and 6 and a predetermined upper surface of the semiconductor substrate 1.

  Next, as described in the fourth embodiment, a lower insulating film having the same composition and properties as the lower insulating film 10 (as a second lower insulating film is grasped) by the same method as the lower insulating film 10 is formed. 30) is additionally formed. That is, the coverage of the lower insulating film 30 when forming the lower insulating film 30 is better (that is, higher) than the coverage of the liner film 11 when forming the liner film 11 described later. In other words, the density of the lower insulating film 30 when forming the lower insulating film 30 is higher than the density of the liner film when forming the liner film 11 described later.

  Here, as shown in FIG. 19, the lower insulating film 30 is formed on the semiconductor substrate 1 adjacent to the gate structures 5 and 6 so as to cover the gate structures 5 and 6 on which the sidewall films SW1 are formed. (The same applies to the finished product). As already described, the lower insulating film 30 can be formed by a thermal CVD method or a plasma CVD method under a predetermined condition (the thermal CVD method is easier to form).

  The film thickness of the lower insulating film 30 is approximately the same as the film thickness of the lower insulating film 10 described in the first embodiment, for example. As shown in FIG. 19, a lower insulating film 35 is constituted by the remaining lower insulating film 10 and the additionally formed lower insulating film 30. Therefore, the film thickness of the lower insulating film 35 at the ends of the gate structures 5 and 6 (more specifically, at the corners of the sidewall film SW1) on the semiconductor substrate 1 side is other than the ends (for example, the gates). It becomes thicker than the film thickness of the lower insulating film 35 in the upper surfaces and side surfaces of the structures 5 and 6.

  Next, as described in the first embodiment, the liner film 11 made of SiN having compressive stress is formed on the lower insulating film 35 in each of the regions 100 and 200 (FIG. 20). Thereafter, the stress change process described in the first embodiment is performed on the liner film 11. Here, the stress change process may be performed after the formation of the upper insulating film 12 described later.

  Next, as described in the first embodiment, the upper insulating film 12 with good coverage is formed on the liner film 11 in each of the regions 100 and 200 (FIG. 21). The film composition and film properties of the upper insulating film 12 are the same as those described in the first embodiment.

  Other configurations and processes are the same as those described in the first embodiment.

  When the semiconductor device is further miniaturized and the pitch between the gate structures 5 and between the gate structures 6 becomes narrow, the thick liner film 11 is formed. In this case, there is a high possibility that the liner films 11 formed between the adjacent gate structures 5 and 6 are in contact with each other. If the liner films 11 come into contact with each other, the liner film 11 becomes too thick in the contact region, and the improvement of the driving force of the MOS transistor is impaired.

  Therefore, as described above, the second sidewall film SW2 is removed after each ion implantation process. Thereby, even if the miniaturization of the semiconductor device advances and the pitch between the adjacent gate structures 5 and 6 becomes narrow, the contact between the liner films 11 as described above can be prevented. Therefore, the improvement of the driving capability of the MOS transistor is not impaired.

  Further, the lower insulating film 35 is formed by partially removing the lower insulating film 10 and additionally forming the lower insulating film 30. Therefore, the film thickness of the lower insulating film 35 at the ends of the gate structures 5 and 6 (more specifically, at the corners of the sidewall film SW1) on the semiconductor substrate 1 side is other than the ends (for example, the gates). It becomes thicker than the film thickness of the lower insulating film 35 in the upper surfaces and side surfaces of the structures 5 and 6.

  Therefore, the angle at the end portions of the gate structures 5 and 6 (the corner portion of the L-shaped first sidewall film SW1) is relaxed. Therefore, refraction of the liner film 11 formed on the lower insulating film 35 is relaxed in the vicinity of the ends of the gate structures 5 and 6. Therefore, even if the stress change process is performed on the liner film 11, it is possible to further suppress the occurrence of slits in the liner film 11 near the ends of the gate structures 5 and 6.

  Needless to say, this embodiment also has the same effect as that of the first embodiment.

FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 element isolation film | membrane, 3,4 well area | region, 5,6 gate structure, 7,8 source / drain area | region, 9 silicide film | membrane, 10,30,35 lower insulating film, 11 liner film | membrane, 12,20 upper layer Insulating film, 100 first region, 200 second region, S1 slit, R1, R2 resist, SW1 first sidewall film, SW2 second sidewall film.

Claims (29)

(A) forming an NMOS transistor having a first gate structure, which is a stacked body in which a gate insulating film and a gate electrode are stacked in that order, on the surface of the semiconductor substrate;
(B) forming a first lower insulating film on the surface of the semiconductor substrate so as to cover the first gate structure;
(C) forming a liner film made of silicon nitride that generates tensile strain on the channel region of the NMOS transistor on the first lower insulating film;
(D) providing a stress change treatment for increasing the stress of the liner film,
When the first lower insulating film is formed, the coverage of the first lower insulating film is
Higher than the coverage of the liner film when the liner film is formed,
A method for manufacturing a semiconductor device. (E) further comprising forming a first upper insulating film on the liner film;
The coverage of the first upper insulating film during the formation of the first upper insulating film is:
Higher than the coverage of the liner film when the liner film is formed,
The method of manufacturing a semiconductor device according to claim 1. (A) forming an NMOS transistor having a first gate structure, which is a stacked body in which a gate insulating film and a gate electrode are stacked in that order, on the surface of the semiconductor substrate;
(B) forming a liner film made of silicon nitride that generates tensile strain on the channel region of the NMOS transistor on the surface of the semiconductor substrate so as to cover the first gate structure;
(C) forming a first upper insulating film on the liner film;
(D) providing a stress change treatment for increasing the stress of the liner film,
The coverage of the first upper insulating film during the formation of the first upper insulating film is:
Higher than the coverage of the liner film when the liner film is formed,
A method for manufacturing a semiconductor device. The stress change process
A process including at least one of a UV irradiation process and a heat process,
The step (D)
Before the first upper insulating film is formed,
4. The method for manufacturing a semiconductor device according to claim 2, wherein the method is a semiconductor device. The stress change process
A process including at least one of a UV irradiation process and a heat process,
The step (D)
After the first upper insulating film is formed,
4. The method for manufacturing a semiconductor device according to claim 2, wherein the method is a semiconductor device. The step (A)
Forming a PMOS transistor having a second gate structure, which is a stacked body in which a gate insulating film and a gate electrode are stacked in that order, on the surface of the semiconductor substrate;
The step (B)
Forming the first lower insulating film on the semiconductor substrate so as to cover the second gate structure;
(F) After the step (B), the method further comprises a step of reducing the thickness of the first lower insulating film formed on the NMOS transistor side.
The method of manufacturing a semiconductor device according to claim 1. The step (A)
Forming a PMOS transistor having a second gate structure, which is a stacked body in which a gate insulating film and a gate electrode are stacked in that order, on the surface of the semiconductor substrate;
The step (B)
Forming the first lower insulating film on the semiconductor substrate so as to cover the second gate structure;
The step (E)
Forming the first upper insulating film for generating compressive strain in the channel region of the PMOS transistor on the semiconductor substrate so as to cover the second gate structure;
(G) removing the first upper insulating film formed on the NMOS transistor side;
(H) After the step (G), forming a second upper insulating film that generates compressive strain in the channel region of the PMOS transistor on the liner film and the first upper insulating film. , Prepare,
When the second upper insulating film is formed, the coverage of the second upper insulating film is
Higher than the coverage of the liner film when the liner film is formed,
The method of manufacturing a semiconductor device according to claim 2. The step (A)
A step of forming a PMOS transistor having a second gate structure, which is a stacked body in which a gate insulating film and a gate electrode are stacked in that order, on the surface of the semiconductor substrate;
The step (B)
A step of forming the liner film on the semiconductor substrate so as to cover the second gate structure;
The step (C)
Forming the first upper insulating film for generating compressive strain in the channel region of the PMOS transistor on the semiconductor substrate so as to cover the second gate structure;
(G) removing the first upper insulating film formed on the NMOS transistor side;
(H) After the step (G), forming a second upper insulating film that generates compressive strain in the channel region of the PMOS transistor on the liner film and the first upper insulating film. Prepared,
When the second upper insulating film is formed, the coverage of the second upper insulating film is as follows.
Higher than the coverage of the liner film when the liner film is formed,
The method of manufacturing a semiconductor device according to claim 3. (I) a step of leaving the first lower insulating film only at an end portion of the first gate structure on the semiconductor substrate side, and removing the first lower insulating film formed other than the end portion; ,
(J) after the step (I), further comprising a step of forming a second lower insulating film on the semiconductor substrate so as to cover the gate structure and the first lower insulating film,
When the second lower insulating film is formed, the coverage of the second lower insulating film is
Higher than the coverage of the liner film in the formation of the liner film,
The method of manufacturing a semiconductor device according to claim 1. (L) A laminated film composed of an L-shaped first sidewall film and a second sidewall film formed on the first sidewall film is formed on the side surface of the first gate structure. And a process of
(M) Implanting impurity ions into the semiconductor substrate on both sides of the first gate structure after the step (L);
(N) After the step (M), further comprising the step of removing the second sidewall film,
The step (B)
(O) forming the first lower insulating film so as to cover the first gate structure formed on the side surface of the first sidewall film;
A method for manufacturing a semiconductor device according to claim 9. The liner film is
Formed by plasma CVD,
4. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method. The first lower insulating film is
Formed by thermal CVD,
The method of manufacturing a semiconductor device according to claim 1. The first upper insulating film is
Formed by thermal CVD,
4. The method for manufacturing a semiconductor device according to claim 2, wherein the method is a semiconductor device. The second lower insulating film is
Formed by thermal CVD,
A method for manufacturing a semiconductor device according to claim 9. The second upper insulating film is
Formed by thermal CVD,
9. A method of manufacturing a semiconductor device according to claim 7, wherein the method is a semiconductor device manufacturing method. A semiconductor substrate;
An NMOS transistor having a first gate structure formed on the surface of the semiconductor substrate and having a gate insulating film and a gate electrode laminated on the semiconductor substrate in that order;
A lower insulating film containing at least oxygen and formed on the semiconductor substrate to cover the first gate structure;
A liner film made of silicon nitride that is formed on the lower insulating film and generates tensile strain in the channel region of the NMOS transistor;
Semiconductor device. The semiconductor device according to claim 16, further comprising an upper insulating film formed on the liner film and containing at least oxygen. A semiconductor substrate;
An NMOS transistor having a first gate structure formed on the surface of the semiconductor substrate and having a gate insulating film and a gate electrode laminated on the semiconductor substrate in that order;
A liner film made of silicon nitride formed on the semiconductor substrate covering the first gate structure and generating tensile strain in a channel region of the NMOS transistor;
An upper layer insulating film formed on the liner film and containing at least oxygen,
Semiconductor device. A semiconductor substrate;
An NMOS transistor having a first gate structure formed on the surface of the semiconductor substrate and having a gate insulating film and a gate electrode laminated on the semiconductor substrate in that order;
A lower insulating film formed on the semiconductor substrate to cover the first gate structure and containing at least oxygen or nitrogen;
A liner film made of silicon nitride that is formed on the lower insulating film and generates tensile strain in the channel region of the NMOS transistor;
The film thickness of the lower insulating film is
A semiconductor device characterized by being thinner than the thickness of the liner film. An upper insulating film formed on the liner film and containing at least oxygen or nitrogen;
The film thickness of the upper insulating film is
Thinner than the thickness of the liner film,
The semiconductor device according to claim 19. A semiconductor substrate;
An NMOS transistor having a first gate structure formed on the surface of the semiconductor substrate and having a gate insulating film and a gate electrode laminated on the semiconductor substrate in that order;
A liner film made of silicon nitride formed on the semiconductor substrate covering the first gate structure and generating tensile strain in a channel region of the NMOS transistor;
An upper insulating film formed on the liner film and containing at least oxygen or nitrogen,
The film thickness of the upper insulating film is
A semiconductor device characterized by being thinner than the thickness of the liner film. A semiconductor substrate;
An NMOS transistor having a first gate structure formed on the surface of the semiconductor substrate and having a gate insulating film and a gate electrode laminated on the semiconductor substrate in that order;
A lower insulating film that covers the first gate structure and is formed on the semiconductor substrate;
A liner film made of silicon nitride that is formed on the lower insulating film and generates tensile strain in the channel region of the NMOS transistor;
The stress of the lower insulating film is
Less than the stress that the liner film has,
A semiconductor device. Further comprising an upper insulating film formed on the liner film;
The stress of the upper insulating film is
23. The semiconductor device according to claim 22, wherein the stress is lower than that of the liner film. A semiconductor substrate;
An NMOS transistor having a first gate structure formed on the surface of the semiconductor substrate and having a gate insulating film and a gate electrode laminated on the semiconductor substrate in that order;
A liner film made of silicon nitride that covers the first gate structure and is formed on the semiconductor substrate and generates tensile strain in the channel region of the NMOS transistor;
An upper insulating film formed on the liner film,
The stress of the upper insulating film is
A semiconductor device characterized by being smaller than the stress of the liner film. A PMOS transistor having a second gate structure which is a stacked body in which a gate insulating film and a gate electrode are stacked on the semiconductor substrate in that order; and
The lower insulating film is
Formed on the semiconductor substrate so as to cover the second gate structure;
The film thickness of the lower insulating film formed on the PMOS transistor side is:
23. The semiconductor device according to claim 16, wherein the semiconductor device is thicker than a film thickness of the lower insulating film formed on the NMOS transistor side. A PMOS transistor having a second gate structure which is a stacked body in which a gate insulating film and a gate electrode are stacked on the semiconductor substrate in that order;
The upper insulating film is
Formed on the semiconductor substrate so as to cover the second gate structure;
A film that generates compressive strain in the channel region of the PMOS transistor;
The film thickness of the upper insulating film formed on the PMOS transistor side is:
Thicker than the film thickness of the upper insulating film formed on the NMOS transistor side,
25. The semiconductor device according to any one of claims 17, 18, 20, 20, 21, 23, and 24. The film thickness of the lower insulating film formed at the end of the first gate structure on the semiconductor substrate side is:
Thicker than the film thickness of the lower insulating film formed in a portion other than the end,
The semiconductor device according to any one of claims 16, 19, and 22. A sidewall film formed on a side surface of the first gate structure, further comprising:
25. The semiconductor device according to any one of claim 16, claim 18, claim 19, claim 21, claim 22, and claim 24. An L-shaped sidewall film formed on a side surface of the first gate structure;
The lower insulating film is
It is formed so as to cover the first gate structure in which the sidewall film is formed,
The film thickness of the lower insulating film formed at the end of the first gate structure on the semiconductor substrate side is:
Thicker than the film thickness of the lower insulating film formed in a portion other than the end,
The semiconductor device according to any one of claims 16, 19, and 22.

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