JP2009145957A - State machine and semiconductor integrated circuit using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To arbitrarily change control contents of a state machine without changing a circuit configuration of hardware with a simple and low-cost hardware configuration. <P>SOLUTION: This Moore type state machine 20 uses a clock synchronous memory 30, and data expressing a state S of the Moore type state machine 20 are stored in each address of the memory 30. The Moore type state machine 20 is behaved as the Moore type state machine 20 operating while varying the state S in synchronization with a clock signal clk by combining an input signal in[j-1:0] to the state machine 20 and the data rdata[m:k] expressing the state S inside read data rdata[m:0] of the memory 30, and inputting them to an address of the memory 30 through a selector 21. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a state machine and a semiconductor integrated circuit controlled by the state machine.

  In general, a semiconductor integrated circuit is controlled using a state machine. A state machine is a circuit that realizes a finite automaton by a circuit, and is a circuit that generates an output signal while changing (transitioning) a state by an input signal every unit time. Input signals, states, and output signals are generally multi-bit.

  Conventionally, as a technique related to this type of state machine, for example, there are those described in the following documents.

International Publication No. WO01 / 061464 Japanese Patent Laid-Open No. 11-53216 (Japanese Patent No. 3063694) JP 10-333881 A (Patent No. 3189875)

  Patent Document 1 describes a state machine including a storage circuit, a comparison circuit, an analysis circuit, and an arithmetic circuit, and a semiconductor device using the state machine and a design method thereof.

  In Patent Document 2, a register group storing state transition information including a next state number and an output signal to be output in the state, a current state number and an input signal are input, and a state next to the register group is input. A combinational logic circuit that outputs a select signal for selecting a register that stores number state transition information; and one register of the register group is selected based on a select signal from the combinational logic circuit, and the state transition information Is implemented by writing state transition information to one or more registers in the register group from the outside. A state machine control circuit technology that can change the state transition is described.

  Patent Document 3 includes a next state logic unit that calculates a next state that is a next state from a current state that is a current state, and at least one current state holding register that holds the current state. In a state machine having a current state holding unit that holds a next state output from the state logic unit as a new current state in synchronization with a clock, the current state is compared with the next state, and the current state and the next state are compared. A technique of a state machine having a comparison unit that stops the supply of the clock to the current state holding unit register when a next state matches is described.

  FIGS. 13A and 13B are diagrams illustrating the configuration and operation for explaining the principle of the state machine described in the conventional patent documents 1 to 3 and the like.

  In the state machine 1, the “next state” is determined by the “current state” (state state) and the “current input” (input signal in). Therefore, the “next state” can be regarded as a function obtained from the “current state” and the “current input”. The function at this time is defined as func1 (state, input).

  There are two methods for generating the output signal out of the state machine 1, and the “current output” that is determined only by the “current state” is called a Moore state machine, and it depends on the “current state” and “current input”. What determines the "current output" is called a Mealy state machine. Therefore, “current output” can be regarded as a function obtained from “current state” or “current input”. The function at this time is assumed to be func2 (state) in the case of the Moore type state machine, and func2 (state, input) in the case of the Mealy type state machine.

FIG. 14 is a block diagram showing the principle of a conventional Moore type state machine.
The Moore state machine 2 holds an arithmetic circuit C1 composed of a combinational circuit for realizing a function func1 for obtaining the next state from the input signal in and the current state, and a next state output from the arithmetic circuit C1. And a calculation circuit C2 including a combinational circuit for realizing a function func2 for obtaining a current output from a current state output from the storage element S.

FIG. 15 is a block diagram showing the principle of a conventional Mealy state machine.
The Mealy type state machine 3 holds an arithmetic circuit C1 composed of a combinational circuit for realizing a function func1 for obtaining the next state from the input signal in and the current state, and the next state output from the arithmetic circuit C1. And a calculation circuit C2 including a combinational circuit for realizing a function func2 for obtaining a current output from the current state and the input signal in.

FIG. 16 is a block diagram showing the principle of a semiconductor integrated circuit having a conventional state machine.
FIG. 16 shows a general configuration when the semiconductor integrated circuit 10 is controlled by the state machine 1. Assume that the semiconductor integrated circuit 10 assumed here operates in synchronization with the rising edge (= rising timing) of the clock signal clk. In other words, the input signal in to the semiconductor integrated circuit 10 and all the elements in the semiconductor integrated circuit (the state state and control signal cs of the state machine 1 and the output signal out of the semiconductor integrated circuit 10) from the rising edge of the clock signal clk. Suppose that it changes after a certain delay time.

FIG. 17 is a timing chart showing an operation in the semiconductor integrated circuit 10 of FIG.
In FIG. 17, PD is a period during which the controlled circuit 11 can use the control signal cs. The timing at which the state state of the state machine 1 and the output signal out (that is, the control signal cs for the control target) change changes slightly after the rising edge of the clock signal clk due to the influence of signal propagation delay or the like. Assuming that the controlled circuit 11 uses the control signal cs from the state machine 1 to perform arithmetic processing according to the function until the next rising edge of the clock signal clk and generates the output signal out, the state machine 1 It is desirable that the output control signal cs changes as quickly as possible.

However, the conventional state machine 1 has the following problems.
As shown in FIG. 16, when the semiconductor integrated circuit 10 is controlled using the state machine 1, the internal structure of the semiconductor integrated circuit 10 is usually fixed, so that the control contents of the state machine 1 in the semiconductor integrated circuit 10 are changed. When doing or modifying, the hardware is redesigned. For example, in the case of a large scale integrated circuit (hereinafter referred to as “LSI”), the process from design to manufacturing must be repeated. Using a programmable LSI (Field Programmable Gate Array, hereinafter referred to as “FPGA”), the hardware circuit configuration can be changed, but the FPGA has a complicated structure and costs. In some cases, the change operation takes several minutes to several hours, and a dedicated tool is required to change the circuit configuration.

  In the state machine control circuit described in Patent Document 2, the control contents can be changed by rewriting the state transition information stored in the register group, but the current state number and input signal are input. Since the combinational logic circuit or the like having a function of outputting a select signal for selecting a register for storing the state transition information of the next state number is configured by hardware, the control content can be changed constantly. Limited within range.

  Therefore, with the conventional technology, it is difficult to arbitrarily change the control contents of the state machine with a simple and low-cost hardware configuration and without changing the hardware circuit configuration.

  In the state machine of the present invention, a Moore state machine is realized by using a selector and a clock synchronous memory.

  Here, the selector is configured to input a write address (write address), and is configured by an input signal to the state machine composed of lower bits or upper bits and bits at different positions with respect to the input signal. A first signal combined with first data representing the current state of the first and second logic levels is input, and when the write enable signal transitioning to the first and second logic levels is at the first logic level, the write address is set. The first signal is selected when the write enable signal is at the second logic level.

  The clock synchronous memory has a storage area composed of a plurality of addresses (addresses). When the write enable signal is at the first logic level, the clock synchronous memory captures write data in synchronization with the clock signal and stores the write data in the storage area. In each address, second data representing the next state of the state machine and third data representing the output signal of the state machine are stored, and when the write enable signal is at the second logic level, Read data having the second and third data from the address of the storage area specified by the first signal selected by the selector within one cycle of the clock signal in synchronization with the clock signal Is read (read), the second data in the read data is supplied to the selector as the first data, and the The third data is a memory to be output to the outside as an output signal of the state machine.

  In another state machine of the present invention, a memory type state machine is realized by using a first selector, a clock synchronous memory, a second selector, and an asynchronous memory.

  Here, the first selector inputs a write address, and is composed of an input signal for the state machine consisting of lower bits or upper bits and bits at different positions with respect to the input signal, and the current state machine When the first signal that is combined with the first data representing the state of the first input is input and the first write enable signal that transitions to the first and second logic levels is the first logic level, the write address And when the first write enable signal is at the second logic level, the first signal is selected.

  The clock synchronous memory has a first storage area consisting of a plurality of addresses, and when the first write enable signal is at the first logic level, the first write data is synchronized with the clock signal. When the second data representing the next state of the state machine is stored in each address of the first storage area and the first write enable signal is at the second logic level, the clock signal is stored. The second data is read from the address of the first storage area designated by the first signal selected by the first selector within one cycle of the clock signal in synchronization with A memory provided as the first data to the first selector.

  The second selector receives the write address and a second signal obtained by combining the input signal and the second data, and makes a transition to the first and second logic levels. When the write enable signal is at the first logic level, the write address is selected, and when the second write enable signal is at the second logic level, the second signal is selected.

  The asynchronous memory has a second storage area having a plurality of addresses, and a second write area when a third write enable signal for transitioning to the first and second logic levels is at the first logic level. The third data representing the current output signal of the state machine is stored in each address of the second storage area by fetching data, and when the second write enable signal is at the second logic level, A memory that reads the third data from an address of the second storage area designated by the second signal selected by the second selector and outputs the third data as an output signal of the state machine to the outside; is there.

  The semiconductor integrated circuit of the present invention includes the state machine of the present invention and a controlled circuit that is controlled by the output of the state machine and performs predetermined processing in synchronization with the clock signal.

  According to the state machine of the present invention, data representing the state of the state machine is stored at each address of the clock synchronous memory, and the state of the input signal to the state machine and the read data of the clock synchronous memory is represented. Combined with data and input to the address of the clock-synchronous memory, it is configured to behave as a state machine that operates while changing its state in synchronization with the clock signal, so a simple and low-cost hardware configuration In addition, it is possible to provide a Moore state machine or a Mealy state machine that can arbitrarily change the control content of the state machine without changing the hardware circuit configuration.

  According to the semiconductor integrated circuit of the present invention, the contents of the memory in the state machine are rewritten from outside the semiconductor integrated circuit, and further from the outside of the product incorporating the semiconductor integrated circuit, thereby changing the control contents of the state machine. It becomes possible to easily change the hardware level for the control content.

  The state machine has a clock synchronous memory, and stores data representing the state of the state machine at each address of the memory, and receives an input signal to the state machine and data representing the state in the read data of the memory. By combining and inputting to the address of the memory, it can behave as a Moore state machine that operates while changing its state in synchronization with the clock signal.

(Configuration of Example 1)
FIG. 1 shows a first embodiment of the present invention, and is a schematic configuration diagram of a Moore state machine realized using a clock synchronous memory.

  This Moore type state machine 20 inputs a j-bit input signal in [j-1: 0] and outputs a k-bit output signal out [k-1: 0], and an address signal Data is written (written) and read (read) to the selector 21 that selects and outputs addr [n: 0] and the address (address) specified by the address signal addr [n: 0]. The clock synchronous memory 30 and the like are used.

  The selector 21 inputs an n + 1 bit write address waddr [n: 0] to the clock synchronous memory 30 and inputs a lower bit or an upper bit (for example, lower j bit) to the state machine 20. The signal in [j-1: 0] and the first data rdata [m: k] representing the state machine state of, for example, the upper i bits of the read data rdata [m: 0] from the clock synchronous memory 30 The address selection is made up of a write enable signal we that receives a first signal IN combined with and transitions to a first logic level (eg, “1”) and a second logic level (eg, “0”). When the signal is “1”, the write address waddr [n: 0] is selected, and when the address selection signal (we) is “0”, the first signal IN is selected, and the address signal as a result of this selection is selected. addr [n: 0] is output and the clock synchronous memory 30 is output. It is intended to give.

  The clock synchronous memory 30 enters the write mode when the write enable signal we is “1” at the edge (for example, rising edge) of the clock signal clk, and the n + 1 bit write address waddr [n: 0] at this time. Write data wdata [m: 0] is written to the address indicated, and when the write enable signal we is “0” at the rising edge of the clock signal clk, the read mode is entered, the address signal addr [n: 0] is taken in, and the clock After a certain delay time (read data output delay) from the rising edge of the signal clk, the stored contents of the address specified by the address signal addr [n: 0] are output as read data rdata [m: 0]. The read data rdata [m: 0] is data in which the first data rdata [m: k] of the upper i bits represents the state of the state machine 20, and the second data rdata [k-1: of lower k bits. 0] is output as the output signal out [k-1: 0] of the state machine 20.

  The address signal addr [n: 0] to the clock synchronous memory 30 is input by the selector 21 when the write enable signal we is “1” (that is, at the time of writing), write data waddr [n: 0]. As shown, when the write enable signal we is “0” (that is, when reading), the upper i bits are the first data rdata [m: k], and the lower j bits are the input signal. The signal is selected by the write enable signal we so that the first signal IN such as in [j-1: 0] is input.

FIG. 2 is a schematic configuration diagram showing the clock synchronous memory 30 in FIG.
The clock synchronous memory 30 is configured by a semiconductor memory or the like that can read the read data rdata [m: 0] within one cycle of the clock signal clk in synchronization with the rising edge of the clock signal clk. The clock synchronous memory 30 includes, for example, an address decoder 31 that decodes the address signal addr [n: 0] given from the selector 21 in synchronization with the rising edge of the clock signal clk. A storage area 32 having an address 2 ^{(n + 1)} is connected. The storage area 32 includes a memory cell array having a plurality of static random access memory cells (hereinafter referred to as “SRAM cells”) that can read and write data, or a plurality of registers. Each address includes upper i-bit first data rdata [m: k] representing a state machine state and lower k-bit second data rdda [k-1: 0] representing a state machine output signal. Stored. An input / output circuit 33 is connected to the storage area 32. When the write enable signal we is “1”, the input / output circuit 33 inputs the write data (wdata [m: 0]) in synchronization with the rising edge of the clock signal clk and applies the write data to the storage area 32. This is a circuit for outputting read data rdata [m: 0] from the storage area 32 in synchronization with the rising edge of the clock signal clk when we is “0”.

  FIG. 3 is a schematic configuration diagram showing the address signal addr [n: 0] for the clock synchronous memory 30 of FIG.

  The address signal addr [n: 0] includes data [n: j] of upper i bits (bit) indicating the current state of the state machine 20 and lower j bits (bit) indicating the current input to the state machine 20. Data [j-1: 0].

  FIG. 4 is a schematic configuration diagram showing the read data rdata [m: 0] of the clock synchronous memory 30 of FIG.

  The read data rdata [m: 0] includes upper-order i-bit (bit) data [m: k] indicating the next state of the state machine 20 and lower-order k bits (bits) indicating the output of the state machine 20 in the next state. ) Data [k-1: 0].

(Operation of Example 1)
In the Moore state machine 20 of the first embodiment, the following write operation (1) to the clock synchronous memory 30 and the read state operation (2) of the state machine are performed.

(1) Write Operation to Memory 30 FIG. 5 is a timing chart showing a write operation to the memory 30 in FIG.
In FIG. 5, times t1, t2, t3,... Of rising edges of the clock signal clk are sample timings of the memory 30. S1, S2, S3,... In {S1, I1}, {S2, I2}, {S3, I3},..., Which are write addresses waddr [n: 0], are Moore state machines to be realized. 20 states are indicated, and I1, I2, I3,... Indicate their input signals. WDATA1, WDATA2, WDATA3,..., Which is the write data wdata [m: 0], is expressed as the following expression (1) by the functions func1, func2.
WDATA1 = {func1 (S1, I1), func2 (func1 (S1, I1))}
WDATA2 = {func1 (S2, I2), func2 (func1 (S2, I2))}
WDATA3 = {func1 (S3, I3), func2 (func1 (S3, I3))}
... (1)

  The write data wdata [m: 0] of Equation (1) calculated in advance is written to each address of the memory 30 in the following procedure.

  In the Moore state machine 20 of FIG. 1, the write enable signal we becomes “1”, the memory 30 enters the write mode, and the selector 21 switches to the write address waddr [n: 0] side. The write address waddr [n: 0] and the write data wdata [m: 0] are input to the state machine 20 in synchronization with the sample timing times t1, t2, t3,... At the rising edge of the clock signal clk. The input write address waddr [n: 0] is selected by the selector 21, and an address signal addr [n: 0] as a selection result is input to the memory 30.

  In the memory 30 of FIG. 2, the input address waddr [n: 0] is decoded by the address decoder 31, and the address of the storage area 32 is designated by the decoding result. The input write data wdata [m: 0] is taken in by the input / output circuit 33 and written to a specified address in the storage area 32. At this time, {func1 (S, I), func2 (func1 The value (S, I))} is written. func1 is a function for determining "next state" from "current state" and "current input", and func2 is a function for determining "current output" from "current state". The value to be written is calculated in advance.

(2) Memory 30 read operation (state machine operation)
FIG. 6 is a timing chart showing the operation of the state machine, which is the read operation of the memory 30 in FIG.

  In FIG. 6, t11, t12, t13,... Are times of rising edges of the clock signal clk, and T is one cycle of the clock signal clk. In the address signal addr [j-1: 0] as the input signal in [j-1: 0], I1, I2, I3,... Indicate each input of the Moore type state machine 20, and the address signal addr [n : j], the upper i-bit read data rdata [m: k], S1, S2, S3,... indicate each state of the state machine 20. O1, O2, O3,... In the output signal out [k-1: 0] of the state machine 20 which is the lower k-bit read data rdata [k-1: 0] indicates each output. DL is the output delay time of the memory 30 from the time t11,... Of the rising edge of the clock signal clk.

Each state S2, S3,... And each output O1, O2, O3,... Is expressed by the function func1, func2 as in the following equation (2).
S2 = func1 (S1, I1) O1 = func2 (S1)
S3 = func1 (S2, I2) O2 = func2 (S2)
O3 = func2 (S3)
... (2)

  When the contents of the memory 30 are set by the write operation of (1), the “current state” and the “current input” are input to the addresses of the memory 30 in the following procedure in the following cycle. “Next state” and “output in the next state” are read from the memory 30.

  In the Moore state machine 20 of FIG. 1, after the write operation to the memory 30 is completed, when the write enable signal we is set to “0”, the memory 30 enters the read mode, and the selector 21 switches to the first signal IN side. . If the clock signal clk and the input signal in [j-1: 0] are input to the state machine 20, the lower-order j bits of the clock signal clk are synchronized with the times t11, t12, t13,. A first signal IN in which the input signal in [j-1: 0] and the upper i-bit read data rdata [m: k] are combined is selected by the selector 21, and the address signal addr [n as a result of this selection is selected. : 0] is input to the memory 30.

  In the memory 30 of FIG. 2, the input address addr [n: 0] is decoded by the address decoder 31, and the address of the storage area 32 is designated by the decoding result. From the designated address, the clock signal clk At each rising edge time t11, t12, t13,..., The read data rdata [m: 0] (that is, the states S2, S3,... And the outputs O2, O3,. Read and output from the input / output circuit 33. Of the output read data rdata [m: 0], the upper i-bit read data rdata [m: k] is data representing the states S2, S3,... Of the state machine 20 and is fed back to the selector 21. Input low-order k-bit read data [k-1: 0] is data representing the output O2, O3,... Of the state machine 20, and is output to the outside as an output signal out [k-1: 0]. Is done. At this time, only reading is repeated for the memory 30. By repeating this reading, the “next state” and the “output in the next state” are sequentially read from the memory 30 and the input / output circuit 33. Is output from.

(Effect of Example 1)
According to the first embodiment, the clock synchronous memory 30 is used, data representing the state S of the Moore state machine 20 is stored in each address of the memory 30, and the input signal in [j− 1: 0] and the data rdata [m: k] representing the state S in the read data rdata [m: 0] of the memory 30 are combined and input to the address of the memory 30 to generate the clock signal clk. Since it is configured to behave as the Moore state machine 20 that operates while changing the state S in synchronization, the following effects (a) to (c) are obtained.

  (A) By changing the data to be written in the memory 30, the behavior of the state machine 20 (that is, the state S and the output O per unit time) can be changed with the same hardware configuration. The number of input signals, the number of output signals, and the number of states of the state machine 20 increase as the control contents of the state machine 20 become more complicated. However, if a memory having a large number of bits of address / read data / write data is used, A complicated state machine 20 can be realized.

  (B) In the case of a conventional state machine, the upper limit value of the operation speed (ie, clock frequency) of the state machine changes depending on the complexity of the control contents of the state machine (ie, the function for determining the state and the output signal). In order to know the upper limit of the clock frequency of the state machine, work called timing analysis is required. On the other hand, in the first embodiment, the upper limit value of the clock frequency is determined by the read data output delay (DL) which is one of the AC characteristics of the memory 30, so it does not depend on the complexity of the control contents of the state machine 20. The upper limit value of the clock frequency can be known in advance. Note that the write operation to the memory 30 is normally performed only once at the time of system startup or the like, so it does not matter even if the write time is long.

  (C) According to the above (a) and (b), a Moore that has a simple and low-cost hardware configuration and can arbitrarily change the control contents of the state machine without changing the hardware circuit configuration. A mold state machine 20 can be provided.

(Configuration of Example 2)
FIG. 7 shows a second embodiment of the present invention, and is a schematic configuration diagram of a memory type state machine realized by using a clock synchronous memory and an asynchronous memory, and shows the first embodiment. Elements common to the elements inside are given common reference numerals.

  This Mealy state machine 20A inputs a j-bit input signal in [j-1: 0] and outputs a k-bit output signal out [k-1: 0]. The first address signal A first selector 21 that selects and outputs addr1 [n: 0], and a clock synchronous type in which data is written to and read from an address specified by the first address signal addr1 [n: 0] The memory 30A, a second selector 22 connected to the output side of the clock synchronous memory 30A, selecting and outputting the second address signal addr2 [n: 0], and the second address signal addr2 [n [0]], an asynchronous memory 40 and the like in which data is written to and read from the address designated by [0].

  As in the first embodiment, the first selector 21 inputs the n + 1-bit write address waddr [n: 0] to the clock synchronous memory 30A, and lower bits or upper bits (for example, the state machine 20A) A lower j bit) input signal in [j-1: 0] and read data rdata1 [i-1: 0] from the memory 30A, for example, a second state representing the current state of the upper i-bit state machine A first signal IN1 combined with data is input, and a first write enable signal we1 transitions to a first logic level (eg, “1”) and a second logic level (eg, “0”). When the address selection signal consisting of "1" is selected, the write address waddr [n: 0] is selected, and when the address selection signal (we1) is "0", the first signal IN1 is selected and the selection result Output the first address signal addr1 [n: 0] This is given to the memory 30A.

  Similar to the clock synchronous memory 30 of the first embodiment, the clock synchronous memory 30A has a first storage area composed of a plurality of addresses, and the first write is performed at the edge (for example, the rising edge) of the clock signal clk. When the enable signal we1 is “1”, the write mode is set. At this time, the n + 1-bit write address waddr [n: 0] indicates the first storage area address indicated by the i + 1-bit first write data wdata1 [ i-1: 0] is written, and when the first write enable signal we1 is “0” at the rising edge of the clock signal clk, the read mode is entered, and the first address signal addr1 [n: 0] is fetched. After a certain delay time (read data output delay) from the rising edge of the clock signal clk, the stored contents of the address in the first storage area specified by the first address signal addr1 [n: 0] are read data rdat. It is output as a1 [i-1: 0].

  The first address signal addr1 [n: 0] for the memory 30A is output by the first selector 21 when the first write enable signal we1 is “1” (that is, during writing). When the address waddr [i-1: 0] is input and when the first write enable signal we1 is “0” (that is, at the time of reading), the upper i bits are the second data rdata1 [ j-1: 0] and selected by the first write enable signal we1 so that the first signal IN1 whose lower j bits are the input signal in [j-1: 0] is input. The

  The second selector 22 inputs the write address waddr [n: 0], the upper i-bit second data rdata1 [i-1: 0], and the lower j-bit input signal in [j-1: 0]. And a second write enable signal we2 that transitions to a first logic level (eg, “1”) and a second logic level (eg, “0”). For example, when the address is “1”, the write address waddr [n: 0] is selected, and when the second write enable signal we2 is “0”, the second signal IN2 is selected. The address signal addr2 [n: 0] is output and given to the asynchronous memory 40.

  Asynchronous memory 40 has a second storage area composed of a plurality of addresses in substantially the same manner as clock synchronous memory 30A, and has a first logic level (for example, “1”) and a second logic level (for example, For example, when the third write enable signal we3 transitioning to “0” is “1”, the second write data wdata2 [k-1: 0] is fetched and the address of the state machine is stored in each address of the second storage area. The third data rdata2 [k-1: 0] representing the current output signal is stored, and the second signal IN2 selected by the second selector 22 when the second write enable signal we2 is “0”. After a certain delay time (read data output delay) from the address of the second storage area specified by, the third data rdata2 [k-1: 0] is read and the output signal out [k-1: 0] Is output as

  The clock synchronous memory 30A according to the second embodiment is configured by an SRAM, a plurality of registers, or the like in substantially the same manner as the clock synchronous memory 30 shown in FIG. 2 according to the first embodiment. Further, the asynchronous memory 40 is configured such that, for example, in FIG. 2, the clock signal clk is deleted, and the address decoder 31 and the input / output circuit 33 operate asynchronously with respect to the clock signal clk.

  FIG. 8 is a schematic configuration diagram showing the first address signal addr1 [n: 0] and the second address signal addr2 [n: 0] for the clock synchronous memory 30A and the asynchronous memory 40 of FIG.

  The address signals addr1 [n: 0] and addr2 [n: 0] are high-order i-bit data [n: j] indicating the current state of the state machine 20A and low-order j indicating the current input to the state machine 20A. It consists of bit data [j-1: 0].

(Operation of Example 2)
In the memory type state machine 20A of the second embodiment, the following write operation (1) for the clock synchronous memory 30A, write operation (2) for the asynchronous memory 40, the clock synchronous memory 30A, and the asynchronous memory The state machine operation (3), which is 40 read operations, is performed.

(1) Write Operation to Memory 30A FIG. 9 is a timing chart showing a write operation to the memory 30A in FIG.
9, times t1, t2, t3,... Of rising edges of the clock signal clk are write timings of the memory 30A. S1, S2, S3,... In {S1, I1}, {S2, I2}, {S3, I3},..., Which are write addresses waddr [n: 0], are memory state machines to be realized. Each state of 20A is shown, and I1, I2, I3,. The first write data wdata1 [i-1: 0] is represented by functions func1 (S1, I1), func1 (S2, I2), funcl (S3, I3),.

  The first write data wdata1 [i-1: 0] is written to each address of the memory 30A by the following procedure.

  In the Mealy state machine 20A of FIG. 7, the first write enable signal we1 becomes “1”, the memory 30A enters the write mode, and the first selector 21 switches to the write address waddr [n: 0] side. In synchronization with the write timing times t1, t2, t3,... Of the rising edge of the clock signal clk, the write address waddr [n: 0] and the first write data wdata1 [i-1: 0] are stored in the state machine 20A. Is input. The input write address waddr [n: 0] is selected by the selector 21, and the first address signal addr1 [n: 0] as the selection result is input to the memory 30A.

  In the memory 30A, the address of the first storage area is designated by the input first address signal addr1 [n: 0]. The input first write data wdata1 [i-1: 0] is written to a specified address in the first storage area. At this time, the value of the function func1 (S, I) is written to the {S, I} address of the memory 30A for each combination of the state S and each input signal I of the state machine 20A to be realized. func1 is a function for determining "next state" from "current state" and "current input".

(2) Write Operation to Memory 40 FIG. 10 is a timing chart showing a write operation to the memory 40 in FIG.
10, times t1, t2, t3,... Of rising edges of the third write enable signal we3 are write timings of the memory 40. The second write data wdata2 [k-1: 0] is represented by functions func2 (S1, I1), func2 (S2, I2), func3 (S3, I3),.

  The second write data wdata2 [k-1: 0] is written to each address of the memory 40 in the following procedure.

  In the memory type state machine 20A of FIG. 7, when the second write enable signal we2 is “1”, the memory 40 is in the write mode, and the second selector 22 is switched to the write address waddr [n: 0] side. In synchronization with the write timing times t1, t2, t3,... Of the rising edge of the third write enable signal we3, the write address waddr [n: 0] and the second write data wdata2 [k-1: 0] Is input to the state machine 20A. The input write address waddr [n: 0] is selected by the selector 22, and the second address signal addr2 [n: 0] as the selection result is input to the memory 40.

  In the memory 40, the address of the second storage area is designated by the input second address signal waddr2 [n: 0]. The input second write data wdata2 [k-1: 0] is written to a specified address in the second storage area. At this time, the value of the function func2 (S, I) is written to the {S, I} address of the memory 40 for each combination of the state S and each input signal I of the memory type state machine 20A to be realized. . func2 is a function for determining "current output" from "current state" and "current input".

(3) Read operation of the memories 30A and 40 (state machine operation)
FIG. 11 is a timing chart showing the operation of the state machine, which is the read operation of the memories 30A and 40 in FIG.

  In FIG. 11, t11, t12, t13,... Are times of rising edges of the clock signal clk, and T is one cycle of the clock signal clk. I1, I2, I3,... In the address signals addr1 [j-1: 0], addr2 [j-1: 0], which are the input signals in [j-1: 0], are each of the memory type state machine 20A. S1, S2, S3,... In the read data rdata1 [i-1: 0] as the address signal addr1 [n: j] and the address signal addr2 [n: j] are indicated in the state machine 20A. Indicates the state. O1, O2, O3,... In the output signal out [k-1: 0], which is the read data rdata2 [k-1: 0], indicates each output of the state machine 20A. DL1 is the output delay time of the memory 30A from the time t11,... Of the rising edge of the clock signal clk, and DL2 is the output delay time of the memory 40 after the output delay time DL1.

Each state S2, S3,... And each output O1, O2, O3,... Is expressed by the function func1, func2 as in the following equation (3).
S2 = func1 (S1, I1) O1 = func2 (S1, I1)
S3 = func1 (S2, I2) O2 = func2 (S2, I2)
O3 = func2 (S3, I3)
... (3)

  When the contents of the memory 30A are set by the write operation of (1), in the next cycle, by inputting “current state” and “current input” to the address of the memory 30A in the following procedure, The “next state” is read from the memory 30A. Further, when the contents of the memory 40 are set by the write operation of (2), the “current state” and “current input” are input to the addresses of the memory 40 by the following procedure, thereby The “current output” is read from the memory 40 after the read data output delay time DL2.

  In the memory type state machine 20A of FIG. 7, after the write operation to the memory 30A and the memory 40 is completed, the first and second write enable signals we1, we2 are set to “0”, and the third write enable signal we3 is set to “1”. Then, the memories 30A and 40 are in the read mode, the first selector 21 is switched to the first signal IN1 side, and the second selector 22 is switched to the second signal IN2 side.

  If the clock signal clk and the input signal in [j-1: 0] are input to the state machine 20A, the input signal in [j-1: 0] and the read data rdada1 [i-1 are generated at every rising edge of the clock signal clk. : 0] is selected by the first selector 21 and the first address signal addr1 [n: 0], which is the selection result, is input to the memory 30A. State machine states S1, S2, S3,... Are read. The second signal IN2 in which the states S1, S2, S3,... And the input signal in [j-1: 0] are combined is selected by the second selector 22, and the second result, which is the result of this selection, is selected. Address signal addr2 [n: 0] is input to the memory 40, and the outputs O1, O2, O3,. At this time, only reading is repeated for the memory 30A and the memory 40, and by repeating this reading, the "current output" is sequentially read from the memory 40 and the output signal out [k- 1: 0].

(Effect of Example 2)
According to the second embodiment, the clock synchronous memory 30A and the asynchronous memory 40 are used to behave as a memory type machine 20A that operates while changing the state S in synchronization with the clock signal clk. There are almost the same effects as in the first embodiment.

  FIG. 12 is a schematic configuration diagram of a system including a state machine according to the third embodiment of the present invention.

  The system 50 includes an LSI, a board, and the like, and has a central processing unit (hereinafter referred to as “CPU”) 51 that performs program control of the entire system. A system bus 52 is connected to the CPU 51, and a communication module 53 for performing communication with the outside and reading data and a memory controller 54 are connected to the system bus 52. One or a plurality of semiconductor integrated circuits (for example, two modules) 60-1 and 60-2 are connected to the memory controller 54. The modules 60-1 and 60-2 include state machines 20-1 and 20-2 shown in FIGS. 1 and 7, and controlled circuits controlled by the state machines 20-1 and 20-2, respectively. 61-1, 61-2, etc. are provided respectively. The memory controller 54 controls writing to a memory provided in the state machines 20-1 and 20-2 of the modules 60-1 and 60-2.

  In the system 50 having such a configuration, for example, the CPU 51 controls the communication module 53 to externally write data to be written to the memories in the state machines 20-1 and 20-2 of the modules 60-1 and 60-2. The state machine 20 of each module 60-1, 60-2 in the system 50 is written by writing the read data into the memory in the state machine 20-1, 20-2 of each module 60-1, 60-2. The control contents of -1 and 20-2 can be easily changed. For example, a server or the like on the Internet communicates with the CPU 51 in the system 50 to easily change the hardware level for the control contents of the state machines 20-1 and 20-2 in the modules 60-1 and 60-2. It becomes possible to do.

(Modification)
The present invention is not limited to the above embodiment. For example, the clock synchronous memories 30 and 30A in FIGS. 1 and 7 are changed to a configuration that operates in synchronization with the falling edge of the clock signal clk, The type memories 30 and 30A and the asynchronous type memory 40 are changed to other circuit configurations other than those shown in FIG. 2, or other types in the Moore type state machine 20 shown in FIG. 1 and the Melee type state machine 20A shown in FIG. Various usage forms and modifications are possible, such as adding a circuit to expand the function.

BRIEF DESCRIPTION OF THE DRAWINGS It is Example 1 of this invention, Comprising: It is a schematic block diagram of the Moore type state machine implement | achieved using the clock synchronous memory. It is a schematic block diagram which shows the clock synchronous memory 30 in FIG. FIG. 3 is a schematic configuration diagram showing an address signal addr [n: 0] for the clock synchronous memory 30 of FIG. 2. FIG. 3 is a schematic configuration diagram showing read data rdata [m: 0] of the clock synchronous memory 30 of FIG. 2. 2 is a timing chart showing a write operation with respect to a memory 30 in FIG. 1. 3 is a timing chart showing an operation of the state machine, which is a read operation of the memory 30 in FIG. 1. FIG. 9 is a schematic configuration diagram of a memory type state machine according to a second embodiment of the present invention, which is realized by using a clock synchronous memory and an asynchronous memory. FIG. 8 is a schematic configuration diagram showing a first address signal addr1 [n: 0] and a second address signal addr2 [n: 0] for the clock synchronous memory 30A and the asynchronous memory 40 of FIG. 8 is a timing chart showing a write operation with respect to a memory 30A in FIG. 8 is a timing chart showing a write operation with respect to a memory 40 in FIG. It is a timing chart which shows operation | movement of the state machine which is read operation | movement of the memories 30A and 40 in FIG. It is a schematic block diagram of the system carrying the state machine which shows Example 3 of this invention. It is a figure which shows the structure and operation | movement for demonstrating the principle of a state machine. It is a block diagram which shows the principle of the conventional Moore type state machine. It is a block diagram which shows the principle of the conventional Miley type | mold state machine. It is a block diagram which shows the principle of the semiconductor integrated circuit which has a state machine. 17 is a timing chart showing an operation in the semiconductor integrated circuit 10 of FIG.

Explanation of symbols

20 Moore State Machine 20A Mealy State Machine 20-1, 20-2 State Machine 21, 22 Selector 30, 30A Clock Synchronous Memory 40 Asynchronous Memory 50 System 60-1, 60-2 Module

Claims (3)

The write address is input, and an input signal to the state machine composed of lower bits or upper bits, and first data that is composed of bits at different positions with respect to the input signal and that represents the current state of the state machine, When the combined first signal is input and the write enable signal transitioning to the first and second logic levels is the first logic level, the write address is selected, and the write enable signal is the second enable signal. A selector for selecting the first signal at a logic level;
A storage area having a plurality of addresses, and when the write enable signal is at the first logic level, the write data is fetched in synchronization with a clock signal, and the next state of the state machine is stored in each address of the storage area. And second data representing the output signal of the state machine are stored, and when the write enable signal is at the second logic level, the clock signal is synchronized with the clock signal. In one cycle, read data having the second and third data is read from the address of the storage area specified by the first signal selected by the selector, and the second data in the read data is read out. Is supplied to the selector as the first data, and the third data is output to the outside as an output signal of the state machine. State machine which is characterized in that a lock synchronous memory. The write address is input, and an input signal to the state machine composed of lower bits or upper bits, and first data that is composed of bits at different positions with respect to the input signal and that represents the current state of the state machine, When the combined first signal is input and the first write enable signal transitioning to the first and second logic levels is the first logic level, the write address is selected, and the first write enable is selected. A first selector that selects the first signal when the signal is at the second logic level;
A first storage area having a plurality of addresses, and when the first write enable signal is at the first logic level, the first write data is fetched in synchronization with a clock signal. The second data representing the next state of the state machine is stored in each address of the state machine, and when the first write enable signal is at the second logic level, the clock signal is synchronized with the clock signal. Within one cycle, the second data is read from the address of the first storage area designated by the first signal selected by the first selector, and the first data is used as the first data. A clock-synchronized memory for the selector
A second write enable that inputs the write address and inputs a second signal that is a combination of the input signal to the state machine and the second data, and makes a transition to the first and second logic levels. A second select that selects the write address when a signal is at the first logic level, and selects the second signal when the second write enable signal is at the second logic level;
A second storage area having a plurality of addresses, and when the third write enable signal transitioning to the first and second logic levels is at the first logic level, the second write data is fetched and the second The third data representing the output signal of the state machine is stored in each address of the second storage area, and is selected by the second selector when the second write enable signal is at the second logic level. And an asynchronous memory that reads out the third data from the address of the second storage area specified by the second signal and outputs it as an output signal of the state machine. State machine. The state machine according to claim 1 or 2,
A semiconductor integrated circuit comprising: a controlled circuit that is controlled by an output of the state machine and performs predetermined processing in synchronization with the clock signal.

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