JP2008283396A - Memory, shift register, integrated circuit and processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory and a shift register which are made small in the scale. <P>SOLUTION: H latches 50A, 50C and 50E for outputting inputted data as they are when signals inputted from a gate terminal are at a high level and interrupting the inputted data, holding the data inputted until then and outputting the held data when the signals inputted from the gate terminal are at a low level and L latches 50B, 50D and 50F for performing the opposite operations are alternately connected. By combining a clock signal control circuit 55 and logic circuits 53-53, clock signals 54 are controlled and the signals inputted to the gate terminal are controlled. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory, a shift register, an integrated circuit, and a processing device.

  An FPGA (Field Programmable Gate Array) is known as a technique for directly realizing program execution by hardware (for example, Patent Document 1).

  The FPGA changes the connection logic between logic circuits by giving logic data as a program, thereby obtaining the operation result in hardware. By performing the calculation using the FPGA, it is possible to obtain a calculation result much faster than the calculation by a CPU (Central Processing Unit) such as a conventional general-purpose computer.

Also, a method has been proposed in which the circuit configuration is reused by dynamically reconfiguring the FPGA. The type of hardware that can be dynamically changed is hereinafter referred to as reconfigurable hardware.
Japanese Patent No. 3540796

  By the way, when realizing reconfigurable hardware as LSI (Large Scale Integration), it is necessary to hold configuration information or internal state information before dynamically changing a circuit configuration. As a mechanism for holding these pieces of information, a shift register using a flip-flop has been conventionally used in order to easily produce a small size.

  The size of the gate size (area) of the mechanism for holding this information occupies most of the gate size of the reconfigurable hardware, which is a problem when the reconfigurable hardware is realized as an LSI. .

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory, a shift register, an integrated circuit and a processing device including the memory that are reduced in size.

In order to achieve the above object, a memory according to the first aspect of the present invention includes:
A memory composed of a plurality of storage area stages,
A gate terminal, an input terminal, and an output terminal; when the clock signal input from the gate terminal is at a high level, the data input from the input terminal is output as it is from the output terminal; A high latch that blocks data input from the input terminal when the input clock signal is at a low level, and holds and holds the data that has been input so far, from the output terminal;
A gate terminal, an input terminal, and an output terminal are provided, and when the clock signal input from the gate terminal is at a high level, the data input from the input terminal is cut off and the data input until then is retained. A low latch that outputs the held data from the output terminal, and outputs the data input from the input terminal as it is from the output terminal when the clock signal input from the gate terminal is at a low level; Prepared,
The plurality of storage area stages are composed of the high latch and the low latch connected alternately,
A clock signal output unit that repeatedly outputs a high level clock signal and a low level clock signal at a predetermined period;
A clock signal control unit for outputting a control signal for controlling the clock signal;
A plurality of logic circuits connected to each of the gate terminals of the high latch and the low latch, inputting the clock signal and the control signal, performing a predetermined operation, and outputting an operation result to the gate terminal;
It is characterized by providing.

In order to achieve the above object, a shift register according to the second aspect of the present invention provides:
A memory composed of a plurality of storage area stages,
A gate terminal, an input terminal, and an output terminal; when the clock signal input from the gate terminal is at a high level, the data input from the input terminal is output as it is from the output terminal; A high latch that blocks data input from the input terminal when the input clock signal is at a low level, and holds and holds the data that has been input so far, from the output terminal;
A gate terminal, an input terminal, and an output terminal are provided, and when the clock signal input from the gate terminal is at a high level, the data input from the input terminal is cut off and the data input until then is retained. A low latch that outputs the held data from the output terminal, and outputs the data input from the input terminal as it is from the output terminal when the clock signal input from the gate terminal is at a low level; Prepared,
The plurality of storage area stages are composed of the high latch and the low latch connected alternately,
A clock signal output unit that repeatedly outputs a high level clock signal and a low level clock signal at a predetermined period;
A clock signal control unit for outputting a control signal for controlling the clock signal;
A plurality of logic circuits connected to each of the gate terminals of the high latch and the low latch, inputting the clock signal and the control signal, performing a predetermined operation, and outputting an operation result to the gate terminal;
It is characterized by providing.

The plurality of logic circuits include an AND circuit and an OR circuit,
The logic circuit whose output is connected to the gate terminal of the high latch is an AND circuit,
The logic circuit whose output is connected to the gate terminal of the low latch is an OR circuit,
The clock signal control unit may be configured to invert the control signal and input it to the OR circuit.

The clock signal control unit includes a plurality of output units corresponding to the high latch and the low latch,
Each of the output units may be configured to output a specific control signal for controlling each of the high latches or each of the low latches in an output cycle that is ½ of the predetermined cycle.

  Each of the output units outputs the specific control signal at a high level at a timing when data is input to the corresponding high latch or the low latch, and the low level at a timing at which data is held in the corresponding high latch or the low latch. The specific control signal may be output.

An integrated circuit according to a third aspect of the present invention is:
The shift register;
A control unit;
A circuit that dynamically changes the circuit configuration based on the control of the control unit and performs an operation according to the circuit configuration;
With
The control unit and the circuit use the shift register as a storage area.

A processing apparatus according to a fourth aspect of the present invention is:
The integrated circuit;
A program storage area for storing a program to be executed by the integrated circuit;
It is characterized by providing.

  According to the present invention, the areas of the memory and the shift register can be reduced. In particular, the area of the integrated circuit including the shift register can be reduced. In addition, it is possible to provide a processing apparatus having a high processing capability including the integrated circuit.

  Hereinafter, the memory, the shift register 60, the reconfigurable hardware 4 as an integrated circuit, and the processing device 10 according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing an overall configuration of a processing apparatus 10 according to an embodiment of the present invention.

  As illustrated in FIG. 1, the processing device 10 includes a reconfigurable hardware 2, a compiling unit 3, and a storage unit 4.

  The reconfigurable hardware 2 includes a reconfigurable circuit 21, a setting unit 22, a control unit 23, and an internal state holding circuit 24.

  The reconfigurable circuit 21 is a circuit that outputs input data after receiving input data and performing a predetermined operation. The reconfigurable circuit 21 can change the setting under the control of the control unit 23. The arithmetic function can be changed by changing the setting. The reconfigurable circuit 21 includes a large number of PEs (Processor Elements), which are the minimum units of a calculation mechanism that performs simple calculations, and a large number of flip-flops that hold intermediate results of the calculations. Moreover, the connection part which can set the connection relation of the input and output of each PE is included. The connection relationship between the PEs is set based on setting data 22 </ b> A supplied by the setting unit 22.

  The input data input to the reconfigurable circuit 21 may be data read from an external storage device such as a magnetic disk device in addition to data input from an input device such as a keyboard. The output data output from the reconfigurable circuit 21 may be output from an output device such as a display device, or may be written in an external storage device, and is control data for controlling peripheral devices. There may be. In the processing device 10 including the reconfigurable hardware 2, the circuit configuration of the reconfigurable circuit 21 can be dynamically changed, and processing corresponding to input data can be executed at high speed. The processing result can be output as output data.

  The setting unit 22 stores setting data 22A. The setting unit 22 supplies setting data 22 </ b> A for setting the reconfigurable circuit 21 to a predetermined circuit configuration under the control of the control unit 23. Upon receiving the setting data 22A, the reconfigurable circuit 21 changes the circuit configuration based on the setting data 22A.

  The control unit 23 controls the operation of the entire reconfigurable hardware 2. In addition, the control unit 23 acquires setting data 42 from the storage unit 4.

  When the circuit configuration of the reconfigurable circuit 21 is changed by the setting unit 22, the internal state holding circuit 24 is held in a flip-flop in the reconfigurable circuit 21 as an intermediate result of calculation before the circuit configuration is changed. This is a circuit for saving intermediate result data and data (internal state data) indicating the circuit configuration before the change. Then, at the timing when the computation after the circuit configuration change is completed, the reconfigurable circuit 21 is returned to the circuit configuration before the change by using the saved internal state data under the control of the control unit 22, and the reconfigurable circuit The intermediate result data is returned to the flip-flop 21. The output of the internal state holding circuit 24 is connected to the reconfigurable circuit 2 by a path unit 25 that functions as a feedback path.

  The compiling unit 3 compiles a source program described in a programming language that can be described in hardware into data (setting data 42) that defines the functions of PEs in the reconfigurable circuit 21 and the connection relationship between the PEs.

  The storage unit 4 stores a source program 41 and setting data 42.

  The source program 41 is written in a program language capable of hardware description (for example, RTL (Register Transfer Level) or C language). The source program 41 is a program to be realized by the reconfigurable hardware 2.

  The setting data 42 defines the function of the PE in the reconfigurable circuit 21 and the connection relationship between the PEs. As described above, the setting data 42 is generated when the compiling unit 3 compiles the source program 41. The generated setting data 42 is stored in the setting unit 22 by the control unit 23. The setting data 22A stored in the setting unit 22 is supplied to the reconfigurable circuit 21 by the setting unit 22. When the setting data 22A is received, the reconfigurable circuit 21 changes the circuit configuration based on the setting data 22A.

  The part for storing the setting data 22A of the setting unit 22 and the internal state holding circuit 24 are configured by the shift register 60 according to the embodiment of the present invention. The shift register 60 according to the embodiment of the present invention is not a D (delay) flip-flop normally employed as a memory cell but a shift register using a D (delay) latch having a smaller gate size than the D flip-flop.

  FIG. 2 is a diagram showing the shift register 60 according to the embodiment of the present invention. As shown in FIG. 2A, the shift register 60 has a 32-bit write bus and is constituted by a D latch 50 at a necessary stage (in this embodiment, 6 stages for simplicity of explanation). Each of the D latches 50 includes a gate terminal (clock input), an input terminal, and an output terminal.

  These D latches 50 output the data inputted from the input terminal as it is from the output terminal when the signal inputted from the gate terminal is at the high level, and also when the signal inputted from the gate terminal is at the low level. There is an H (high) latch that blocks data input from an input terminal, holds data that has been input so far, and outputs the retained data from the output terminal. Contrary to the H latch, when the signal input from the gate terminal is at a high level, the data input from the input terminal is cut off, and the data input up to that time is retained. There is an L (low) latch that outputs the data inputted from the input terminal as it is from the output terminal when the signal inputted from the gate terminal is at a low level. The shift register 60 of this embodiment has a configuration in which H latches and L latches are alternately connected. The output terminal and input terminal of each D latch are connected.

  In this embodiment, the D latches 50A, 50C, and 50E are H latches, and the D latches 50B, 50D, and 50F are L latches.

  The L latch may be one in which a negative circuit (NOT circuit) is connected to the gate terminal of the H latch.

  As shown in FIG. 2B, an AND circuit (AND circuit) 51 is connected to the gate terminal of the H latch of the shift register 60 of this embodiment, and an OR circuit is connected to the gate terminal of the L latch. (OR circuit) 52 is connected. A clock signal (CLK) 54 and a control signal from the clock signal control circuit 55 are input to the logical sum circuit 51 and the logical product circuit 51. A negation circuit (NOT circuit) is provided in the path from the clock signal control circuit 55 to the AND circuit 51, and the control signal from the clock signal control circuit 55 is inverted and input to the AND circuit 51.

  The logical product circuit 51 and the logical sum circuit 52 include two input terminals and one output terminal. The AND circuit 51 is a circuit that outputs “1” (high level) only when “1” (high level) is input to all input terminals. The OR circuit 52 is a circuit that outputs “1” (high level) when “1” (high level) is input to at least one input terminal. The negation circuit 53 has one input terminal and one output terminal. The negative circuit 53 is a circuit that outputs “0” (low level) when “1” (high level) is input, and outputs “1” (high level) when “0” (low level) is input. is there.

  The clock signal 54 is a signal whose voltage periodically repeats a high level and a low level. The clock signal 54 is generated from, for example, a crystal oscillator.

  The clock signal control circuit 55 is a circuit for controlling the clock signal 54 input to the gate terminals of the H latch and the L latch. The clock signal input to the gate terminals of the H latch and the L latch by performing a logical operation on the clock signal 54 and the control signal output from the clock signal control circuit 55 via the logical product circuit 51 or the logical sum circuit 52. 54 is controlled.

  The clock signal control circuit 55 includes a control circuit 56 and a control register 57. The control circuit 56 is a circuit for controlling a control signal output from the clock signal control circuit 55. The control register 57 is provided with registers (for example, D flip-flops) of the same number (6 stages in this embodiment) as the number of stages of the D latch 60 constituting the shift register 60. Each control register 57 corresponds to each D latch. Then, the data stored in each control register 57 is output as a control signal at a half cycle (ie, double speed) of the clock signal 54 under the control of the control circuit 56.

  FIG. 3 is a diagram showing the operation of the clock signal control circuit 55 (particularly the control register 57). In this embodiment, the control register 57 is provided in six stages (57A to 57F).

  First, under the control of the control circuit 56, data indicating “1” is stored in the first-stage control register 57A at time T1. At the same time, data (high level signal) indicating “1” is output from the control register 57A to the AND circuit 51 connected to the D latch 50A. At time T2, data indicating “1” is also stored in the second-stage control register 57B. At the same time, data (high level signal) indicating “1” is output from the control register 57A to the AND circuit 51 connected to the D latch 50A, output from the control register 57B, and inverted by the negation circuit 53. The data (low level signal) indicating “0” is output to the OR circuit 52 connected to the D latch 50B. That is, data indicating “1” is sequentially stored in all the stages at a predetermined cycle (T2−T1 = T1). At the same time, data (high level signal) indicating “1” is output to the AND circuit 51 to which each control register 57 is connected. Further, data (low level signal) indicating “0” is output to the OR circuit 52 to which each control register 57 is connected.

  When data indicating “1” is stored in all stages, the data is inverted and data indicating “0” is stored in the control register 57. That is, data indicating “0” is stored in the control register 57F at the sixth stage at time T8. At the same time, data (low level signal) indicating “0” is output from the control register 57F to the OR circuit 52 connected to the D latch 50F.

  In this manner, the control circuit 56 sequentially stores data indicating “1” in the control register 57 at a predetermined cycle (T1), and inverts to indicate “0” when storage to the end control register 57 is completed. Store the data.

  The CLK edge in FIG. 3 indicates the edge of the clock signal 54, the upward arrow indicates the rising edge of the clock signal 54, and the downward arrow indicates the falling edge of the clock signal 54. In this way, the control signal and the clock signal 54 are synchronized. The cycle of the clock signal 54 is T3-T1 = T2 = T1 * 2. That is, it is twice the operation cycle of the control circuit 56.

  FIG. 4 is a timing chart of data and signals input to each D latch 50. The time in the figure may coincide with the time used in FIG. “Data” in the figure indicates data input to each D latch 50. This figure shows an example in which data A to data F are sequentially input to the shift register 60. The period in which the data A to data F are sequentially input coincides with the period of the clock signal 54.

  “CLK” in the figure indicates the clock signal 54. The “control signal” indicates a control signal input from the clock signal control circuit 55 to the AND circuit 51 connected to each D latch 50. The “control signal (inverted)” indicates an inverted control signal input from the clock signal control circuit 55 to the OR circuit 52 connected to each D latch 50 via the negation circuit 53.

  That is, a logical circuit (logical product circuit 51 or logical sum circuit 52) connected to each D latch 50 is shown. “AND” and “OR” indicate calculation results of the corresponding logic circuits, and are signals input to the gate terminals of the respective D latches 50.

  FIG. 5 is a diagram schematically showing data input to the shift register 60. As shown in FIGS. 4 and 5, data A is input to the D latch 50A at time T1, and since it is an H latch, data is input at time T2, which is the timing when the signal input to the gate terminal becomes “0”. Hold A (latch). Data B is input at time T3, and data B is held at time T4. Data C is input at time T5, and data C is held at time T6. Data D is input at time T7, and data D is held at time T8. Data E is input at time T9, and data E is held at time T10. Data F is input at time T11, and data F is held at time T12. Thus, the D latch 50A finally holds the data F.

  The data A is input to the D latch 50B at time T2, and since it is an L latch, the data A is held (latched) at time T3, which is the timing when the signal input to the gate terminal becomes “1”. Data B is input at time T4, and data B is held at time T5. Data C is input at time T6, and data C is held at time T7. Data D is input at time T8, and data D is held at time T9. Data E is input at time T10, and data E is held at time T11. After time T11, since the signal input to the gate terminal is “1”, the data E is continuously held. Thus, the D latch 50B finally holds the data E.

  Since the data A is input to the D latch 50C at time T3 and is an H latch, the data A is held (latched) at time T4, which is the timing when the signal input to the gate terminal becomes “0”. Data B is input at time T5, and data B is held at time T6. Data C is input at time T7, and data C is held at time T8. Data D is input at time T9, and data D is held at time T10. After time T10, since the signal input to the gate terminal is “0”, the data D is continuously held. Thus, the D latch 50C finally holds the data D.

  Since the data A is input to the D latch 50D at time T4 and is an L latch, the data A is held (latched) at time T5 when the signal input to the gate terminal becomes “1”. Data B is input at time T6, and data B is held at time T7. Data C is input at time T8, and data C is held at time T9. After time T9, since the signal input to the gate terminal is “1”, the data C is held. Thus, the D latch 50D finally holds the data C.

  The data A is input to the D latch 50E at time T5, and since it is an H latch, the data A is held (latched) at time T6, which is the timing when the signal input to the gate terminal becomes “0”. Data B is input at time T7, and data B is held at time T8. After time T8, since the signal input to the gate terminal is “0”, data B is continuously held. Thus, the D latch 50E finally holds the data B.

  Since the data A is input to the D latch 50F at time T6 and is an L latch, the data A is held (latched) at time T7, which is the timing when the signal input to the gate terminal becomes “1”. After time T7, since the signal input to the gate terminal is “1”, data A is continuously held. Thus, the D latch 50F finally holds the data A.

  In this manner, the shift register 60 using the D latch can sequentially store data without requiring a decoding circuit as in the control for storing data with an address. Since the shift register 60 uses the D latch 50 having a gate size ½ of that of the flip-flop as a memory cell, the gate size of the shift register 60 can be reduced. As a result, the size of the reconfigurable hardware 2 (integrated circuit) can be reduced. In addition, information can be processed at high speed by the processing device 10 including the reconfigurable hardware 2.

  The data stored in the shift register 60 can be output in parallel by arranging signal lines in parallel from each D latch 50 as shown in FIG.

(Modification)
In the above embodiment, the memory according to the embodiment of the present invention functions as a shift register by allowing the clock control circuit 55 to output a control signal so as to be sequentially stored in each D latch 50. . When the control circuit 56 controls the control register 57, an arbitrary control signal can be output.

  For example, as shown in FIGS. 7 and 8, the data stored in the D latch 50 may be sequentially output at a predetermined timing. In the example of FIG. 7, the data is sequentially output every two cycles from time T10. In order to operate in this way, the control circuit 56 may be controlled to store data in the control register 57 as shown in FIGS. The example of FIGS. 9 and 10 is the same as the example shown in FIG. 3 until time T10. After time T11, the control circuit 56 sequentially fills “1” from the output end register (in this example, the control register 57F) to the control register 57B in the input direction, and then turns back to control. "0" is filled up to the register 57F. The operation from time T22 is the same as the operation from time T1.

  By controlling in this way, the memory according to the embodiment of the present invention can be used as a delay line or FIFO (First In First Out) having a memory capacity twice as large as the minimum delay. It can be used for weights outside the frame.

  The present invention is not limited to the above-described embodiment, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above embodiment, the part for storing the setting data 22A of the setting unit 22 and the internal state holding circuit 24 are configured by the shift register 60. However, only one of them is the shift register 60 and the other is the stack. Other registers may be used.

  The clock signal control circuit 55 outputs a control signal using the control register 57, but is not limited to this as long as it can output a control signal that can achieve the object of the present invention. You may make it output.

  Further, as shown in FIG. 2A, the clock signal control circuit 55, the logical product circuit 51, the logical sum circuit 52, and the negation circuit 53 are combined to control the clock signal 54. For example, the combination of the logic circuits is arbitrary as long as the same control can be executed in combination with the clock signal control circuit 55.

It is a block diagram which shows the whole structure of the processing apparatus which concerns on embodiment of this invention. It is a figure which shows the shift register which concerns on embodiment of this invention. It is a figure which shows operation | movement of a clock signal control circuit. 4 is a timing chart of data and signals input to each D latch. It is the figure which represented typically the data input into a shift register. It is a figure for demonstrating the output of the information from a shift register. It is the figure which represented typically the data input into the shift register of a modification. It is the figure which represented typically the data input into the shift register of a modification. It is a figure which shows operation | movement of the clock signal control circuit of a modification. It is a figure which shows operation | movement of the clock signal control circuit of a modification.

Explanation of symbols

2 Reconfigurable hardware 3 Compile unit 4 Storage unit 10 Processing device 21 Reconfigurable circuit 22 Setting unit 22A Setting data 23 Control unit 24 Internal state holding circuit 25 Path unit 41 Source program 42 Setting data 50 D latch 51 AND circuit 52 OR circuit 53 NOT circuit 54 clock signal 55 clock signal control circuit 56 control circuit 57 control register 60 shift register

Claims (7)

A memory composed of a plurality of storage area stages,
A gate terminal, an input terminal, and an output terminal; when the clock signal input from the gate terminal is at a high level, the data input from the input terminal is output as it is from the output terminal; A high latch that shuts off data input from the input terminal when the input clock signal is at a low level, holds data that has been input until then, and outputs the data that is held from the output terminal;
A gate terminal, an input terminal, and an output terminal are provided, and when the clock signal input from the gate terminal is at a high level, the data input from the input terminal is blocked, and the data input until then is retained. A low latch that outputs the held data from the output terminal and outputs the data input from the input terminal as it is from the output terminal when the clock signal input from the gate terminal is at a low level; Prepared,
The plurality of storage area stages are composed of the high latch and the low latch that are alternately connected,
A clock signal output unit that repeatedly outputs a high level clock signal and a low level clock signal at a predetermined period;
A clock signal controller for outputting a control signal for controlling the clock signal;
A plurality of logic circuits that are connected to the gate terminals of the high latch and the low latch, respectively, input the clock signal and the control signal, perform a predetermined operation, and output an operation result to the gate terminal;
A memory comprising:   A shift register having the memory configuration according to claim 1. The plurality of logic circuits include an AND circuit and an OR circuit,
The logic circuit whose output is connected to the gate terminal of the high latch is an AND circuit,
The logic circuit whose output is connected to the gate terminal of the low latch is an OR circuit,
The shift register according to claim 2, wherein the clock signal control unit inverts the control signal and inputs the inverted control signal to the OR circuit. The clock signal control unit includes a plurality of output units corresponding to the high latch and the low latch,
4. The shift register according to claim 2, wherein each of the output units outputs a specific control signal for controlling the high latches or the low latches in an output cycle that is ½ of the predetermined cycle. 5. . Each of the output units outputs the specific control signal at a high level at a timing when data is input to the corresponding high latch or the low latch, and the low level at a timing at which data is held in the corresponding high latch or the low latch. The shift register according to claim 3 or 4, wherein a specific control signal is output. A shift register according to any one of claims 2 to 5,
A control unit;
A circuit that dynamically changes the circuit configuration based on the control of the control unit and performs an operation according to the circuit configuration;
With
The integrated circuit, wherein the control unit and the circuit use the shift register as a storage area. An integrated circuit according to claim 6;
A program storage unit for storing a program to be executed by the integrated circuit;
A processing apparatus comprising: