JP2003122561A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device capable of reducing power consumption. SOLUTION: This information processing device comprises a D0 resistor 101 and a D1 resistor 102 having one input and two outputs. One data of two outputs is read by a data line X, the other data is read by a data line Y, and the read data is calculated by a pipeline divided by a plurality of pipeline resistors. The device further comprises a third resistor 110 for storing either of the two data read from the D0 resistor 101 and a selection circuit 108 for selecting either of the results calculated by an output from the third resistor 110 and the pipeline according to an instruction and outputting the selected results to the D1 resistor 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to an information processing device having a pipeline structure synchronized with a clock.

[0002]

2. Description of the Related Art A data path unit of a conventional information processing apparatus is shown in FIG. The data path is divided into four parts by clock-controlled flip-flops 510 to 512, and they are referred to as a decode stage, an execution stage, a memory stage, and a store stage from the top.

First, in the decoding stage, two pieces of data are read from the register file 501 and stored in the flip-flop group 510. The register file 501 shown here is composed of a plurality of registers, and has names D0 and D1, respectively.

At the execution stage, a flip-flop group 51
The two operands read from 0 are input to the arithmetic circuit 502, and the arithmetic result is stored in the flip-flop 511.

In the memory stage, the flip-flop 5
The data output from 11 is calculated by the combinational circuit 503 and stored in the flip-flop 512.

At the store stage, the flip-flop 51
The data output from 2 is stored in the register file 501 through the combination circuit 504.

A block diagram of the register file 501 is shown in FIG.

Reference numeral 601 denotes a register D0 controlled by CLK1, which receives the data line Z as an input and connects its output to the tristate buffers 603 and 604. Reference numeral 602 denotes a register D1 controlled by CLK2, which receives the data line Z as an input and connects its output to the tristate buffers 605 and 606. A tri-state buffer 603 receives the output of the register D0 as an input and outputs the output to the data line X. A tri-state buffer 604 receives the output of the register D0 as an input and outputs the output to the data line Y.
Reference numeral 605 is a tri-state buffer, which is a register D.
The output of 1 is input and the output is output to the data line X. 6
Reference numeral 06 denotes a tri-state buffer, which is a register D1.
The output of is input and the output is output to the data line Y.

Now, the register D of the register file 501
The operation of a register-to-register move instruction (hereinafter referred to as a register-to-register move instruction) that moves data from 0 to D1 is shown in FIGS.
Will be explained. At the decode stage, the value from the register D0 of 601 is read. As shown in FIG. 6, data is read from the D0 register 601, the control of the tri-state buffer 603 is activated, and the data line X
Is output to. At this time, all other tristate buffers connected to the data line X are turned off. The data read to the data line X is stored in the flip-flop 5
Stored in 10.

Next, in the execution stage, the data read from the flip-flop 510 is the arithmetic circuit 502.
And is stored in the flip-flop 511.

In the memory stage, the flip-flop 5
The data stored in 11 is read out, and the combinational circuit 50
3 and is stored in the flip-flop 512.

At the store stage, the flip-flop 5
The data stored in 12 passes through the combinational circuit 504,
It is stored in the register D1 inside the register file 501. In FIG. 6, CLK2 is activated and CLK1
Will not be activated and data will be written to the D1 register 602.

This state is shown in FIG. FIG. 7 is a pipeline diagram including decoding, execution, memory, and store stages. 701 is an inter-register move instruction (mov d
0, d1), at time 1, the register transfer instruction 701 is in the decode stage, at time 2, this instruction is in the execution stage, at time 3, in the memory stage, At time 4, it means that it is on the store stage.

Here, a register transfer instruction (mov d0 d1)
Is an instruction to move the value stored in the 601 D0 register shown in FIG. 6 to the 602 D1 register.

The instructions indicated by 702, 703 and 704 are other arbitrary instructions.

[0016]

In such a conventional information processing control device, when the register-to-register move instruction is performed, the data before the move passes through all the pipeline stages, so that the power consumption is large. It was supposed to be done.

The present invention has been made in order to solve such a problem, and provides an information processing apparatus capable of reducing power consumption.

[0018]

An information processing apparatus according to claim 1 has a first register and a second register each having one input and two outputs.
And one of the two outputs of the first register and the second register is read to the first data line,
The other is read to the second data line, and the read data is an information processing device that is arithmetically processed by a pipeline divided by a plurality of pipeline registers and read from the first register. A third register that stores one of the two data and one of the output of the third register and the result of the arithmetic processing by the pipeline are selected according to the instruction, and the selected result is stored in the second register. It is provided with a selection circuit for outputting.

According to the information processing apparatus of the first aspect, in executing the inter-register moving instruction, the data read from the general-purpose register is stored in the register, selected by the selection circuit, and input to the general-purpose register. The pipeline operation can be stopped except for the cycle of reading from the register and writing to the general-purpose register. That is, in the register-to-register transfer instruction, the stages after the execution stage are not operated, so that it is possible to provide an information processing device with low power consumption.

The information processing apparatus according to claim 2 has one input and two inputs.
It has a first register and a second register with an output, and one of the two outputs of the first register and the second register is read to the first data line and the other is the second data line. Is an information processing device that is arithmetically processed by a pipeline divided by a plurality of pipeline registers, and stores one of the two data read from the first register. A third register for storing, a selection circuit for selecting one of the output of the third register and the result of operation processing by the pipeline according to the instruction, and outputting the selection result to the second register, And a tristate circuit capable of outputting the output of the register 3 to at least one of the first bus and the second bus.

According to the information processing apparatus of the second aspect, in addition to the same effect as the first aspect, even if the instruction following the inter-register moving instruction has an instruction to read the second register, the operation is performed. There is no problem.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram of a general-purpose register file according to a first embodiment of the present invention. For example, the general-purpose register is composed of a plurality of 1-input / 2-output registers, but here, for simplification, the case of two general-purpose register files will be described.

Reference numeral 101 denotes a register D0 controlled by CLK1, which receives the output of the selection circuit 107 and connects the output to the tristate buffers 103 and 104.

Reference numeral 102 is a register D1 controlled by CLK2, which receives the output of the selection circuit 108 as an input and connects the output to the tristate buffers 105 and 106.

A tri-state buffer 103 receives the output of the D0 register 101 as an input and outputs the output to the data line X which is a bus, for example.

A tri-state buffer 104 receives the output of the D0 register 101 as an input and outputs the output to, for example, a data line Y which is a bus.

Reference numeral 105 denotes a tri-state buffer which receives the output of the D1 register 102 as an input and outputs the output to the data line X.

Reference numeral 106 denotes a tri-state buffer which receives the output of the D1 register 102 as an input and outputs the output to the data line Y.

Reference numeral 107 denotes a 2-input selection circuit, which selects the output of the register 110 and the data line Z and outputs the selection result to the input of the D0 register 101.

Reference numeral 108 denotes a 2-input selection circuit which selects the output of the register 110 and the data line Z and outputs the selection result to the input of the D1 register 102.

Reference numeral 110 denotes a register, which receives the data line X as an input and outputs the output to the selection circuits 107 and 108.

FIG. 2 is a timing chart when an instruction is operated by the hardware configuration shown in FIG. 5 using the register shown in FIG. 1 of the present invention.

The pipeline is divided into four stages of decoding, execution, memory and store.

Reference numeral 201 denotes an inter-register movement instruction (mov d0, d
The operation in each pipeline stage of 1) is shown. Time 2
The inter-register move instruction is in the decode stage, at time 3, this inter-register move instruction is in the execution stage, at time 4, this inter-register move instruction is in the memory stage, and at time 5, this register The move instruction is on the store stage.

202, 203, and 204 are three instructions following the register-to-register movement instruction 201.

The operation of executing the register-to-register move instruction using the general-purpose register configured as shown in FIG. 1 will be described with reference to FIGS. 1, 2 and 5. The register file 501 shown in FIG. 5 is assumed to replace the register file 120 shown in FIG. 1 here.

First, a register transfer instruction (mov d0, d1)
Consider the case where there is no instruction for reading the D1 register 102 in the following three instructions (202, 203, 204).

The register transfer instruction (mov d0, d1) is D0.
This is an instruction to read the value of the register 101 and write it to the D1 register 102.

At time 2 in FIG. 2, it is assumed that this instruction is in the decode stage. At this time, data is read from the D0 register 101 shown in FIG. 1, the tri-state buffer 103 is activated, and the value of the D0 register 101 is output to the data line X. And in the next cycle D0
The value of the register 101 is stored in the register 110.

At subsequent time points 3 and 4, the inter-register movement instruction 201 in FIG. 2 shifts to execution and memory stage operation, but the registers 510 and 511 in FIG. 5 are not operated and the previous values are held. Leave. Therefore,
The register-to-register move instruction is not operated in the execution or memory stage.

At subsequent time 5, the register 512 in FIG. 5 does not operate, and the data stored in the register 110 (data read from the D0 register 101 at time 2) is passed through the selector, that is, the selection circuit 108. , D1 register 102.

As shown in FIG. 2, when the inter-register transfer instruction 201 is in the decode stage (time 5),
At the same time, the assembler instruction is arranged so that the storage destination register for storing the execution result of the instruction in the store stage does not become the D1 register 102. At this time, the instruction in the store stage has the storage destination register D
Since it is designated to other than the 1 register 102, the data does not collide when stored.

As described above, when the value of the D1 register 102 is not used as the source for the three instructions 202 to 204 following the register movement instruction, the register movement instruction (mov d0, d1) is used according to the present invention. Of the execution, memory, and store stage registers 5 in FIG.
The register-to-register move instruction can be executed without disturbing the pipeline without operating 10, 511 and 512.

Since the registers 510, 511 and 512 are not operated, the arithmetic circuit 502 and the combinational circuits 503 and 504 existing between them are not operated, so that there is no charge / discharge of electric charges and low power consumption can be achieved.

However, the register move instruction (mov
In the subsequent three instructions of d0, d1), the D1 register 102
If there is an instruction to read, the following three instructions cannot execute the data code stage until the register move instruction (mov d0, d1) completes the store stage, so pipeline stall occurs and performance is degraded. Will be deteriorated.

(Second Embodiment) FIG. 3 is a block diagram of a general-purpose register file according to a second embodiment of the present invention. Here, for simplification, as in the first embodiment,
The case of two general-purpose register files 320 will be described.

FIG. 3 has a configuration in which tristate buffers 312 and 313 are added to FIG.

The tri-state buffer 312 receives the output of the register 110 and connects the output to the data line X. Also, tri-state buffer 3
13 has a configuration in which the output of the register 110 is input and the output is connected to the data line Y.

FIG. 4 is a timing chart when an instruction is operated with the hardware configuration shown in FIG. 5 using the register file 320 shown in FIG. 3 of the present invention.

The pipeline is divided into four stages of decoding, execution, memory and store.

Reference numeral 401 denotes an inter-register move instruction (mov d0, d
The operation in each pipeline stage of 1) is shown. Time 2
The inter-register move instruction is in the decode stage, at time 3, this inter-register move instruction is in the execution stage, at time 4, this inter-register move instruction is in the memory stage, and at time 5, this register The move instruction is on the store stage.

Reference numerals 402, 403, and 404 are the three instructions following the register movement instruction 401.

First, a register transfer instruction (mov d0, d1)
Consider the case where there is no instruction for reading the D1 register 102 in the following three instructions (402, 403, 404).

At this time, as described above, in each stage of execution, memory and store, the register 510,
Since register-to-register move instructions can be executed without disturbing the pipeline without operating 511 and 512, it is possible to reduce power consumption without lowering performance.

Next, a register transfer instruction (mov d0, d1)
Consider a case where an instruction for reading the D1 register 102 exists in the following three instructions (402, 403, 404).

For example, as indicated by 402 in FIG. 4, D is immediately (402) immediately after the register moving instruction (mov d0, d1).
Consider a case where there is an instruction (hereinafter, referred to as a D1 operation instruction) for reading and operating the 1 register 102.

At time 2 shown in FIG. 4, it is assumed that the register move instruction 401 has not entered the decode stage and the subsequent D1 operation instruction has not entered the pipeline stage.

At time 2, the register transfer instruction 4
01 reads data from the D0 register 101, activates the tri-state buffer 103, outputs the data to the data line X, and stores the value of the D0 register 101 in the register 110.

At subsequent time 3, the register movement instruction 401 advances to the execution stage, and the D1 operation instruction 402 advances to the decode stage.

At this time, the D1 operation instruction 402 controls to read the value of the register 110. This is because the value of the D1 register 102 used is the value of the D0 register 101 stored by the instruction 401. Therefore, the value of the D1 register 102 read by the instruction 402 needs to read the value of the register 110. That is, the value stored in the register 110 is output to the data line X or Y through the tri-state buffer 312 or 313.

On the other hand, the instruction 401 that has proceeded to the execution stage at time 3 does not operate the register 510, so that the execution stage does not consume power.

At the subsequent time 4, the register transfer instruction 401 and the D1 operation instruction 402 move to the memory and execution stages, respectively.

Regarding the inter-register transfer instruction 401, the register 511 does not operate, and the previous value is held and does not operate. On the other hand, the D1 operation instruction 402 is the register 5
10 is operated and the operation is executed in the execution stage.

At subsequent time 5, instructions 401 and 402
Moves to the store stage and the memory stage, respectively.

In the instruction 401, the register 512 does not operate, and the data stored in the register 110 is
It is stored in the D1 register 102 via the selector 108. On the other hand, the instruction 402 is in the memory stage, and the register 511 operates to perform the processing.

Thus, the register move instruction (mov d
0, d1) Even if the instruction 402 to read and operate the D1 register 102 is arranged in the instruction subsequent to 401, the instruction 40
Since the registers 510, 511, and 512 of the execution, memory, and store stages do not operate in the pipeline progress of No. 1, power consumption can be suppressed. In addition, the subsequent D1
Even if there is an instruction 402 for reading and operating the register 102, the pipeline is not disturbed, and the pipeline operation can be performed without degrading the performance.

In this embodiment, the instruction 402 for reading and operating the D1 register 102 is arranged immediately after the register moving instruction 401, but the instruction 402 does not hinder the operation even if it is arranged thereafter.

In the present embodiment, the register move instruction (mov d0, d1) has been described, but the power consumption can be reduced similarly in the instruction such as mov imm, d1 for storing an immediate value in the register. It is possible to plan.

[0069]

According to the information processing apparatus of claim 1,
When executing the register-to-register move instruction, the data read from the general-purpose register is stored in the register, selected by the selection circuit, and input to the general-purpose register. Therefore, except the cycle of reading from the general-purpose register and writing to the general-purpose register. ,
The operation of the pipeline can be stopped. That is, in the register-to-register transfer instruction, the stages after the execution stage are not operated, so that it is possible to provide an information processing device with low power consumption.

According to the information processing apparatus of the second aspect, in addition to the same effect as that of the first aspect, even when the instruction following the inter-register movement instruction has an instruction to read the second register, the operation is performed. There is no problem.

[Brief description of drawings]

FIG. 1 is a block diagram of a general-purpose register according to a first embodiment of this invention.

FIG. 2 is a pipeline chart diagram when FIG. 1 is used.

FIG. 3 is a block diagram of a general-purpose register according to a second embodiment of the present invention.

FIG. 4 is a pipeline chart diagram when FIG. 3 is used.

FIG. 5 is a block diagram of a data path.

FIG. 6 is a block diagram of a conventional general-purpose register.

FIG. 7 is a pipeline chart diagram when FIG. 6 is used.

[Explanation of symbols]

101, 102, 110 registers 103, 104, 105, 106 tri-state buffers 107, 108 selection circuits 312, 313 tri-state buffers 501 register files 510, 511, 512 registers 502 arithmetic circuits 503, 504 combinational circuits

Claims (2)

[Claims] 1. A first register and a second register having one input and two outputs, wherein one of the two outputs of the first register and the second register is read to a first data line. Is output and the other is read to the second data line, and the read data is an information processing device that is arithmetically processed by a pipeline divided by a plurality of pipeline registers. A third register that stores one of the two read data, and one of the output of the third register and the result of the arithmetic processing by the pipeline are selected according to the instruction,
An information processing apparatus comprising a selection circuit that outputs a selection result to the second register. 2. A first register and a second register having one input and two outputs, wherein one of the two outputs of the first register and the second register is read to a first data line. Is output and the other is read to the second data line, and the read data is an information processing device that is arithmetically processed by a pipeline divided by a plurality of pipeline registers. A third register that stores one of the two read data, and one of the output of the third register and the result of the arithmetic processing by the pipeline are selected according to the instruction,
Information processing including a selection circuit that outputs a selection result to the second register, and a tri-state circuit that can output the output of the third register to at least one of the first bus and the second bus apparatus.