JP2009145830A - Image signal processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time, after the start of horizontal synchronization, until the starting of displaying of OSD information. <P>SOLUTION: The problem to be solved is solved, by providing a video register 14 for storing a vertical position contained in on-screen display information and for specifying the horizontal line of staring the display of the on-screen display information; a video memory (VRAM) 12 for storing a display content contained in the on-screen display information; and a memory controller 16 for reading out collectively the vertical positions stored in the video register 14, for retrieving the propriety of consistency with the horizontal line, serving as a current display object and for reading out the display content corresponding to the vertical position from the video memory 12, when there is a consistent vertical position. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a video signal processing apparatus that displays a character superimposed on a video such as a television broadcast.

  Character information is superimposed on video signals such as television broadcasts, and characters based on the caption information are superimposed on an image displayed based on the video signals, or a graphic screen based on graphic information is superimposed. An on-screen display (OSD) process for displaying is generally performed.

  Caption information in closed captions is superimposed on a predetermined horizontal line of a television broadcast video signal. For example, caption information is superimposed on the 21st line (21H) as a 16-bit NRZ signal. A horizontal line on which caption information is superimposed includes a horizontal synchronization signal Hsync, a color burst Cb, a clock run-in signal CRI, a start bit STB, and actual caption information CAP in this order. The actual caption information CAP includes a character code representing a character to be displayed following a caption mode (POPON, PAINTON, ROLLUP), a code indicating a text mode, a control code portion indicating a display position address, a display color, and the like. In addition to this, a control code such as memory control indicating the start / end of display may be included as necessary. In the closed caption, the character image corresponding to each character code is relatively small image data of about 8 × 8 (or 16 × 16).

  On the other hand, in the case of graphic display, graphic image data is associated with a character code for processing. The image corresponding to each character code in the graphic display is relatively large image data such as 32 × 32 in length. Image data associated with the character code for graphic display is also stored in the image memory, and is read from the processing unit and used during graphic display processing.

  In such character display processing, display on / off for each horizontal line, vertical position (display start horizontal line) at which display is started, and display contents are as shown in FIG. (VRAM). The video signal processing device detects the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync of the video signal, and after detecting the vertical synchronization signal Vsync, counts the number of times the horizontal synchronization signal Hsync is received, and becomes the current display target. When the displayed horizontal line coincides with the vertical position of the information stored in the VRAM 12 and the content is turned on, the display content is displayed as the OSD.

  In the above process, it is determined whether or not the OSD information needs to be displayed on the horizontal line after detection of the horizontal synchronization signal Hsync. At this time, it is necessary to read out information on all the vertical positions and check whether or not the information matches the horizontal line currently being displayed. The display of OSD information cannot be started until this search process is completed. However, since the information related to the OSD is stored in the VRAM, the vertical position information is sequentially read for each bus width of the memory as a characteristic of the memory, and it is determined whether or not it matches the horizontal line currently being displayed. There is a problem that it takes time to start displaying OSD information.

  In particular, with the recent increase in the operating frequency of displays, it is desired to shorten the time from the detection of the horizontal synchronization signal Hsync to the start of OSD information display.

  In view of the above problems, an object of the present invention is to provide a video signal processing apparatus that can shorten the time from horizontal synchronization to the start of display of OSD information.

  The present invention relates to a video signal processing apparatus that performs processing for superimposing and displaying image data based on on-screen display information on a video reproduced from a video signal, the video signal processing device being included in the on-screen display information, and the on-screen display A video register for storing a vertical position for specifying a horizontal line to start displaying information, a video memory for storing display contents included in the on-screen display information, and a vertical position stored in the video register. A memory controller that reads in a batch, searches for a match with a horizontal line currently being displayed, and reads a display content corresponding to the vertical position from the video memory when a matching vertical position exists; It is characterized by providing.

  Here, it is preferable that the video register is capable of reading the vertical position all at once in one cycle of the system clock.

  The video register is included in the on-screen display information, and further stores display on / off information indicating whether to display the on-screen display information. The memory controller is stored in the video register. When the display ON / OFF information is read together with the current vertical position, and it is searched whether the read vertical position matches the horizontal line currently being displayed, and there is a matching vertical position When the display on / off information corresponding to the vertical position is to be displayed, it is preferable to read the display content corresponding to the vertical position from the video memory.

  According to the present invention, the time from the horizontal synchronization to the start of OSD information display can be shortened.

  As shown in FIG. 1, a video signal processing apparatus according to an embodiment of the present invention includes a main processing unit (CPU) 10, a video memory (VRAM) 12, a video register 14, a memory controller 16, an image memory (CGRAM) 18, A CGRAM controller 20, a color data memory (CLUTRAM) 22, a CLUTRAM controller 24, and a video data generator 26 are configured.

  The CGRAM 18 is a memory that stores and holds image data in a memory space associated with the character information of caption information and graphic information. In the case of closed captioning, bit information of 8 × 8 (or 16 × 16) image data is stored and held in a memory space associated with each character code. In the case of graphic information, bit information of image data of 32 × 32 is stored and held in a memory space associated with each character code.

  The CLUTRAM 22 is a memory that stores and holds data relating to display colors of caption information and graphic information. In the present embodiment, a color code is assigned to each display color, and the CLUTRAM 22 stores data indicating the display color in a memory space assigned to each color code.

  The video signal processing device uses these CGRAM 18 and CLUTRAM 22 to generate a video signal for displaying caption information and graphic information on a display.

  The main processing unit 10 has a function of integrally controlling each unit of a video signal processing apparatus such as a processing unit that processes a video signal such as a television broadcast. The main processing unit 10 performs processing for accessing the CGRAM 18 and the CLUTRAM 22 and updating the image data and color data stored and stored in the CGRAM 18 and the CLUTRAM 22 in accordance with input of image data and color data from the outside.

  When the main processing unit 10 receives caption information extracted from the video signal and graphic information for on-screen display, the main processing unit 10 analyzes the information and stores it in the VRAM 12 and the video register 14.

  Caption information includes caption mode (POPON, PAINTON, ROLLUP), code indicating text mode, display position address (vertical position (display start horizontal line) and horizontal display position or horizontal display interval at which display is started), and display color A character code representing a character to be displayed is included following the control code portion representing the above.

  When the main processing unit 10 receives the caption information extracted from the video signal extraction unit, the main processing unit 10 analyzes the caption information to display a caption mode, a code indicating a text mode, a display position address, a display color, and a character code representing a character to be displayed. Ask for. As shown in FIG. 2, the main processing unit 10 stores display on / off information and a vertical position at which display is started in the video register 14. Further, as shown in FIG. 3, the main processing unit 10 displays the display size, the horizontal display position, or the horizontal display interval in the memory space of the VRAM 12 corresponding to the address of each display position in a format corresponding to the caption mode and the text mode. The character code representing the character to be displayed and the data indicating the display color are written.

  Graphic information is processed similarly. The graphic information includes at least a display position address (vertical position (display start horizontal line) and horizontal display position or horizontal display interval at which display is started), a control code representing a display color, and a character code representing a character to be displayed. Composed. The character code of the graphic information is generally standardized similarly to the caption information. The image corresponding to each character code in the graphic display is relatively large image data such as 32 × 32 in length.

  When the main processing unit 10 receives the graphic information extracted from the video signal extraction unit, the main processing unit 10 analyzes the graphic information to obtain a display position address, a display color, and a character code representing a character to be displayed. Similar to the caption information, the main processing unit 10 stores the display on / off information and the vertical position at which the display is started in the video register 14, as shown in FIG. Further, as shown in FIG. 3, the main processing unit 10 displays a display size, a horizontal display position or a horizontal display interval, a character code representing a character to be displayed, and its display in the memory space of the VRAM 12 corresponding to the address of each display position. Write color data.

  The VRAM 12 is a memory that holds the contents displayed on the display. The VRAM 12 is a so-called text VRAM, and stores and holds data indicating a display size, a horizontal display position or a horizontal display interval, a character code representing a character to be displayed, and a display color thereof. When the VRAM 12 receives the display size, the horizontal display position or horizontal display interval, the character code representing the character to be displayed, and the data indicating the display color from the main processing unit 10, the VRAM 12 memory space corresponding to the address of the display position The information is stored and held in The VRAM 12 can be read and written in synchronization with the system clock of the video signal processing apparatus, and can access data having a capacity corresponding to the bus width of the data bus every cycle of the system clock.

  The video register 14 stores caption information and graphic information on / off information and a vertical position (display start horizontal line) at which display is started. The video register 14 can be read and written in synchronization with the system clock of the video signal processing apparatus, and can read all data held at every cycle of the system clock at a time.

  The memory controller 16 receives a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync of a video signal from an external synchronization signal detection unit (not shown), and synchronizes with the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync, The image information stored in the VRAM 12 is read and output to each part of the video signal processing apparatus.

  Specifically, when the vertical synchronization signal Vsync is received, the built-in counter is reset, and then the number of times the horizontal synchronization signal Hsync is received is counted using the built-in counter. When the horizontal synchronization signal Hsync is received, the video register 14 is accessed, the caption information and graphic information display on / off information stored in the video register 14 and the vertical position at which display is started are read, and the display is set to on. It is searched whether or not there is data that matches the count value of the horizontal line that is the current display target and the vertical position at which display is started. If the display is set to ON and there is data that matches the current horizontal line count value and the vertical position where the display starts, the display size, horizontal display position or horizontal display interval, display A character code representing the character to be displayed and data indicating its display color are extracted from the VRAM 12.

  In the present embodiment, as shown in FIG. 4, display on / off information and the vertical position at which display is started are stored and held in a video register 14 that can be read out in one cycle, so that display from the video register 14 can be performed. Since comparison processing can be performed by reading on / off information and a vertical position at which display is started, processing for checking whether or not there is OSD information to be displayed on a horizontal line that is currently displayed is conventionally performed. Can also be performed quickly. As a result, it is possible to shorten the time to start displaying the OSD information after the horizontal synchronization.

  The memory controller 16 transfers the display size and display position address (horizontal display position or horizontal display interval) to the video data generation unit 26. Further, the character code and its display color are output to the CGRAM controller 20.

  The CGRAM controller 20 receives a character code to be displayed from the memory controller 16, accesses the memory space of the CGRAM 18 corresponding to the character code, reads image data corresponding to the character code, and sends it to the video data generation unit 26. Output. Further, the CGRAM controller 20 further transfers the color code indicating the display color of the character to be displayed transferred from the memory controller 16 to the CLUTRAM controller 24.

  The CLUTRAM controller 24 receives the color code indicating the display color of the character transferred from the CGRAM controller 20, reads out the color data of the display color corresponding to the color code from the CLUTRAM 22, and outputs it to the video data generation unit 26. The color data is, for example, the intensity of each color of red (R), green (G), and blue (B) corresponding to the color code.

  The video data generation unit 26 displays the display size output from the memory controller 16, the display position address (horizontal display position or horizontal display interval), the image data of the display target character output from the CGRAM controller 20, and the CLUTRAM. The color data of the character to be displayed output from the controller 24 is received, and a video signal for actual display on the display is generated based on the information.

  Based on the character image data received from the CGRAM controller 20 and the character color data received from the CLUTRAM controller 24, the video data generation unit 26 displays the character at a position in the display screen corresponding to the display position address. A video signal is generated so as to be displayed in the display color of the color code. This video signal generation processing can be performed in the same manner as existing processing.

It is a block diagram which shows the structure of the video signal processing apparatus in embodiment of this invention. It is a figure which shows the memory content of the video register in embodiment of this invention. It is a figure which shows the memory content of VRAM in embodiment of this invention. It is a timing chart explaining the process of the video signal processing apparatus in the embodiment of the present invention. It is a figure which shows the memory content of the conventional VRAM.

Explanation of symbols

  10 main processing unit, 12 video memory (VRAM), 14 video register, 16 memory controller, 18 image memory (CGRAM), 20 CGRAM controller, 22 color data memory (CLUTRAM), 24 CLUTRAM controller, 26 video data generating unit.

Claims (3)

A video signal processing apparatus that performs processing for displaying image data based on on-screen display information superimposed on video reproduced from a video signal,
A video register that is included in the on-screen display information and stores a vertical position for specifying a horizontal line to start displaying the on-screen display information;
A video memory for storing display contents included in the on-screen display information;
Read the vertical position stored in the video register at a time, search whether it matches the horizontal line that is currently displayed,
A memory controller that reads display content corresponding to the vertical position from the video memory when a matching vertical position exists;
A video signal processing apparatus comprising: The video signal processing apparatus according to claim 1,
The video signal processing apparatus according to claim 1, wherein the video register is capable of reading the vertical position all at once in one cycle of a system clock. The video signal processing apparatus according to claim 1 or 2,
The video register further includes display on / off information included in the on-screen display information and indicating whether to display the on-screen display information.
The memory controller collectively reads display on / off information together with the vertical position stored in the video register,
A search is performed as to whether or not the read vertical position matches the horizontal line currently being displayed, and when there is a matching vertical position, display on / off information corresponding to the vertical position is displayed. The video signal processing apparatus reads out the display content corresponding to the vertical position from the video memory.

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