JP2009141256A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2009141256A
JP2009141256A JP2007318471A JP2007318471A JP2009141256A JP 2009141256 A JP2009141256 A JP 2009141256A JP 2007318471 A JP2007318471 A JP 2007318471A JP 2007318471 A JP2007318471 A JP 2007318471A JP 2009141256 A JP2009141256 A JP 2009141256A
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Prior art keywords
pad
semiconductor device
holding portion
voltage holding
semiconductor
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JP2007318471A
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Japanese (ja)
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Hirosuke Baba
浩佐 馬場
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Toyota Motor Corp
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Toyota Motor Corp
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Priority to JP2007318471A priority Critical patent/JP2009141256A/en
Priority to PCT/JP2008/070287 priority patent/WO2009075149A1/en
Publication of JP2009141256A publication Critical patent/JP2009141256A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for expanding an active region for manufacturing necessary semiconductor structure, in which a semiconductor device functions. <P>SOLUTION: In a semiconductor device 2, at least part of a pad 12 formed on the surface is formed at a breakdown voltage holding unit 65 arranged around the interior of the perimeter of the surface of a semiconductor substrate 4. In conventional technology, at least part of the pad 12 formed on the inner side of the breakdown voltage holding unit 65 is formed on the breakdown voltage holding unit 65, so an area of a pad region 10 on the inner side the breakdown voltage holding unit 65 can be reduced. In this way, an active region 8 for manufacturing necessary semiconductor structure, in which the semiconductor device 2 functions inside the breakdown voltage holding unit 65, can be enlarged. By forming laminated structure 20, which contains a conductive film, between the pad 12 and the breakdown voltage holding unit 65, a local electric field cannot be applied to the breakdown voltage holding unit 65, so a deterioration in holding property of the semiconductor device 2 can be prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、導電性ワイヤを接続固定するパッドが表面に形成されている半導体装置に関する。   The present invention relates to a semiconductor device in which pads for connecting and fixing conductive wires are formed on the surface.

半導体装置と外部回路、あるいは半導体装置と他の半導体装置を電気的に接続するために、ワイヤボンディング方法が知られている。ワイヤボンディング方法では、半導体装置の表面にパッドを形成しておく。ワイヤボンディング方法では、一端が外部回路等に接続固定されている導電性ワイヤを半導体装置のパッド上にまで引き伸ばし、その導電性ワイヤをパッドに接続固定し、パッドに接続固定した導電性ワイヤをパッド上で切断する。
半導体装置は半導体基板を備えており、半導体基板内に複数の半導体領域が形成されている。複数の半導体領域を組み合わせることによって半導体素子が構成されている。前記パッドは、半導体素子を構成する少なくとも一つの半導体領域に導通している。 A wire bonding method is known for electrically connecting a semiconductor device and an external circuit, or a semiconductor device and another semiconductor device. In the wire bonding method, pads are formed on the surface of a semiconductor device. In the wire bonding method, a conductive wire whose one end is connected and fixed to an external circuit or the like is extended onto the pad of the semiconductor device, the conductive wire is connected and fixed to the pad, and the conductive wire connected and fixed to the pad is padded. Cut above.
The semiconductor device includes a semiconductor substrate, and a plurality of semiconductor regions are formed in the semiconductor substrate. A semiconductor element is formed by combining a plurality of semiconductor regions. The pad is electrically connected to at least one semiconductor region constituting the semiconductor element.

種々のパッドを必要とする半導体装置が存在する。例えば電力制御用の半導体装置の場合、制御する電流が流れる導電性ワイヤを接続固定する少なくとも１つの電力用パッドと、半導体装置のオン・オフを切り換える信号を伝える導電性ワイヤを接続固定する小信号パッドを必要とする。小信号パッドにはこの他に、半導体装置を流れている電流量に対応する信号を伝える導電性ワイヤをボンディングするパッドや、半導体装置の温度に対応する信号を伝える導電性ワイヤをボンディングするパッドが存在することもある。   There are semiconductor devices that require various pads. For example, in the case of a semiconductor device for power control, a small signal for connecting and fixing at least one power pad for connecting and fixing a conductive wire through which a current to be controlled flows and a conductive wire for transmitting a signal for switching on and off of the semiconductor device Requires a pad. In addition to this, the small signal pad includes a pad for bonding a conductive wire for transmitting a signal corresponding to the amount of current flowing through the semiconductor device, and a pad for bonding a conductive wire for transmitting a signal corresponding to the temperature of the semiconductor device. May exist.

高耐圧半導体装置の場合、半導体基板の終端領域に電界が集中しやすく、それが原因となって半導体装置の耐圧能力が低下することが知られている。この問題に対処するために半導体基板の表面の外周に沿って外周の内側を一巡するＦＬＲ（Field Limiting Ring）あるいはリサーフ構造等が形成されている耐圧保持部を設ける技術が知られている。
半導体装置の表面に、導電性ワイヤを接続固定するパッドと、耐圧保持部が設けられている半導体装置が特許文献１，２に開示されている。 In the case of a high breakdown voltage semiconductor device, it is known that the electric field tends to concentrate on the termination region of the semiconductor substrate, which causes the breakdown voltage capability of the semiconductor device to decrease. In order to deal with this problem, a technique is known in which a breakdown voltage holding portion in which an FLR (Field Limiting Ring) or a RESURF structure or the like that makes a round around the outer periphery of the surface of the semiconductor substrate is formed.
Patent Documents 1 and 2 disclose a semiconductor device in which a pad for connecting and fixing a conductive wire and a withstand voltage holding portion are provided on the surface of the semiconductor device.

特開２００４−１５８６０３号公報JP 2004-158603 A 特開平８−３０６９３７号公報JP-A-8-306937

耐圧保持部を利用して耐圧能力を向上させている半導体装置では、耐圧保持部の内側に半導体装置が機能するのに必要な半導体領域の組合せ構造(半導体構造)を収容しなければならない。
また、耐圧保持部を利用して耐圧能力を向上させている半導体装置では、半導体素子を構成する半導体領域に導通しているパッドを、耐圧保持部の内側の領域に形成しなければならない。 In a semiconductor device in which the withstand voltage capability is improved by using the withstand voltage holding portion, a combination structure (semiconductor structure) of semiconductor regions necessary for the functioning of the semiconductor device must be accommodated inside the withstand voltage holding portion.
Further, in a semiconductor device in which the withstand voltage capability is improved by using the withstand voltage holding portion, a pad that is electrically connected to the semiconductor region that constitutes the semiconductor element must be formed in a region inside the withstand voltage holding portion.

パッドの下方に位置する半導体基板には、半導体素子を構成する半導体領域群の組合せ構造を製造できないことが多い。パッドに印加する電圧によって半導体素子の動作が不安定になることを避ける必要があったり、あるいはパッドに現れる電圧が予定外に変動することを避けるためにパッドの下方に厚い酸化膜を形成する必要があったりする。厚い酸化膜を形成する範囲には、半導体構造を製造できないことが多い。従って、パッドが大型であるほど、半導体素子を構成する半導体構造を作り込める有効領域が縮小する。   In many cases, it is not possible to manufacture a combination structure of semiconductor region groups constituting a semiconductor element on a semiconductor substrate located below a pad. It is necessary to avoid the unstable operation of the semiconductor element due to the voltage applied to the pad, or to form a thick oxide film below the pad in order to prevent the voltage appearing on the pad from fluctuating unexpectedly. There is. In many cases, a semiconductor structure cannot be manufactured in a range where a thick oxide film is formed. Therefore, the larger the pad, the smaller the effective area in which the semiconductor structure constituting the semiconductor element can be made.

導電性ワイヤを接続固定するだけであれば小型のパッドで足りるのに対し、パッドに接続固定した導電性ワイヤの延長部をパッド上で切断する場合には、それ以上に大きなパッドを必要とする。パッド上で導電性ワイヤを切断する場合には、パッドに接続固定されている導電性ワイヤを工具によってパッドに押し付け、その状態で導電性ワイヤの延長部を引っ張ることによって切断する。その為、導電性ワイヤを切断する際に、半導体装置の表面に引き摺り痕がついてしまう。半導体装置の表面を覆っている保護膜の表面に引き摺り痕が形成されて保護膜が損傷することを避ける必要がある。引き摺り痕によって保護膜の表面が損傷することを避けるためには、引き摺り痕の形成範囲にまで広がっているパッドを必要とする。パッドに引き摺り痕形成領域を確保する必要があることからパッドが大型化してしまう。パッドを小型化するのは難しい。
耐圧保持部を利用して耐圧能力を向上させている半導体装置では、耐圧保持部の内側にパッドを形成する必要があるところ、そのパッドを小型化するのが困難であることから、半導体素子を構成する半導体構造を作り込める有効領域が縮小してしまう。 A small pad is sufficient if only the conductive wire is connected and fixed, but a larger pad is required to cut the extension of the conductive wire connected and fixed to the pad on the pad. . When cutting the conductive wire on the pad, the conductive wire connected and fixed to the pad is pressed against the pad with a tool, and the conductive wire is cut by pulling the extension of the conductive wire in that state. Therefore, when the conductive wire is cut, a drag mark is left on the surface of the semiconductor device. It is necessary to prevent the protective film from being damaged due to drag marks formed on the surface of the protective film covering the surface of the semiconductor device. In order to prevent the surface of the protective film from being damaged by the drag mark, a pad that extends to the range in which the drag mark is formed is required. Since it is necessary to secure a dragging mark formation region on the pad, the pad is enlarged. It is difficult to reduce the size of the pad.
In a semiconductor device in which the withstand voltage capability is improved using the withstand voltage holding portion, it is necessary to form a pad inside the withstand voltage holding portion, and it is difficult to downsize the pad. The effective area in which the semiconductor structure to be formed can be made is reduced.

以上をまとめると、下記の事情が存在していることがわかる。
（１）半導体基板の表面の外周の内側を一巡する耐圧保持部によって耐圧能力を向上させている半導体装置の場合、半導体素子を構成する半導体領域と導通するパッドを耐圧保持部の内側に収容しなければならない。
（２）ワイヤボンディング方法では、半導体装置の保護膜の表面が損傷することを避けるために、大型のパッドが必要とされ、パッドを小型化することが難しい。
（３）耐圧保持部を利用して耐圧能力を向上させている半導体装置では、パッドの存在によって、半導体素子を構成する半導体構造を作り込める有効領域が縮小してしまう。
本発明では、耐圧保持部の内側に占めるパッドの面積を小型化し、半導体素子を構成する半導体構造を作り込める有効領域を拡大する技術を提供する。 In summary, it can be seen that the following circumstances exist.
(1) In the case of a semiconductor device in which the withstand voltage capability is improved by a withstand voltage holding portion that goes around the inside of the outer periphery of the surface of the semiconductor substrate, a pad that is connected to the semiconductor region constituting the semiconductor element is accommodated inside the withstand voltage holding portion. There must be.
(2) In the wire bonding method, a large pad is required to avoid damaging the surface of the protective film of the semiconductor device, and it is difficult to downsize the pad.
(3) In a semiconductor device in which the withstand voltage capability is improved using the withstand voltage holding portion, the presence of the pad reduces the effective area in which the semiconductor structure constituting the semiconductor element can be formed.
The present invention provides a technique for reducing the area of the pad that occupies the inside of the withstand voltage holding portion and expanding the effective region in which the semiconductor structure constituting the semiconductor element can be formed.

従来の技術では、耐圧保持部によって耐圧能力を向上させている半導体装置の場合、耐圧保持部の内側に形成されている半導体構造を構成する半導体領域に導通するパッドを耐圧保持部の内側の領域に留めなければならなかった。
本発明者は、パッドのうち、半導体構造を構成する半導体領域に導通する部分については耐圧保持部の内側の領域に形成しなければならないものの、保護膜が損傷することを避けるための摺り痕形成領域については、耐圧保持部上あるいはその外側に形成できることに着目した。
もっとも、不用意に耐圧保持部上にパッドを伸ばすと、パッドの電圧が耐圧保持構造に影響し、耐圧能力が低下してしまう。本発明者は、パッドの電圧が耐圧保持部の特性に影響しないようする技術を活用することによって、耐圧保持部の内側から少なくとも耐圧保持部上にまでパッドの伸ばすことに成功し、耐圧保持部の内側に占めるパッドの面積を小型化に成功した。
なお、通常は、耐圧保持部上またはその外側に摺り痕形成領域が確保される向きで導電性ワイヤを接続するが、逆方向に用いてもよい。いずれの接続方向でも、耐圧保持部の内側に占めるパッドの面積を小型化することができる。 In the conventional technology, in the case of a semiconductor device whose withstand voltage capability is improved by a withstand voltage holding part, a pad conducting to a semiconductor region constituting a semiconductor structure formed inside the withstand voltage holding part is provided in an area inside the withstand voltage holding part. Had to stay on.
The inventor of the present invention has to form a portion of the pad that is conductive to the semiconductor region constituting the semiconductor structure in a region inside the pressure-resistant holding portion, but to prevent the protective film from being damaged. It has been noted that the region can be formed on or outside the pressure holding portion.
However, if the pad is inadvertently extended on the withstand voltage holding portion, the voltage of the pad affects the withstand voltage holding structure, and the withstand voltage capability decreases. The present inventor succeeded in extending the pad from the inside of the withstand voltage holding unit to at least the withstand voltage holding unit by utilizing a technique for preventing the voltage of the pad from affecting the characteristics of the withstand voltage holding unit. The area of the pad that occupies the inside of the pad was successfully reduced.
Normally, the conductive wire is connected in such a direction that a scum mark formation region is secured on or outside the pressure-resistant holding portion, but it may be used in the opposite direction. In any connection direction, the area of the pad occupying the inside of the pressure resistant holding portion can be reduced.

本発明で創作された半導体装置は半導体基板を備えており、耐圧保持部とパッドが形成されている。耐圧保持部は、半導体基板の表面の外周の内側を一巡している。耐圧保持部よりも内側の半導体基板内には複数の半導体領域が形成されており、複数の半導体領域を組み合わせることによって半導体素子が構成されている。パッドは、耐圧保持部よりも内側から少なくとも耐圧保持部上に伸びており、半導体素子を構成する少なくとも一つの半導体領域に導通している。少なくとも耐圧保持部の半導体基板とパッド間には、半導体基板の側から第１絶縁膜と導電膜と第２絶縁膜の順に積層されている積層構造が形成されている。パッドは、その積層構造によって耐圧保持部から絶縁されている。   The semiconductor device created by the present invention includes a semiconductor substrate, and is formed with a withstand voltage holding portion and a pad. The withstand voltage holding portion makes a round inside the outer periphery of the surface of the semiconductor substrate. A plurality of semiconductor regions are formed in the semiconductor substrate inside the withstand voltage holding portion, and a semiconductor element is configured by combining the plurality of semiconductor regions. The pad extends from the inside of the withstand voltage holding part to at least the withstand voltage holding part and is electrically connected to at least one semiconductor region constituting the semiconductor element. A laminated structure in which a first insulating film, a conductive film, and a second insulating film are laminated in this order from the semiconductor substrate side is formed at least between the semiconductor substrate and the pad of the breakdown voltage holding portion. The pad is insulated from the breakdown voltage holding portion by the laminated structure.

本発明の半導体装置では、従来技術では耐圧保持部よりも内側の領域に配置されていたパッドの少なくとも一部を、耐圧保持部上に形成する。これにより、耐圧保持部よりも内側の領域に形成されるパッドの面積を縮小することができ、半導体装置が機能するのに必要な半導体構造を製造できる有効面積を拡大することができる。   In the semiconductor device of the present invention, at least a part of the pad arranged in the region inside the withstand voltage holding part in the prior art is formed on the withstand voltage holding part. Thereby, the area of the pad formed in the region inside the withstand voltage holding portion can be reduced, and the effective area where the semiconductor structure necessary for the functioning of the semiconductor device can be increased.

耐圧保持部上にパッドを形成した場合、たとえ耐圧保持部とパッドの間を絶縁しても、パッドの電圧によってパッドから発生した電界が、パッドと対向している範囲の耐圧保持部に局所的に影響してしまう。この局所的な影響によって耐圧保持部の電界分布が大きく変化すると、半導体装置の耐圧特性が悪化してしまう。
本発明の半導体装置では、耐圧保持部とパッドの間に、耐圧保持部の側から順に第１絶縁膜と導電膜と第２絶縁膜が積層されている積層構造が形成されている。すなわち、耐圧保持部とパッドの間に、耐圧保持部とパッドの双方から絶縁されている導電膜が形成されている。
本発明の半導体装置では、パッドと耐圧保持部の間に両者から絶縁されている導電膜を形成しているために、パッドから発生した電界が耐圧保持部に直接的に印加されることがなく、導電膜を介して耐圧保持部に印加される。この結果、耐圧保持部に対するパッドの電圧の影響が緩和される。耐圧特性保持部の電界分布がパッドの電圧によって大きく変化することがなく、半導体装置の耐圧特性が低下することを防ぐことができる。 When a pad is formed on the withstand voltage holding part, even if the insulation between the withstand voltage holding part and the pad is insulated, the electric field generated from the pad by the pad voltage is locally applied to the withstand voltage holding part in the range facing the pad. Will be affected. When the electric field distribution of the withstand voltage holding portion changes greatly due to this local influence, the withstand voltage characteristics of the semiconductor device deteriorate.
In the semiconductor device of the present invention, a stacked structure in which a first insulating film, a conductive film, and a second insulating film are stacked in this order from the side of the breakdown voltage holding part is formed between the breakdown voltage holding part and the pad. That is, a conductive film that is insulated from both the withstand voltage holding part and the pad is formed between the withstand voltage holding part and the pad.
In the semiconductor device of the present invention, since the conductive film insulated from both is formed between the pad and the withstand voltage holding portion, the electric field generated from the pad is not directly applied to the withstand voltage holding portion. The voltage is applied to the withstand voltage holding portion through the conductive film. As a result, the influence of the pad voltage on the withstand voltage holding portion is mitigated. The electric field distribution of the withstand voltage characteristic holding portion is not greatly changed by the voltage of the pad, and it is possible to prevent the withstand voltage characteristics of the semiconductor device from being deteriorated.

本発明の半導体装置では、導電膜がパッドよりも広く広がっていることが好ましい。すなわち、導電膜が、パッドのうちの耐圧保持部上に形成されている部分に対応する対応領域と、その対応領域から耐圧保持部上に広がっている拡大領域を備えていることが好ましい。
この場合、パッドと耐圧保持部間の相互作用がより確実に遮断される。パッドの電圧によって半導体装置の耐圧特性が低下することを確実に防ぐことができる。 In the semiconductor device of the present invention, the conductive film is preferably wider than the pad. In other words, the conductive film preferably includes a corresponding region corresponding to a portion of the pad formed on the breakdown voltage holding portion and an enlarged region extending from the corresponding region onto the breakdown voltage holding portion.
In this case, the interaction between the pad and the pressure resistant holding portion is more reliably blocked. It is possible to reliably prevent the breakdown voltage characteristics of the semiconductor device from being reduced by the pad voltage.

本発明の半導体装置では、パッドが耐圧保持部よりもさらに外側に伸びていてもよい。この場合、耐圧保持部よりも外側に位置しているパッドは半導体基板から絶縁しておく。
これにより、耐圧保持部よりも内側に形成されるパッドの面積をさらに縮小することができ、半導体装置が機能するのに必要な半導体構造を製造できる有効領域をさらに拡大することができる。 In the semiconductor device of the present invention, the pad may extend further to the outside than the breakdown voltage holding portion. In this case, the pad located outside the pressure holding part is insulated from the semiconductor substrate.
As a result, the area of the pad formed on the inner side of the breakdown voltage holding portion can be further reduced, and the effective region in which the semiconductor structure necessary for the functioning of the semiconductor device can be further expanded.

本発明の半導体装置では、パッドのうちの耐圧保持部上に形成されている部分の形状において、耐圧保持部の周方向に測定した幅が、周方向に直交する方向に測定した幅よりも広いことが好ましい。
本発明の半導体装置では、耐圧保持部が半導体基板の外周に沿って一巡している。すなわち、耐圧保持部は半導体装置の周方向に沿って広く形成されている。
そのため、耐圧保持部上に形成されているパッドの形状を、耐圧保持部の形状にあわせて周方向に沿って広く形成することによって、パッドのうちの耐圧保持部上に形成されている部分の面積を広く形成することができる。これによって、耐圧保持部よりも内側に形成されているパッドの面積をさらに縮小することができ、半導体装置が機能するのに必要な半導体構造を製造できる有効領域をさらに拡大することができる。 In the semiconductor device of the present invention, in the shape of the portion of the pad formed on the breakdown voltage holding portion, the width measured in the circumferential direction of the breakdown voltage holding portion is wider than the width measured in the direction orthogonal to the circumferential direction. It is preferable.
In the semiconductor device of the present invention, the withstand voltage holding portion makes a round along the outer periphery of the semiconductor substrate. That is, the breakdown voltage holding portion is formed widely along the circumferential direction of the semiconductor device.
Therefore, by forming the shape of the pad formed on the withstand voltage holding portion widely along the circumferential direction in accordance with the shape of the withstand voltage holding portion, the portion of the pad formed on the withstand voltage holding portion A wide area can be formed. As a result, the area of the pad formed on the inner side of the withstand voltage holding portion can be further reduced, and the effective region in which the semiconductor structure necessary for the functioning of the semiconductor device can be further expanded.

本発明の半導体装置では、耐圧保持部とパッドの間に形成されている積層構造が耐圧保持部の全域に渡って形成されていることが好ましい。これにより、耐圧保持部と導電膜が対向している領域の面積をさらに広げることができる。パッド電圧にとって耐圧保持部に印加される電界の強度をさらに弱めることができ、半導体装置の耐圧特性が悪化する現象を確実に防ぐことができる。   In the semiconductor device of the present invention, it is preferable that the laminated structure formed between the pressure holding portion and the pad is formed over the entire area of the pressure holding portion. Thereby, the area of the area | region where the pressure | voltage resistant holding | maintenance part and the electrically conductive film are facing can be expanded further. For the pad voltage, the strength of the electric field applied to the breakdown voltage holding portion can be further reduced, and the phenomenon that the breakdown voltage characteristics of the semiconductor device are deteriorated can be surely prevented.

本発明によれば、耐圧保持部よりも内側に形成されるパッドの面積を縮小することができる。半導体装置が機能するのに必要な半導体構造を製造できる有効領域を拡大することができる。これにより、半導体装置の電気的特性を向上することができ、良質な半導体装置を製造することができる。   According to the present invention, it is possible to reduce the area of the pad formed on the inner side of the pressure resistant holding portion. The effective area where the semiconductor structure necessary for the semiconductor device to function can be manufactured can be expanded. Thereby, the electrical characteristics of the semiconductor device can be improved, and a high-quality semiconductor device can be manufactured.

以下に説明する実施例の主要な特徴を最初に整理する。
（特徴１）導電性ワイヤは、パッドのうちの耐圧保持部上に形成されている部分に接続固定されている。
（特徴２）導電性ワイヤは、耐圧保持部の外側から内側に引っ張ることによって切断されている。
（特徴３）導電性ワイヤは、耐圧保持部の内側から外側に引っ張ることによって切断されている。
（特徴４）導電性ワイヤは、耐圧保持部の周方向に引っ張ることによって切断されている。 The main features of the embodiments described below are first organized.
(Feature 1) The conductive wire is connected and fixed to a portion of the pad formed on the pressure holding portion.
(Feature 2) The conductive wire is cut by pulling from the outside to the inside of the pressure holding portion.
(Feature 3) The conductive wire is cut by pulling from the inside to the outside of the pressure-resistant holding portion.
(Feature 4) The conductive wire is cut by pulling in the circumferential direction of the pressure-resistant holding portion.

（第１実施例）
図１に、本発明を具現化した半導体装置２を示す。半導体装置２では、終端耐圧領域１８が半導体基板４の外周の内側を一巡している。終端耐圧領域１８には、耐圧保持部６５が形成されている。耐圧保持部６５にはＦＬＲ６５ａとＦＬＲ６５ｂが形成されている。耐圧保持部６５の内側には、半導体装置が機能するのに必要な半導体構造を製造できる有効領域８とパッド領域１０が形成されており、終端耐圧領域１８の耐圧保持部６５の外側には非有効領域６が形成されている。
パッド領域１０から耐圧保持部６５に至る範囲の半導体装置２の表面には、パッド１２が形成されている。パッド１２と耐圧保持部６５の間には、積層構造２０が形成されている。積層構造２０は、パッド１２のうちの耐圧保持部６５上に形成されている部分に対応する対応領域２４と、その対応領域２４から耐圧保持部６５上に広がっている拡大領域２６を備えている。積層構造２０はまた、パッド１２のうちのパッド領域１０に形成されている部分と半導体基板４の間にも形成されている。積層構造２０は、図２に示すように、第１絶縁膜７４と導電膜７６と第２絶縁膜７８を順に積層することで構成されている。積層構造２０は、パッド１２と耐圧保持部６５を絶縁している。
半導体装置２の有効領域８の表面にはエミッタ電極パッド１６が露出しており、エミッタ電極パッド１６に導電性ワイヤ２２がボンディングされている。導電性ワイヤ２２は、エミッタ電極パッド１６と外部回路（図示されていない）を電気的に接続している。図示番号１４はトレンチゲート電極用の導電性ワイヤを示し、パッド１２にボンディングされている。トレンチゲート電極用の導電性ワイヤ１４は、パッド１２と外部回路（図示されていない）を電気的に接続している。
パッド領域１０の半導体基板４内には半導体構造が形成されていない。パッド領域１０が小さいほど、半導体装置が機能するのに必要な半導体構造を製造できる有効領域８を広くすることができる。 (First embodiment)
FIG. 1 shows a semiconductor device 2 embodying the present invention. In the semiconductor device 2, the termination breakdown voltage region 18 makes a round around the inner periphery of the semiconductor substrate 4. A breakdown voltage holding portion 65 is formed in the termination breakdown voltage region 18. FLR 65a and FLR 65b are formed in the breakdown voltage holding portion 65. An effective region 8 and a pad region 10 in which a semiconductor structure necessary for the functioning of the semiconductor device can be manufactured are formed inside the withstand voltage holding portion 65, and there is a non-existence outside the withstand voltage holding portion 65 in the termination withstand voltage region 18. An effective area 6 is formed.
A pad 12 is formed on the surface of the semiconductor device 2 in a range from the pad region 10 to the breakdown voltage holding portion 65. A laminated structure 20 is formed between the pad 12 and the pressure resistant holding portion 65. The stacked structure 20 includes a corresponding region 24 corresponding to a portion of the pad 12 formed on the pressure holding portion 65 and an enlarged region 26 extending from the corresponding region 24 onto the pressure holding portion 65. . The stacked structure 20 is also formed between a portion of the pad 12 formed in the pad region 10 and the semiconductor substrate 4. As illustrated in FIG. 2, the stacked structure 20 is configured by sequentially stacking a first insulating film 74, a conductive film 76, and a second insulating film 78. The stacked structure 20 insulates the pad 12 from the pressure resistant holding portion 65.
An emitter electrode pad 16 is exposed on the surface of the effective region 8 of the semiconductor device 2, and a conductive wire 22 is bonded to the emitter electrode pad 16. The conductive wire 22 electrically connects the emitter electrode pad 16 and an external circuit (not shown). Reference numeral 14 denotes a conductive wire for the trench gate electrode, which is bonded to the pad 12. The conductive wire 14 for the trench gate electrode electrically connects the pad 12 and an external circuit (not shown).
A semiconductor structure is not formed in the semiconductor substrate 4 in the pad region 10. The smaller the pad region 10, the wider the effective region 8 in which a semiconductor structure necessary for the function of the semiconductor device can be manufactured.

半導体装置２のII−II断面における断面図を図２に示す。
図２に示すように、半導体装置２の有効領域８には、絶縁ゲート型バイポーラトランジスタ（Insulated Gate Bipolar Transistorであり、以下ではＩＧＢＴという）が形成されている。半導体装置２は、ｎ型の半導体基板４に形成されており、ｎ型の半導体基板４が未加工状態で残っている部分によって、ドリフト領域４６が形成されている。ドリフト領域４６の表面側に、ｐ型不純物を低濃度に含むボディ領域４８が積層されている。ボディ領域４８の表面に臨む位置に、ｎ型不純物を高濃度に含んでいるエミッタ領域５４が形成されている。エミッタ領域５４は、ボディ領域４８によって、ドリフト領域４６から隔てられている。
エミッタ領域５４の表面から、エミッタ領域５４とボディ領域４８を貫通し、ドリフト領域４６に達するトレンチ５６が形成されている。トレンチ５６の底面と壁面はゲート絶縁膜６０で被覆されており、トレンチ５６の内側にトレンチゲート電極５８が充填されている。トレンチゲート電極５８が形成されている範囲の半導体装置２の表面には酸化膜５２が形成されている。酸化膜５２の表面を含む有効領域８内の半導体装置２の表面には、エミッタ電極パッド１６が形成されている。エミッタ電極パッド１６は、エミッタ領域５４に導通している。
また、半導体装置２のパッド領域１０から耐圧保持部６５に至る範囲の表面には積層構造２０が形成されており、積層構造２０の表面にパッド１２が形成されている。トレンチゲート電極５８は図示しない断面で、パッド１２に接続されている。パッド１２が形成されているパッド領域１０には、ｐ型不純物を高濃度に含むｐ型拡散領域５０が形成されている。ｐ型拡散領域５０は、半導体基板４の表面に臨む位置に形成されており、ｐ型不純物を含むボディ領域４８の終端部と接続し、電気的に導通している。
半導体基板４の裏面側には、ｐ型不純物を高濃度に含むコレクタ領域４４が形成されている。半導体装置２の裏面には、コレクタ電極４２が形成されている。コレクタ電極４２は、コレクタ領域４４と導通している。 A sectional view of the semiconductor device 2 taken along the line II-II is shown in FIG.
As shown in FIG. 2, an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, hereinafter referred to as IGBT) is formed in the effective region 8 of the semiconductor device 2. The semiconductor device 2 is formed on an n-type semiconductor substrate 4, and a drift region 46 is formed by a portion where the n-type semiconductor substrate 4 remains unprocessed. A body region 48 containing a p-type impurity at a low concentration is stacked on the surface side of the drift region 46. An emitter region 54 containing an n-type impurity at a high concentration is formed at a position facing the surface of the body region 48. Emitter region 54 is separated from drift region 46 by body region 48.
A trench 56 that penetrates the emitter region 54 and the body region 48 and reaches the drift region 46 is formed from the surface of the emitter region 54. The bottom surface and wall surface of the trench 56 are covered with a gate insulating film 60, and a trench gate electrode 58 is filled inside the trench 56. An oxide film 52 is formed on the surface of the semiconductor device 2 in a range where the trench gate electrode 58 is formed. An emitter electrode pad 16 is formed on the surface of the semiconductor device 2 in the effective region 8 including the surface of the oxide film 52. The emitter electrode pad 16 is electrically connected to the emitter region 54.
In addition, a laminated structure 20 is formed on the surface of the semiconductor device 2 ranging from the pad region 10 to the withstand voltage holding portion 65, and the pad 12 is formed on the surface of the laminated structure 20. The trench gate electrode 58 has a cross section (not shown) and is connected to the pad 12. A p-type diffusion region 50 containing a high concentration of p-type impurities is formed in the pad region 10 where the pad 12 is formed. The p-type diffusion region 50 is formed at a position facing the surface of the semiconductor substrate 4, is connected to the terminal portion of the body region 48 containing p-type impurities, and is electrically connected.
A collector region 44 containing a high concentration of p-type impurities is formed on the back side of the semiconductor substrate 4. A collector electrode 42 is formed on the back surface of the semiconductor device 2. The collector electrode 42 is electrically connected to the collector region 44.

半導体装置２の終端耐圧領域１８の半導体基板４の表面に臨む位置に、ｐ型不純物を高濃度に含むガードリング６６ａ、６６ｂが形成されている。ガードリング６６ａ、６６ｂは、半導体装置２のオフ時に空乏層を終端耐圧領域１８の広い範囲に伸ばし、電界が集中して半導体装置２の耐圧特性が低下することを防ぐ。ガードリング６６ａ、６６ｂの形成本数は必要な耐圧特性によって変化し、図２に示すように２本形成される場合もあれば、３本以上が形成される場合もあれば、１本のみ形成される場合もある。
パッド領域１０から終端耐圧領域１８に至る範囲の半導体基板４の表面には、酸化膜５２が形成されている。酸化膜５２には、ガードリング６６ａ、６６ｂに対応する位置にコンタクトホール６２ａ、６２が形成されている。ガードリング６６ａ、６６ｂに対応する位置の酸化膜５２の表面には、導電性のフィールドプレート６４ａ、６４ｂが形成されている。ガードリング６６ａとフィールドプレート６４ａはコンタクトホール６２ａを通して導通している。ガードリング６６ａとフィールドプレート６４ａによってＦＬＲ６５ａが形成されている。ガードリング６６ｂとフィールドプレート６４ｂはコンタクトホール６２ｂを通して導通している。ガードリング６６ｂとフィールドプレート６４ｂによってＦＬＲ６５ｂが形成されている。
酸化膜５２の表面に、積層構造２０が形成されている。積層構造２０は、第１絶縁膜７４と導電膜７６と第２絶縁膜７８を順に積層することで構成されている。第１絶縁膜７４は、フィールドプレート６４ａ、６４ｂの表面を覆っている。積層構造２０の表面にパッド１２が形成されている。積層構造２０は、パッド１２と耐圧保持部６５を絶縁し、相互作用を遮断している。 Guard rings 66a and 66b containing p-type impurities at a high concentration are formed at positions facing the surface of the semiconductor substrate 4 in the termination breakdown voltage region 18 of the semiconductor device 2. The guard rings 66a and 66b extend the depletion layer to a wide range of the termination breakdown voltage region 18 when the semiconductor device 2 is turned off, and prevent the breakdown voltage characteristics of the semiconductor device 2 from being reduced due to the concentration of the electric field. The number of guard rings 66a and 66b formed varies depending on the required withstand voltage characteristics. As shown in FIG. 2, two guard rings 66a and 66b may be formed, or three or more may be formed, or only one may be formed. There is also a case.
An oxide film 52 is formed on the surface of the semiconductor substrate 4 in a range from the pad region 10 to the termination breakdown voltage region 18. In the oxide film 52, contact holes 62a and 62 are formed at positions corresponding to the guard rings 66a and 66b. Conductive field plates 64a and 64b are formed on the surface of the oxide film 52 at positions corresponding to the guard rings 66a and 66b. The guard ring 66a and the field plate 64a are electrically connected through the contact hole 62a. An FLR 65a is formed by the guard ring 66a and the field plate 64a. The guard ring 66b and the field plate 64b are electrically connected through the contact hole 62b. An FLR 65b is formed by the guard ring 66b and the field plate 64b.
A laminated structure 20 is formed on the surface of the oxide film 52. The stacked structure 20 is configured by sequentially stacking a first insulating film 74, a conductive film 76, and a second insulating film 78. The first insulating film 74 covers the surfaces of the field plates 64a and 64b. Pads 12 are formed on the surface of the laminated structure 20. The laminated structure 20 insulates the pad 12 and the pressure-resistant holding part 65 and blocks the interaction.

本実施例の半導体装置２では、図１に示すように、半導体装置２をボンディング装置(図示されていない)にセットしてワイヤボンディング処理を実行する。ボンディング装置は、導電性ワイヤ１４をパッド１２に接続固定し、導電性ワイヤ１４の延長部分を切断する。それに先立って、導電性ワイヤ１４の図示しない端部は、外部回路に接続固定されている。ボンディング装置は、導電性ワイヤ１４をパッド１２に接続固定した後に、導電性ワイヤ１４の延長部分を引っ張って導電性ワイヤ１４を切断する。この際に、パッド１２に引き摺り痕２８が形成される。その様子を図８〜図１２のワイヤボンディング方法の手順を用いて説明する。   In the semiconductor device 2 of the present embodiment, as shown in FIG. 1, the semiconductor device 2 is set in a bonding apparatus (not shown) and a wire bonding process is executed. The bonding apparatus connects and fixes the conductive wire 14 to the pad 12 and cuts the extended portion of the conductive wire 14. Prior to that, the end (not shown) of the conductive wire 14 is connected and fixed to an external circuit. After bonding and fixing the conductive wire 14 to the pad 12, the bonding apparatus pulls an extended portion of the conductive wire 14 to cut the conductive wire 14. At this time, a drag mark 28 is formed on the pad 12. This will be described using the procedure of the wire bonding method shown in FIGS.

図８〜図１２は、外部回路１４６と半導体装置２をワイヤボンディングする方法を示す。図８に示すように、導電性ワイヤ１４はボンディング装置のクランプ１３８及びウェッジ・ツール１３４を通って、その先端がウェッジ・ツール１３４の底面１３４ａから突出している。クランプ１３８は導電性ワイヤ１４を把持する機能を持っている。クランプ１３８は支え１３６によってウェッジ・ツール１３４と連結されており、クランプ１３８とウェッジ・ツール１３４は相対的に移動できる。
このワイヤボンディング方法では、まず図９に示すように、ウェッジ・ツール１３４の底面１３４ａを外部回路１４６のパッド１４８に押し付け、導電性ワイヤ１４に超音波振動を加えてパッド１４８と導電性ワイヤ１４をボンディングする。パッド１４８の表面にボンディング痕１５０が形成される。
次に図１０に示すように、導電性ワイヤ１４とクランプ１３８とウェッジ・ツール１３４の全体を次のボンディング先である半導体装置２のパッド１２上に移動する。この際に、導電性ワイヤ１４はウェッジ・ツール１３４の底面１３４ａから引き出される。次に図１１に示すように、ウェッジ・ツール１３４の底面１３４ａを半導体装置２のパッド１２に押し付け、導電性ワイヤ１４に超音波振動を加えてパッド１２と導電性ワイヤ１４をボンディングする。パッド１２表面にボンディング痕１５２が形成される。 8 to 12 show a method of wire bonding the external circuit 146 and the semiconductor device 2. As shown in FIG. 8, the conductive wire 14 passes through the clamp 138 and the wedge tool 134 of the bonding apparatus, and its tip protrudes from the bottom surface 134 a of the wedge tool 134. The clamp 138 has a function of gripping the conductive wire 14. The clamp 138 is connected to the wedge tool 134 by a support 136, and the clamp 138 and the wedge tool 134 are relatively movable.
In this wire bonding method, first, as shown in FIG. 9, the bottom surface 134 a of the wedge tool 134 is pressed against the pad 148 of the external circuit 146, and ultrasonic vibration is applied to the conductive wire 14 to bond the pad 148 and the conductive wire 14. Bond. Bonding marks 150 are formed on the surface of the pad 148.
Next, as shown in FIG. 10, the entire conductive wire 14, clamp 138, and wedge tool 134 are moved onto the pad 12 of the semiconductor device 2 as the next bonding destination. At this time, the conductive wire 14 is pulled out from the bottom surface 134 a of the wedge tool 134. Next, as shown in FIG. 11, the bottom surface 134 a of the wedge tool 134 is pressed against the pad 12 of the semiconductor device 2, and ultrasonic vibration is applied to the conductive wire 14 to bond the pad 12 and the conductive wire 14. Bonding marks 152 are formed on the surface of the pad 12.

パッド１２に導電性ワイヤ１４をボンディング後、図１１に示すように、ウェッジ・ツール１３４をパッド１２上に置いたまま、クランプ１３８をウェッジ・ツール１３４に対して矢印１５４の方向に移動させる。これによりパッド１２とウェッジ・ツール１３４に挟まれた導電性ワイヤ１４は引きちぎられる。この際に、図１２に示すように、引きちぎられた導電性ワイヤ１４はパッド１２の表面に引き摺り痕２８を形成する。その後、ウェッジ・ツール１３４とクランプ１３８は一体となって矢印１５６の方向に引き上げられ、ワイヤボンディング方法を終了する。
図１３に示すように、パッド１２がボンディング痕１５２と同程度の面積である場合、引き摺り痕２８がパッド１２を超えて形成され、半導体装置２の表面の保護膜が損傷する。保護膜に損傷した場合、損傷から半導体装置２の内部に不純物などが進入し、半導体装置２の特性低下及び破損の原因となる。その為、パッド１２上で導電性ワイヤ１４を切断する場合には、引き摺り痕２８の形成範囲を含む程度にまでパッド１２を拡大して形成する必要がある。 After bonding the conductive wire 14 to the pad 12, the clamp 138 is moved in the direction of arrow 154 relative to the wedge tool 134 while the wedge tool 134 remains on the pad 12 as shown in FIG. As a result, the conductive wire 14 sandwiched between the pad 12 and the wedge tool 134 is torn off. At this time, as shown in FIG. 12, the torn conductive wire 14 forms a drag mark 28 on the surface of the pad 12. Thereafter, the wedge tool 134 and the clamp 138 are pulled together in the direction of the arrow 156, and the wire bonding method is completed.
As shown in FIG. 13, when the pad 12 has the same area as the bonding mark 152, the drag mark 28 is formed beyond the pad 12, and the protective film on the surface of the semiconductor device 2 is damaged. When the protective film is damaged, impurities or the like enter the semiconductor device 2 due to the damage, causing deterioration of the characteristics and damage of the semiconductor device 2. Therefore, when cutting the conductive wire 14 on the pad 12, it is necessary to enlarge the pad 12 to an extent that includes the formation range of the drag mark 28.

半導体装置２のパッド１２に引き摺り痕２８が形成されるのは、導電性ワイヤ１４を引きちぎる場合に限らない。ウェッジ・ツール１３４に導電性ワイヤ１４を切断するためのワイヤ・カッタが存在し、導電性ワイヤ１４をカッタで切断する場合にも、引き摺り痕２８が形成されることがある。この場合でも、半導体装置２の保護膜に損傷が生じるのをさけるためには、パッド１２を拡大して引き摺り痕２８がパッド１２内に留まるようにしておく必要があった。   The reason why the drag mark 28 is formed on the pad 12 of the semiconductor device 2 is not limited to the case where the conductive wire 14 is torn off. The wire cutter for cutting the conductive wire 14 exists in the wedge tool 134, and the drag mark 28 may be formed even when the conductive wire 14 is cut by the cutter. Even in this case, in order to prevent the protective film of the semiconductor device 2 from being damaged, it is necessary to enlarge the pad 12 so that the drag mark 28 remains in the pad 12.

本実施例の半導体装置２でも、図１に示すように、導電性ワイヤ１４との接続固定に必要な領域だけではなく、引き摺り痕２８が形成される領域を含む程度に広いパッド１２を形成する。その為、引き摺り痕２８がパッド１２の外側に形成されることがない。半導体装置２の有効領域８に損傷が生じるのを防ぐことができる。
それに対して、図７は耐圧保持部６５の内側に位置するパッド５１２のサイズを図１の場合と同じサイズとし、しかも、パッド５１２を耐圧保持部６５の内側に留めた場合を示す。この場合、引き摺り痕２８がパッド１２の外側に形成され、有効領域８に損傷が生じてしまう。 Also in the semiconductor device 2 of the present embodiment, as shown in FIG. 1, not only a region necessary for connection and fixation with the conductive wire 14 but also a pad 12 that is wide enough to include a region where a drag mark 28 is formed. . Therefore, the drag mark 28 is not formed outside the pad 12. It is possible to prevent the effective region 8 of the semiconductor device 2 from being damaged.
On the other hand, FIG. 7 shows a case in which the size of the pad 512 located inside the pressure holding portion 65 is the same as that in FIG. 1 and the pad 512 is held inside the pressure holding portion 65. In this case, the drag mark 28 is formed outside the pad 12, and the effective region 8 is damaged.

本実施例の半導体装置２では、引き摺り痕２８が形成される領域を覆う程度に広く形成されたパッド１２を利用するとともに、パッド１２の一部が耐圧保持部６５上に形成されている。そのため、図６に示すようにパッド４１２の全てが耐圧保持部６５の内側に形成されていた従来技術の半導体装置４０２に比べて、本実施例のパッド領域１０の面積を縮小することができる。これによって、半導体装置２内の有効領域８の面積を拡大することができ、半導体装置２の電気的特性を向上することができる。   In the semiconductor device 2 of the present embodiment, the pad 12 formed so wide as to cover the region where the drag mark 28 is formed is used, and a part of the pad 12 is formed on the breakdown voltage holding portion 65. Therefore, the area of the pad region 10 of this embodiment can be reduced as compared with the conventional semiconductor device 402 in which all of the pads 412 are formed inside the breakdown voltage holding portion 65 as shown in FIG. As a result, the area of the effective region 8 in the semiconductor device 2 can be increased, and the electrical characteristics of the semiconductor device 2 can be improved.

さらに本実施例の半導体装置２では、図２に示すように、耐圧保持部６５とパッド１２の間に積層構造２０が形成されている。積層構造２０は、耐圧保持部６５の側から第１絶縁膜７４と導電膜７６と第２絶縁膜７８の順に積層されて形成されており、これによって、耐圧保持部６５とパッド１２の間には、耐圧保持部６５のＦＬＲ６５ａ、６５ｂとパッド１２の両方から絶縁された導電膜７６が形成される。また、図１に示すように、本実施例の半導体装置２では、耐圧保持部６５上に形成される積層構造２０（導電膜７６を含む）が、耐圧保持部６５上に形成されるパッド１２に比べて広く形成されている。   Furthermore, in the semiconductor device 2 of the present embodiment, as shown in FIG. 2, the laminated structure 20 is formed between the pressure resistance holding portion 65 and the pad 12. The laminated structure 20 is formed by laminating the first insulating film 74, the conductive film 76, and the second insulating film 78 in this order from the pressure withstand voltage holding unit 65 side. A conductive film 76 is formed that is insulated from both the FLRs 65 a and 65 b of the withstand voltage holding portion 65 and the pad 12. Further, as shown in FIG. 1, in the semiconductor device 2 of the present embodiment, the stacked structure 20 (including the conductive film 76) formed on the breakdown voltage holding portion 65 includes the pad 12 formed on the breakdown voltage holding portion 65. It is formed wider than

耐圧保持部６５とパッド１２の間に導電物質で形成された層が存在しない場合、パッド１２から発生した電界が、パッド１２と対向する領域の耐圧保持部６５に局所的に印加される。この局所的な電界により耐圧保持部６５における半導体基板４内の電界分布が大きく変化すると、半導体装置の耐圧特性が悪化してしまう。
本実施例の半導体装置２では、耐圧保持部６５とパッド１２の間に導電膜７６が形成されている。その為、パッド１２から発生した電界は、耐圧保持部６５に直接的には印加されず、導電膜７６を介して耐圧保持部６５に印加される。また、図１に示すように、耐圧保持部６５上に形成されている導電膜７６が、耐圧保持部６５上に形成されているパッド１２に比べて広いことから、パッド１２から発生した電界は導電膜７６を通過する際に、その範囲が広がる。耐圧保持部６５に局所的な電界が印加されることを抑制することができる。この結果、耐圧保持部６５の電界分布が大きく変化することがなく、半導体装置２の耐圧特性が悪化することを防ぐことができる。 When there is no layer formed of a conductive material between the withstand voltage holding unit 65 and the pad 12, an electric field generated from the pad 12 is locally applied to the withstand voltage holding unit 65 in a region facing the pad 12. When the electric field distribution in the semiconductor substrate 4 in the breakdown voltage holding portion 65 changes greatly due to this local electric field, the breakdown voltage characteristics of the semiconductor device are deteriorated.
In the semiconductor device 2 of the present embodiment, a conductive film 76 is formed between the breakdown voltage holding portion 65 and the pad 12. Therefore, the electric field generated from the pad 12 is not directly applied to the withstand voltage holding unit 65 but applied to the withstand voltage holding unit 65 through the conductive film 76. Further, as shown in FIG. 1, since the conductive film 76 formed on the breakdown voltage holding portion 65 is wider than the pad 12 formed on the breakdown voltage holding portion 65, the electric field generated from the pad 12 is When passing through the conductive film 76, the range is expanded. Application of a local electric field to the withstand voltage holding unit 65 can be suppressed. As a result, the electric field distribution of the withstand voltage holding portion 65 does not change greatly, and the withstand voltage characteristics of the semiconductor device 2 can be prevented from deteriorating.

本実施例の半導体装置２では、第１絶縁膜７４と第２絶縁膜７８がポリイミドなどの誘電率の低い絶縁膜であることが好ましい。第２絶縁膜７８の誘電率が低いと、パッド１２の電荷によって導電膜７６が分極する程度を抑えることができる。第１絶縁膜７４の誘電率が低いと、導電膜７６の分極によって耐圧保持部６５の表面に帯電する電荷量を抑制することができる。パッド１２と耐圧保持部６５の間の相互作用を弱めることができる。パッド１２が耐圧保持部６５上に配置されることによる悪影響を実質的に防ぐことができる。   In the semiconductor device 2 of this embodiment, the first insulating film 74 and the second insulating film 78 are preferably insulating films having a low dielectric constant such as polyimide. When the dielectric constant of the second insulating film 78 is low, the degree to which the conductive film 76 is polarized by the charge of the pad 12 can be suppressed. When the dielectric constant of the first insulating film 74 is low, the amount of charge charged on the surface of the withstand voltage holding portion 65 due to polarization of the conductive film 76 can be suppressed. The interaction between the pad 12 and the pressure resistant holding portion 65 can be weakened. It is possible to substantially prevent an adverse effect caused by the pad 12 being disposed on the pressure resistant holding portion 65.

（第２実施例）
本発明の半導体装置では、パッド１２が耐圧保持部６５よりも外側の非有効領域６に形成されているともに、非有効領域６の半導体基板から絶縁されている部分をさらに備えていることが好ましい。
図３に、本発明の第２実施例の半導体装置１０２を示す。本実施例の半導体装置１０２では、パッド１１２が、耐圧保持部６５の内側から上部を通り越して外側にまで伸びている。パッド１１２と耐圧保持部６５の間、ならびに、パッド１１２と耐圧保持部６５よりも外側の非有効領域６の半導体基板の間に、第１実施例の半導体装置２と同様の積層構造１２０が形成されている。
本実施例の半導体装置１０２では、パッド１１２の少なくとも一部が非有効領域６に形成されていることによって、パッド領域１１０の面積をさらに縮小することができ、半導体装置１０２が機能するのに必要な半導体構造を製造できる有効領域１０８の面積をさらに拡大することができる。 (Second embodiment)
In the semiconductor device of the present invention, it is preferable that the pad 12 is formed in the non-effective region 6 outside the breakdown voltage holding portion 65 and further includes a portion insulated from the semiconductor substrate in the non-effective region 6. .
FIG. 3 shows a semiconductor device 102 according to the second embodiment of the present invention. In the semiconductor device 102 of the present embodiment, the pad 112 extends from the inside of the pressure-resistant holding part 65 to the outside through the upper part. A stacked structure 120 similar to that of the semiconductor device 2 of the first embodiment is formed between the pad 112 and the breakdown voltage holding portion 65 and between the pad 112 and the semiconductor substrate in the ineffective region 6 outside the breakdown voltage holding portion 65. Has been.
In the semiconductor device 102 of this embodiment, at least a part of the pad 112 is formed in the ineffective region 6, so that the area of the pad region 110 can be further reduced and is necessary for the semiconductor device 102 to function. The area of the effective region 108 that can manufacture a simple semiconductor structure can be further expanded.

（第３実施例）
本発明の半導体装置では、パッドのうちの耐圧保持部上に形成されている部分の形状において、耐圧保持部の周方向に測定した幅が、周方向に直交する方向に測定した幅よりも広いことが好ましい。
図４に、本発明の第３実施例の半導体装置２０２を示す。本実施例の半導体装置２０２では、パッド２１２の少なくとも一部が耐圧保持部６５上に形成されている。パッド２１２の耐圧保持部６５上に形成された部分では、該部分の周方向２３０に測定した幅Ｌ１と周方向２３０に直交する方向に測定した幅Ｌ２において、Ｌ１＞Ｌ２の関係を持って形成されている。また、パッド２１２と耐圧保持部６５の間には第１実施例の半導体装置２と同様な積層構造２２０が形成されている。この実施例では、導電性ワイヤ１４が、耐圧保持部６５の周方向２３０に引っ張ることによって切断されている。
本実施例の半導体装置２０２では、図４に示すように、耐圧保持部６５が半導体装置２０２の周方向２３０に沿って広く形成されている。その為、パッド２１２のうちの耐圧保持部６５上に形成されている部分を、周方向２３０に広く形成することによって、耐圧保持部６５の上にパッド２０２を広く形成することができる。これにより、耐圧保持部６５の内側に形成されるパッド領域２１０の面積をさらに縮小することができ、半導体装置２０２が機能するのに必要な半導体構造を製造できる有効領域２０８をさらに拡大することができる。 (Third embodiment)
In the semiconductor device of the present invention, in the shape of the portion of the pad formed on the breakdown voltage holding portion, the width measured in the circumferential direction of the breakdown voltage holding portion is wider than the width measured in the direction orthogonal to the circumferential direction. It is preferable.
FIG. 4 shows a semiconductor device 202 according to the third embodiment of the present invention. In the semiconductor device 202 of this embodiment, at least a part of the pad 212 is formed on the breakdown voltage holding portion 65. The portion of the pad 212 formed on the pressure resistance holding portion 65 is formed with a relationship of L1> L2 in the width L1 measured in the circumferential direction 230 of the portion 212 and the width L2 measured in the direction orthogonal to the circumferential direction 230. Has been. Further, a stacked structure 220 similar to that of the semiconductor device 2 of the first embodiment is formed between the pad 212 and the breakdown voltage holding portion 65. In this embodiment, the conductive wire 14 is cut by pulling in the circumferential direction 230 of the pressure resistant holding portion 65.
In the semiconductor device 202 of the present embodiment, as shown in FIG. 4, the breakdown voltage holding portion 65 is widely formed along the circumferential direction 230 of the semiconductor device 202. Therefore, the pad 202 can be widely formed on the breakdown voltage holding portion 65 by forming a portion of the pad 212 formed on the breakdown voltage holding portion 65 wide in the circumferential direction 230. As a result, the area of the pad region 210 formed inside the breakdown voltage holding portion 65 can be further reduced, and the effective region 208 in which a semiconductor structure necessary for the functioning of the semiconductor device 202 can be further expanded. it can.

（第４実施例）
本発明の半導体装置では、積層構造が耐圧保持部の全域に亘って形成されていることが好ましい。
図５に、本発明の第３実施例の半導体装置３０２を示す。本実施例の半導体装置３０２では、パッド３１２の少なくとも一部が耐圧保持部６５上に形成されている。また、パッド３１２と耐圧保持部６５の間には第１実施例の半導体装置２と同様な積層構造３２０が形成されている。本実施例の半導体装置３０２では、積層構造３２０が耐圧保持部６５の全域に亘って形成されている。
本実施例の半導体装置３０２では、図５に示すように、積層構造３２０が耐圧保持部６５の全域に亘って形成されている。その為、導電膜７６と耐圧保持部６５が対向している領域の面積をさらに広げることができる。これにより、耐圧保持部６５に印加される電界をさらに弱めることができ、半導体装置３０２の耐圧特性が悪化してしまうことを防ぐことができる。 (Fourth embodiment)
In the semiconductor device of the present invention, it is preferable that the laminated structure is formed over the entire area of the withstand voltage holding portion.
FIG. 5 shows a semiconductor device 302 according to a third embodiment of the present invention. In the semiconductor device 302 of this embodiment, at least a part of the pad 312 is formed on the breakdown voltage holding unit 65. Further, a stacked structure 320 similar to that of the semiconductor device 2 of the first embodiment is formed between the pad 312 and the breakdown voltage holding portion 65. In the semiconductor device 302 of this embodiment, the stacked structure 320 is formed over the entire area of the withstand voltage holding portion 65.
In the semiconductor device 302 of this embodiment, as shown in FIG. 5, the laminated structure 320 is formed over the entire area of the withstand voltage holding portion 65. Therefore, the area of the region where the conductive film 76 and the withstand voltage holding portion 65 are opposed can be further increased. As a result, the electric field applied to the withstand voltage holding unit 65 can be further weakened, and deterioration of the withstand voltage characteristics of the semiconductor device 302 can be prevented.

以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時の請求項に記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

第１実施例の半導体装置を示した図である。It is the figure which showed the semiconductor device of 1st Example. 第１実施例の半導体装置の断面図である。It is sectional drawing of the semiconductor device of 1st Example. 第２実施例の半導体装置を示した図である。It is the figure which showed the semiconductor device of 2nd Example. 第３実施例の半導体装置を示した図である。It is the figure which showed the semiconductor device of 3rd Example. 第４実施例の半導体装置を示した図である。It is the figure which showed the semiconductor device of 4th Example. 従来技術の半導体装置を示した図である。It is the figure which showed the semiconductor device of the prior art. 従来技術の半導体装置を示した図である。It is the figure which showed the semiconductor device of the prior art. ワイヤボンディング方法の手順を示した図である。It is the figure which showed the procedure of the wire bonding method. ワイヤボンディング方法の手順を示した図である。It is the figure which showed the procedure of the wire bonding method. ワイヤボンディング方法の手順を示した図である。It is the figure which showed the procedure of the wire bonding method. ワイヤボンディング方法の手順を示した図である。It is the figure which showed the procedure of the wire bonding method. ワイヤボンディング方法の手順を示した図である。It is the figure which showed the procedure of the wire bonding method. ワイヤボンディング方法における従来技術の問題点を示す。The problem of the prior art in the wire bonding method is shown.

符号の説明Explanation of symbols

２・・・・・半導体装置
４・・・・・半導体基板
６・・・・・非有効領域
８・・・・・有効領域
１０・・・・パッド領域
１２・・・・パッド
１４・・・・導電性ワイヤ
１６・・・・エミッタ電極パッド
１８・・・・終端耐圧領域
２０・・・・積層構造
２２・・・・導電性ワイヤ
２４・・・・対応領域
２６・・・・拡大領域
２８・・・・引き摺り痕
４２・・・・コレクタ電極
４４・・・・コレクタ領域
４６・・・・ドリフト領域
４８・・・・ボディ領域
５０・・・・ｐ型拡散領域
５２・・・・酸化膜
５４・・・・エミッタ領域
５６・・・・トレンチ
５８・・・・トレンチゲート電極
６０・・・・ゲート絶縁膜
６２・・・・コンタクトホール
６２ａ、６２ｂ・・・コンタクトホール
６４・・・・フィールドプレート
６４ａ、６４ｂ・・・フィールドプレート
６５・・・・耐圧保持部
６５ａ、６５ｂ・・・ＦＬＲ
６６・・・・ガードリング
６６ａ、６６ｂ・・・ガードリング
７４・・・・第１絶縁膜
７６・・・・導電膜
７８・・・・第２絶縁膜
１０２・・・半導体装置
１０８・・・有効領域
１１０・・・パッド領域
１１２・・・パッド
１２０・・・積層構造
１３４・・・ウェッジ・ツール
１３４ａ・・・ウェッジ・ツールの底面
１３６・・・支え
１３８・・・クランプ
１４６・・・外部回路
１４８・・・リード
１５０・・・ボンディング痕
１５２・・・ボンディング痕
１５４・・・矢印
１５６・・・矢印
２０２・・・半導体装置
２０８・・・有効領域
２１０・・・パッド領域
２１２・・・パッド
２２０・・・積層構造
２３０・・・周方向
３０２・・・半導体装置
３１２・・・パッド
３２０・・・積層構造
４０２・・・半導体装置
４１２・・・パッド
５１２・・・パッド 2... Semiconductor device 4... Semiconductor substrate 6... Non-effective area 8... Effective area 10... Pad area 12. · Conductive wire 16 ··· Emitter electrode pad 18 ··· Termination withstand voltage region 20 ··· Multilayer structure 22 ··· Conductive wire 24 ··· Corresponding region 26 ··· Expansion region 28 ... Drag mark 42 ... Collector electrode 44 ... Collector region 46 ... Drift region 48 ... Body region 50 ... P-type diffusion region 52 ... Oxide film 54... Emitter region 56... Trench 58... Trench gate electrode 60... Gate insulating film 62 ... Contact holes 62 a and 62 b Contact hole 64. Plate 64a, 64b ... feel Plate 65 .... breakdown voltage holding portion 65a, 65b ··· FLR
66... Guard rings 66 a and 66 b... Guard ring 74... First insulating film 76... Conductive film 78. Effective area 110 ... Pad area 112 ... Pad 120 ... Laminated structure 134 ... Wedge tool 134a ... Wedge tool bottom surface 136 ... Support 138 ... Clamp 146 ... External Circuit 148 ... Lead 150 ... Bonding trace 152 ... Bonding trace 154 ... Arrow 156 ... Arrow 202 ... Semiconductor device 208 ... Effective area 210 ... Pad area 212 ... Pad 220 ... Laminated structure 230 ... Circumferential direction 302 ... Semiconductor device 312 ... Pad 320 ... Laminated structure 402 ... Semiconductor device 412 ... Pad 51 ... Pad

Claims (5)

半導体基板の表面の外周の内側を一巡している耐圧保持部と、
前記耐圧保持部よりも内側に形成されており、前記半導体基板内に形成されている複数の半導体領域を組み合わせて構成されている半導体素子と、
前記耐圧保持部よりも内側から少なくとも前記耐圧保持部上に伸びており、前記半導体素子を構成する少なくとも一つの半導体領域に導通しているとともに、前記耐圧保持部から絶縁されているパッドと、
少なくとも前記耐圧保持部の半導体基板と前記パッド間に形成されており、前記半導体基板の側から第１絶縁膜と導電膜と第２絶縁膜の順に積層されている積層構造と、
を備えている半導体装置。 A pressure-resistant holding part that makes a round inside the outer periphery of the surface of the semiconductor substrate;
A semiconductor element formed on the inner side of the pressure-resistant holding portion and configured by combining a plurality of semiconductor regions formed in the semiconductor substrate;
A pad extending from at least the pressure holding portion from the inside to the pressure holding portion, and is electrically connected to at least one semiconductor region constituting the semiconductor element, and is insulated from the pressure holding portion,
A laminated structure formed at least between the semiconductor substrate and the pad of the withstand voltage holding portion and laminated in the order of the first insulating film, the conductive film and the second insulating film from the semiconductor substrate side;
A semiconductor device comprising: 前記導電膜は、前記パッドのうちの前記耐圧保持部上に形成されている部分に対応する対応領域と、その対応領域から前記耐圧保持部上に広がっている拡大領域を備えていることを特徴とする請求項１の半導体装置。   The conductive film includes a corresponding region corresponding to a portion of the pad formed on the breakdown voltage holding portion, and an enlarged region extending from the corresponding region onto the breakdown voltage holding portion. The semiconductor device according to claim 1. 前記パッドは、前記耐圧保持部よりもさらに外側に伸びており、前記耐圧保持部よりも外側に位置しているパッドが前記半導体基板から絶縁されていることを特徴とする請求項１または２に記載の半導体装置。   3. The pad according to claim 1, wherein the pad extends further outward than the pressure holding portion, and the pad located outside the pressure holding portion is insulated from the semiconductor substrate. The semiconductor device described. 前記パッドのうちの前記耐圧保持部上に形成されている部分の形状において、前記耐圧保持部の周方向に測定した幅が、前記周方向に直交する方向に測定した幅よりも広いことを特徴とする請求項１〜３のいずれか１項に記載の半導体装置。   In the shape of the portion of the pad formed on the pressure holding portion, the width measured in the circumferential direction of the pressure holding portion is wider than the width measured in the direction perpendicular to the circumferential direction. The semiconductor device according to claim 1. 前記第１絶縁膜と導電膜と第２絶縁膜が、前記耐圧保持部の全域に亘って形成されていることを特徴とする請求項１〜４のいずれか１項に記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the first insulating film, the conductive film, and the second insulating film are formed over the entire area of the breakdown voltage holding portion.
JP2007318471A 2007-12-10 2007-12-10 Semiconductor device Pending JP2009141256A (en)

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JPH02153570A (en) * 1988-12-06 1990-06-13 Toshiba Corp Semiconductor element
JP2002222952A (en) * 2001-01-26 2002-08-09 Toshiba Corp High withstand voltage semiconductor device
JP2007103792A (en) * 2005-10-06 2007-04-19 Kawasaki Microelectronics Kk Semiconductor device

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JPS61278161A (en) * 1985-06-04 1986-12-09 Tdk Corp High withstand voltage semiconductor device
JPH0241456U (en) * 1988-09-09 1990-03-22

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JPH02153570A (en) * 1988-12-06 1990-06-13 Toshiba Corp Semiconductor element
JP2002222952A (en) * 2001-01-26 2002-08-09 Toshiba Corp High withstand voltage semiconductor device
JP2007103792A (en) * 2005-10-06 2007-04-19 Kawasaki Microelectronics Kk Semiconductor device

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