JP2009141144A - Semiconductor memory device, and methods of manufacturing and driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of preventing characteristic deterioration due to a hot carrier without any increase in parasitic resistance, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor memory device has a semiconductor layer 3 formed on a glass substrate 1, a charge holding film 21 made of an ONO (Oxide-Nitride-Oxide) film formed on the semiconductor layer 3, and a gate electrode 22 provided on the charge holding film 21. Further, the semiconductor memory device has a source/drain region 23 provided to the semiconductor layer 3 to overlap with the gate electrode 22 and made of a compound of a semiconductor and a metal such as nickel silicide. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, a manufacturing method thereof, and a data erasure driving method.

MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type memory elements, floating gate type memory elements and other memory elements having MIS (Metal-Insulator-Semiconductor) type field effect transistor structures are generally single drain structures. Is used, and data writing is performed using channel hot carrier injection into a charge holding film such as an ONO (Oxide-Nitride-Oxide) film or a floating gate.
The source region and the drain region in the single drain structure are ion-implanted at a high concentration with any of P, As, and Sb in the case of an N-type channel device and B in the case of a P-type channel device, using a gate electrode as a mask. Thereafter, it is formed by activation annealing. Accordingly, since the source region and the drain region can be formed at positions that are self-aligned with respect to the gate electrode, variation in element characteristics can be reduced.

  FIG. 8 shows an example of a semiconductor memory device manufactured by the prior art. In the semiconductor memory device shown in FIG. 8, a polycrystalline silicon 53 is formed on a glass substrate 51 via a protective insulating film 52, and a gate insulating film 54 and a gate electrode 55 are laminated on the polycrystalline silicon 53. A source region 56 and a drain region 57 are formed by implanting B into the crystalline silicon 53 using the gate electrode 55 as a mask and annealing it. In this semiconductor memory device, an interlayer insulating film 61, a source electrode 62, and a drain electrode 63 are further formed.

However, as shown in FIG. 9, in the memory element having the MIS field effect transistor structure using the single drain structure, the length T at which the gate electrode 13 overlaps the source region 56 and the drain region 57 is 600. It is small because it is a part formed by thermal diffusion of B (boron) by activated annealing at a temperature of 0 ° C. or lower. Therefore, resistance to channel hot carriers is weak. That is, the channel hot carrier H at the time of data writing is depleted at the drain end by the channel hot carrier C injected into the insulating film near the drain end, and further, the inversion layer is formed, thereby forming the drain region. 57 easily causes an offset S with respect to the gate electrode 55. In particular, when a data read operation is performed with the offset as the source side, the deterioration of the S value (subthreshold coefficient), the deterioration of the on-current due to the decrease of the on-current, and the like become remarkable, and good data retention characteristics are obtained. Absent. The S value is a value representing an increase in gate voltage necessary for the drain current to increase by one digit in the subthreshold region. That is, S = 1 / (d (log ₁₀ (Id)) / dVg) (Id is the drain current).

Further, for example, Patent Document 1 discloses a nonvolatile memory transistor that realizes low power consumption. In the memory transistor of Patent Document 1, a first insulating film, a floating gate, a second insulating film, and a control electrode are stacked on a semiconductor layer, and titanium, tungsten, cobalt, molybdenum, or the like is formed on a semiconductor layer on the side of the gate. In this structure, a metal layer is formed by sputtering, and then silicided by heat treatment to form a source region and a drain region. With this configuration, a Schottky junction is formed at the boundary between the channel region, the source region, and the drain region. Since the potential barrier of the Schottky junction is smaller than the potential barrier of the pn junction, a current can be flowed by applying a low voltage, and thus low power consumption can be realized.
However, the memory transistor with this structure also has low resistance to channel hot carriers, and therefore, an offset is easily generated, and the deterioration of the S value, the deterioration of the on-current, and the like become remarkable.

Further, for example, an element made of a semiconductor formed on a glass substrate, for example, an element formed on a low melting point inorganic semiconductor such as Ge, or a material having a relatively low melting point or softening point such as metal is used for the gate electrode. Processes after implanting impurities into at least the source region and the drain region, such as devices and devices using a high dielectric constant film (for example, HfO ₂ , ZrO ₂ , Ta ₂ O _5, etc.) as part of the charge retention film However, when it is performed at a low temperature of about 600 ° C. or lower, the activation rate of impurities in the source region and the drain region is low. For this reason, the carrier density of the source region and the drain region is not sufficiently high, and therefore the characteristic deterioration due to hot carriers becomes more remarkable.

Data is generally written by channel hot carriers or carrier injection into the charge holding film using FN (Fowler-Nordheim) type tunneling from the substrate. Ideally, the data is erased by injecting substantially the same amount of charge having a polarity opposite to that of the charge into a region of the charge holding film where the charge has been captured by the data write operation.
However, data erasure is generally performed by carrier injection into a charge holding film using hot carriers generated by FN type tunneling injection from the substrate or band-to-band tunneling in the vicinity of the drain (or source) junction. However, it is not easy to align the carrier injection position at the time of data erasing with respect to the region where the charge is captured by the data write operation in the charge holding film, and to inject substantially the same amount of charge having the opposite polarity to the charge. Absent. Therefore, over-erasure is likely to occur, and device characteristics are likely to be deteriorated.

In particular, when an element is formed on a thin-film semiconductor on an SOI (Silicon-on-Insulator) substrate or a glass substrate, since there is no body contact, a carrier having a polarity opposite to that of the channel carrier is removed from the semiconductor by FN tunneling. It is impossible to inject into the charge holding film or carrier injection into the charge holding film by band-to-band tunneling. Even if the body contact is provided, the element area becomes very large, or the semiconductor region covered by the gate electrode through the charge retention film becomes large, so that the capacitance between the gate electrode and the semiconductor increases, and the reading speed is increased. There is a problem of inviting a decline.
JP 2004-296852 A

  SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to provide a semiconductor memory device that can suppress deterioration of characteristics due to hot carriers without an increase in parasitic resistance and a manufacturing method thereof, and to require a body contact. It is another object of the present invention to provide a data erasure driving method that suppresses over-erasure.

  In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention includes a semiconductor layer, a charge holding film formed on the semiconductor layer, a gate electrode provided on the charge holding film, and the semiconductor The layer has a source / drain region made of a compound of a semiconductor and a metal, which is provided so as to overlap the gate electrode.

According to the semiconductor memory device having the above configuration, since the source / drain regions made of a compound of a semiconductor and a metal overlap with the gate electrode, channel hot carriers generated at the time of data writing or the like are generated in the charge retention film or the source. The source / drain region is not depleted by being trapped in an insulating film near the drain region. Therefore, the source / drain region can be prevented from being offset with respect to the gate electrode. Thereby, it is possible to prevent the deterioration of the S value during reading and the deterioration of the on-current.
For example, when channel hot carriers are injected into the charge holding film near the drain region, the band is modulated on the semiconductor surface under the carrier injection region, and an accumulation layer is formed. Since the band on the surface of the semiconductor layer is modulated, the width of the Schottky barrier between the semiconductor layer and the drain region is reduced, and the Schottky barrier height is reduced due to the mirror image effect. Accordingly, since the drain region and the storage layer are electrically connected, data can be erased by FN (Fowler-Nordheim) type tunneling of carriers in the storage layer by applying a bias voltage between the drain region and the gate electrode. Become. Therefore, data can be erased without body contact.

  In one embodiment, the overlap length is 2 to 100 nm. By setting the overlap length to 2 nm or more, a Schottky barrier height modulation effect by applying a voltage to the gate electrode can be reliably obtained. When the overlap length is smaller than 2 nm, the surface of the compound compound of the semiconductor and the metal is slightly oxidized by residual oxygen in the atmosphere in the heat treatment process during the manufacturing process. The barrier height modulation effect may not be obtained. Further, if the overlap length is excessively large, the data read speed is reduced due to the increase of the overlap capacitance, the leakage current between the gate electrode and the source / drain region is increased, and a short circuit is caused. The following is desirable. Therefore, the length of the overlap is desirably 2 to 100 nm, but more preferably 5 to 30 nm. This makes it possible to achieve both a sufficient overlap length for modulation of the Schottky barrier height and a sufficiently small overlap capacity, so that data reading and data writing by channel hot carrier injection are performed at high speed. I can do it. Further, the increase in leakage current between the gate electrode and the source / drain region and the probability of short circuit are very small, so that the reliability of the element is improved.

In one embodiment of the semiconductor memory device, the compound of the semiconductor and the metal is a compound of a semiconductor constituting the semiconductor layer and Ni, Co, Ti, Er, Yb, or Pt. .
The metal is preferably Ni, Co, Ti, Er, Yb, or Pt. For example, when the semiconductor layer is silicon, Ni, Co, Ti, Er, Yb, and Pt react with silicon at 600 ° C. or lower to form a metal silicide, so that this metal silicide can be used as a source / drain. . For example, NiSi is about 320 to 550 ° C., CoSi is about 400 to 600 ° C., TiSi is about 500 to 600 ° C., ErSi _x (typically x = 1.7) is about 400 to 600 ° C., YbSi _x (x ≈2) can be formed at about 600 ° C., and PtSi can be formed at about 400 to 600 ° C. In addition, although the composition ratio of the metal of these metal silicides and a silicon | silicone has shown typical, the composition ratio can change with process conditions, such as reaction temperature. Such a metal silicide has a very low resistance compared to the impurity diffusion layer, and the metal silicide / silicon interface exhibits extremely stable and highly reproducible rectification characteristics compared to a normal metal / silicon interface. Good device characteristics can be easily obtained. Further, since these metal silicides can be formed by a self-aligned silicidation process, the source / drain regions can be easily formed.

In one embodiment, the semiconductor layer is silicon, and the compound of the semiconductor and the metal is NiSi.
According to the semiconductor memory device having the above-described configuration, NiSi is the lowest resistance phase among nickel silicides, and has a lower resistance than other metal silicides that can be formed at 600 ° C. or lower. The data reading speed can be improved. Since NiSi can be formed at about 320 to 550 ° C., a low resistance source / drain can be formed at a process temperature of 600 ° C. or less.

In one embodiment, the semiconductor layer has a region containing an impurity having a conductivity type opposite to that of the semiconductor layer in a region in contact with the source / drain region. The conductivity type of the semiconductor is preferably N type.
According to the semiconductor memory device having the above configuration, when a voltage is applied at the time of writing, the height and width of the Schottky barrier between the semiconductor layer and the source / drain regions are modulated, and carriers passing through the channel under the gate electrode are modulated. As a result, the height of the Schottky barrier is effectively reduced, so that the parasitic resistance is reduced. At the same time, the height of the Schottky barrier with respect to the carrier having a polarity opposite to that of the carrier is increased, so that a junction leakage current when a reverse bias is applied can be suppressed. Since the semiconductor memory device of the present invention is a P-type MOS, a high-speed write operation and erase operation can be realized at a low voltage.
Note that a region containing an impurity having a conductivity type opposite to that of the semiconductor layer may be completely depleted.

In one embodiment, the charge retention film is a laminated film in which silicon oxide, silicon nitride, and silicon oxide are sequentially deposited.
According to the semiconductor memory device having the above-described configuration, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type memory element can be configured.

In one embodiment, the charge retention film is a stacked film in which silicon oxide, a conductive material, and silicon oxide are sequentially deposited, or silicon oxide, a conductive material, silicon oxide, silicon nitride, and oxide. It is a laminated film deposited in the order of silicon.
According to the semiconductor memory device configured as described above, a floating gate type memory element can be configured.

In one embodiment, the conductive material is any one of Si, TiN, TaN, NiSi, and Ge.
According to the semiconductor memory device having the above configuration, a floating gate type memory element can be easily configured by using any one of Si, TiN, TaN, NiSi, and Ge as the conductive material. Further, since the Fermi level of Si, TiN, TaN, NiSi, and Ge is located near the center of the band gap of silicon oxide, good memory retention characteristics can be obtained. Further, since the Fermi level of Si, TiN, TaN, NiSi, and Ge is located near the center of the band gap of silicon, particularly when the semiconductor is silicon, good data storage characteristics can be obtained.

In one embodiment of the semiconductor memory device, the semiconductor is provided on a glass substrate.
According to the semiconductor memory device having the above configuration, the process temperature is limited to about 600 ° C. or less. In contrast to the commonly used source / drain regions formed by high-concentration impurity doping, offsets due to channel hot carriers are likely to occur because a sufficient activation rate cannot be obtained. In the device, since the source / drain regions are not depleted, characteristic deterioration due to channel hot carriers is unlikely to occur.

In one embodiment, the semiconductor is Ge or amorphous silicon.
According to the semiconductor memory device having the above configuration, the process temperature is limited to about 600 ° C. or less. In contrast to the commonly used source / drain regions formed by high-concentration impurity doping, offsets due to channel hot carriers are likely to occur because a sufficient activation rate cannot be obtained. In the device, since the source / drain regions are not depleted, characteristic deterioration due to channel hot carriers is unlikely to occur.

The method of manufacturing a semiconductor memory device according to the second aspect of the present invention includes a step of forming a source / drain region with a compound of a semiconductor and a metal in a semiconductor layer, and a step of forming a charge retention film on the semiconductor layer. And a step of forming a gate electrode on the charge retention film so as to overlap the source / drain regions in this order.
According to the method for manufacturing a semiconductor memory device, the semiconductor memory device can be easily manufactured.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: forming a charge holding film on a semiconductor layer; forming a gate electrode on the charge holding film; And a step of forming a source / drain region by a chemical reaction between a semiconductor and a metal in a self-aligned position in this order.
According to the manufacturing method of the semiconductor memory device having the above-described configuration, the source / drain regions can be formed in a self-aligned manner with respect to the gate electrode, so that variations in element characteristics can be reduced.

  According to a fourth aspect of the present invention, there is provided a data erasing drive method for a semiconductor memory device, comprising: a gate electrode that is in contact with a region in the charge retention film in which charges are trapped; When the polarity of the charge is positive, the potential of the gate electrode is higher, or when the polarity of the charge is negative, the potential of the gate electrode is lower. , A potential gradient is provided.

  According to the data erasing method of the semiconductor memory device having the above configuration, for example, when channel hot carriers are injected into the charge retention film in the vicinity of the drain region, the band is modulated on the surface of the semiconductor layer under the carrier injection region, and the storage layer is formed. It is formed. Since the band on the surface of the semiconductor layer is modulated, the width of the Schottky barrier between the semiconductor layer and the drain region is reduced, and the Schottky barrier height is reduced due to the mirror image effect. Accordingly, since the drain region and the storage layer are electrically connected, data can be erased by FN (Fowler-Nordheim) type tunneling of carriers in the storage layer by applying a bias voltage between the drain region and the gate electrode. Become. Therefore, since data can be erased without a body contact, the present invention can also be applied when an element is formed on a thin film semiconductor layer grown on an SOI substrate or a glass substrate.

  Further, the FN type tunneling occurs most efficiently in the region where the channel hot carriers are injected in the charge retention film. Therefore, the FN type tunneling is selectively opposite to the channel hot carriers in the region where the channel hot carriers are injected. Data can be erased by injecting polar carriers. Further, as the net amount of charge trapped in the charge retention film decreases, the amount of modulation of the Schottky barrier height and width decreases, so the amount of carrier injection by FN tunneling decreases. Therefore, over-erasure can be suppressed and deterioration of element characteristics can be prevented.

  As is apparent from the above, according to the semiconductor memory device, the manufacturing method thereof, and the data erasing driving method of the present invention, there are provided a semiconductor memory device and a manufacturing method thereof capable of suppressing characteristic deterioration due to hot carriers without increasing parasitic resistance. Further, there is provided a data erasure driving method that does not require a body contact and suppresses over-erasure.

Hereinafter, a semiconductor memory device and a manufacturing method thereof according to the present invention will be described in detail with reference to illustrated embodiments.
In addition, in each embodiment, although it demonstrates centering on the case where the polycrystalline silicon formed on the glass substrate is used, the semiconductor which can be used for this invention is not limited to the polycrystalline silicon formed on the said glass substrate, Any semiconductor can be used.
However, for example, an element made of a semiconductor formed on a glass substrate, for example, an element formed on a low melting point inorganic semiconductor such as Ge, or a material having a relatively low melting point or softening point such as a metal is used for the gate electrode. Processes after implanting impurities into at least the source region and the drain region, such as devices and devices using a high dielectric constant film (for example, HfO ₂ , ZrO ₂ , Ta ₂ O _5, etc.) as part of the charge retention film Is limited to about 600 ° C. or less, the impurity activation rate in the source region and drain region formed by doping impurities in the semiconductor at a high concentration is lowered, and the characteristic deterioration due to hot carriers is increased. The effect of improving the characteristics according to the present invention is particularly great.

  In each embodiment, the description is focused on a P-type channel element. However, an N-type channel element can be formed by reversing the conductivity type of impurities and reversing holes and electrons. Of course, both types of elements may be formed on the same substrate.

(Embodiment 1)
The semiconductor memory device according to the first embodiment forms a MIS (Metal-Insulator-Semiconductor) type field effect transistor having an ONO film as a charge retention film on polycrystalline silicon grown on a glass substrate, the source region and The drain region is made of NiSi and is disposed so as to partially overlap the gate electrode.

1A to 1E are cross-sectional views of a semiconductor memory device shown in the order of steps for explaining the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention, and FIG. 2 shows the first embodiment of the present invention. Sectional drawing of the semiconductor device of this is shown.
As shown in FIG. 1A, a resist 4 is applied on a polycrystalline silicon 3 in which N-type polycrystalline silicon grown on a glass substrate 1 via a protective insulating film 2 is formed in an island shape, and lithography technology is applied. Thus, regions to be the source region 5 and the drain region 6 are opened. The polycrystalline silicon is preferably CG silicon (continuous grain boundary silicon). For example, the island-shaped polycrystalline silicon 3 forms one island-shaped polycrystalline silicon corresponding to one pixel of the liquid crystal display device. Subsequently, a Ni film and then a TiN film are deposited by sputtering, for example, to form a TiN / Ni laminated film 5. The thickness of the Ni film is preferably not less than 1/4 of the thickness of the polycrystalline silicon 3 and not more than the thickness of the polycrystalline silicon 3, and is not less than 1/3 and not more than 2/3 of the thickness of the polycrystalline silicon 3. It is more desirable to obtain the best characteristics. By setting the thickness of the Ni film to ¼ or more of the thickness of the polycrystalline silicon 3, nickel silicide formed in a later step can be formed in contact with the protective insulating film 2. It can be reduced. Further, if the thickness of the Ni film is larger than the thickness of the polycrystalline silicon 3, an excessive silicidation reaction occurs, and the overlap of the source / drain region with the gate electrode increases, and the gate electrode and the source / drain region are short-circuited. Problems such as cause are likely to occur. Further, the TiN film is preferably 10 nm or more and 100 nm or less. The TiN film has an effect of preventing oxidation of a metal such as Ni or a semiconductor and metal compound such as nickel silicide during the silicidation reaction, but a sufficient effect cannot be obtained when the film thickness is 10 nm or less. If the TiN film is too thick, the sputtering time becomes longer, and it takes a very long time to remove the TiN film in a later process, causing a short circuit between the gate electrode and the source / drain region. Therefore, the film thickness is preferably 100 nm or less.
Co, Ti, Er, Yb, or Pt may be used instead of Ni.

Note that although N-type polycrystalline silicon is used for the semiconductor layer here, the conductivity type is not limited to N-type, and any type may be used as long as the completed transistor can operate as a P-type channel element. For example, P-type polycrystalline silicon is used to operate as an N-type channel element by the effect of fixed charges in an insulating film formed in contact with polycrystalline silicon or the interface state at the grain boundary of polycrystalline silicon. Is also possible. Similarly, when an N-type channel element is formed, conductive polycrystalline silicon that operates as an N-type channel element may be used. However, in the first embodiment, the P-type channel element achieves a faster write operation and erase operation at a lower voltage than the N-type channel element, and the memory window becomes larger.
The thickness of the semiconductor layer is desirably 10 to 100 nm, and more desirably 30 to 60 nm. Since the threshold value of the transistor depends on the thickness of the semiconductor layer, if the thickness is 10 nm or less, the variation in threshold value due to the variation in the thickness of the semiconductor layer increases, making it difficult to secure a memory window. In order to suppress leakage current, the thickness of the semiconductor layer is preferably 100 nm or less. If the thickness of the semiconductor layer is 30 to 60 nm, the effect of the memory of the present invention can be obtained more remarkably.

Next, as shown in FIG. 1B, the TiN / Ni laminated film 5 on the resist is lifted off by performing ultrasonic cleaning in a resist stripping solution. Thereafter, it is preferable to sufficiently wash with an organic solvent such as acetone and IPA (isopropyl alcohol) and ultrapure water so that the peeled Ni does not reattach.
Next, as shown in FIG. 1C, RTA (Rapid Thermal Annealing) is performed at about 450 ° C. to form the NiSi region 6. The temperature of RTA may be about 320 ° C to 550 ° C. The RTA time may be, for example, 30 seconds to 10 minutes. Thereafter, unreacted Ni is removed in a mixed solution of sulfuric acid and hydrogen peroxide solution. The NiSi region 6 functions as a source and a drain.
RTA temperatures when Co, Ti, Er, Yb, or Pt is used instead of Ni are about 400 to 600 ° C., about 500 to 600 ° C., about 400 to 600 ° C., about 600 ° C., and 400 to 600, respectively. By setting the temperature to about 0 ° C., CoSi, TiSi, ErSi _x (typically x = 1.7), YbSi _x (x≈2), and PtSi can be formed. Although the composition ratio of metal to silicon in these metal silicides is typical, the composition ratio may vary depending on process conditions such as the RTA temperature.

NiSi formed here is the lowest resistance phase among nickel silicides and is most preferable. However, Ni _x Si (x≈2) may be formed by performing RTA at about 320 ° C. or less, or 550 to 600. NiSi _x (x≈2) may be formed by performing RTA at about 0 ° C. When using a semiconductor substrate to which a high temperature process such as a single crystal silicon substrate or an SOI (Silicon-on-Insulator) substrate is used, NiSi _x (x≈2) is formed by performing RTA at about 550 ° C. or more. It is also possible.

Thus, since NiSi is a low resistance silicide that can be formed at about 600 ° C. or lower, for example, it is formed on a low melting point inorganic semiconductor such as an element formed on a semiconductor grown on a glass substrate, for example, Ge. Device, a device using a material having a relatively low melting point or softening point such as a metal for the gate electrode, a high dielectric constant film (for example, HfO ₂ , ZrO ₂ , Ta ₂ O _5, etc.) as part of the charge retention film This is particularly effective when at least the source region and drain region forming step and the subsequent processes are limited to about 600 ° C. or lower, as in the case of manufacturing an element or the like in which is used. Alternatively, an Au layer may be deposited instead of the TiN / Ni laminated film 5 to form gold silicide.

  Next, as shown in FIG. 1D, the first silicon oxide film is 10 nm, the silicon nitride film is 20 nm, and the second silicon oxide film is formed by, for example, CVD (Chemical Vapor Deposition). An ONO (Oxide-Nitride-Oxide) film 11 is formed by sequentially depositing 20 nm. Each film thickness is arbitrary, but the film thickness of the second silicon oxide film is preferably larger than the film thickness of the first silicon oxide film. This is because carrier injection from the gate electrode can be suppressed particularly when carrier injection by an FN (Fowler-Nordheim) type tunnel is performed.

Further, instead of the ONO film 11, by using a laminated film deposited in the order of silicon oxide, silicon, silicon oxide, a laminated film deposited in the order of silicon oxide, polycrystalline silicon, ONO film, etc., a floating gate type storage element It can also be. The silicon in the laminated film is not limited to single crystal silicon but may be amorphous silicon or polycrystalline silicon.
Thereafter, a gate conductive film 12 is deposited. For example, a TaN film and a W film may be sequentially deposited by sputtering, for example, 50 nm and 150 nm. Each film thickness is arbitrary.

Next, after applying a resist and patterning the resist by a lithography technique, the ONO film 11 and the gate conductive film 12 are etched by, for example, RIE (Reactive Ion Etching), and FIG. As shown in FIG. 2, a gate insulating film 21 and a gate electrode 22 are formed. At this time, patterning is performed so that both ends of the gate electrode 22 partially overlap the upper portion of the NiSi region 6. The length T in the gate length direction in which the gate electrode 22 overlaps the NiSi region 6 is formed to be 2 to 100 nm. Further, the overlapping length is preferably 5 to 30 nm.
Next, as shown in FIG. 2, by forming the interlayer insulating film 25 and the upper wirings 26 and 27, the semiconductor memory device of the present invention is completed.

  In the semiconductor memory device according to the present invention, since the source region 23 and the drain region 24 are formed of NiSi, depletion occurs even when hot carriers are injected into the insulating film on the ends of the source region 23 and the drain region 24 made of NiSi. It does not become. Therefore, characteristic deterioration due to hot carriers can be extremely suppressed. Further, since the source region 23 and the drain region 24 are formed so as to overlap the gate electrode 22, the height of the Schottky barrier between NiSi / polycrystalline silicon forming the source region 23 and the drain region 24 is increased. And the width are modulated by applying a bias voltage to the gate electrode 13.

Next, a memory operation in the semiconductor memory device of the present invention will be described.
Hereinafter, one of the source region 23 and the drain region 24 made of NiSi is called a first electrode, and the other is called a second electrode.
First, data writing is performed by injecting channel hot carriers (holes) generated by applying a positive bias to the gate electrode 22 and the first electrode into the charge holding film 21 in the vicinity of the first electrode. For example, 10V is applied to the gate electrode 22, 10V is applied to the first electrode, and 0V is applied to the second electrode.
At this time, since the source region 23 and the drain region 24 made of a compound of a semiconductor and a metal overlap the gate electrode 22, channel hot carriers generated at the time of data writing or the like are generated in the charge holding film 21 and the source region 23. By being trapped in the insulating film near the drain region 24, the source region 23 and the drain region 24 can be prevented from being depleted and offset with respect to the gate electrode 22. Therefore, it is possible to prevent the deterioration of the S value during reading and the deterioration of the on-current.

  For example, data is read by applying 5 V to the gate electrode 22, 0 V to the first electrode, and applying a lower positive bias, for example 3 V, to the second electrode than when writing. When holes are trapped in the charge holding film 21 in the vicinity of the first electrode, the threshold voltage shifts positively and the current between the first electrode and the second electrode decreases, so that data can be read out. It becomes.

Data erasure will be described with reference to FIG. FIG. 3 shows only a part of FIG. 2 and shows a part necessary for explaining the data erasing operation.
As shown in FIG. 3, when holes 504 are trapped in the ONO film 100 near the first electrode 501, an electron accumulation layer 503 is induced under the ONO film 100 in which holes are trapped. The Further, since the height and width of the Schottky barrier between the first electrode 501 and the storage layer 503 are modulated by the electric field generated by the trapped holes 504, the electric field between the first electrode 501 and the storage layer 503 is modulated. The resistance becomes smaller. When the density of the trapped holes 504 is sufficiently high, the first electrode 501 and the storage layer 503 are ohmically connected. In this case, for example, when −40 V is applied to the gate electrode 22, 0 V is applied to the first electrode 501, and the second electrode 502 is open, electron injection from the polycrystalline silicon 3 to the ONO film 100 is performed by FN tunneling. Happens.

At this time, since the electric field between the trapped holes 504 and the polycrystalline silicon 3 is the largest among the ONO film 100, the electron injection by the FN type tunneling from the storage layer 503 to the ONO film 100 is the most efficient. It often happens and therefore the trapped holes 504 can be selectively canceled.
Further, if the net density of the holes 504 captured by electron injection is reduced, the efficiency of electron injection by FN tunneling is reduced, and the height of the Schottky barrier between the polycrystalline silicon 3 and the first electrode 501 is reduced. In addition, the amount of modulation of the width decreases, and the efficiency of electron supply from the first electrode 501 to the polycrystalline silicon 3 decreases. Therefore, the net density of the trapped holes 504 is reduced, and the electron injection by the FN type tunneling is automatically suppressed, and overerasing can be suppressed.
It should be noted that by switching the applied voltage of the first electrode and the second electrode, data writing, data reading, data reading by channel hot carrier (hole) injection into the ONO film 100 in the vicinity of the second electrode are performed. It can also be erased. That is, 2 bits of data can be stored per element.

(Embodiment 2)
Similar to the semiconductor memory device of the first embodiment, the semiconductor memory device of the second embodiment is a MIS (Metal-Insulator-Semiconductor) type electric field having an ONO film as a charge retention film on polycrystalline silicon grown on a glass substrate. An effect transistor is formed, and its source region and drain region are made of NiSi and are arranged so as to overlap the gate electrode. Furthermore, the semiconductor memory device of Embodiment 2 is characterized in that P-type regions are formed at the source region end portion and the drain region end portion by solid-layer diffusion from NiSi.

4F to 4H are cross-sectional views of the semiconductor device shown in the order of steps for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention.
First, as shown in the first embodiment, the steps of FIGS. 1A to 1E are performed.
Next, as shown in FIG. 4F, a third silicon oxide film 31 is deposited by, eg, CVD. Here, the third silicon oxide film 31 functions as an implantation protective film at the time of B implantation described later, and can suppress contamination and damage at the time of B implantation. Furthermore, in the annealing step described later, B can be prevented from diffusing outward, so that solid phase diffusion from the source region 5 and drain region 6 made of NiSi to the polycrystalline silicon 3 occurs efficiently, and P-type The B concentration in the region 32 can be increased.

Next, as shown in FIG. 4G, B is ion-implanted into the NiSi region 6 using the gate electrode 22 as a mask, and then annealed at about 400 ° C. in a nitrogen atmosphere or an inert gas atmosphere. The annealing temperature may be about 350 to 550 ° C., but is preferably equal to or lower than the temperature at which the NiSi region 6 is formed. By this annealing, B is segregated near the NiSi region 6 / polycrystalline silicon 3 interface by solid phase diffusion from the NiSi region 6, and has a relatively high concentration in the polycrystalline silicon 3 near the source region 5 and the drain region 6. A P-type region 32 is formed.
The P-type region 32 may be completely depleted. The P-type region 32 effectively reduces the Schottky barrier height for the holes between the NiSi region 6 and the polycrystalline silicon 3, so that the parasitic resistance can be reduced and the Schottky barrier height for the electrons can be reduced. Since it increases effectively, junction leakage during reverse bias application can be suppressed. Note that In may be used instead of B. In the case of an N-type channel element, the same effect can be obtained by using any one of P, As, Sb, and S instead of B.

Even if the P-type region 32 is depleted by hot carrier injection into the ONO film 21, the NiSi region 6 is formed so as to overlap the gate electrode 22. Little degradation occurs.
Next, as shown in FIG. 4H, the interlayer insulating film 25 and the upper wirings 26 and 27 are formed to complete the semiconductor memory device of the present invention.
The write operation, read operation, and erase operation of the second embodiment are the same as those of the first embodiment.

(Embodiment 3)
Similar to the semiconductor memory device of the first embodiment, the semiconductor memory device of the third embodiment is a MIS (Metal-Insulator-Semiconductor) type electric field having an ONO film as a charge retention film on polycrystalline silicon grown on a glass substrate. The effect transistor is configured, and the source region and the drain region are made of NiSi formed by a self-aligned silicide process, and are arranged so as to overlap the gate electrode.

FIG. 5A to FIG. 6F are cross-sectional views of the semiconductor device shown in the order of steps for explaining the method of manufacturing the semiconductor device according to the third embodiment of the present invention.
As shown in FIG. 5A, on a polycrystalline silicon 3 in which P-type polycrystalline silicon grown on a glass substrate 1 through a protective insulating film 2 is formed in an island shape, for example, CVD (Chemical Vapor Deposition; The first silicon oxide film is deposited by 10 nm, the silicon nitride film is deposited by 20 nm, and the second silicon oxide film is deposited by 20 nm by sequential deposition to form the ONO film 11, and then the TaN film is deposited by 50 nm and W A film 12 is sequentially deposited to 150 nm to form a gate conductive film 12.
The thickness of the semiconductor layer is desirably 10 to 100 nm, and more desirably 30 to 60 nm. Since the threshold value of the transistor depends on the thickness of the semiconductor layer, if the thickness is 10 nm or less, the variation in threshold value due to the variation in the thickness of the semiconductor layer increases, making it difficult to secure a memory window. In order to suppress leakage current, the thickness of the semiconductor layer is preferably 100 nm or less. If the thickness of the semiconductor layer is 30 to 60 nm, the effect of the memory of the present invention can be obtained more remarkably.

  Instead of the ONO film 11, a stacked gate film deposited in the order of silicon oxide, silicon and silicon oxide, a stacked film deposited in the order of silicon oxide, silicon and ONO film, etc. may be used to form a floating gate type memory element. it can. The silicon in the laminated film may be amorphous silicon or polycrystalline silicon. Further, TiN, TaN, or Ge may be used instead of silicon in the laminated film.

Next, after applying a resist and patterning the resist by a lithography technique, the gate conductive film 11 and the ONO film 12 are etched by, for example, RIE (Reactive Ion Etching), as shown in FIG. A gate insulating film 21 and a gate electrode 22 are formed. Thereafter, a third silicon oxide film 35 is deposited by about 10 to 20 nm by, for example, the CVD method.
Next, as shown in FIG. 5C, the gate sidewall 36 is formed by etching back the third silicon oxide film 35 by RIE. The thickness of the gate side wall 36 is preferably smaller than that of the polycrystalline silicon 3. This is easily realized by setting the film thickness of the third silicon oxide film 35 to be smaller than the film thickness of the polycrystalline silicon 3. By making the thickness of the gate sidewall 36 smaller than the thickness of the polycrystalline silicon 3, it is easy to form a metal silicide (for example, NiSi) formed in a later process so as to overlap the gate electrode 22. It becomes.

Next, as shown in FIG. 6D, a Ni film and then a TiN film are deposited by sputtering, for example, to form a TiN / Ni laminated film 5. The thickness of the Ni film is preferably not less than 1/4 of the thickness of the polycrystalline silicon 3 and not more than the thickness of the polycrystalline silicon 3, and is not less than 1/3 and not more than 2/3 of the thickness of the polycrystalline silicon 3. It is more desirable to obtain the best characteristics. By setting the thickness of the Ni film to ¼ or more of the thickness of the polycrystalline silicon 3, nickel silicide formed in a later step can be formed in contact with the protective insulating film 2. It can be reduced. Further, if the thickness of the Ni film is larger than the thickness of the polycrystalline silicon 3, an excessive silicidation reaction occurs, and the overlap of the source / drain region with the gate electrode increases, and the gate electrode and the source / drain region are short-circuited. Problems such as cause are likely to occur. Further, the TiN film is preferably 10 nm or more and 100 nm or less. The TiN film has an effect of preventing oxidation of a metal such as Ni or a semiconductor and metal compound such as nickel silicide during the silicidation reaction, but a sufficient effect cannot be obtained when the film thickness is 10 nm or less. If the TiN film is too thick, the sputtering time becomes longer, and it takes a very long time to remove the TiN film in a later process, causing a short circuit between the gate electrode and the source / drain region. Therefore, the film thickness is preferably 100 nm or less.
Co, Ti, Er, Yb, or Pt may be used instead of Ni.

Next, as shown in FIG. 6E, the NiSi region 38 is formed in a self-aligned manner by performing RTA at about 450 ° C. At this time, the NiSi region 38 is formed so as to overlap the gate electrode 22. Usually, by performing RTA at about 320 ° C. to about 550 ° C., NiSi of the lowest resistance phase is formed, and is most preferable, but NiSi _y (y ≠ 1) may be obtained due to excess or deficiency of silicon. Thereafter, unreacted Ni is removed in a mixed solution of sulfuric acid and hydrogen peroxide solution. The NiSi region 38 functions as a source and a drain. The distance at which the NiSi region 38 overlaps the gate electrode 22 can be implemented by controlling the thickness of the Ni film.
The length T in the gate length direction in which the gate electrode 22 overlaps the NiSi region 38 is formed to be 2 to 100 nm. By setting the overlap length to 2 nm or more, a Schottky barrier height modulation effect by applying a voltage to the gate electrode can be reliably obtained. When the overlap length is smaller than 2 nm, the surface of the compound compound of the semiconductor and the metal is slightly oxidized by residual oxygen in the atmosphere in the heat treatment process during the manufacturing process. The barrier height modulation effect may not be obtained. Further, if the overlap length is excessively large, the data read speed is reduced due to the increase of the overlap capacitance, the leakage current between the gate electrode and the source / drain region is increased, and a short circuit is caused. The following is desirable. The overlap length is desirably 2 to 100 nm, but more preferably 5 to 30 nm. This makes it possible to achieve both a sufficient overlap length for modulation of the Schottky barrier height and a sufficiently small overlap capacity, so that data reading and data writing by channel hot carrier injection are performed at high speed. I can do it. Further, the increase in leakage current between the gate electrode and the source / drain region and the probability of short circuit are very small, so that the reliability of the element is improved.
RTA temperatures when Co, Ti, Er, Yb, or Pt is used instead of Ni are about 400 to 600 ° C., about 500 to 600 ° C., about 400 to 600 ° C., about 600 ° C., and 400 to 600, respectively. By setting the temperature to about 0 ° C., CoSi, TiSi, ErSi _x (typically x = 1.7), YbSi _x (x≈2), and PtSi can be formed. Although the composition ratio of metal to silicon in these metal silicides is typical, the composition ratio may vary depending on process conditions such as the RTA temperature.

Thus, since NiSi is a low resistance silicide that can be formed at about 600 ° C. or lower, it is formed on a low melting point inorganic semiconductor such as an element formed on a semiconductor grown on a glass substrate, such as Ge. A device in which a material having a relatively low melting point or softening point such as a metal is used for the gate electrode, and a high dielectric constant film (for example, HfO ₂ , ZrO ₂ , Ta ₂ O _5, etc.) in a part of the charge retention film. This is particularly effective when at least the source region and drain region forming steps and the subsequent processes are limited to about 600 ° C. or lower, as in the case of manufacturing elements used.
Next, as shown in FIG. 5F, by forming the interlayer insulating film 25 and the upper wirings 26 and 27, the semiconductor memory device of the present invention is completed.
The write operation, read operation, and erase operation of the third embodiment are the same as those of the first embodiment.

(Embodiment 4)
The semiconductor memory device according to the fourth embodiment has a structure of the semiconductor memory device according to the third embodiment in which P-type regions are formed at the source region end portion and the drain region end portion by solid layer diffusion from the NiSi region 38. .
7F to 7H are cross-sectional views of the semiconductor device shown in the order of steps for explaining the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention.

First, as shown in the third embodiment, the steps of FIGS. 5A to 6E are performed.
Next, as shown in FIG. 7F, after the volume of the fourth silicon oxide film 41 is about 10 nm, B is ion-implanted into the polycrystalline silicon 3 using the gate electrode 22 and the gate sidewall 36 as a mask.
Next, as shown in FIG. 7G, annealing is performed at about 400 ° C. in a nitrogen atmosphere or an inert gas atmosphere. The annealing temperature may be about 350 to 550 ° C., but is preferably equal to or lower than the temperature at which the NiSi region 6 is formed. By this annealing, B segregates near the NiSi region 6 / polycrystalline silicon 3 interface, and a relatively high concentration P-type region 42 is formed in the polycrystalline silicon 3 near the NiSi region 6. The P-type region 42 may be completely depleted. This effectively reduces the Schottky barrier height for the holes between the NiSi region 6 / polycrystalline silicon 3, thereby reducing the parasitic resistance and effectively increasing the Schottky barrier height for the electrons. Since it becomes large, junction leakage can be suppressed. Note that In may be used instead of B. In the case of an N-type channel element, the same effect can be obtained by using any one of P, As, Sb, and S instead of B.
Next, as shown in FIG. 7H, the interlayer insulating film 25 and the upper wirings 26 and 27 are formed by a known method, thereby completing the semiconductor memory device of the present invention.
The write operation, read operation, and erase operation of the fourth embodiment are the same as those of the first embodiment.

It is a figure which shows the manufacturing process of the semiconductor memory device of 1st Embodiment of this invention. It is a figure which shows the last process of the semiconductor memory device of 1st Embodiment. In the semiconductor memory device of this invention, it is sectional drawing of a semiconductor memory device for demonstrating the data erasing method. It is a figure which shows the manufacturing process of the semiconductor memory device of 2nd Embodiment of this invention, and shows the manufacturing process of the semiconductor memory device following FIG.1 (e). It is a figure which shows the manufacturing process of the semiconductor memory device of 3rd Embodiment of this invention. FIG. 5 is a diagram for illustrating the manufacturing process for the semiconductor memory device according to the third embodiment, which is subsequent to FIG. 4. It is a figure which shows the manufacturing process of the semiconductor memory device of 4th Embodiment of this invention, and shows the manufacturing process of the semiconductor memory device following FIG.5 (e). It is sectional drawing of the memory element which has a MIS type field effect transistor structure using the single drain structure which is a prior art. It is sectional drawing for demonstrating the problem of the memory element which has a MIS type field effect transistor structure using the single drain structure which is a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Glass substrate 3 Polycrystalline silicon 4 Resist 5 TiN / Ni laminated film 6 NiSi area | region 21 ONO film | membrane 22 Gate electrode 26, 27 Upper electrode 32, 42 N-type area | region 31 3rd silicon oxide film 36 Gate side wall 41 4th oxidation Silicon film 100 ONO film 101 Conductive film for gate 501 First electrode 502 Second electrode 503 Storage layer 504 Captured holes

Claims (12)

A semiconductor layer;
A charge retention film formed on the semiconductor layer;
A gate electrode provided on the charge retention film;
A semiconductor memory device having a source / drain region made of a compound of a semiconductor and a metal provided on the semiconductor layer so as to partially overlap the gate electrode.   The semiconductor memory device according to claim 1, wherein a length of the overlap is 2 to 100 nm.   The semiconductor memory device according to claim 1, wherein the compound of the semiconductor and the metal is a compound of a semiconductor constituting the semiconductor layer and Ni, Co, Ti, Er, Yb, or Pt.   The semiconductor memory device according to claim 1, wherein the semiconductor layer is silicon, and the compound of the semiconductor and the metal is NiSi.   The semiconductor memory device according to claim 1, wherein the semiconductor layer includes a region containing an impurity having a conductivity type opposite to that of the semiconductor layer in a region where the semiconductor layer is in contact with the source / drain region.   The charge retention film may be a laminated film deposited in the order of silicon oxide, silicon nitride, silicon oxide, a laminated film deposited in the order of silicon oxide, conductive material, silicon oxide, or silicon oxide, conductive material, silicon oxide, The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a laminated film deposited in the order of silicon nitride and silicon oxide.   The semiconductor device according to claim 6, wherein the conductive material is any one of Si, TiN, TaN, NiSi, and Ge.   The semiconductor memory device according to claim 1, wherein the semiconductor layer is provided on a glass substrate. The semiconductor memory device according to claim 1, wherein the semiconductor layer is made of Ge or amorphous silicon. Forming a source / drain region with a compound of a semiconductor and a metal in the semiconductor layer;
Forming a charge retention film on the semiconductor layer;
And a step of forming a gate electrode on the charge retention film so as to overlap the source / drain regions in this order. Forming a charge retention film on the semiconductor layer;
Forming a gate electrode on the charge retention film;
A method of manufacturing a semiconductor memory device, wherein a step of forming a source / drain region by a chemical reaction between a semiconductor and a metal at a position self-aligned with the gate electrode is performed in this order.   When the polarity of the charge is positive between the gate electrode and the region of the source / drain region that is in contact with the region in which the charge in the charge retention film is trapped, the potential of the gate electrode 10. The semiconductor according to claim 1, wherein a potential gradient is applied so that the potential of the gate electrode is lower when the charge has a higher polarity or when the charge has a negative polarity. 11. A data erasing drive method for a storage device.

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