JP2006310831A - Semiconductor device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor device, a manufacturing method thereof, and a driving method thereof, through provision of a semiconductor device including a memory with a simple structure. <P>SOLUTION: A memory has a layer including an organic compound as a dielectric. By applying a voltage to a pair of electrodes, state change accompanied by abrupt change in volume (such as bubble generation) is generated between the pair of electrodes. Acting force based on the state change promotes short-circuiting between the pair of electrodes. Specifically, a bubble generating area is provided in a memory element to generate a bubble between a first conductive layer and a second conductive layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of storing data and transmitting / receiving data, a manufacturing method thereof, and a driving method thereof.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, development of semiconductor devices that transmit and receive data in a non-contact manner using electromagnetic waves or radio waves has been promoted, and these semiconductor devices are called RF (Radio Frequency) tags, wireless tags, electronic tags, transponders, and the like. . Most semiconductor devices currently in practical use have a circuit using a semiconductor substrate (also called an IC (Integrated Circuit) chip) and an antenna, and a memory and a control circuit are built in the IC chip. ing.

Semiconductor devices that can send and receive data without contact are in widespread use in some areas such as railway boarding cards and electronic money cards, but it is an urgent issue to provide inexpensive semiconductor devices for further spread. Met. In view of the above circumstances, an object of the present invention is to provide a semiconductor device including a memory having a simple structure, and to provide an inexpensive semiconductor device and a manufacturing method thereof.

The present invention provides a memory having a layer containing an organic compound as a dielectric, and applying a voltage between a pair of electrodes causes a state change accompanied by a steep volume change (such as bubble generation) between the pair of electrodes. . A short circuit between a pair of electrodes is promoted by an action force based on this state change.

  The configuration of the invention disclosed in this specification includes a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction perpendicular to the first direction, and a storage element. The memory element has a stacked structure of a first conductive layer constituting the bit line, a layer containing an organic compound, and a second conductive layer constituting the word line, and the memory element includes: A semiconductor device having a bubble generation region and generating bubbles between the first conductive layer and the second conductive layer.

  Note that the bubble generation region may be a part of the first conductive layer, a part of the layer containing an organic compound, or a part of the second conductive layer included in the memory element. For example, a conductive material that easily generates bubbles due to heat may be used as the first conductive layer material of the organic memory. The first conductive layer may be doped with an inert element such as nitrogen or argon. When the first conductive layer is formed by a sputtering method, the first conductive layer may be formed in an atmosphere containing an inert element such as nitrogen or argon, and the inert element may be included in the first conductive layer.

When a part of the layer containing an organic compound is used as a bubble generation region, a material that easily generates bubbles due to Joule heat generated by applying a voltage between a pair of electrodes is used as a dielectric of an organic memory. Good. For example, an organic substance that decomposes when an electron is supplied to generate gas, typically a carboxylate (such as ammonium benzoate or tetrabutylammonium acetate) can be used. In addition, when a layer containing an organic compound is formed using a coating method, a solvent that is easily vaporized is used in the coating process, so that bubbles are easily generated due to Joule heat generated by applying a voltage between a pair of electrodes. .

Moreover, if the fluidity at the time of melting of the layer containing the organic compound is increased, bubbles are likely to be generated. Accordingly, it is desirable to use a material having a low glass transition temperature for the layer containing an organic compound so that the layer can be easily melted when a voltage is applied. Another structure of the present invention is a plurality of bit lines extending in the first direction. And a plurality of word lines extending in a second direction perpendicular to the first direction, and a storage element, the storage element including a first conductive layer constituting the bit line, an organic compound And the organic compound containing layer has a glass transition temperature of 50 ° C. or higher and 200 ° C. or lower, preferably 50 ° C. or higher and 100 ° C. or lower. A semiconductor device characterized by containing an organic compound. If the glass transition temperature of the organic compound is less than 50 ° C., the initial characteristics of the organic memory are likely to be unstable and affected by heat generated from the outside (an integrated circuit, IC, panel, battery, etc. provided around the memory). There is a fear. In addition, when the glass transition temperature of the organic compound is higher than 200 ° C., it is difficult to melt unless a voltage is applied at a high voltage value or for a long time, so that the fluidity is small and bubbles are hardly generated.

In addition, when forming a layer containing an organic compound by vapor deposition, a film is formed in an atmosphere containing an inert element such as nitrogen or argon, and the inert element such as nitrogen or argon is included in the layer. Also good. In particular, a layer containing an organic compound formed by an evaporation method has a glass transition temperature as low as 200 ° C. or lower, and can be liquefied or vaporized at a heating temperature of 100 ° C. to 300 ° C.

Further, as the second conductive layer material of the organic memory, a conductive material that easily generates bubbles due to heat may be used. When the second conductive layer is formed using a vapor deposition method, a film may be formed in an atmosphere containing an inert element such as nitrogen or argon, and the inert element may be included in the second conductive layer.

  In each of the above configurations, the semiconductor device generates a bubble from the bubble generation region by applying a voltage between the first conductive layer and the second conductive layer, and a pressure based on the generation of the bubble. Thus, one of the features is that the first conductive layer and the second conductive layer are short-circuited to facilitate data writing to the memory element. Due to the pressure based on the generation of bubbles, the gap between the first conductive layer and the second conductive layer is partially varied, and the voltage is more concentrated at a location where the gap is narrower than other regions. Therefore, a short circuit is likely to occur. In addition, when bubbles generated by applying a voltage are gathered, it is difficult to apply a voltage to the gathered region.

  In each of the above structures, the semiconductor device generates bubbles from the bubble generation region by heat generated between the first conductive layer and the second conductive layer, and generates pressure by pressure based on the generation of bubbles. One feature is to facilitate writing to the memory element by partially displacing the distance between the first conductive layer and the second conductive layer.

In addition, minute bubbles (1 μm to 10 μm) are formed due to volume shrinkage that occurs when a voltage is applied. You may short-circuit the metal wiring of the upper and lower sides of the layer containing an organic compound through this bubble.

In addition, bubbles may be formed in advance before voltage application, and upper and lower metal wirings may be short-circuited through the bubbles. Another configuration of the present invention includes a plurality of bit lines extending in the first direction, A plurality of word lines extending in a second direction perpendicular to the first direction; and a memory cell including a memory element, wherein the memory element includes a first conductive layer constituting the bit line; And a layered structure of a layer containing an organic compound and a second conductive layer constituting the word line, and the memory element has bubbles between the first conductive layer and the second conductive layer. A semiconductor device characterized by the above.

If bubbles are formed in advance before the voltage is applied, bubbles are further generated by the heat generated between the first conductive layer and the second conductive layer when the voltage is applied. The pressure based on the memory element can facilitate writing by changing the distance between the first conductive layer and the second conductive layer.

In the above structure, the bubble overlaps part of the first conductive layer and part of the second conductive layer, and one part of the first conductive layer and one part of the second conductive layer are overlapped. The semiconductor device is characterized in that the distance from the part is larger than the other part.

One feature of the present invention is that a voltage is applied to a memory element including a stack of a first conductive layer, a layer containing an organic compound, and a second conductive layer, and the first conductive layer and the second conductive layer are applied. A bubble is generated between the conductive layer, and the writing based on the generation of the bubble facilitates the writing of the memory element by short-circuiting the first conductive layer and the second conductive layer. This is a method for driving a semiconductor device.

One feature of the present invention is that voltage is applied to a memory element including a stack of a first conductive layer, a layer containing an organic compound, and a second conductive layer, heat is generated in the memory element, and the memory element Bubbles are generated between the first conductive layer and the second conductive layer by the generated heat, and the space between the first conductive layer and the second conductive layer is generated by pressure based on the generation of the bubbles. This is a method for driving a semiconductor device, which facilitates writing data to the memory element by displacing the memory element.

Each of the above structures is a method for driving a semiconductor device, wherein the layer containing an organic compound contains an organic compound having a glass transition temperature of 50 ° C. to 200 ° C.

  According to the present invention, a semiconductor device including a memory with a simple structure can be provided, and an inexpensive semiconductor device can be provided. In addition, according to the present invention, writing into a memory cell can be performed with low power consumption.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and it is easy for those skilled in the art to make various changes in form and details without departing from the spirit and scope of the present invention. Understood. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
FIG. 1 is a cross-sectional view of an example of a semiconductor device of the present invention, specifically, a memory element including an organic compound layer (hereinafter also referred to as an organic memory).

FIG. 1A shows a cross-sectional view of two memory elements provided over a substrate 10 having an insulating surface. FIG. 1A shows a state before writing.

  On a substrate 10 having an insulating surface, a first conductive layer 11a constituting a bit line of a first memory element and a first conductive layer 11b constituting a bit line of a second memory element are provided. . As the first conductive layers 11a and 11b, a conductive material that easily generates bubbles due to heat may be used.

  In addition, an insulator 12 is provided so as to cover the peripheral edge portion of the first conductive layer. The insulator 12 is disposed at the boundary with the adjacent memory element and covers the periphery of the first conductive layers 11a and 11b. As the insulator 12, an inorganic material having oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like A single-layer structure such as these or a stacked structure thereof can be used. In addition, the insulator 12 is formed with a single layer or a stacked structure using an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or epoxy. Alternatively, an inorganic material and an organic material may be stacked.

  The second conductive layer 14 includes gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), One element selected from cobalt (Co), copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), or the like A single layer or a laminated structure made of an alloy containing a plurality of can be used. The second conductive layer 14 is preferably made of a material that does not allow bubbles generated when a voltage is applied between the pair of electrodes.

Further, a layer containing an organic compound (a layer 13a containing an organic compound of the first memory element and an organic compound of the second memory element) is interposed between the first conductive layers 11a and 11b and the second conductive layer 14. A layer 13b) is provided. As the layers 13a and 13b containing an organic compound, a layer made of an organic compound material having conductivity is provided in a single layer or a stacked structure. As a specific example of the organic compound material having conductivity, a material having carrier transportability can be used. The layers 13a and 13b containing an organic compound may be made of a material that easily generates bubbles due to heat.

  A cross-sectional view after data is written by applying a voltage to one of the two memory elements, that is, the first memory element is illustrated in FIG.

  When a voltage exceeding a certain voltage value is applied to the first conductive layer 11a and the second conductive layer 14 of the first memory element, the layer 13a containing the organic compound is melted and fluidized by Joule heat or the like. It becomes easy. Further, bubbles 16 are generated by Joule heat due to the application of a voltage, or partial peeling occurs near the interface between layers due to an impact accompanying voltage application, and the first conductive layer is generated by pressure based on the generation of the bubbles 16 and partial peeling. There is a variation in the distance between 11a and the second conductive layer. And since a voltage will concentrate more on the location where the space | interval became narrower than the other area | region, the short circuit location 15 is formed. In addition, the first conductive layer may be deformed and partially bulged by an impact due to voltage application, and bubbles or partial peeling may occur around the bulged portion.

  Thus, since the conductivity of the first memory element changes, two values corresponding to the initial state and after the conductivity change can be stored.

  Some examples in which a bubble generation region is provided in the memory element are shown below.

  When forming the memory element, a film is formed by depositing an inert gas or the like in the atmosphere by an evaporation method to form a layer 23a containing the organic compound of the memory element. Voltage is applied to the first conductive layer 21a and the second conductive layer 24a, and various gas components in the layer mainly gather from the layer 23a containing an organic compound to form bubbles 26. As shown in FIG. In this case, the bubble generation region of the memory element can be said to be a portion sandwiched between the first conductive layer 21a and the second conductive layer 24a of the layer 23a containing an organic compound. Note that the first conductive layer 21 a is formed over the substrate 20 having an insulating surface, and the peripheral edge portion of the first conductive layer 21 a is covered with the partition wall 22.

  As another example, when the memory element is formed, the first conductive layer 21b of the memory element is formed by sputtering and forming an atmosphere containing an inert gas or the like. A state in which a voltage is applied between the first conductive layer 21b and the second conductive layer 24b, and various gas components are gathered mainly from the first conductive layer 21b to form bubbles 26. 2 (B). In this case, the bubble generation region of the memory element can be said to be the first conductive layer 21b.

  As another example, when forming a memory element, a film is formed by adding an inert gas or the like to the atmosphere by a sputtering method, the first conductive layer 21c of the memory element is formed, and the atmosphere is not generated by an evaporation method. A second conductive layer 24c of the memory element is formed by forming a film containing an active gas or the like. By applying a voltage between the first conductive layer 21c and the second conductive layer 24c, various gas components gather from the first conductive layer 21c and the second conductive layer 24c to form bubbles 26. FIG. 2 (C) shows the state. In this case, the bubble generation region of the memory element can be said to be both the first conductive layer 21c and the second conductive layer 24c.

  Further, the present invention is not limited to the above three examples, and a bubble generation region can be provided in the memory element.

Further, FIG. 3 shows a cross-sectional TEM photograph of a portion where bubbles are actually formed between a pair of electrodes when a voltage is applied between the pair of electrodes of the organic memory (2 mm × 2 mm square size). In FIG. 3, it is possible to observe a portion where bubbles having a diameter of 7 μm to 8 μm are formed, the portion where the second conductive layer is pushed up, and the portion where the film thickness of the layer containing the organic compound is reduced. . The layer containing an organic compound having a uniform film thickness before voltage application has changed greatly after voltage application, and the distance between the pair of electrodes is displaced. In addition, although the short circuit location is not shown by FIG. 3, this organic memory is short-circuited.

In the stacked structure of the organic memory shown in FIG. 3, a transparent conductive layer having a thickness of 110 nm obtained by sputtering is used as the first conductive layer. As the transparent conductive layer of the organic memory, ITO (indium tin oxide) or ITSO (indium tin oxide containing silicon oxide obtained by sputtering using a target containing 2 to 10% by weight of silicon oxide in ITO) is used. . In addition to ITSO, a transparent conductive film such as a light-transmitting oxide conductive film (IZO) in which silicon oxide is included and indium oxide is mixed with 2 to 20% zinc oxide (ZnO) may be used. Here, this transparent conductive layer uses ITO (ITSO) containing a small amount of Si. Further, as the second conductive layer, an aluminum film having a thickness of 270 nm obtained by an evaporation method is used. Further, as a layer containing an organic compound provided between the first conductive layer and the second conductive layer, TPD (4,4′-bis [N- (3-methyl Phenyl) -N-phenyl-amino] -biphenyl). The glass transition temperature _{T g} of the TPD is 60 ° C..

  Moreover, the spectrum measurement of the X-ray microanalyzer (EDX) was performed with respect to the peripheral location in which the bubble was formed. The EDX measurement position of the peripheral part where the bubble is formed is shown in the TEM photograph shown in FIG. FIG. 12 shows the results of EDX spectrum measurement at the positions (six locations) shown in FIG.

In this EDX spectrum measurement, secondary X-rays emitted by irradiating the measurement site with an electron beam (200 keV) are measured. A Cu peak is observed in each spectrum because the mesh having the collodion film is made of Cu. Although the mesh portion is not irradiated with an electron beam, it is considered that a part of the irradiated electron beam is scattered when it hits the sample, and the Cu characteristic X-ray is observed when it hits the mesh portion. ing. Since Cu is also observed in the seventh spectrum for the collodion film shown as a reference, it can be determined that the peak of Cu is not essential. Moreover, although there is a spectrum in which C and Ga also appear, it may be observed because of contamination and FIB incident ions.

The first spectrum is the measurement result for the glass substrate, the second spectrum is the measurement result for ITO (first conductive layer) containing a small amount of Si, and the third spectrum is the measurement result for TPD. . The fifth spectrum is a measurement result for aluminum (second conductive layer), the sixth spectrum is a measurement result for a carbon coat layer deposited during FIB processing, and the seventh spectrum is It is the data for the collodion film shown as a reference.

The measurement result for the bubble portion is the fourth spectrum, and the spectral components shown are Cu and C. As described above, Cu is a mesh. The C detected as the spectral component of the fourth spectrum is much smaller than the peak of C in the spectrum in TPD and is comparable to the spectrum for the reference collodion film.

Therefore, from the results of TEM observation and EDX measurement, it was confirmed that no substance was present in the bubble portion.

(Embodiment 2)
FIG. 4A shows an example of a structure of the memory device of the present invention. A bit line including a memory cell array 422 in which memory cells 421 are provided in a matrix, a column decoder 426a, a reading circuit 426b, and a selector 426c. A driver circuit 426, a word line driver circuit 424 having a row decoder 424a and a level shifter 424b, and an interface 423 having a write circuit and the like for exchanging signals with the outside. Note that the structure of the memory device 416 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

  The memory cell 421 includes a first conductive layer constituting the word line Wy (1 ≦ y ≦ n), a second conductive layer constituting the bit line Bx (1 ≦ x ≦ m), and a layer containing an organic compound And have. The layer containing an organic compound is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer. The word line Wy extending in the X direction and the bit line Bx extending in the Y direction intersect with each other, and a single storage element is formed at one intersection. In this specification, a crossing portion is referred to as a memory element, and a region surrounded by word lines and bit lines (a region including the memory element) is referred to as a memory cell. In addition, a partition made of an insulating material is provided between adjacent storage elements so as to cover the periphery of each first conductive layer.

  Note that a highly conductive element, compound, or the like is used as a material for the first conductive layer and the second conductive layer. Desirably, a conductive material that easily generates bubbles due to heat may be used. For example, a sputtering method using an ITO target having an oxygen content of 17 wt% to 18 wt% may be formed in an atmosphere containing oxygen, and 18 wt% or more of oxygen may be included in the first conductive layer. . Instead of the atmosphere containing oxygen, a film may be formed in an atmosphere containing an inert element such as nitrogen or argon, and the first conductive layer may contain the inert element.

In addition, the layer including an organic compound provided between the first conductive layer and the second conductive layer includes an organic compound, an inorganic insulator, or an organic compound and an inorganic compound whose conductivity is changed by an electric action. It is a layer formed by mixing.

In this embodiment mode, data is written to the memory cell by applying an electrical action. Since the conductivity of the memory cell having the above structure changes before and after voltage application, two values corresponding to “initial state” and “after conductivity change” can be stored.

The layer including an organic compound provided between the first conductive layer and the second conductive layer may be provided as a single layer, or a plurality of layers may be stacked. As the organic compound provided between the first conductive layer and the second conductive layer, an organic compound material having a high hole-transport property or an organic compound material having a high electron-transport property can be used. The layer containing an organic compound can be formed by vapor deposition, electron beam vapor deposition, sputtering, CVD, or the like. Moreover, the mixed layer containing an organic compound and an inorganic compound can be formed by simultaneously forming the respective materials. The co-evaporation method using resistance heating evaporation, the co-evaporation method using electron beam evaporation, and resistance heating. It can be formed by a combination of the same or different methods such as co-evaporation by vapor deposition and electron beam vapor deposition, film formation by resistance heating vapor deposition and sputtering, and film formation by electron beam vapor deposition and sputtering.

As an organic compound material having a high hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine compounds (that is, compounds having a benzene ring-nitrogen bond) and phthalocyanines (abbreviations) : H ₂ Pc), copper A phthalocyanine compound such as phthalocyanine (abbreviation: CuPc) or vanadyl phthalocyanine (abbreviation: VOPc) can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher.

As an organic compound material having a high electron-transport property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and a metal complex having a quinoline skeleton or a benzoquinoline skeleton Materials can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher.

Here, a change in conductivity of the memory element before and after voltage application will be described.

When a voltage is applied between the first conductive layer and the second conductive layer, a current flows and heat is generated. The layer containing an organic compound provided between the first conductive layer and the second conductive layer has fluidity when the temperature rises to the glass transition temperature of the material constituting the layer containing the organic compound. Become. If the fluidity of the material increases, the distance between the first conductive layer and the second conductive layer is likely to change.

  When a voltage is applied, bubbles are generated from the first conductive layer or the layer containing an organic compound, thereby causing a state change accompanied by a sharp volume change between the pair of electrodes. The action force based on this state change promotes a short circuit between the pair of electrodes. In some cases, partial peeling near the interface between layers may occur due to an impact caused by voltage application. Therefore, the conductivity of the memory element before and after voltage application changes.

As a result, writing into the memory cell can be performed with low power consumption.

  Next, an operation for reading data from the memory element is described (see FIG. 4B). Here, the reading circuit 426b includes a resistance element 446 and a sense amplifier 447. However, the structure of the reading circuit 426b is not limited to the above structure, and may have any structure.

  Data is read by applying a voltage between the first conductive layer and the second conductive layer and reading the electrical resistance of the memory element. For example, as described above, when data is written by an electrical action, the resistance value Ra1 when no electrical action is applied and the resistance value when a short circuit between two conductive films is applied by applying an electrical action. Rb1 satisfies Ra1> Rb1. Data is read by electrically reading such a difference in resistance value.

  For example, when reading data from one memory cell 421 arranged in the xth column and the yth row from a memory cell array 422 including a plurality of memory cells, first, the row decoder 424a, the column decoder 426a, and the selector 426c The bit line Bx in the x column and the word line Wy in the y row are selected. Then, the insulating layer included in the memory cell 421 and the resistance element 446 are connected in series. Thus, when a voltage is applied across the two resistance elements connected in series, the potential of the node α is resistance-divided according to the resistance value Ra or Rb of the memory element (layer containing the organic compound). It becomes a potential. The potential of the node α is supplied to the sense amplifier 447, and the sense amplifier 447 determines whether it has information “0” or “1”. Thereafter, a signal including information of “0” and “1” determined by the sense amplifier 447 is supplied to the outside.

According to the above method, the state of the electrical resistance of the memory element is read as a voltage value using the difference in resistance value and resistance division. However, a method of comparing current values may be used. This is because, for example, the current value Ia1 when no electrical action is applied between the first conductive layer and the second conductive layer, and the resistance when the electrical action is shorted between the two conductive films. The value Ib1 uses that Ia1 <Ib1 is satisfied.

  Since a memory element having the above structure and a semiconductor device including the memory element are nonvolatile memories, a small, thin, and lightweight semiconductor device is provided without the need to incorporate a battery for holding data. Can do.

  Note that in this embodiment, a passive matrix memory element with a simple structure of a memory circuit and a semiconductor device including the memory element are described as examples; however, an active matrix memory circuit is provided. Even in this case, data can be written or read in the same manner.

Further, this embodiment mode can be freely combined with Embodiment Mode 1.

(Embodiment 3)
In this embodiment, a memory device having a structure different from that in Embodiment 2 is described. Specifically, a case where the structure of the memory device is an active matrix type will be described.

  FIG. 5A illustrates an example of a structure of the memory device described in this embodiment. A memory cell array 522 in which memory cells 521 are provided in a matrix, a column decoder 526a, a reading circuit 526b, and a selector 526c are included. A bit line driving circuit 526 having a word line driving circuit 524 having a row decoder 524a and a level shifter 524b, an interface 523 having a writing circuit and the like and performing exchange with the outside. Note that the structure of the memory device 516 here is just an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a write circuit may be provided in the bit line driver circuit.

  The memory cell 521 includes a first wiring configuring a word line Wy (1 ≦ y ≦ n), a second wiring configuring a bit line Bx (1 ≦ x ≦ m), a transistor 540, and a memory element 541. And a memory cell 521. The memory element 541 has a structure in which an insulating layer (a layer containing an organic compound) is sandwiched between a pair of conductive layers.

  A top view of the memory cell array 522 corresponding to the block diagram of FIG. 5A is shown in FIG.

In the memory cell array 522, first wirings 505a and 505b extending in a first direction and second wirings 502 extending in a second direction perpendicular to the first direction are provided in a matrix. The first wiring is connected to the source or drain electrode of the transistors 540a and 540b, and the second wiring is connected to the gate electrodes of the transistors 540a and 540b. Further, the first conductive layer 506a and the first conductive layer 506b are connected to the source electrode or the drain electrode of the transistor 540a and the transistor 540b which are not connected to the first wiring, respectively. A memory element 541a and a memory element 541b are provided by a stacked structure of the first conductive layer 506b, the layer 512 containing an organic compound, and the second conductive layer 513. A partition wall (insulating layer) 507 is provided between each adjacent memory cell 521, and a layer 512 containing an organic compound and a second conductive layer 513 are stacked over the first conductive layer and the partition wall 507. .

In addition, the protective layer 514 is provided over the second conductive layer 513. Thin film transistors (TFTs) are used as the transistors 540a and 540b. FIG. 6 shows a cross-sectional view taken along the chain line AB in FIG. In FIG. 6, the same reference numerals are used for the same portions as those in FIGS. 5A and 5B.

The memory device in FIG. 6 is provided over a substrate 500 having an insulating surface, and includes a first base insulating layer 501a, a second base insulating layer 501b, a gate insulating layer 508, a first interlayer insulating layer 509, a first interlayer insulating layer 509, Two interlayer insulating layers 511 are provided. In addition, the semiconductor layer 504a included in the transistor 540a, the gate electrode layer 502a, and a wiring 505a serving also as a source or drain electrode layer are provided over the substrate 500. In addition, a semiconductor layer 504b included in the transistor 540b, a gate electrode layer 502b, and a wiring 505b serving also as a source electrode layer or a drain electrode layer are provided over the substrate 500.

  Here, the example of the top gate type TFT has been described, but the present invention can be applied regardless of the TFT structure. For example, the invention can be applied to a bottom gate type (reverse stagger type) TFT or a forward stagger type TFT. Is possible. Further, the invention is not limited to a single-gate transistor, and may be a multi-gate transistor having a plurality of channel formation regions, for example, a double-gate transistor.

  In addition, the present invention is not limited to the TFT structure of FIG. 6, and if necessary, a lightly doped drain (LDD) structure having an LDD region between a channel formation region and a drain region (or source region). Also good. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. Further, a so-called GOLD (Gate-Drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film may be employed.

  Here, an example of a thin film transistor provided over a glass substrate as the transistors 540a and 540b is shown; however, the transistor 540a and 540b is not particularly limited, and a field effect transistor formed over a semiconductor substrate such as Si as the transistors 540a and 540b ( FET) can also be used. Alternatively, an SOI substrate may be used as a substrate, and an element formation layer may be provided thereover. In this case, the SOI substrate may be formed by using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate.

Further, in this embodiment mode, data can be written or read as in Embodiment Mode 2.

Here, in the case of an active matrix device, a case where data in a memory element portion is read by an electrical action will be described with reference to specific examples in FIGS. 7A and 7B.

Here, an example in the case of the configuration shown in FIG. 7B will be described. The reading circuit 526b includes a resistance element and a sense amplifier 547. However, the structure of the reading circuit 526b is not limited to the above structure, and may have any structure.

  Data is read by applying a voltage between the first conductive layer and the second conductive layer and reading the electrical resistance of the memory element. For example, as described above, when data is written by an electrical action, the resistance value Ra1 when no electrical action is applied and the resistance value when a short circuit between two conductive films is applied by applying an electrical action. Rb1 satisfies Ra1> Rb1. Data is read by electrically reading such a difference in resistance value.

  For example, when reading data from one memory cell 521 arranged in the xth column and the yth row from a memory cell array 522 including a plurality of memory cells, first, the row decoder 524a, the column decoder 526a, and the selector 526c The bit line Bx in the x column and the word line Wy in the y row are selected. Then, the insulating layer included in the memory cell 521 and the resistance element are connected in series. Thus, when a voltage is applied across the two resistance elements connected in series, the potential of the node α is resistance-divided according to the resistance value Ra or Rb of the memory element (layer containing the organic compound). It becomes a potential. Then, the potential of the node α is supplied to the sense amplifier 547, and it is determined whether the sense amplifier 547 has information “0” or “1”. Thereafter, a signal including information of “0” and “1” determined by the sense amplifier 547 is supplied to the outside.

  FIG. 7A illustrates a current-voltage characteristic 551 of a memory element portion in which data “0” is written in the memory element portion, a current-voltage characteristic 552 of memory element portion in which data “1” is written, A current-voltage characteristic 553 of the resistance element is shown, and here, a case where a transistor 546 is used as the resistance element is shown. A case where 3 V is applied between the first conductive layer 506a and the second conductive layer 513 as an operation voltage when reading data is described.

  In FIG. 7A, in a memory cell having a memory element portion where data of “0” is written, an intersection 554 between the current-voltage characteristic 551 of the memory element portion and the current-voltage characteristic 553 of the transistor serves as an operating point. At this time, the potential of the node α is V1 (V). The potential of the node α is supplied to the sense amplifier 547, and the data stored in the memory cell is determined to be “0” in the sense amplifier 547.

  On the other hand, in a memory cell having a memory element portion in which data of “1” is written, the intersection 555 between the current-voltage characteristic 552 of the memory element portion and the current-voltage characteristic 553 of the transistor serves as an operating point. The potential of α is V2 (V) (V1> V2). The potential of the node α is supplied to the sense amplifier 547, and the data stored in the memory cell is determined as “1” in the sense amplifier 547.

  As described above, the data stored in the memory cell can be determined by reading the resistance-divided potential according to the resistance value of the memory element portion 541.

Further, this embodiment mode can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

(Embodiment 4)
In this embodiment, an example of a semiconductor device including the memory device described in the above embodiment will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates by induced electromagnetic waves, and a radio system that communicates using radio waves, but any system may be used. In addition, there are two types of antennas used for data transmission. When one antenna is provided on a substrate on which a plurality of elements and memory elements are provided, the other is provided with a plurality of elements and memory elements. In some cases, a terminal portion is provided over the substrate, and an antenna provided over another substrate is connected to the terminal portion.

  Here, a structural example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of elements and memory elements will be described with reference to FIGS.

  FIG. 8 illustrates a semiconductor device having a memory device formed of an active matrix type. A transistor portion 330 including transistors 310a and 310b over a substrate 300, a transistor portion 340 including transistors 320a and 320b, an insulating layer 301a, An element formation layer 335 including 301b, 308, 309, 311, 316, and 314 is provided, and a storage element portion 325 and a conductive layer 343 functioning as an antenna are provided above the element formation layer 335.

  Note that here, the case where the memory element portion 325 or the conductive layer 343 functioning as an antenna is provided above the element formation layer 335 is shown; however, the structure is not limited thereto, and the memory element portion 325 or the conductive layer 343 functioning as an antenna is provided. Can be provided below the element formation layer 335 or in the same layer.

  The memory element portion 325 includes memory elements 315a and 315b. The memory element 315a has a partition wall (insulating layer) 307a, a partition wall (insulating layer) 307b, an insulating layer 312 and a second conductive layer on the first conductive layer 306a. The memory element 315b includes a partition wall (insulating layer) 307b, a partition wall (insulating layer) 307c, an insulating layer 312 and a second conductive layer 313 which are stacked over the first conductive layer 306b. Is provided. In addition, an insulating layer 314 that covers the second conductive layer 313 and functions as a protective film is formed.

In addition, the memory element 315a includes a first conductive layer 306a, and the first conductive layer 306a is connected to the source electrode layer or the drain electrode layer of the transistor 310a. In addition, the memory element 315b includes a first conductive layer 306b, and the first conductive layer 306b is connected to a source electrode layer or a drain electrode layer of the transistor 310b. That is, each storage element is connected to one transistor. In addition, although the insulating layer 312 is formed over the entire surface so as to cover the first conductive layers 306a and 306b and the partition walls (insulating layers) 307a, 307b, and 307c, the insulating layer 312 may be selectively formed in each memory cell. . Note that the memory elements 315a and 315b can be formed using any of the materials and manufacturing methods described in the above embodiment modes.

  In the memory element 315a, an element having a rectifying property may be provided between the first conductive layer 306a and the insulating layer 312 or between the insulating layer 312 and the second conductive layer 313. The above-described materials can also be used for the rectifying element. The same applies to the memory element 315b.

  Here, the conductive layers 342 and 343 functioning as antennas are provided over a conductive layer 341 formed using the same layer as the second conductive layer 313. Note that a conductive layer functioning as an antenna may be formed using the same layer as the second conductive layer 313.

  As a material of the conductive layer 343 functioning as an antenna, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al ), Manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 343 functioning as an antenna, various printing methods such as vapor deposition, sputtering, CVD, screen printing, and gravure printing, a droplet discharge method, or the like can be used.

  The transistors 310a, 310b, 310c, and 310d included in the element formation layer 335 can be provided using a p-channel TFT, an n-channel TFT, or a combination of these. Further, any structure of the semiconductor layer included in the transistors 310a, 310b, 310c, and 310d may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) may be formed. The p channel type or the n channel type may be used. Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source and drain regions and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  Alternatively, the transistors 310a, 310b, 310c, and 310d included in the element formation layer 335 may be organic transistors in which a semiconductor layer included in the transistor is formed using an organic compound. In this case, the element formation layer 335 including an organic transistor can be formed using a printing method, a droplet discharge method, or the like over a flexible substrate such as plastic as the substrate 300. By using a printing method, a droplet discharge method, or the like, a semiconductor device can be manufactured at lower cost.

  The element formation layer 335, the memory elements 315a and 315b, and the conductive layer 343 functioning as an antenna can be formed by vapor deposition, sputtering, CVD, printing, droplet discharge, or the like as described above. . Note that a different method may be used depending on each place. For example, a transistor that requires high-speed operation is provided by forming a semiconductor layer made of Si or the like on a substrate and then crystallizing it by heat treatment, and then forming a transistor that functions as a switching element above the element formation layer by a printing method or An organic transistor can be provided by a droplet discharge method.

Note that a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor is typically formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

  Alternatively, transfer to a flexible substrate may be performed using a peeling technique. In that case, after a release layer or a separation layer is provided over a first substrate such as a glass substrate, a TFT and a memory are manufactured. Then, peeling occurs in the layer of the peeling layer or at the interface, or the separation layer is removed and the TFT and the memory are peeled from the first substrate. Then, the peeled TFT and memory may be transferred to a second substrate which is a flexible substrate.

Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment Mode 3.

(Embodiment 5)
The configuration of the semiconductor device of this embodiment will be described with reference to FIG. 9A. As shown in FIG. 9A, a semiconductor device 620 of the present invention has a function of communicating data without contact, and controls to control a power supply circuit 611, a clock generation circuit 612, a data demodulation / modulation circuit 613, and other circuits. The circuit includes a circuit 614, an interface circuit 615, a memory circuit 616, a data bus 617, an antenna (antenna coil) 618, a sensor 621, and a sensor circuit 622.

The power supply circuit 611 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 620 based on the AC signal input from the antenna 618. The clock generation circuit 612 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 620 based on the AC signal input from the antenna 618. The data demodulation / modulation circuit 613 has a function of demodulating / modulating data communicated with the reader / writer 619. The control circuit 614 has a function of controlling the memory circuit 616. The antenna 618 has a function of transmitting and receiving electromagnetic waves or radio waves. The reader / writer 619 controls communication with the semiconductor device, control, and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

The memory circuit 616 includes a memory element in which an insulating layer that is changed by an external electric action or light irradiation is sandwiched between a pair of conductive layers. Note that the memory circuit 616 may include only a memory element in which an insulating layer is sandwiched between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to one or more selected from, for example, DRAM, SRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

The sensor 623a is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 623b detects a change in impedance, reactance, inductance, voltage, or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 614.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. An electronic device illustrated here is a mobile phone, which includes housings 700 and 706, a panel 701, a housing 702, a printed wiring board 703, operation buttons 704, and a battery 705 (see FIG. 9B). The panel 701 is detachably incorporated in the housing 702, and the housing 702 is fitted to the printed wiring board 703. The shape and size of the housing 702 are changed as appropriate in accordance with the electronic device in which the panel 701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 703 have any of functions of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 701 is fixedly connected to the printed wiring board 703 via the connection film 708. The panel 701, the housing 702, and the printed wiring board 703 are housed in the housings 700 and 706 together with the operation buttons 704 and the battery 705. A pixel region 709 included in the panel 701 is arranged so as to be visible from an opening window provided in the housing 700.

As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight. With the above characteristics, the limited space inside the casings 700 and 706 of the electronic device can be used effectively. .

The semiconductor device of the present invention has a simple structure in which an insulating layer (that is, a layer containing an organic compound sandwiched between a pair of electrodes) that is changed by an external electric action is sandwiched between a pair of conductive layers. Since the memory element is included, an electronic device using an inexpensive semiconductor device can be provided. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

Note that the housings 700 and 706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be changed into various modes depending on functions and uses.

Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, or Embodiment Mode 4.

(Embodiment 6)
According to the present invention, a semiconductor device functioning as a wireless chip can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 10A), packaging containers (wrapping paper, Bottle, etc., see FIG. 10C), recording medium (DVD software, video tape, etc., see FIG. 10B), vehicles (bicycle, etc., see FIG. 10D), personal items (bags, glasses, etc.) ), Foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and goods such as luggage tags (see FIGS. 10E and 10F) for use. be able to. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

The semiconductor device 910 of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device 910 of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. Further, by providing the semiconductor device 910 of the present invention to bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and forgery can be prevented by utilizing this authentication function. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

This embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, or Embodiment Mode 5.

Sectional drawing which shows the mode of the memory element of this invention before and behind voltage application. Sectional drawing which shows the mode of bubble generation. The figure which shows the TEM photograph of the formation location of a bubble. 10A and 10B illustrate a passive matrix memory device and a reading circuit. FIG. 11 illustrates an active matrix memory device. FIG. 14 is a cross-sectional view illustrating an active matrix memory device. 4A and 4B illustrate a current-voltage characteristic and a diagram illustrating a reading circuit. Sectional drawing of the semiconductor device of this invention. 8A and 8B illustrate a structure example of a semiconductor device of the present invention and an electronic device having the structural example. 4A and 4B each illustrate a usage pattern of a semiconductor device of the invention. FIG. 4 is a partially enlarged view of a bubble forming portion and a TEM photograph showing a portion where EDX spectrum measurement is performed. The figure which shows the result of the spectrum measurement of EDX.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 11a 1st conductive layer 11b 1st conductive layer 12 Partition 13a Layer 13b containing an organic compound 14b Layer containing an organic compound 14 Second conductive layer 15 Short-circuit place 16 Bubble 20 Substrate 21a having an insulating surface First conductive Layer 21b first conductive layer 21c first conductive layer 22 partition wall 23a layer 23b containing organic compound layer 23b layer containing organic compound layer 24a layer containing organic compound second conductive layer 24b second conductive layer 24c second conductive layer Layer 26 Bubble 300 Substrate 301a Insulating layer 301b Insulating layer 306a First conductive layer 306b First conductive layer 307a Partition (insulating layer)
307b Partition wall (insulating layer)
307c Partition wall (insulating layer)
308 Insulating layer 309 Insulating layer 310a Transistor 310b Transistor 311 Insulating layer 312 Insulating layer 313 Second conductive layer 314 Insulating layer 315a Memory element 315b Memory element 316 Insulating layer 320a Transistor 320b Transistor 330 Transistor part 340 Transistor part 341 Conductive layer 342 Conductive layer 343 Conductive layer 416 Memory device 421 Memory cell 422 Memory cell array 423 Interface 424 Word line driver circuit 424a Row decoder 424b Level shifter 426 Bit line driver circuit 426a Column decoder 426b Read circuit 426c Selector 446 Resistance element 447 Sense amplifier 500 Substrate 501a having an insulating surface First base insulating layer 501b Second base insulating layer 502 Second wiring 502a Gate electrode layer 502 The gate electrode layer 504a semiconductor layer 504b semiconductor layer 505a first wiring 505b first wiring 506a first conductive layer 506b first conductive layer 507 partition wall (insulating layer)
508 Gate insulating layer 509 First interlayer insulating layer 511 Second interlayer insulating layer 512 Layer containing organic compound 513 Second conductive layer 514 Protective layer 516 Memory device 521 Memory cell 522 Memory cell array 523 Interface 524 Word line driver circuit 524a Row decoder 524b Level shifter 526 Bit line drive circuit 526a Column decoder 526b Read circuit 526c Selector 540 Transistor 540a Transistor 540b Transistor 541 Memory element 541a Memory element 541b Memory element 546 Transistor 547 Sense amplifier 551 Current voltage characteristic 552 Memory element part current voltage characteristic 553 Current Voltage characteristics 554 Intersection 555 Intersection 611 Power supply circuit 612 Clock generation circuit 613 Data demodulation / modulation circuit 614 Control circuit 615 IN Over interface circuit 616 memory circuit 617 data bus 618 antenna (antenna coil)
619 Reader / writer 620 Semiconductor device 621 Sensor 622 Sensor circuit 700 Case 701 Panel 702 Housing 703 Printed wiring board 704 Operation button 705 Battery 706 Case 708 Connection film 709 Pixel region 910 Semiconductor device

Claims (14)

A plurality of storage elements,
The memory element has a stacked structure of a first conductive layer, a layer containing an organic compound, and a second conductive layer,
The semiconductor device, wherein the memory element has a bubble generation region. A plurality of storage elements,
The memory element has a stacked structure of a first conductive layer, a layer containing an organic compound, and a second conductive layer,
The memory element has a bubble generation region, and the bubble generation region includes at least part of the first conductive layer. A plurality of storage elements,
The memory element has a stacked structure of a first conductive layer, a layer containing an organic compound, and a second conductive layer,
The memory element has a bubble generation region, and the bubble generation region includes at least part of a layer including the organic compound. A plurality of storage elements,
The memory element has a stacked structure of a first conductive layer, a layer containing an organic compound, and a second conductive layer,
The memory device has a bubble generation region, and the bubble generation region includes at least part of the second conductive layer. 5. The method according to claim 1, wherein a voltage is applied between the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer are formed from the bubble generation region. Forming a bubble in a layer, and writing to the memory element is facilitated by short-circuiting the first conductive layer and the second conductive layer by pressure based on the generation of the bubble apparatus. 5. The first conductive layer and the second conductive layer according to claim 1, wherein the first conductive layer and the second conductive layer are formed from the bubble generation region by heat generated between the first conductive layer and the second conductive layer. And writing data to the memory element by partially displacing the gap between the first conductive layer and the second conductive layer by a pressure based on the generation of the bubble. A semiconductor device characterized by being promoted. 7. The semiconductor device according to claim 1, wherein the layer including an organic compound includes an organic compound having a glass transition temperature of 50 ° C. or higher and 200 ° C. or lower. 8. The semiconductor device according to claim 1, further comprising a plurality of bit lines extending in a first direction and a plurality of word lines extending in a second direction perpendicular to the first direction. Have
The semiconductor device, wherein the first conductive layer is electrically connected to the bit line, and the second conductive layer is electrically connected to the word line. A plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction perpendicular to the first direction; and a storage element;
The memory element has a stacked structure of a first conductive layer constituting the bit line, a layer containing an organic compound, and a second conductive layer constituting the word line,
The layer containing an organic compound contains an organic compound having a glass transition temperature of 50 ° C. or higher and 200 ° C. or lower. A plurality of bit lines extending in a first direction; a plurality of word lines extending in a second direction perpendicular to the first direction; and a storage element;
The memory element has a stacked structure of a first conductive layer constituting the bit line, a layer containing an organic compound, and a second conductive layer constituting the word line,
The memory device has at least one bubble between a first conductive layer and a second conductive layer. In Claim 10, the bubble is overlapped with a part of the first conductive layer and a part of the second conductive layer,
The semiconductor device is characterized in that a distance between a part of the first conductive layer and a part of the second conductive layer is larger than other parts. A voltage is applied to a memory element having a stack of a first conductive layer, a layer containing an organic compound, and a second conductive layer,
Generating bubbles between the first conductive layer and the second conductive layer;
A driving method of a semiconductor device, wherein writing of a memory element is facilitated by short-circuiting the first conductive layer and the second conductive layer by pressure based on generation of bubbles. A voltage is applied to a memory element having a stack of a first conductive layer, a layer containing an organic compound, and a second conductive layer, heat is generated in the memory element,
Bubbles are generated between the first conductive layer and the second conductive layer by heat generated in the memory element;
A driving method of a semiconductor device, characterized in that writing to a memory element is facilitated by displacing a distance between the first conductive layer and the second conductive layer by pressure based on generation of bubbles. 14. The method for driving a semiconductor device according to claim 12, wherein the layer including an organic compound includes an organic compound having a glass transition temperature of 50 ° C. to 200 ° C.